Array substrate, preparation method thereof and display panel

Abstract

The invention discloses an array substrate, a preparation method thereof and a display panel. The array substrate comprises a substrate, a first active layer and a second conductive layer. The first conductive layer comprises a first electrode part and a second electrode part, and the first electrode part and the second electrode part are in contact connection with the first channel part on the two sides of the first channel part. The second conducting layer comprises a first grid electrode, and the orthographic projection of the first grid electrode on the substrate and the orthographic projection of the first channel part on the substrate are overlapped, so that the first grid electrode serves as the grid electrode of the first channel part, and the electric conduction of the first channel part is controlled. The first electrode part and the second electrode part of the conductive material are in direct contact with the first channel part and serve as a source region and a drain region of the first transistor, the first electrode part and the second electrode part of the conductive material do not need to be conducted, the preparation process is simplified, source and drain electrode wires do not need to be hollowed out, the hole digging area of the source and drain electrode wires is saved, and the manufacturing cost is reduced. And the first channel part with smaller channel length can be conveniently designed, and the device area of the transistor is reduced.

Description

Technical Field

[0001] This application relates to the field of display, specifically to an array substrate, its fabrication method, and a display panel. Background Technology

[0002] Organic light-emitting diodes (OLEDs) and flat panel displays based on light-emitting diodes (LEDs) are widely used in various consumer electronics products such as mobile phones, televisions, laptops, and desktop computers due to their advantages such as high image quality, energy saving, thin body and wide range of applications, becoming the mainstream of display devices.

[0003] However, the performance of current OLED display products needs to be improved. Summary of the Invention

[0004] This application provides an array substrate, a method for fabricating the same, and a display panel, aiming to improve the performance of OLED display products.

[0005] A first aspect of this application provides an array substrate, the array substrate comprising: a substrate; a first conductive layer disposed on one side of the substrate, the first conductive layer including a first electrode portion and a second electrode portion disposed at intervals along a direction parallel to the substrate; a first active layer disposed on one side of the substrate and including a first channel portion at least partially located between the first electrode portion and the second electrode portion, one side of the first channel portion being in contact with the first electrode portion, and the other side of the first channel portion being in contact with the second electrode portion; a second conductive layer disposed on the side of the first active layer facing or away from the substrate, the second conductive layer including a first gate, the orthographic projection of the first gate portion onto the substrate covering the orthographic projection of the first channel portion onto the substrate, the first electrode portion, the second electrode portion, the first channel portion and the first gate portion constituting a first transistor.

[0006] According to an embodiment of the first aspect of this application, the material of the first channel portion includes oxide, the materials of the first electrode portion and the first channel portion are different, and the materials of the second electrode portion and the first channel portion are different.

[0007] According to any of the foregoing embodiments of the first aspect of this application, the materials of the first electrode portion and the second electrode portion include at least one of metal oxide, metal, and metal nitride.

[0008] According to any of the foregoing embodiments of the first aspect of this application, in a direction parallel to the substrate, the length of the portion of the first channel portion located between the first electrode portion and the second electrode portion is 0.05 μm to 2 μm.

[0009] According to any of the foregoing embodiments of the first aspect of this application, in a direction parallel to the substrate, the length of the portion of the first channel portion located between the first electrode portion and the second electrode portion is 0.1 μm to 1 μm.

[0010] According to any of the foregoing embodiments of the first aspect of this application, the first electrode portion and / or the second electrode portion cover the surface of the first channel portion that is away from the substrate.

[0011] According to any of the foregoing embodiments of the first aspect of this application, the first channel portion covers the surface of the first electrode portion away from the substrate, and / or, the first channel portion covers the surface of the second electrode portion away from the substrate.

[0012] According to any of the foregoing embodiments of the first aspect of this application, it further includes: a third conductive layer located between the substrate and the first conductive layer, the third conductive layer including a first conductive portion, wherein the orthographic projection of the first conductive portion on the substrate and the orthographic projection of the first channel portion on the substrate at least partially overlap.

[0013] According to any of the foregoing embodiments of the first aspect of this application, the third conductive layer is reused as the second conductive layer, and the first conductive portion is reused as the first gate; or, the second conductive layer is located on the side of the first active layer away from the substrate.

[0014] According to any of the foregoing embodiments of the first aspect of this application, the portion of the first channel portion located between the first electrode portion and the second electrode portion has its orthogonal projection onto the substrate located within the orthogonal projection of the first conductive portion onto the substrate.

[0015] According to any of the foregoing embodiments of the first aspect of this application, the material of the third conductive layer includes titanium.

[0016] According to any of the foregoing embodiments of the first aspect of this application, the third conductive layer further includes a first electrode plate disposed at a distance from the first conductive portion, wherein the orthographic projection of the first electrode plate on the substrate overlaps with the orthographic projection of the first electrode portion or the second electrode portion on the substrate, and the first electrode plate and the first electrode portion or the second electrode portion form a first capacitor.

[0017] According to any of the foregoing embodiments of the first aspect of this application, it further includes: a fourth conductive layer located on the side of the first active layer away from the substrate, the fourth conductive layer including a second conductive portion, wherein the orthographic projection of the first channel portion on the substrate and the orthographic projection of the second conductive portion on the substrate at least partially overlap.

[0018] According to any of the foregoing embodiments of the first aspect of this application, the fourth conductive layer is reused as the second conductive layer, and the second conductive portion is reused as the first gate; or, the second conductive layer is located on the side of the first active layer facing the substrate.

[0019] According to any of the foregoing embodiments of the first aspect of this application, the portion of the first channel portion located between the first electrode portion and the second electrode portion has its orthogonal projection onto the substrate located within the orthogonal projection of the second conductive portion onto the substrate.

[0020] According to any of the foregoing embodiments of the first aspect of this application, the orthographic projection of the first electrode portion onto the substrate and the orthographic projection of the second conductive portion onto the substrate at least partially overlap.

[0021] According to any of the foregoing embodiments of the first aspect of this application, the orthographic projection of the second electrode portion onto the substrate and the orthographic projection of the second conductive portion onto the substrate at least partially overlap.

[0022] According to any of the foregoing embodiments of the first aspect of this application, the fourth conductive layer further includes a second electrode plate disposed at a distance from the second conductive portion, wherein the orthographic projection of the second electrode plate on the substrate overlaps with the orthographic projection of the first electrode portion or the second electrode portion on the substrate, and the second electrode plate and the first electrode portion or the second electrode portion form a second capacitor.

[0023] According to any of the foregoing embodiments of the first aspect of this application, it further includes: a second transistor located on one side of the substrate, the second transistor including a third electrode portion, a fourth electrode portion, a second channel portion and a second gate, the third electrode portion and the fourth electrode portion being spaced apart, at least a portion of the second channel portion being located between the third electrode portion and the fourth electrode portion, and the second channel portion being in contact with the third electrode portion and the fourth electrode portion, the orthographic projection of the second gate portion on the substrate and the orthographic projection of the second channel portion on the substrate at least partially overlapping; wherein, one of the third electrode portion and the fourth electrode portion includes a first electrode plate region, one of the first electrode portion and the second electrode portion and the first gate portion includes a second electrode plate region, the orthographic projection of the first electrode plate region on the substrate and the orthographic projection of the second electrode plate region on the substrate overlap, and the first electrode plate region and the second electrode plate region form a third capacitor.

[0024] According to any of the foregoing embodiments of the first aspect of this application, one of the first electrode portion and the second electrode portion includes a second electrode plate region, and the first electrode plate region and the first gate are on the same layer.

[0025] According to any of the foregoing embodiments of the first aspect of this application, the first electrode region and the first gate are spaced apart.

[0026] According to any of the foregoing embodiments of the first aspect of this application, the first electrode region and the first gate are electrically connected.

[0027] According to any of the foregoing embodiments of the first aspect of this application, the first electrode region and the first gate are integrally disposed.

[0028] According to any of the foregoing embodiments of the first aspect of this application, the orthographic projection of the first channel portion onto the substrate and the orthographic projection of the second electrode region onto the substrate at least partially overlap.

[0029] According to any of the foregoing embodiments of the first aspect of this application, the first gate includes a second electrode region, the first gate is located on the side of the first electrode portion and the first channel portion away from the substrate, and the third electrode portion and the fourth electrode portion are located on the side of the first gate away from the substrate.

[0030] According to any of the foregoing embodiments of the first aspect of this application, the first electrode plate region is electrically connected to the first electrode portion or the second electrode portion.

[0031] According to any of the foregoing embodiments of the first aspect of this application, it further includes: a fifth conductive layer disposed on the side of the first active layer away from the substrate, the fifth conductive layer including a third electrode portion and a fourth electrode portion; a second active layer disposed on the side of the first active layer away from the substrate and including a second channel portion; and a sixth conductive layer disposed on the side of the second active layer facing or away from the substrate, the sixth conductive layer including a second gate.

[0032] An embodiment of the second aspect of this application provides a display panel that includes an array substrate of any of the above embodiments.

[0033] An embodiment of the third aspect of this application provides a method for fabricating an array substrate, comprising: Provide a substrate; A first conductive layer is prepared on one side of a substrate, the first conductive layer including a first electrode portion and a second electrode portion disposed at intervals along a direction parallel to the substrate; A first active layer is formed on one side of a substrate. The first active layer includes a first channel portion located at least partially between a first electrode portion and a second electrode portion. One side of the first channel portion is in contact with the first electrode portion, and the other side of the first channel portion is in contact with the second electrode portion. A second conductive layer is prepared on the side of the first active layer facing or away from the substrate. The second conductive layer includes a first gate. The orthogonal projection of the first gate onto the substrate covers the orthogonal projection of the first channel onto the substrate. The first electrode, the second electrode, the first channel, and the first gate constitute a first transistor.

[0034] According to an embodiment of this application, the array substrate includes a substrate, a first active layer, and a second conductive layer. The first conductive layer includes a first electrode portion and a second electrode portion, which are in contact with the first channel portion on both sides of the first channel portion. The second conductive layer includes a first gate, the orthographic projection of the first gate onto the substrate and the orthographic projection of the first channel portion onto the substrate overlap, such that the first gate serves as the gate of the first channel portion, controlling the electrical conduction of the first channel portion. The first electrode portion and the second electrode portion of the conductive material are in direct contact with the first channel portion, serving as the source and drain regions of the first transistor. The first electrode portion and the second electrode portion of the conductive material do not need to be conductord, simplifying the fabrication process. Furthermore, there is no need to hollow out the source and drain wiring, saving the hole area for the source and drain wiring. This also facilitates the design of a first channel portion with a shorter channel length, reducing the device area of ​​the transistor and contributing to a higher PPI (Pixels Per Inch), thereby improving the performance of the display product. Attached Figure Description

[0035] Other features, objects, and advantages of this application will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings, in which the same or similar reference numerals denote the same or similar features, and the drawings are not drawn to scale.

[0036] Figure 1 This is a partial cross-sectional view of an array substrate provided in an embodiment of this application; Figure 2 yes Figure 1 The equivalent circuit diagram; Figure 3a This is a partial cross-sectional view of the display panel in another embodiment; Figure 3b This is a partial cross-sectional view of the display panel in another embodiment; Figure 4 This is a partial cross-sectional view of the display panel in yet another embodiment; Figure 5 This is a partial cross-sectional view of the display panel in another embodiment; Figure 6 This is a partial cross-sectional view of the display panel in another embodiment; Figure 7 yes Figure 6 The equivalent circuit diagram; Figure 8 This is a partial cross-sectional view of the display panel in another embodiment; Figure 9 This is a partial cross-sectional view of the display panel in another embodiment; Figure 10 This is a partial cross-sectional view of the display panel in another embodiment; Figure 11 yes Figure 10 The equivalent circuit diagram; Figure 12 This is a partial cross-sectional view of the display panel in another embodiment; Figure 13 yes Figure 12 The equivalent circuit diagram; Figure 14 This is a partial cross-sectional view of the display panel in another embodiment; Figure 15 yes Figure 14 The equivalent circuit diagram; Figure 16 This is a partial cross-sectional view of the display panel in another embodiment; Figure 17 yes Figure 16 The equivalent circuit diagram; Figure 18 This is a flowchart illustrating the fabrication process of an array substrate provided in an embodiment of this application.

[0037] Explanation of reference numerals in the attached figures: 10. Array substrate; T1, first transistor; T2, second transistor; Q1, first electrode region; Q2, second electrode region; 100. Substrate; 200, First conductive layer; 210, First electrode portion; 220, Second electrode portion; 230, First insulating layer; 300. First active layer; 310. First channel section; 400, Second conductive layer; 410, First gate; 420, Second insulating layer; 421, First sub-layer; 422, Second sub-layer; 500, Third conductive layer; 510, First conductive part; 520, First electrode plate; 600, Fourth conductive layer; 610, Second conductive part; 620, Second electrode plate; 700, Fifth conductive layer; 710, Third electrode section; 720, Fourth electrode section; 730, Third insulating layer; 800, Second active layer; 810, Second channel section; 900, Sixth conductive layer; 910, Second gate; C1, the first capacitor; C2, the second capacitor; C3, the third capacitor; X, the first direction. Detailed Implementation

[0038] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. The components of the embodiments of this application described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.

[0039] Therefore, the following detailed description of the embodiments of this application provided in the accompanying drawings is not intended to limit the scope of the claimed application, but merely to illustrate selected embodiments of the application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.

[0040] It should be noted that similar reference numerals and letters in the following figures indicate similar items; therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures. It should be noted that, unless otherwise specified, different features in the embodiments of this application can be combined with each other.

[0041] For certain elements, terms such as "above" or "over" are sometimes used when describing their location, and "below" or "under" are used when describing the location of elements located in the opposite direction. Furthermore, when using terms such as "above," "over," "below," "under," or "relative" to define the positional relationship between two elements, this includes not only the state where the two elements are directly adjacent, but also the state where the two elements are separated by gaps or other elements. Additionally, the terms "first," "second," and "third," etc., are used only for distinguishing descriptions and should not be construed as indicating or implying relative importance. At least one may include one or more. At least one may include one or more. At least part may include some or all.

[0042] With the rapid development of near-eye display technologies such as virtual reality (VR) and augmented reality (AR), the pixel density (PPI) of display panels needs to reach ultra-high levels of 1200 to 4000 to achieve an immersive visual experience. This places extremely high miniaturization requirements on thin-film transistor (TFT) devices in backplane technology. Traditional oxide TFTs are considered one of the candidate technologies for high-resolution displays due to their moderate mobility and good uniformity. However, within the extremely limited pixel space constrained by ultra-high PPI, how to reduce device size, maintain sufficient driving capability, and integrate the necessary storage capacitors has become the core challenge facing current backplane technology.

[0043] In current mainstream oxide TFT backplane technology, a conductor-enhancing process is typically used to dope the source / drain (S / D) regions of the oxide active layer to form ohmic contacts. Subsequently, vias are formed through interlayer dielectric (ILD) etching, and metal is deposited to connect the S / D electrodes to the signal traces. While this process is mature, it typically involves the following steps: first, forming oxide channels; then, ion implantation or plasma treatment of the S / D regions to achieve conductor enhancement; and finally, electrode extraction and capacitor construction using multilayer photomasks.

[0044] The aforementioned existing technologies exhibit significant problems when applied to ultra-high PPI applications: First, the conductor fabrication process in the oxide S / D region is difficult to precisely control carrier concentration and diffusion depth, easily leading to channel characteristic degradation and performance dispersion. Second, the ILD vias etched to lead out the S / D metal traces occupy the already limited pixel area, further compressing the layout space available for storage capacitors (Cst). Third, the channel length of oxide TFTs in traditional structures is limited by the conductor fabrication process and contact resistance, making it difficult to scale down proportionally, resulting in a large device size that cannot meet the fundamental requirement of ultra-high PPI for pixel circuit miniaturization. Therefore, a novel device structure is urgently needed that avoids the conductor fabrication process, shortens the channel length, and efficiently integrates capacitors.

[0045] To address the aforementioned technical problems, this application provides an array substrate, its fabrication method, and a display panel. The following description, in conjunction with the accompanying drawings, will illustrate various embodiments of the array substrate, its fabrication method, and the display panel.

[0046] Please refer to the following: Figure 1 and Figure 2 , Figure 1 This is a partial cross-sectional view of an array substrate provided in an embodiment of this application; Figure 2 yes Figure 1 The equivalent circuit diagram.

[0047] like Figure 1 and Figure 2As shown, a first aspect embodiment of this application provides an array substrate 10, which includes: a substrate 100; a first conductive layer 200 disposed on one side of the substrate 100, the first conductive layer 200 including a first electrode portion 210 and a second electrode portion 220 disposed at intervals along a direction parallel to the substrate (hereinafter, the first direction X is explained as the direction parallel to the substrate); and a first active layer 300 disposed on one side of the substrate 100 and including a first channel portion 310 at least partially located between the first electrode portion 210 and the second electrode portion 220. One side of the first channel portion 310 is in contact with the first electrode portion 210, and the other side of the first channel portion 310 is in contact with the second electrode portion 220. The second conductive layer 400 is disposed on the side of the first active layer 300 facing or away from the substrate 100. The second conductive layer 400 includes a first gate 410. The orthogonal projection of the first gate 410 on the substrate 100 covers the orthogonal projection of the first channel portion 310 on the substrate 100. The first electrode portion 210, the second electrode portion 220, the first channel portion 310 and the first gate 410 constitute the first transistor T1.

[0048] According to an embodiment of this application, the array substrate 10 includes a substrate 100, a first active layer 300, and a second conductive layer 400. The first conductive layer 200 includes a first electrode portion 210 and a second electrode portion 220, which are in contact with the first channel portion 310 on both sides of the first channel portion 310. The second conductive layer 400 includes a first gate 410, the orthographic projection of the first gate 410 onto the substrate 100 and the orthographic projection of the first channel portion 310 onto the substrate 100 overlap, such that the first gate 410 serves as the gate of the first channel portion 310, controlling the electrical conduction of the first channel portion 310. The first electrode portion 210 and the second electrode portion 220 of the conductive material are in direct contact with the first channel portion 310, serving as the source and drain regions of the first transistor T1. The first electrode portion 210 and the second electrode portion 220 of the conductive material do not need to be conductive, simplifying the fabrication process. Furthermore, there is no need to hollow out the source and drain wiring, saving the hole area for the source and drain wiring. It is also easier to design a first channel portion 310 with a shorter channel length, reducing the device area of ​​the transistor and facilitating the achievement of high PPI (Pixels Per Inch), thereby improving the performance of the display product.

[0049] In some alternative embodiments, the material of the first channel portion 310 includes oxide, the material of the first electrode portion 210 is different from that of the first channel portion 310, and the material of the second electrode portion 220 is different from that of the first channel portion 310.

[0050] In these alternative embodiments, the material of the first channel portion 310 includes oxide, and the materials of the first electrode portion 210 and the first channel portion 310 are different, as are the materials of the second electrode portion 220 and the first channel portion 310. The first electrode portion 210 and the second electrode portion 220 are made of highly conductive metal materials and directly contact the channel of the oxide first channel portion 310. This eliminates the complex steps of conducting oxide in conventional processes, while reducing carrier diffusion phenomena that may occur during the conducting process, thus improving the stability and uniformity of the device. The first electrode portion 210 and the second electrode portion 220 of the conductive material are in direct contact with the first channel portion 310, serving as the source and drain regions of the first transistor T1. The first electrode portion 210 and the second electrode portion 220 of the conductive material do not need to be conductive, simplifying the fabrication process. Furthermore, there is no need to hollow out the source and drain wiring, saving the hole area for the source and drain wiring. It is also easier to design a first channel portion 310 with a shorter channel length, reducing the device area of ​​the oxide transistor and facilitating the achievement of high PPI (Pixels Per Inch), thereby improving the performance of the display product.

[0051] Optionally, the materials of the first electrode portion 210 and the second electrode portion 220 include at least one of metal oxides, metals, and metal nitrides. For example, ITO, IZO, Ti, W, Cu, TiN, TaN, etc.

[0052] In some optional embodiments, in the first direction X, the length D0 of the portion of the first channel portion 310 located between the first electrode portion 210 and the second electrode portion 220 is 0.05 μm to 2 μm. For example, the length of the first channel portion 310 is 0.05 μm, 0.5 μm, 1 μm, 2 μm, etc. The portion of the first channel portion 310 located between the first electrode portion 210 and the second electrode portion 220 refers to the portion where the orthographic projection of the first channel portion 310 on the substrate 100 lies between the orthographic projections of the first electrode portion 210 and the second electrode portion 220 on the substrate 100, and the orthographic projection of this portion on the substrate 100 does not overlap with the orthographic projections of the first electrode portion 210 and the second electrode portion 220 on the substrate 100.

[0053] In these optional embodiments, the length of the first channel portion 310 is greater than or equal to 0.05 μm, which can improve the problems caused by the increased resistance and decreased current of the first transistor T1 due to the excessively small width of the first channel portion 310, resulting in insufficient brightness, grayscale distortion, and decreased charging rate. The length of the first channel portion 310 is less than or equal to 2 μm, which can improve the problem of the increased device area of ​​the first transistor T1 due to the excessively large width of the first channel, making it difficult to adapt to high PPI application scenarios.

[0054] Optionally, in the first direction X, the length D0 of the portion of the first channel portion 310 located between the first electrode portion 210 and the second electrode portion 220 is 0.1 μm to 1 μm.

[0055] In some alternative embodiments, the first channel portion 310 is located on the side of the first conductive layer 200 facing or away from the substrate 100.

[0056] Please see Figure 3a and Figure 3b , Figure 3a This is a partial cross-sectional view of the display panel in another embodiment; Figure 3b This is a partial cross-sectional view of the display panel in another embodiment.

[0057] like Figure 3a and 3b As shown, optionally, the first electrode portion 210 and / or the second electrode portion 220 cover a portion of the first channel portion 310 that faces away from the surface of the substrate 100. When the first active layer 300 is prepared first and the first conductive layer 200 is prepared later, the first electrode portion 210 and / or the second electrode portion 220 of the first conductive layer 200 cover a portion of the first channel portion 310 that faces away from the surface of the substrate 100.

[0058] Optionally, the first channel portion 310 covers the surface of the first electrode portion 210 that is away from the substrate 100, and / or the first channel portion 310 covers the surface of the second electrode portion 220 that is away from the substrate 100.

[0059] In these optional embodiments, when the first channel portion 310 is located on the side of the first conductive layer 200 facing the substrate 100, the first channel portion 310 can be partially covered by the first electrode portion 210 or the second electrode portion 220 to strengthen the ohmic contact between the first channel portion 310 and the first electrode portion 210 and the second electrode portion 220. When the first channel portion 310 is located on the side of the first conductive layer 200 away from the substrate 100, the first channel portion 310 can partially cover the surface of the first electrode portion 210 or the surface of the second electrode portion 220 to strengthen the ohmic contact between the first channel portion 310 and the first electrode portion 210 and the second electrode portion 220. This helps to reduce contact resistance, improve carrier injection efficiency, and enhance the current drive capability of the device. When the first conductive layer 200 is prepared first and the first active layer 300 is prepared later, the first channel portion 310 of the first active layer 300 covers the portion of the first electrode portion 210 that is away from the surface of the substrate 100, and / or, the first channel portion 310 covers the portion of the second electrode portion 220 that is away from the surface of the substrate 100.

[0060] Please see Figure 4 and Figure 5 , Figure 4 This is a partial cross-sectional view of the display panel in yet another embodiment; Figure 5 This is a partial cross-sectional view of the display panel in another embodiment.

[0061] like Figure 4 and Figure 5 As shown, in some optional embodiments, it further includes: a third conductive layer 500 located between the substrate 100 and the first conductive layer 200, the third conductive layer 500 including a first conductive portion 510, the orthographic projection of the first conductive portion 510 on the substrate 100 and the orthographic projection of the first channel portion 310 on the substrate 100 at least partially overlap.

[0062] In these alternative embodiments, a first conductive portion 510 is provided below the first channel portion 310. The first conductive portion 510 can serve as a shielding layer for the first channel portion 310 to block reflected light from the substrate 100 side, reduce the impact of reflected light on the first channel portion 310, and the first conductive portion 510 can also absorb hydrogen, thereby improving the device reliability of the first transistor T1.

[0063] Optionally, the third conductive layer 500 is reused as the second conductive layer 400, and the first conductive portion 510 is reused as the first gate 410; or, the second conductive layer 400 is located on the side of the first active layer 300 away from the substrate 100.

[0064] Optionally, the portion of the first channel portion 310 located between the first electrode portion 210 and the second electrode portion 220 has its orthogonal projection onto the substrate 100 within the orthogonal projection of the first conductive portion 510 onto the substrate 100. This increases the shielding area of ​​the first conductive portion 510, improves its light-blocking and hydrogen-absorbing capabilities, and enhances device reliability. When the first conductive portion 510 is reused as the first gate 410, the first gate 410 can completely cover and effectively control the entire channel region, avoiding edge leakage and improving the device's subthreshold swing and switching characteristics.

[0065] Optionally, the material of the third conductive layer 500 may include titanium. Titanium metal has good hydrogen absorption properties and can absorb hydrogen atoms introduced during the process, preventing hydrogen atoms from having an adverse effect on the oxide semiconductor layer, thereby significantly improving the threshold voltage stability and long-term reliability of the oxide TFT.

[0066] Please see Figure 6 and Figure 7 , Figure 6 This is a partial cross-sectional view of the display panel in another embodiment; Figure 7 yes Figure 6 The equivalent circuit diagram.

[0067] like Figure 6 and Figure 7As shown, in some optional embodiments, the third conductive layer 500 further includes a first electrode plate 520 spaced apart from the first conductive portion 510. The orthographic projection of the first electrode plate 520 on the substrate 100 overlaps with the orthographic projection of the first electrode portion 210 or the second electrode portion 220 on the substrate 100, and the first electrode plate 520 and the first electrode portion 210 or the second electrode portion 220 form a first capacitor C1.

[0068] In these alternative embodiments, the first electrode plate 520 and the first electrode portion 210 or the second electrode portion 220 overlap by projection to form a first capacitor C1. This design utilizes the existing conductive layer to form the storage capacitor, without requiring additional pixel area, simplifying the process flow, greatly saving layout space, and facilitating the realization of high PPI displays.

[0069] Optionally, the array substrate 10 further includes a first insulating layer 230, which is located between the third conductive layer 500 and the first conductive layer 200. The dielectric constant of the first insulating layer 230 is greater than or equal to 7. Using a high dielectric constant material as a gate insulating layer can generate a stronger gate electric field at the same physical thickness, enhancing the gate's control over the channel charge, reducing the subthreshold swing of the first transistor T1, and improving the device reliability of the first transistor T1. Optionally, the first transistor T1 is a driving transistor. Optionally, the material of the first insulating layer 230 includes at least one of HfO2, ZrO2, TiO2, and Ta2O5. The first insulating layer 230 is prepared using an atomic layer deposition (ALD) process.

[0070] Please see Figure 8 and Figure 9 , Figure 8 This is a partial cross-sectional view of the display panel in another embodiment; Figure 9 This is a partial cross-sectional view of the display panel in another embodiment.

[0071] like Figure 8 and Figure 9 As shown, in some optional embodiments, it further includes: a fourth conductive layer 600 located on the side of the first active layer 300 away from the substrate 100, the fourth conductive layer 600 including a second conductive portion 610, the orthographic projection of the first channel portion 310 on the substrate 100 and the orthographic projection of the second conductive portion 610 on the substrate 100 at least partially overlap.

[0072] In these alternative embodiments, the orthographic projection of the first channel portion 310 onto the substrate 100 and the orthographic projection of the second conductive portion 610 onto the substrate 100 at least partially overlap. The second conductive portion 610 can serve as a top gate electrode to achieve effective channel control, or it can serve as an independent conductive layer for wiring or building capacitors, thereby enhancing the flexibility and functionality of device design.

[0073] Optionally, the fourth conductive layer 600 is reused as the second conductive layer 400, and the second conductive portion 610 is reused as the first gate 410; or, the second conductive layer 400 is located on the side of the first active layer 300 facing the substrate.

[0074] Optionally, the portion of the first channel portion 310 located between the first electrode portion 210 and the second electrode portion 220 has its orthographic projection on the substrate 100 within the orthographic projection of the second conductive portion 610 on the substrate 100. When the second conductive portion 610 is multiplexed as the first gate 410, the first gate 410 can completely cover and effectively control the entire channel region, avoiding edge leakage and improving the subthreshold swing and switching characteristics of the device.

[0075] In some alternative embodiments, the orthographic projection of the first electrode portion 210 onto the substrate 100 and the orthographic projection of the second conductive portion 610 onto the substrate 100 at least partially overlap.

[0076] In these alternative embodiments, during the annealing process of the device, the second conductive part 610 can isolate the external environment to a certain extent, reduce the direct impact of water and oxygen on the lower first electrode part 210 and the first channel part 310, improve the device reliability of the first electrode part 210 and the first channel part 310, and ensure that there is a good ohmic contact between the first electrode part 210 and the first channel part 310.

[0077] In some alternative embodiments, the orthographic projection of the second electrode portion 220 onto the substrate 100 and the orthographic projection of the second conductive portion 610 onto the substrate 100 at least partially overlap.

[0078] In these alternative embodiments, during the annealing process of the device, the second conductive part 610 can isolate the external environment to a certain extent, reduce the direct impact of water and oxygen on the lower second electrode part 220 and the first channel part 310, improve the device reliability of the second electrode part 220 and the first channel part 310, and ensure good ohmic contact between the second electrode part 220 and the first channel part 310.

[0079] Please see Figure 10 and Figure 11 , Figure 10 This is a partial cross-sectional view of the display panel in another embodiment; Figure 11 yes Figure 10 The equivalent circuit diagram.

[0080] like Figure 10 and Figure 11As shown, in some optional embodiments, the fourth conductive layer 600 further includes a second electrode plate 620 disposed at a distance from the second conductive portion 610. The orthographic projection of the second electrode plate 620 on the substrate 100 overlaps with the orthographic projection of the first electrode portion 210 or the second electrode portion 220 on the substrate 100, and the second electrode plate 620 and the first electrode portion 210 or the second electrode portion 220 form a second capacitor C2.

[0081] In these alternative embodiments, the second electrode plate 620 and the first electrode portion 210 or the second electrode portion 220 overlap by projection to form a second capacitor C2, which further increases the way of integrating storage capacitors in each pixel. With the cooperation of multiple metal layers, a larger capacitance value can be achieved in a limited space to meet the charge storage requirements of high refresh rate displays.

[0082] Optionally, the array substrate 10 further includes a second insulating layer 420, located between the first conductive layer 200 and the fourth conductive layer 600. The first insulating layer 230 includes a first sub-layer 421 and a second sub-layer 422, with the second sub-layer 422 located on the side of the first sub-layer 421 facing away from the substrate 100. The first sub-layer 421 and the second sub-layer 422 are made of different materials. Optionally, the first sub-layer 421 and the second sub-layer 422 include at least one of SiOx and SiNx. Optionally, the material of the first sub-layer 421 includes SiOx. The SiOx first sub-layer 421 is in direct contact with the first channel portion 310, and its excellent interface compatibility enables the formation of a contact interface with low defect density, effectively suppressing charge traps, thereby significantly improving the subthreshold swing and threshold voltage stability of the first transistor T1. Optionally, the material of the second sub-layer 422 includes SiNx. The second sub-layer 422 of SiNx has a higher dielectric constant. The higher dielectric constant enhances the gate capacitance per unit area, enabling the first gate 410 to achieve more effective electric field control of the first channel portion 310 with a lower voltage, thereby improving the driving capability and switching speed of the device.

[0083] Please see Figures 12 to 17 , Figure 12 This is a partial cross-sectional view of the display panel in another embodiment; Figure 13 yes Figure 12 The equivalent circuit diagram; Figure 14 This is a partial cross-sectional view of the display panel in another embodiment; Figure 15 yes Figure 14 The equivalent circuit diagram; Figure 16 This is a partial cross-sectional view of the display panel in another embodiment; Figure 17 yes Figure 16 The equivalent circuit diagram.

[0084] like Figures 12 to 17As shown, in some optional embodiments, it further includes: a second transistor T2, located on one side of the substrate 100, the second transistor T2 including a third electrode portion 710, a fourth electrode portion 720, a second channel portion 810 and a second gate 910, the third electrode portion 710 and the fourth electrode portion 720 being spaced apart, at least a portion of the second channel portion 810 being located between the third electrode portion 710 and the fourth electrode portion 720, and the second channel portion 810 being in contact with the third electrode portion 710 and the fourth electrode portion 720, the second gate 910... The orthographic projection of the substrate 100 and the orthographic projection of the second channel portion 810 on the substrate 100 at least partially overlap; wherein, one of the third electrode portion 710 and the fourth electrode portion 720 includes a first electrode region Q1, one of the first electrode portion 210 and the second electrode portion 220 and the first gate 410 includes a second electrode region Q2, the orthographic projection of the first electrode region Q1 on the substrate 100 and the orthographic projection of the second electrode region Q2 on the substrate 100 overlap, and the first electrode region Q1 and the second electrode region Q2 form a third capacitor C3.

[0085] In these alternative embodiments, the second plate region Q2 of the first transistor T1 forms a third capacitor C3 with the first plate region Q1 of the second transistor T2. This design utilizes existing film and electrode structures without introducing any additional dedicated capacitor electrode layers, significantly reducing the total number of film layers, reducing device thickness and process complexity, while ensuring tight integration and excellent electrical matching between the capacitor and the transistor.

[0086] In some optional embodiments, one of the first electrode portion 210 and the second electrode portion 220 includes a second electrode plate region Q2, and the first electrode plate region Q1 and the first gate 410 are on the same layer.

[0087] In these alternative embodiments, the first electrode region Q1 and the first gate 410 are on the same layer, and the third electrode portion 710 or the fourth electrode portion 720 of the first electrode region Q1 can be fabricated simultaneously with the first gate 410. This utilizes the existing film layer structure, eliminates the need to introduce any additional conductive layer, significantly reduces the total number of film layers, reduces device thickness and process complexity, and ensures tight integration between transistors.

[0088] Optionally, the first electrode region Q1 and the first gate 410 are spaced apart.

[0089] Optionally, the first electrode region Q1 and the first gate 410 are electrically connected, so that the first electrode region Q1 and the first gate 410 are at the same potential, which simplifies the wiring design of the pixel circuit, reduces the number of signal lines, and improves the stability of the device.

[0090] Optionally, the first electrode region Q1 and the first gate 410 are integrally disposed, so that the first electrode region Q1 and the first gate 410 are at the same potential, which simplifies the wiring design of the pixel circuit, reduces the number of signal lines, and improves the stability of the device.

[0091] In some alternative embodiments, the orthographic projection of the first channel portion 310 onto the substrate 100 and the orthographic projection of the first electrode region Q1 onto the substrate 100 at least partially overlap.

[0092] In these alternative embodiments, the first electrode region Q1 extends above the first channel portion 310 to serve as the gate of the first channel portion 310, which simplifies the wiring design of the pixel circuit, reduces the number of signal lines, and improves device stability.

[0093] In some alternative embodiments, the first gate 410 includes a second electrode region Q2, the first gate 410 is located on the side of the first electrode portion 210 and the first channel portion 310 away from the substrate 100, and the third electrode portion 710 and the fourth electrode portion 720 are located on the side of the first gate 410 away from the substrate 100.

[0094] In these alternative embodiments, the first gate 410 overlaps with the third electrode portion 710 or the fourth electrode portion 720 to form a capacitor.

[0095] Optionally, the first electrode region Q1 is electrically connected to the first electrode portion 210 or the second electrode portion 220, allowing the formed capacitor to be directly connected in parallel or series with the first transistor T1 and the second transistor T2. This facilitates charge storage, signal holding, or reset operations in the pixel circuit, improving the integrity and reliability of the circuit function. Optionally, the first electrode region Q1 is electrically connected to the first electrode portion 210 or the second electrode portion 220 via a via.

[0096] Optionally, it further includes: a fifth conductive layer 700 disposed on the side of the first active layer 300 away from the substrate 100, the fifth conductive layer 700 including a third electrode portion 710 and a fourth electrode portion 720; a second active layer 800 disposed on the side of the first active layer 300 away from the substrate 100 and including a second channel portion 810; and a sixth conductive layer 900 disposed on the side of the second active layer 800 facing or away from the substrate 100, the sixth conductive layer 900 including a second gate 910.

[0097] Optionally, the second conductive layer 400 is located on the side of the first active layer 300 facing away from the substrate 100, and the fifth conductive layer 700 is located on the side of the second conductive layer 400 facing away from the substrate 100. The array substrate 10 further includes a third insulating layer 730, which is located between the second conductive layer 400 and the fifth conductive layer 700. The dielectric constant of the third insulating layer 730 is greater than or equal to 7. The first electrode region Q1 is electrically connected to the first electrode portion 210 or the second electrode portion 220, and the first gate 410 includes the second electrode region Q2. The third insulating layer 730 is made of a high dielectric constant material, which can enhance the capacitance value of the third capacitor C3. Optionally, the material of the third insulating layer 730 includes at least one of HfO2, ZrO2, TiO2, and Ta2O5. The third insulating layer 730 is prepared using an atomic layer deposition (ALD) process.

[0098] Please see Figure 18 See also Figures 1 to 17 , Figure 18 This is a flowchart illustrating the fabrication process of an array substrate provided in an embodiment of this application.

[0099] like Figures 1 to 18 As shown, an embodiment of the third aspect of this application provides a method for fabricating an array substrate 10, comprising: Step S01: Provide a substrate 100; Step S02: A first conductive layer 200 is prepared on one side of the substrate 100. The first conductive layer 200 includes a first electrode portion 210 and a second electrode portion 220 disposed at intervals along a direction parallel to the substrate 100. Step S03: A first active layer 300 is formed on one side of the substrate 100. The first active layer 300 includes a first channel portion 310 located at least partially between the first electrode portion 210 and the second electrode portion 220. One side of the first channel portion 310 is in contact with the first electrode portion 210, and the other side of the first channel portion is in contact with the second electrode portion 220. Step S04: A second conductive layer 400 is prepared on the side of the first active layer 300 facing or away from the substrate 100. The second conductive layer 400 includes a first gate 410. The orthogonal projection of the first gate 410 onto the substrate 100 covers the orthogonal projection of the first channel portion 310 onto the substrate 100. The first electrode portion 210, the second electrode portion 220, the first channel portion 310 and the first gate 410 constitute the first transistor T1.

[0100] According to the fabrication method of the array substrate 10 of this application embodiment, a first conductive layer 200 is fabricated in step S02. A first active layer 300 is fabricated in step S03. A second conductive layer 400 is fabricated in step S04. The first conductive layer 200 includes a first electrode portion 210 and a second electrode portion 220, which are in contact with the first channel portion 310 on both sides of the first channel portion 310. The second conductive layer 400 includes a first gate 410, the orthographic projection of the first gate 410 on the substrate 100 and the orthographic projection of the first channel portion 310 on the substrate 100 overlap, such that the first gate 410 serves as the gate of the first channel portion 310, controlling the electrical conduction of the first channel portion 310. The first electrode portion 210 and the second electrode portion 220 of the conductive material are in direct contact with the first channel portion 310, serving as the source and drain regions of the first transistor T1. The first electrode portion 210 and the second electrode portion 220 of the conductive material do not need to be conductive, simplifying the fabrication process. Furthermore, there is no need to hollow out the source and drain wiring, saving the hole area for the source and drain wiring. It is also easier to design a first channel portion 310 with a shorter channel length, reducing the device area of ​​the transistor and facilitating the achievement of high PPI (Pixels Per Inch), thereby improving the performance of the display product.

[0101] In some possible implementations, this application also provides a display panel, which includes the array substrate 10 described in this application. The display panel may include devices with image processing capabilities, such as mobile phones, desktop computers, laptops, tablets, automotive displays, wearable devices, etc. Because this display panel includes the array substrate 10 described in this application, its reliability is higher.

[0102] The display panel may also include at least one film layer such as a light-emitting layer, an encapsulation layer, a touch layer, a polarizer, a color filter substrate, and a protective cover. These film layers may also be bonded to the display panel via adhesive layers such as OCA (Optical Clear Adhesive).

[0103] Optionally, the pixel driving circuit includes a driving transistor and a data transistor. The source of the data transistor is connected to a data line providing the data signal "Data", the gate of the data transistor is connected to a scan line providing the scan signal "Scan", and the drain of the data transistor is connected to the gate of the driving transistor. The two ends of the storage capacitor are respectively connected to the gate and source of the driving transistor, and the drain of the driving transistor is connected to the light-emitting device. The pixel driving circuit of this application is not limited to the 2T1C pixel driving circuit, but can also be other pixel driving circuits, such as 7T1C, 8T1C pixel driving circuits, etc. Optionally, the first transistor T1 and the second transistor T2 in the embodiments of this application can be either driving transistors or data transistors.

[0104] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0105] The embodiments described above are merely illustrative of several implementations of the present invention, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these all fall within the protection scope of the present invention. Therefore, the protection scope of this invention patent should be determined by the appended claims.

[0106] Although this application has been described with reference to preferred embodiments, various modifications can be made thereto and components can be replaced with equivalents without departing from the scope of this application. In particular, the technical features mentioned in the various embodiments can be combined in any manner, provided there is no structural conflict. This application is not limited to the specific embodiments disclosed herein, but includes all technical solutions falling within the scope of the claims.

Claims

1. An array substrate, characterized in that, The array substrate includes: Substrate; A first conductive layer is disposed on one side of the substrate, and the first conductive layer includes a first electrode portion and a second electrode portion disposed at intervals along a direction parallel to the substrate. A first active layer is disposed on one side of the substrate and includes a first channel portion located at least partially between the first electrode portion and the second electrode portion. One side of the first channel portion is in contact with the first electrode portion, and the other side of the first channel portion is in contact with the second electrode portion. A second conductive layer is disposed on the side of the first active layer facing or away from the substrate. The second conductive layer includes a first gate, the orthogonal projection of the first gate onto the substrate covers the orthogonal projection of the first channel portion onto the substrate, and the first electrode portion, the second electrode portion, the first channel portion and the first gate constitute a first transistor.

2. The array substrate according to claim 1, characterized in that, The material of the first channel portion includes oxide; the materials of the first electrode portion and the first channel portion are different; the materials of the second electrode portion and the first channel portion are different. Preferably, the materials of the first electrode portion and the second electrode portion include at least one of metal oxide, metal, and metal nitride; Preferably, in the direction parallel to the substrate, the length of the portion of the first channel located between the first electrode portion and the second electrode portion is 0.05 μm to 2 μm; Preferably, in the direction parallel to the substrate, the length of the portion of the first channel located between the first electrode portion and the second electrode portion is 0.1 μm to 1 μm; Preferably, the first electrode portion and / or the second electrode portion cover a portion of the surface of the first channel portion that faces away from the substrate; Preferably, the first channel portion covers the surface of the first electrode portion that is away from the substrate, and / or, the first channel portion covers the surface of the second electrode portion that is away from the substrate.

3. The array substrate according to claim 1, characterized in that, Also includes: A third conductive layer is located between the substrate and the first conductive layer. The third conductive layer includes a first conductive portion, and the orthographic projection of the first conductive portion on the substrate and the orthographic projection of the first channel portion on the substrate at least partially overlap. Preferably, the third conductive layer is reused as the second conductive layer, and the first conductive portion is reused as the first gate. Alternatively, the second conductive layer is located on the side of the first active layer that is away from the substrate; Preferably, the portion of the first channel portion located between the first electrode portion and the second electrode portion has its orthographic projection on the substrate within the orthographic projection of the first conductive portion on the substrate. Preferably, the material of the third conductive layer includes titanium; Preferably, the third conductive layer further includes a first electrode plate spaced apart from the first conductive portion, wherein the orthographic projection of the first electrode plate on the substrate overlaps with the orthographic projection of the first electrode portion or the second electrode portion on the substrate, and the first electrode plate and the first electrode portion or the second electrode portion form a first capacitor.

4. The array substrate according to claim 1, characterized in that, Also includes: A fourth conductive layer is located on the side of the first active layer away from the substrate. The fourth conductive layer includes a second conductive portion, and the orthographic projection of the first channel portion on the substrate and the orthographic projection of the second conductive portion on the substrate at least partially overlap. Preferably, the fourth conductive layer is reused as the second conductive layer, and the second conductive portion is reused as the first gate. Alternatively, the second conductive layer is located on the side of the first active layer facing the substrate; Preferably, the portion of the first channel portion located between the first electrode portion and the second electrode portion has its orthographic projection on the substrate within the orthographic projection of the second conductive portion on the substrate. Preferably, the orthographic projection of the first electrode portion onto the substrate and the orthographic projection of the second conductive portion onto the substrate at least partially overlap; Preferably, the orthographic projection of the second electrode portion onto the substrate and the orthographic projection of the second conductive portion onto the substrate at least partially overlap; Preferably, the fourth conductive layer further includes a second electrode plate disposed at a distance from the second conductive portion, wherein the orthographic projection of the second electrode plate on the substrate overlaps with the orthographic projection of the first electrode portion or the second electrode portion on the substrate, and the second electrode plate and the first electrode portion or the second electrode portion form a second capacitor.

5. The array substrate according to claim 1, characterized in that, Also includes: A second transistor is located on one side of the substrate. The second transistor includes a third electrode portion, a fourth electrode portion, a second channel portion, and a second gate. The third electrode portion and the fourth electrode portion are spaced apart. At least a portion of the second channel portion is located between the third electrode portion and the fourth electrode portion. One side of the second channel portion is in contact with the third electrode portion, and the other side of the second channel portion is in contact with the fourth electrode portion. The orthographic projection of the second gate portion on the substrate and the orthographic projection of the second channel portion on the substrate at least partially overlap. Wherein, one of the third electrode portion and the fourth electrode portion includes a first electrode plate region, one of the first electrode portion and the second electrode portion and the first gate includes a second electrode plate region, the orthographic projection of the first electrode plate region on the substrate and the orthographic projection of the second electrode plate region on the substrate overlap, and the first electrode plate region and the second electrode plate region form a third capacitor.

6. The array substrate according to claim 5, characterized in that, One of the first electrode portion and the second electrode portion includes the second electrode plate region, and the first electrode plate region and the first gate are on the same layer; Preferably, the first electrode region and the first gate are spaced apart; Preferably, the first electrode region and the first gate are electrically connected; Preferably, the first electrode plate region and the first gate are integrally formed; Preferably, the orthographic projection of the first channel portion onto the substrate and the orthographic projection of the first electrode region onto the substrate at least partially overlap.

7. The array substrate according to claim 5, characterized in that, The first gate includes the second electrode region, the first gate is located on the side of the first electrode portion and the first channel portion away from the substrate, and the third electrode portion and the fourth electrode portion are located on the side of the first gate away from the substrate; Preferably, the first electrode plate region is electrically connected to the first electrode portion or the second electrode portion.

8. The array substrate according to claim 5, characterized in that, Also includes: A fifth conductive layer is disposed on the side of the first active layer away from the substrate, and the fifth conductive layer includes the third electrode portion and the fourth electrode portion; The second active layer is disposed on the side of the first active layer away from the substrate and includes the second channel portion; A sixth conductive layer is disposed on the side of the second active layer facing or away from the substrate, and the sixth conductive layer includes the second gate.

9. A display panel, characterized in that, Includes the array substrate as described in any one of claims 1-8.

10. A method for preparing an array of electrode plates, characterized in that, include: Provide a substrate; A first conductive layer is formed on one side of the substrate, the first conductive layer including a first electrode portion and a second electrode portion disposed at intervals along a direction parallel to the substrate; A first active layer is formed on one side of the substrate. The first active layer includes a first channel portion located at least partially between the first electrode portion and the second electrode portion. One side of the first channel portion is in contact with the first electrode portion, and the other side of the first channel portion is in contact with the second electrode portion. A second conductive layer is formed on the side of the first active layer facing or away from the substrate. The second conductive layer includes a first gate. The orthogonal projection of the first gate onto the substrate covers the orthogonal projection of the first channel portion onto the substrate. The first electrode portion, the second electrode portion, the first channel portion, and the first gate constitute a first transistor.

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