Hybrid channel power semiconductor device and manufacturing method thereof

Abstract

A semiconductor device is provided. The semiconductor device may include a silicon carbide substrate, a silicon layer formed on a first side of the silicon carbide substrate, a gate oxide layer formed on the silicon layer, a gate terminal formed on the gate oxide layer, a drain terminal formed on a second side of the silicon carbide substrate opposite the first side, and source terminals formed on a first side of the silicon carbide substrate and at opposite ends of the silicon layer.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to U.S. Nonprovisional Patent Application No. 18 / 891,966, filed September 20, 2024, and U.S. Provisional Patent Application No. 63 / 539,743, filed September 21, 2023, the contents of which are incorporated herein by reference in their entirety. Technical Field

[0003] This disclosure relates generally to power semiconductor devices, and more specifically to power semiconductor devices having a mixed channel comprising silicon carbide and silicon. Summary of the Invention

[0004] According to one aspect of one or more examples, a semiconductor device is provided, the semiconductor device comprising a silicon carbide substrate, a silicon layer formed on a first side of the silicon carbide substrate, a gate oxide layer formed on the silicon layer, a gate terminal formed on the gate oxide layer, a drain terminal formed on a second side of the silicon carbide substrate opposite to the first side, and source terminals formed on the first side of the silicon carbide substrate and located at opposite ends of the silicon layer. The silicon carbide substrate may be made of n-type silicon carbide. The source terminals may be made of n-type silicon. The doping concentration of the n-type silicon in the source terminals may be higher than the doping concentration of the n-type silicon in the silicon carbide substrate. The source terminals may at least partially overlap with the gate terminal. The thickness of the gate oxide layer may be less than the thickness of the silicon layer. The drain terminals may be made of n-type silicon carbide. The doping concentration of the n-type silicon in the drain terminals may be higher than the doping concentration of the n-type silicon in the silicon carbide substrate. The semiconductor device may further include a first p-well region and a second p-well region, as well as a first P+ region and a second P+ region. The first p-well region and the second p-well region are disposed in the silicon carbide substrate and located at opposite ends of the silicon layer. The first P+ region and the second P+ region are respectively located within the first p-well region and the second p-well region. The source terminal may be formed within the first p-well region and the second p-well region. The first p-well region and the second p-well region may be made of p-type silicon carbide. The first P+ region and the second P+ region may be made of p-type silicon. The semiconductor device may further include a polysilicon layer on the gate oxide layer. The gate terminal may be formed on the polysilicon layer.

[0005] According to one aspect of one or more examples, a method of manufacturing a semiconductor device is provided. The method may include: forming a first N+ region for a drain terminal of the semiconductor device on one side of a silicon carbide substrate; forming a silicon layer on an opposite side of the silicon carbide substrate opposite to the side where the first N+ region is formed; forming a gate oxide layer on the silicon layer; forming a gate terminal on the gate oxide layer; and forming a second N+ region and a third N+ region on opposite sides of the silicon layer to form a source terminal. The method may further include forming a first p-well region and a second p-well region in the silicon carbide substrate and at opposite ends of the silicon layer, and forming a first P+ region and a second P+ region within the first p-well region and the second p-well region. The second N+ region and the third N+ region may be formed within the first p-well region and the second p-well region, respectively. The first p-well region and the second p-well region may be made of p-type silicon carbide, and the second N+ region and the third N+ region may be made of n-type silicon. The first N+ region may be made of n-type silicon carbide. The method may further include forming a polysilicon layer on the gate oxide layer. The gate terminal may be formed on the polysilicon layer. The second N+ region and the third N+ region may at least partially overlap with the gate oxide layer. A portion of the silicon carbide substrate may extend between the first p-well region and the second p-well region. Attached Figure Description

[0006] Figure 1 A semiconductor device based on one or more examples is shown.

[0007] Figures 2A to 2F Manufacturing is shown according to various examples. Figure 1 Methods for developing semiconductor devices. Detailed Implementation

[0008] Reference will now be made to the various examples shown in the accompanying drawings, in which the same reference numerals always denote the same elements. These examples may be presented in various forms, and are not limited to those described herein.

[0009] Figure 1 A semiconductor device 100 according to one or more examples is shown. Figure 1 The semiconductor device 100 shown may include a silicon carbide (SiC) substrate 110. Silicon carbide is commonly used as a substrate to create many semiconductor devices and, compared to other materials, can result in reduced switching losses, higher power density, improved heat dissipation, and increased bandwidth. Some semiconductor devices, such as metal-oxide-semiconductor field-effect transistors (MOSFETs), include a gate oxide layer, which is a dielectric layer separating the silicon carbide substrate from the gate electrode, which may be made of a metal or other conductive material.

[0010] When a gate oxide layer is formed on a silicon carbide substrate, the interface between the silicon carbide substrate and the gate oxide layer (e.g., a gate oxide layer made of silicon dioxide) can be very rough. This rough interface can reduce carrier mobility in the silicon carbide substrate, potentially limiting device performance. (Reference) Figure 1 A silicon (Si) layer 120 can be grown or deposited on the first side of the silicon carbide (SiC) substrate 110. For example, such as Figure 1 As shown, a silicon layer 120 is formed on the first side of the silicon carbide substrate 110. Figure 1 (as in the example on the top side). Depending on one or more examples, silicon layer 120 can be approximately 100 Å to 500 Å thick, although other thicknesses can be used depending on the application. For example, the amount of silicon used to create silicon layer 120 may depend on the thickness of the gate oxide layer 130 to be formed on silicon layer 120. Figure 1 As shown, a gate oxide layer 130 can be formed on the silicon layer 120. For example, the gate oxide layer 130 can be a silicon dioxide (SiO2) layer, which can be formed or grown by thermal oxidation of the silicon layer 120. A polysilicon layer 140 can be formed on the gate oxide layer 130, which will ultimately form the gate terminal of the semiconductor device 100. For example, the gate terminal can be formed of metal, polysilicon, or other suitable materials.

[0011] Figure 1 The semiconductor device may include two p-wells 150A and 150B, which are formed within the silicon carbide substrate 110 and located at opposite ends of the silicon layer 120, and on either side of the gate terminal. Figure 1 As shown, p-wells 150A and 150B may partially overlap below the gate terminals and may be made of p-type silicon carbide. Source terminals may be formed on a first side of the silicon carbide substrate 110 and located at opposite ends of the silicon layer 120. For example, as... Figure 1 As shown, the source terminal can be formed by forming two N+ regions 160A and 160B within corresponding p-wells 150A and 150B. For example, N+ region 160A can be formed within p-well 150A, and N+ region 160B can be formed within p-well 150B. These two N+ regions 160A and 160B can be made of n-type silicon, and the doping concentration of the n-type silicon can be higher than the doping concentration of the n-type silicon carbide substrate 110. The gate terminal and gate oxide layer 130 can extend to at least partially overlap with the two N+ regions 160A and 160B. Figure 1The illustrated semiconductor device 100 may further include a body terminal formed by two P+ regions 170A and 170B formed within respective p-wells 150A and 150B. For example, P+ region 170A may be formed within p-well 150A, and P+ region 170B may be formed within p-well 150B. Both P+ regions 170A and 170B may be formed of p-type silicon, and the doping concentration of these two P+ regions may be higher than the doping concentration of p-wells 150A and 150B. Both P+ regions 170A and 170B may be located near corresponding N+ regions 160A and 160B. For example, P+ region 170A is located near N+ region 160A, and P+ region 170B is located near N+ region 160B. The semiconductor device 100 may also include an N+ region 180, which will ultimately form the drain terminal of the semiconductor device 100. The drain terminal can be formed on the second side of the silicon carbide substrate 110 opposite to the first side. For example, as... Figure 1 As shown, the drain terminal is located on the bottom side of the silicon carbide substrate 110. The drain terminal may be composed of an N+ region 180, which may be made of n-type silicon carbide, and the doping concentration of the N+ region may be higher than the doping concentration of the n-type silicon carbide in the silicon carbide substrate 110.

[0012] During operation, when a positive voltage is applied to the gate terminal, an n-type channel is formed. This channel originates from the two N+ regions 160A and 160B constituting the source terminal, passes through the silicon layer 120 and the silicon carbide substrate 110, and extends to the drain terminal. The interface formed by the silicon layer 120 and the gate oxide layer 130 is smoother than the interface formed by the silicon carbide substrate 110 and the gate oxide layer 130, which can improve carrier mobility. This hybrid channel, comprising silicon and silicon carbide, can provide higher carrier mobility while retaining the potential advantages of the silicon carbide substrate 110, such as reduced switching losses, increased power density, improved heat dissipation, and increased bandwidth.

[0013] Figures 2A to 2F Manufacturing process is shown Figure 1 Method 200 for semiconductor device 100.

[0014] exist Figure 2A In this method 200, one can begin with a silicon carbide substrate 110, in... Figure 2A In the example shown, the silicon carbide substrate is made of n-type silicon carbide. A higher doping concentration n-type (N+) silicon-carbon region 180 may be formed on one side of the silicon carbide substrate 110, which will ultimately serve as the drain terminal of the semiconductor device 100.

[0015] Figure 2BThe diagram illustrates the operation of forming a silicon layer 120 on a silicon carbide substrate 110. The silicon layer 120 may be formed on a side of the silicon carbide substrate 110 opposite to the side where the N+ region 180 is formed. The silicon layer 120 may be implanted into the silicon carbide substrate 110. According to one or more examples, the silicon layer 120 may be formed by bonding a silicon wafer to the silicon carbide substrate 110.

[0016] Figure 2C The operation of forming two P-well regions 150A and 150B at two lateral ends of a silicon carbide substrate 110 is illustrated. The two P-well regions 150A and 150B can be made of p-type silicon carbide. Figure 2C As shown, two p-type (P+) regions 170A and 170B with higher doping concentrations can be implanted into corresponding P-wells 150A and 150B. For example, P+ region 170A can be implanted into P-well 150A, and P+ region 170B can be implanted into P-well 150B. According to one or more examples, P+ regions 170A and 170B can be made of p-type silicon. P+ regions 170A and 170B can ultimately form the body terminal of semiconductor device 100.

[0017] Figure 2D The illustration shows the operation of implanting highly doped n-type (N+) regions 160A and 160B into respective P-wells 150A and 150B according to one or more examples. For example, N+ region 160A may be implanted into P-well 150A, and N+ region 160B may be implanted into P-well 150B. N+ regions 160A and 160B may be made of n-type silicon and may ultimately form the source terminals of semiconductor device 100.

[0018] Figure 2E The operation of adding a gate oxide layer 130 and a polysilicon layer 140 according to one or more examples is illustrated. Figure 2E In this process, a gate oxide layer 130 may be formed on the silicon layer 120. According to one or more examples, the gate oxide layer 130 may extend across the width of the silicon carbide substrate 110. By forming the gate oxide layer 130 on the silicon layer 120, rather than on the silicon carbide substrate 110, carrier mobility can be improved, which can enhance the performance of the semiconductor device 100. Figure 2E As shown, a polysilicon layer 140 can be formed on the gate oxide layer 130, which will ultimately form the gate terminal of the semiconductor device 100. Although in Figure 2E The example shown uses polysilicon, but metals or other suitable materials can also be used to form the gate terminals.

[0019] Figure 2FThe illustration shows the operation of adding contacts to form terminals of a semiconductor device 100 according to one or more examples. For example, contact 210 may be added to polysilicon layer 140 to form a gate terminal, and contacts 220A and 220B may be added to N+ regions 160A and 160B and P+ regions 170A and 170B located on either side of the gate terminal to form source terminals. For example, contact 220A is added to N+ region 160A and P+ region 170A, and contact 220B is added to N+ region 160B and P+ region 170B. Figure 2F In the example, the body terminal can be coupled to the source terminal. A contact 230 can also be added to the N+ region 180 on the opposite side of the silicon carbide substrate 110 to form a drain terminal.

[0020] although Figures 2A to 2F The operations of method 200 shown are illustrated in a specific order, but these operations may be performed in a different order, and additional operations may be included, as those skilled in the art will understand.

[0021] Various examples have been disclosed herein in conjunction with the foregoing description and accompanying drawings. It should be understood that describing and illustrating each combination and sub-combination of these examples literally would be an undue repetition. Therefore, all examples can be combined in any manner and / or combination, and this specification (including the accompanying drawings) should be construed as constituting a complete written description of all combinations and sub-combinations of the examples described herein, as well as the manner and process of their preparation and use, and should support the claims for any such combinations or sub-combinations.

[0022] Those skilled in the art will understand that the examples described herein are not limited to those specifically shown and described above. Furthermore, unless the contrary is mentioned above, it should be noted that all figures are not drawn to scale. Various modifications and variations are possible in accordance with the above teachings.

Claims

1. A semiconductor device, the semiconductor device comprising: silicon carbide substrate; A silicon layer is formed on a first side of the silicon carbide substrate; A gate oxide layer, the gate oxide layer being formed on the silicon layer; A gate terminal, wherein the gate terminal is formed on the gate oxide layer; Drain terminal, the drain terminal being formed on a second side of the silicon carbide substrate opposite to the first side; as well as Source terminals are formed on the first side of the silicon carbide substrate and located at opposite ends of the silicon layer.

2. The semiconductor device of claim 1, wherein the silicon carbide substrate is made of n-type silicon carbide.

3. The semiconductor device of claim 2, wherein the source terminal is made of n-type silicon.

4. The semiconductor device of claim 3, wherein the doping concentration of the n-type silicon at the source terminal is higher than the doping concentration of the n-type silicon carbide on the silicon carbide substrate.

5. The semiconductor device of claim 1, wherein the source terminal at least partially overlaps with the gate terminal.

6. The semiconductor device of claim 1, wherein the thickness of the gate oxide layer is less than the thickness of the silicon layer.

7. The semiconductor device of claim 2, wherein the drain terminal is made of n-type silicon carbide.

8. The semiconductor device of claim 7, wherein the doping concentration of the n-type silicon carbide at the drain terminal is higher than the doping concentration of the n-type silicon carbide on the silicon carbide substrate.

9. The semiconductor device according to claim 1, wherein the semiconductor device comprises: A first p-well region and a second p-well region are disposed in the silicon carbide substrate and located at opposite ends of the silicon layer; as well as The first P+ region and the second P+ region are located within the first p-well region and the second p-well region, respectively. The source end effector is formed in the first p-well region and the second p-well region.

10. The semiconductor device of claim 9, wherein a portion of the silicon carbide substrate extends between the first p-well region and the second p-well region.

11. The semiconductor device of claim 9, wherein the first p-well region and the second p-well region are made of p-type silicon carbide.

12. The semiconductor device of claim 9, wherein the first P+ region and the second P+ region are made of p-type silicon.

13. The semiconductor device of claim 9, wherein the semiconductor device comprises: A polysilicon layer is located on the gate oxide layer, wherein the gate terminal is formed on the polysilicon layer.

14. A method for manufacturing a semiconductor device, the method comprising: A first N+ region for the drain terminal of the semiconductor device is formed on one side of the silicon carbide substrate; A silicon layer is formed on the side of the silicon carbide substrate opposite to the side that forms the first N+ region; A gate oxide layer is formed on the silicon layer, and a gate terminal is formed on the gate oxide layer; as well as A second N+ region and a third N+ region are formed on opposite sides of the silicon layer to form source terminals.

15. The method of claim 14, wherein the method comprises: A first p-well region and a second p-well region are formed in the silicon carbide substrate and at opposite ends of the silicon layer; as well as A first P+ region and a second P+ region are formed within the first p-well region and the second p-well region; The second N+ region and the third N+ region are respectively formed in the first p-well region and the second p-well region.

16. The method of claim 15, wherein the first p-well region and the second p-well region are made of p-type silicon carbide, and the second N+ region and the third N+ region are made of n-type silicon.

17. The method of claim 16, wherein the first N+ region is made of n-type silicon carbide.

18. The method of claim 14, the method comprising forming a polysilicon layer on the gate oxide layer, wherein the gate terminal is formed on the polysilicon layer.

19. The method of claim 14, wherein the second N+ region and the third N+ region at least partially overlap with the gate oxide layer.

20. The method of claim 15, wherein a portion of the silicon carbide substrate extends between the first p-well region and the second p-well region.

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