Micro-electro-mechanical system and preparation method thereof

Abstract

The invention relates to a micro-electro-mechanical system and a preparation method thereof, and relates to the technical field of micro-electro-machinery. The micro electro mechanical system comprises a substrate, a supporting structure and a first sealing structure, the supporting structure is arranged on one side of the substrate, a plurality of first cavities are formed between the supporting structure and the substrate, the supporting structure is provided with through holes, and the through holes are communicated with the first cavities through channels; the orthographic projection of the via hole on the substrate and the orthographic projection of the first cavity on the substrate are not overlapped; the first sealing structure is arranged at the via hole and used for sealing the via hole. According to the micro-electro-mechanical system, side edge sealing is achieved, the thickness of the supporting structure is not increased, the optical characteristic and the electromechanical characteristic of the supporting structure are not affected, large-aperture sealing can be achieved, the sealing performance is good, cost is low, and efficiency is high.

Description

Microelectromechanical systems and their fabrication methods Technical Field

[0001] This disclosure relates to the field of microelectromechanical technology, and more specifically, to a microelectromechanical system and its fabrication method. Background Technology

[0002] For some micro-electro-mechanical systems (MEMS) devices, there are three main methods for sealing: First, bonding packaging is used for sealing, but this method has problems such as high cost, low efficiency, large bonding area, and difficulty in guaranteeing bonding yield. Second, laser melting silicon technology is used to seal the vias, but this method requires precise alignment, long-term gas replacement, low efficiency, and high processing costs. Third, thermal oxidation sealing is used, but this method is difficult to seal vias with wide diameters.

[0003] It should be noted that the information disclosed in the background section above is only used to enhance the understanding of the background of this disclosure, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention

[0004] The purpose of this disclosure is to overcome the shortcomings of the prior art and provide a microelectromechanical system and its fabrication method, which achieves side sealing without increasing the thickness of the support structure or affecting the optical and electromechanical properties of the support structure. It can achieve sealing of larger apertures, and has good sealing performance, low cost and high efficiency.

[0005] According to one aspect of this disclosure, a microelectromechanical system is provided, comprising:

[0006] Substrate;

[0007] A support structure is disposed on one side of the substrate, and a plurality of first chambers are provided between the support structure and the substrate. The support structure has through holes, and the through holes communicate with each of the first chambers through channels. The orthographic projection of the through holes on the substrate does not overlap with the orthographic projection of the first chambers on the substrate.

[0008] A first sealing structure is disposed at the through hole to seal the through hole.

[0009] In one embodiment of this disclosure, the substrate is made of a conductive material, and the support structure is made of a conductive material;

[0010] The microelectromechanical system further includes an insulating dielectric layer; the insulating dielectric layer is disposed between the substrate and the support structure;

[0011] The first cavity is located between the support structure and the insulating dielectric layer.

[0012] In one embodiment of this disclosure, the support structure is made of an insulating material;

[0013] The microelectromechanical system also has a metal conductive structure, which is disposed on the side of the support structure away from the substrate; the metal conductive structure corresponds one-to-one with the first chamber.

[0014] The orthographic projection of the first chamber onto the substrate lies within the orthographic projection of the metal conductive structure onto the substrate; the various metal conductive structures are electrically connected to each other.

[0015] In one embodiment of this disclosure, the substrate is made of a conductive material, and the support structure is made of an insulating material;

[0016] Electronic components are installed in the first chamber.

[0017] In one embodiment of this disclosure, the microelectromechanical system further has a second sealing structure;

[0018] The second sealing structure is disposed on the side of the first sealing structure away from the substrate, and the second sealing structure completely covers the first sealing structure.

[0019] In one embodiment of this disclosure, a second chamber is further provided between the support structure and the substrate, the second chamber being connected to the first chamber through the channel, and the orthographic projection of the through hole on the substrate is located within the orthographic projection of the second chamber on the substrate;

[0020] The orthographic projection of the second chamber onto the substrate does not overlap with the orthographic projection of the first chamber onto the substrate, and the orthographic projection area of ​​the second chamber onto the substrate is smaller than the orthographic projection area of ​​the first chamber onto the substrate.

[0021] In one embodiment of this disclosure, the first sealing structure has a second sub-sealing structure and a third sub-sealing structure connected in sequence;

[0022] The second sub-sealing structure is disposed on the inner wall of the through hole; the third sub-sealing structure is disposed on the side of the through hole away from the substrate, and the third sub-sealing structure completely covers the through hole; the second sealing structure completely covers the third sub-sealing structure.

[0023] In one embodiment of this disclosure, along the same direction, the distance from the center of the through hole to the edge of the third sub-sealing structure is 3 to 4 times the distance from the center of the through hole to the edge of the through hole.

[0024] According to another aspect of this disclosure, a method for fabricating the above-described microelectromechanical system is provided, comprising the following steps:

[0025] A patterned sacrificial structure is formed on a substrate, the sacrificial structure having interconnected first chamber sacrificial structures and channel sacrificial structures;

[0026] The support structure is formed on the sacrificial structure, the support structure covering the sacrificial structure and the substrate not covered by the sacrificial structure;

[0027] A through hole is formed in the support structure, the through hole exposing a portion of the channel sacrificial structure to form a first structure;

[0028] The first structure is placed in a sacrificial structure etchant to remove the sacrificial structure from the first structure, forming the second structure;

[0029] A sealing layer is formed on the second structure to seal the through hole;

[0030] Remove the excess sealing layer from the second structure to form the first sealing structure, thus obtaining the microelectromechanical system.

[0031] In one embodiment of this disclosure, a sealing layer is formed on the second structure by PECVD or LPCVD to seal the through hole.

[0032] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description

[0033] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure. It is obvious that the drawings described below are merely some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0034] Figure 1 is a schematic diagram of the structure of the microelectromechanical system in the first embodiment of this disclosure.

[0035] Figure 2 is a schematic diagram of the structure of the microelectromechanical system in the first embodiment of this disclosure.

[0036] Figure 3 is a schematic diagram of the structure of the microelectromechanical system in the first embodiment of this disclosure.

[0037] Figure 4 is a schematic diagram of the structure of the microelectromechanical system in the first embodiment of this disclosure.

[0038] Figure 5 is a schematic diagram of the structure of the microelectromechanical system in the first embodiment of this disclosure.

[0039] Figure 6 is a schematic diagram of the structure of the microelectromechanical system in the first embodiment of this disclosure.

[0040] Figure 7 is a schematic diagram of the structure of the microelectromechanical system in the first embodiment of this disclosure.

[0041] Figure 8 is a schematic diagram of the structure of the microelectromechanical system in the first embodiment of this disclosure.

[0042] Figure 9 is a schematic diagram of the structure of the microelectromechanical system in the second embodiment of this disclosure.

[0043] Figure 10 is a schematic diagram of the structure of the microelectromechanical system in the second embodiment of this disclosure.

[0044] Figure 11 is a schematic diagram of the microelectromechanical system in the second embodiment of this disclosure.

[0045] Figure 12 is a schematic diagram of the structure of the microelectromechanical system in the second embodiment of this disclosure.

[0046] Figure 13 is a schematic diagram of the microelectromechanical system in the second embodiment of this disclosure.

[0047] Figure 14 is a schematic diagram of the structure of the microelectromechanical system in the second embodiment of this disclosure.

[0048] Figure 15 is a schematic diagram of the microelectromechanical system in the second embodiment of this disclosure.

[0049] Figure 16 is a schematic diagram of the microelectromechanical system in the second embodiment of this disclosure.

[0050] Figure 17 is a schematic diagram of the structure of the microelectromechanical system in the second embodiment of this disclosure.

[0051] Figure 18 is a schematic diagram of the structure of the microelectromechanical system in the embodiments of this disclosure.

[0052] Figure 19 is a schematic diagram of the structure of the microelectromechanical system in the embodiments of this disclosure.

[0053] Figure 20 is a schematic diagram of the structure of the microelectromechanical system in the embodiments of this disclosure.

[0054] Figure 21 is a schematic diagram of the structure of the microelectromechanical system in the embodiments of this disclosure.

[0055] Explanation of reference numerals in the attached figures:

[0056] 1. Substrate; 2. Support structure; 3. Insulating dielectric layer; 4. Metal conductive structure; 5. First chamber; 6. Through hole; 7. Second chamber; 8. First sealing structure; 81. First sub-sealing structure; 82. Second sub-sealing structure; 83. Third sub-sealing structure; 9. Second channel; 10. Second sealing structure; 11. Sacrificial structure; 12. Channel; 13. First channel. Detailed Implementation

[0057] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the embodiments set forth herein; rather, they are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the exemplary embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar structures, and therefore detailed descriptions of them will be omitted. Furthermore, the drawings are merely illustrative of this disclosure and are not necessarily drawn to scale.

[0058] Although relative terms such as "up" and "down" are used in this specification to describe the relative relationship of one component of an icon to another, these terms are used only for convenience, such as according to the orientation of the examples shown in the accompanying drawings. It is understood that if the device of the icon is flipped upside down, the component described as "up" will become the component described as "down." When a structure is "up" of another structure, it may mean that the structure is integrally formed on the other structure, or that the structure is "directly" mounted on the other structure, or that the structure is "indirectly" mounted on the other structure through another structure.

[0059] The terms “a,” “one,” “the,” “the,” and “at least one” are used to indicate the presence of one or more elements / components / etc.; the terms “including” and “having” are used to indicate an open-ended inclusion and to mean that there may be other elements / components / etc. in addition to the listed elements / components / etc.; the terms “first,” “second,” and “third,” etc., are used only as markers and are not a limitation on the number of objects.

[0060] Structural layer A is located on the side of structural layer B that faces away from the conductive substrate. This can be understood as structural layer A being formed on the side of structural layer B that faces away from the conductive substrate. When structural layer B is a patterned structure, some structures of structural layer A may also be located at the same physical height as structural layer B or at a lower physical height than structural layer B, where the conductive substrate serves as the height reference.

[0061] In this disclosure, rectangles, circles, or polygons are not strictly defined; they can be approximate rectangles, circles, or polygons. Small deformations due to tolerances are possible, as are chamfered corners, curved edges, and other deformations.

[0062] In this disclosure, “about” means a value that is not strictly limited and allows for process and measurement errors.

[0063] With the development of semiconductor technology, Micro-Electro-Mechanical Systems (MEMS) devices, which are related to it, are widely used in more and more fields such as aerospace, petroleum, chemical industry, automobile, and consumer electronics due to their small size, high integration and mass production. Examples of MEMS devices include pressure sensors, temperature sensors, accelerometers, gyroscopes, image sensors, photoelectric sensors, and ultrasonic oscillators.

[0064] Most MEMS devices have complex structures, and their core physical quantity sensing structures often require independent sealing to isolate them from the influence of dust, moisture, grease, and gases in the environment. Furthermore, the core physical quantity sensing structures often have specific requirements, so the sealing structure must meet these requirements. For example, in some MEMS optical devices, the functional areas of the support structure typically require high light transmittance or the filtering of specific wavelengths; therefore, the sealing material used for sealing vias must not remain on the functional areas of the support structure. For some MEMS resonant devices, the support structure is also a primary functional structure, with high requirements for its mechanical and electrical properties, such as thickness, stiffness, and dielectric constant. Sealing material used for sealing vias is generally not allowed to deposit on the functional areas of the support structure. For instance, a Capacitive Micro-Machined Ultrasonic Transducer (CMUT) is an electrostatic conversion ultrasonic sensor that uses micromechanical technology and capacitive sensing principles to achieve high-precision, high-sensitivity ultrasonic detection and measurement. The basic structure of a CMUT consists of a parallel plate capacitor composed of a conductive support structure and a fixed electrode. There is an airtight chamber between the support structure and the fixed electrode as a functional area. When ultrasound acts on the support structure, it changes the capacitance value of the capacitor, thereby generating an electrical signal.

[0065] In the first related technology, bonding packaging technology is used to seal the vias. A bonding area is reserved on the MEMS device, and corresponding holes and grooves are prepared on another wafer, such as single crystal silicon or glass, to form a cap. Then the device and the cap are bonded together by silicon-silicon bonding, anodic bonding, or metal hot pressing. This packaging method requires at least two wafers, which is expensive, inefficient, occupies a large area of ​​the bonding area, and has difficulty in guaranteeing the bonding yield.

[0066] In the second related technology, laser melting silicon technology is used to seal the through hole, but this sealing method requires precise alignment, long-term gas replacement, low efficiency, and high processing cost.

[0067] Among the third related technologies, the sealing method of using thermal oxidation technology to seal the vias (by oxidizing the supporting structure material by introducing oxygen into a furnace tube at ≥1000℃ to achieve sealing of the vias) has several limitations: first, the material of the supporting structure must be monocrystalline silicon or polycrystalline silicon; second, it is only suitable for sealing vias with small diameters and is difficult to seal vias with larger diameters, for example, it is difficult to seal vias with a diameter greater than 6μm; and third, it requires high process temperatures.

[0068] To address at least one of the above problems, the design approach of this disclosure is as follows:

[0069] For some MEMS optical devices, the support structure usually requires high transmittance or to filter out specific wavelengths. Therefore, sealing material is not allowed to remain on the functional area of ​​the support structure. For some MEMS resonant devices, the support structure is also the main functional structure. There are high requirements for the mechanical and electrical properties of the structure, such as thickness, stiffness, and dielectric constant. Sealing material is usually not allowed to be deposited on the functional area of ​​the support structure.

[0070] Therefore, referring to Figures 7 and 15, the via 6 in this disclosure is not located on the functional area directly opposite the support structure 2, but is placed on the side of the functional area of ​​the support structure 2. Referring to Figures 5 and 6, the functional area and the via 6 are connected through channel 12. During the fabrication process, by connecting the via 6 and the functional area, the sacrificial layer etchant can flow when the sacrificial layer is released. Then, the via 6 is sealed using plasma-enhanced chemical vapor deposition (PECVD) or low-pressure chemical vapor deposition (LPCVD). Finally, the sealing material in the area outside the sealing position is etched clean using photolithography and etching methods. This achieves the purpose of sealing the functional area without increasing the thickness of the support structure 2 and without affecting the optical and electromechanical properties of the support structure 2.

[0071] Specifically, this disclosure provides a microelectromechanical system.

[0072] In the first embodiment of this disclosure, the microelectromechanical system is an optical device.

[0073] In this example, referring to Figures 1-7, where Figure 5 is a cross-sectional view at the section line (dashed line in Figure 1), the microelectromechanical system (MEMS) has a substrate 1 and a support structure 2 disposed on one side of the substrate 1. The substrate 1 is made of a conductive material, and the support structure 2 is made of an insulating material (in this example, the insulating material should have good light transmittance). A first chamber 5 (serving as the functional area of ​​the support structure 2) is located between the support structure 2 and the substrate 1. Electronic components (not shown in the figures; in this example, the electronic components can be optical electronic components) are disposed within the first chamber 5. The support structure 2 also has a via 6. The orthographic projection of the via 6 onto the substrate 1 does not coincide with the orthographic projection of the first chamber 5 onto the substrate 1, and the via 6 communicates with the first chamber 5 through a channel 12. A first sealing structure 8 is disposed at the via 6, sealing the via 6 and thus sealing the first chamber 5. The orthographic projection of the first sealing structure 8 on the substrate 1 does not coincide with the orthographic projection of the first chamber 5 on the substrate 1. In this disclosure, the through hole 6 is set on the side of the first chamber 5 (functional area) and connected through the channel 12. In this way, the first chamber 5 (functional area) can be sealed without increasing the thickness of the support structure 2, and without affecting the optical and electromechanical characteristics of the support structure 2.

[0074] In one embodiment of this disclosure, referring to FIG7, the surface of the substrate 1 near the support structure 2 is a plane (the side of the substrate 1 away from the support structure 2 is also a plane, which is simply drawn in the figure and is not shown). This facilitates the formation of multiple first chambers 5 with the same shape, thereby improving the stability of the microelectromechanical system.

[0075] In one embodiment of this disclosure, referring to Figures 7 and 1, a second chamber 7 is further provided between the support structure 2 and the substrate 1. The second chamber 7 is provided with a through-hole 6 communicating with the outside, and the second chamber 7 is connected to the first chamber 5 through a channel 12. Thus, by connecting the first chamber 5 to the second chamber 7, the through-hole 6 connects all the first chambers 5. In this example, there is a gap between the orthographic projection of the second chamber 7 on the substrate 1 and the orthographic projection of the first chamber 5 on the substrate 1. In other words, the orthographic projection of the second chamber 7 on the substrate 1 does not coincide with the orthographic projection of the first chamber 5 on the substrate 1. It is understood that the orthographic projection of the through-hole 6 on the substrate 1 does not coincide with the orthographic projection of the first chamber 5 on the substrate 1, and the orthographic projection of the through-hole 6 on the substrate 1 is located within the orthographic projection of the second chamber 7 on the substrate 1. The first chambers 5 provide vibration space for the substrate 1 and the support structure 2. In this disclosure, the through hole 6 is located on the side of the first chamber 5 to achieve side sealing of the through hole 6, and there is no requirement for the diameter of the through hole 6, so it will not interfere with the performance of the ultrasonic transducer.

[0076] In one embodiment of this disclosure, referring to FIG7, the upper surface (the surface away from the substrate 1) and the lower surface (the surface close to the substrate 1) of the first chamber 5 are parallel. In this disclosure, parallel means that the angle formed by the two surfaces is greater than -10° and less than 10°. Therefore, it also includes the state where the angle is greater than -5° and less than 5°.

[0077] In one embodiment of this disclosure, the orthogonal projection of the via 6 on the substrate 1 is within the orthogonal projection of the second chamber 7 on the substrate 1, and the orthogonal projection of the via 6 on the substrate 1 is smaller than the orthogonal projection of the second chamber 7 on the substrate 1. In this example, the size of the second chamber 7 is not required.

[0078] In one embodiment of this disclosure, referring to Figures 7 and 16, the area of ​​the first chamber 5 is larger than the area of ​​the second chamber 7. This ensures that the first chamber 5 (functional area) accounts for a certain proportion of the total area of ​​the microelectromechanical system (MEMS), thus guaranteeing the performance of the MEMS.

[0079] In one embodiment of this disclosure, the number of first chambers 5 is greater than the number of second chambers 7. This ensures that the area ratio of the first chambers 5 (functional areas) in the microelectromechanical system is maintained, thus ensuring the functionality of the microelectromechanical system.

[0080] In one embodiment of this disclosure, there are multiple first chambers 5, and each first chamber 5 is interconnected with a second chamber 7. Specifically, the microelectromechanical system includes multiple rows of first chambers 5 arranged in an array and multiple rows of second chambers 7 arranged in an array. Each row of first chambers 5 has multiple first chambers 5, and each row of second chambers 7 has multiple second chambers 7; each first chamber 5 and each second chamber 7 are interconnected.

[0081] In one example, referring to Figure 18, the microelectromechanical system (MEMS) includes multiple functional units. Each functional unit includes a second chamber 7 and multiple first chambers 5 adjacent to the second chamber 7. In this example, there are four first chambers 5. Each second chamber 7 and its four adjacent first chambers 5 are connected via a channel 12. In this example, the channel 12 can be a T-shaped channel 12 (dual channel 12). The first channel 13 of the T-shaped channel 12 connects two adjacent first chambers 5, and the second channel 9 of the T-shaped channel 12 connects the first channel 13 and the second chamber 7, thereby achieving communication between each first chamber 5 and the second chamber 7. In adjacent functional units, adjacent first chambers 5 are connected via a single channel 12, thus achieving mutual communication between all first chambers 5 and all second chambers 7 in the entire MEMS. In other examples, the number of first chambers 5 in a functional unit can be 2, 3, 8, 16, 32, 64, 128, 133, 256, etc. Of course, the number of first chambers 5 may also be other numbers not shown. In this disclosure, the number of first chambers 5 is not limited.

[0082] In another example, referring to Figure 19, the microelectromechanical system (MEMS) includes multiple functional units. Each functional unit includes a second chamber 7 and multiple first chambers 5 adjacent to the second chamber 7. In this example, there are four first chambers 5. Each second chamber 7 and its adjacent first chambers 5 are connected by a channel 12. In this example, the channel 12 can be a T-shaped channel 12 (dual channel 12). The first channel 13 of the T-shaped channel 12 connects two adjacent first chambers 5, and the second channel 9 of the T-shaped channel 12 connects the first channel 13 and the second chamber 7, thereby achieving communication between each first chamber 5 and the second chamber 7. Adjacent functional units share a first chamber 5, which is connected to the two first chambers 5 on both sides by a cross-shaped channel 12. In one example, the number of first chambers 5 in a functional unit can be 2, 3, 8, 16, 32, 64, 128, 133, 256, etc. Of course, the number of first chambers 5 can also be other numbers not shown. In this disclosure, the number of first chambers 5 is not limited.

[0083] In other examples, the functional units can also be connected in other ways not listed above, as long as the first chamber 5 and the second chamber 7 can be interconnected.

[0084] In one embodiment of this disclosure, referring to FIG16, the size of channel 12 is smaller than the size of the first chamber 5. In other words, channel 12 can be at the same height as the first chamber 5, and the width of the orthographic projection of channel 12 on substrate 1 is smaller than the width of the orthographic projection of the first chamber 5 on substrate 1. Referring to FIGS. 16a and 16b, along the same direction, the width d1 of channel 12 is smaller than the width d2 of the first chamber 5. In this way, the arrangement of channel 12 will not affect the area ratio of the first chamber 5 (functional area) in the microelectromechanical system, and channel 12 will not interfere with the function of the first chamber 5, thereby not affecting the optical and electromechanical characteristics of the support structure 2. In this example, based on the T-shaped channel 12, the width of the first channel 13 can be greater than the width of the second channel 9, and the size of channel 12 can be adjusted according to the connected chambers.

[0085] In one embodiment of this disclosure, the shape of the first chamber 5 can be rectangular, circular, polygonal, etc. In one example of this disclosure, referring to FIG16, the shape of the first chamber 5 is a regular octagon. In this example, the shape of the first chamber 5 is different from the shape of the second chamber 7; the shape of the first chamber 5 is a regular octagon, and the shape of the second chamber 7 is a quadrilateral.

[0086] In other examples, the shape of the first chamber 5 is the same as the shape of the second chamber 7.

[0087] In one embodiment of this disclosure, a first sealing structure 8 is used to seal the through hole 6. In one example, the first sealing structure 8 may be provided only at the through hole 6 to seal the through hole 6. In another example, referring to FIG6, the first sealing structure 8 has a first sub-sealing structure 81, a second sub-sealing structure 82, and a third sub-sealing structure 83 connected in sequence. The first sub-sealing structure 81 is disposed on the inner wall of the second chamber 7, the first chamber 5, and the channel 12; the second sub-sealing structure 82 is disposed at the through hole 6, connecting the first sub-sealing structure 81 and the third sub-sealing structure 83; the third sub-sealing structure 83 is disposed on the side of the support structure 2 away from the substrate 1, and the orthographic projection of the third sub-sealing structure 83 on the substrate 1 is not less than the orthographic projection of the through hole 6 on the substrate 1. Thus, the entire third sub-sealing structure 83 can ensure the sealing of the through hole 6 and guarantee the airtightness. In this example, the first sub-sealing structure 81, the second sub-sealing structure 82, and the third sub-sealing structure 83 are integrally formed.

[0088] In one embodiment of this disclosure, the thickness of the first sub-sealing structure 81 can be reduced by adjusting the size of the through hole 6, thereby ensuring the optical performance of the microelectromechanical system, such as light transmittance.

[0089] In one embodiment of this disclosure, the horizontal cross-section of the through hole 6 is circular. In other examples, the shape of the through hole 6 may also be other shapes not listed, and this disclosure does not limit it.

[0090] In one embodiment of this disclosure, referring to Figures 6 and 7, Figure 7 is a cross-sectional view from the perspective of the cutting line (dashed line in Figure 16). The orthographic projection of the third sub-sealing structure 83 on the substrate 1 is located within the orthographic projection of the second chamber 7 and the channel 12 as a whole on the substrate 1. In this way, the optical performance of the entire support structure 2 can be guaranteed without increasing the thickness of the entire structure.

[0091] In one example, the orthographic projection of the third sub-sealing structure 83 on the substrate 1 is located within the orthographic projection of the second chamber 7 on the substrate 1, and the orthographic projection area of ​​the third sub-sealing structure 83 on the substrate 1 is equal to the orthographic projection area of ​​the second chamber 7 on the substrate 1. In this way, the leakage rate of the chamber can be minimized to ensure long-term stability, without increasing the thickness of the support structure 2.

[0092] In one example, the distance between the edge of the third sub-sealing structure 83 and the center of the through hole 6 is 3-4 times the distance between the edge of the through hole 6 and the center of the through hole 6. This minimizes the leakage rate of the first chamber 5, ensuring long-term stability, without increasing the thickness of the support structure 2.

[0093] In one embodiment of this disclosure, the thickness of the second sub-sealing structure 82 is not less than the thickness of the first sub-sealing structure 81, and the thickness of the third sub-sealing structure 83 is not less than the thickness of the second sub-sealing structure 82.

[0094] In one embodiment of this disclosure, referring to FIG20, the first sealing structure 8 can be fabricated using plasma-enhanced chemical vapor deposition (PECVD) technology. In this example, the diameter of the via 6 is defined as D, and the thickness T of the third sub-sealing structure 83 is defined as... P 1 is greater than 2D, and the maximum thickness T of the second sub-sealing structure 82 is greater than 2D. P 2. The minimum thickness T of the second sub-sealing structure 82 is between 0.25D and 0.3D. P 3 is approximately 0.1D, and the thickness T of the first sub-sealing structure 81 is... P 4. T P 5 is 0.1D, and the minimum thickness of the second sub-sealing structure 82 is basically equal to the thickness of the first sub-sealing structure 81.

[0095] In another embodiment of this disclosure, referring to FIG21, the first sealing structure 8 can be fabricated using low-pressure chemical vapor deposition (LPCVD) technology. In this example, the diameter of the via 6 is defined as D, and the thickness T of the third sub-sealing structure 83 is defined as... L 1. The maximum thickness T of the second sub-sealing structure 82 is not less than 0.9D. L 2 is between 0.45D, and the minimum thickness T of the second sub-sealing structure 82 is between 0.45D and 0.45D. L 3 is approximately 0.3D, and the thickness T of the first sub-sealing structure 81 is... L 4 and T L 5 is 0.3D, and the minimum thickness of the second sub-sealing structure 82 is basically equal to the thickness of the first sub-sealing structure 81.

[0096] In one embodiment of this disclosure, the microelectromechanical system (MEMS) further includes a second sealing structure 10, which is disposed on the side of the first sealing structure 8 away from the substrate 1. The orthographic projection of the third sub-sealing structure 83 on the substrate 1 is within the orthographic projection of the second sealing structure 10 on the substrate 1, and the orthographic projection of the third sub-sealing structure 83 on the substrate 1 is smaller than the orthographic projection of the second sealing structure 10 on the substrate 1. Thus, by using the second sealing structure 10 to cover the third sub-sealing structure 83 for double sealing, a better sealing effect can be achieved. In this example, the thickness of the second sealing structure 10 can be 1 / 3D to 1 / 2D. This thickness ensures a better sealing effect without excessively increasing the thickness of the MEMS. For example, the thickness of the second sealing structure 10 can be 1 / 3D. Another example is that the thickness of the second sealing structure 10 can be 2 / 5D. Yet another example is that the thickness of the second sealing structure 10 can be 1 / 2D. In other examples, the thickness of the second sealing structure 10 can be other thicknesses not shown.

[0097] In one embodiment of this disclosure, the microelectromechanical system (MEMS) may further include a drive circuit for providing the MEMS with the required current and voltage.

[0098] Based on the above structure, the fabrication method of the microelectromechanical system in this disclosure is as follows:

[0099] S001. Referring to Figure 2, which is a schematic diagram of the structure from the perspective of the cross-section in Figure 1, a sacrificial layer is deposited on the substrate 1, and the sacrificial layer is patterned by photolithography and dry etching, retaining only the sacrificial layer at the specified locations (the second chamber 7, the first chamber 5, and the sacrificial layer at the connecting channel 12 need to be set), forming a sacrificial structure 11. The sacrificial structure 11 includes a first chamber sacrificial structure, a second chamber sacrificial structure, and a channel sacrificial structure. The top view of the sacrificial structure 11 is shown in Figure 8. In this example, the material of the substrate 1 is single-crystal silicon.

[0100] S002, Referring to Figure 3, a layer of silicon nitride is deposited as the support structure 2;

[0101] S003. Referring to Figure 4, a via 6 is formed by photolithography and etching on the support structure 2 corresponding to the second chamber 7 to obtain the first structure, wherein the side of the support structure 2 away from the substrate 1 is photoresist.

[0102] S004. Referring to Figure 5, the first structure is placed in the sacrificial layer etchant, and the etchant will etch all the sacrificial structures 11 clean through the through hole 6 to obtain the second structure. In this step, the sacrificial structure 11 can be removed through the through hole 6, so that the second chamber 7, the first chamber 5 and the channel 12 are formed at the sacrificial structure 11.

[0103] S005. Referring to Figure 6, a sealing layer is formed using PECVD or LPCVD to achieve sealing of the through hole 6; specifically:

[0104] In one example, referring to Figure 20, a layer of silicon nitride or silicon oxide is deposited using PECVD to seal the via 6. Typically, the silicon nitride deposition temperature can be 400℃~450℃ (for example, silicon nitride deposition temperatures can be 400℃, 410℃, 425℃, 435℃, 450℃, etc.), and the silicon oxide deposition temperature can be 350℃~400℃ (for example, silicon oxide deposition temperatures can be 350℃, 375℃, 385℃, 390℃, 400℃, etc.). Generally, the sealing layer prepared by PECVD defines the diameter of the via 6 as D, and the thickness of the third sub-sealing structure 83 as T. P 1 is greater than 2D, and the maximum thickness T of the second sub-sealing structure 82 is greater than 2D. P 2 is between 0.25D and 0.3D, and the minimum thickness T of the second sub-sealing structure 82 is... P 3 is approximately 0.1D, and the thickness T of the first sub-sealing structure 81 is... P 4. T P 5 is 0.1D, the minimum thickness of the second sub-sealing structure 82 is basically equal to the thickness of the first sub-sealing structure 81, and the gap G of the second chamber 7 after sealing. P The height is reduced by approximately 0.2D, and the final support structure has a thickness of 2T. PIncrease by approximately 2.1D;

[0105] In another example, referring to Figure 21, a layer of silicon nitride or silicon oxide is deposited using LPCVD to seal the via 6. Generally, the deposition temperature of silicon nitride can be 780℃~850℃ (for example, silicon nitride deposition temperatures can be 780℃, 800℃, 820℃, 840℃, 850℃, etc.), and the deposition temperature of silicon oxide can be 680℃~720℃ (for example, silicon oxide deposition temperatures can be 680℃, 690℃, 700℃, 710℃, 720℃, etc.). Typically, the sealing layer prepared by LPCVD defines the diameter of the via 6 as D, and the thickness of the third sub-sealing structure 83 as T. L 1. The maximum thickness T of the second sub-sealing structure 82 is not less than 0.9D. L 2 is approximately 0.45D, and the minimum thickness T of the second sub-sealing structure 82 is... L 3 is approximately 0.3D, and the thickness T of the first sub-sealing structure 81 is... L 4. T L 5 is 0.3D, and the clearance height G of the second chamber 7 after sealing. L Reducing by approximately 0.6D, the final support structure has a thickness of 2T. L The increase is approximately 1.2D. In this example, compared to the PECVD film deposition sealing method, the LPCVD deposition temperature is higher, but it is still compatible with IC processes; the LPCVD sealing requires a thinner sealing layer, but the gap between the support structure 2 and the substrate 1 is smaller than that of the PECVD sealing method;

[0106] S006. Referring to Figure 6, excess sealing layer is removed using photolithography and dry etching, leaving only the sealing material at the via 6, forming the first sealing structure 8, thus completing the fabrication of the microelectromechanical system. In this step, the first sealing structure 8 fills and seals the via 6, thereby keeping the first chamber 5 in a sealed state.

[0107] In one embodiment of this disclosure, the sacrificial layer etchant can be an HF solution, such as a standard buffered oxide etchant (BOE). In other examples, the sacrificial layer etchant can also be other solutions not shown.

[0108] In the second embodiment of this disclosure, the microelectromechanical system is a resonant device. In this example, a capacitive micro-machined ultrasonic transducer (CMUT) is used as an example. Referring to Figures 9-17, the capacitive micro-machined ultrasonic transducer has a substrate 1, and an insulating dielectric layer 3 and a support structure 2 are sequentially disposed on one side of the substrate 1.

[0109] In this example, substrate 1 is made of a conductive material and has electrical conductivity. Substrate 1 serves as the lower electrode plate of the capacitive micromechanical ultrasonic transducer. In one example, the material of substrate 1 can be low-resistivity silicon. In another example, the material of substrate 1 can be single-crystal silicon. In other examples, the material of substrate 1 can also be other materials not shown, as long as the corresponding functional requirements are met.

[0110] In this example, the support structure 2 can be made of a conductive material and has conductivity. The support structure 2 serves as the upper electrode plate of the capacitive micromechanical ultrasonic transducer.

[0111] In this example, referring to Figures 15 and 16, where Figure 15 is a schematic diagram from the perspective of the cross-section line (dashed line in Figure 16), a first chamber 5 is provided between the support structure 2 and the insulating dielectric layer 3. A through-hole 6 is provided on the support structure 2. The orthographic projection of the through-hole 6 onto the substrate 1 does not coincide with the orthographic projection of the first chamber 5 onto the substrate 1, and the through-hole 6 communicates with the first chamber 5 through a channel 12. A first sealing structure 8 is provided at the through-hole 6, which seals the through-hole 6, thereby sealing the first chamber 5. The orthographic projection of the first sealing structure 8 onto the substrate 1 does not coincide with the orthographic projection of the first chamber 5 onto the substrate 1. In this disclosure, the through-hole 6 is located on the side of the first chamber 5 (functional area) and communicates through the channel 12. This achieves sealing of the first chamber 5 (functional area) without increasing the thickness of the support structure 2 and without affecting the optical and electromechanical characteristics of the support structure 2.

[0112] In one embodiment of this disclosure, the surface of the substrate 1 near the support structure 2 is planar (the side of the substrate 1 away from the support structure 2 is also planar, which is simply drawn in the figure and not shown), which is beneficial for forming multiple first chambers 5 with the same shape, thereby facilitating the formation of a stable capacitor structure and improving the stability of the microelectromechanical system.

[0113] In one embodiment of this disclosure, referring to Figures 13-15, a second chamber 7 is further provided between the support structure 2 and the insulating dielectric layer 3. The second chamber 7 is provided with a through hole 6 communicating with the outside, and the second chamber 7 is connected to the first chamber 5 through a channel 12. Thus, by connecting the first chamber 5 to the second chamber 7, the through hole 6 connects all the first chambers 5. In this example, there is a gap between the orthographic projection of the second chamber 7 onto the insulating dielectric layer 3 and the orthographic projection of the first chamber 5 onto the insulating dielectric layer 3. In other words, the orthographic projection of the second chamber 7 onto the insulating dielectric layer 3 does not coincide with the orthographic projection of the first chamber 5 onto the insulating dielectric layer 3. It can be understood that the orthographic projection of the through hole 6 onto the insulating dielectric layer 3 does not coincide with the orthographic projection of the first chamber 5 onto the insulating dielectric layer 3, and the orthographic projection of the through hole 6 onto the insulating dielectric layer 3 is located within the orthographic projection of the second chamber 7 onto the insulating dielectric layer 3. The first chambers 5 provide vibration space for the support structure 2. In this disclosure, the through hole 6 is located on the side of the first chamber 5 to achieve side sealing of the through hole 6, and there is no requirement for the diameter of the through hole 6, so it will not affect the performance of the ultrasonic transducer.

[0114] In one embodiment of this disclosure, the upper surface (the surface away from the substrate 1) and the lower surface (the surface close to the substrate 1) of the first chamber 5 are parallel. In this disclosure, parallel means that the angle formed by the two surfaces is greater than -10° and less than 10°. Therefore, it also includes the state where the angle is greater than -5° and less than 5°.

[0115] In one embodiment of this disclosure, the orthogonal projection of the via 6 on the substrate 1 is within the orthogonal projection of the second chamber 7 on the substrate 1, and the orthogonal projection of the via 6 on the substrate 1 is smaller than the orthogonal projection of the second chamber 7 on the substrate 1. In this example, the size of the second chamber 7 is not required.

[0116] In one embodiment of this disclosure, the area of ​​the first chamber 5 is larger than the area of ​​the second chamber 7. This ensures that the first chamber 5 (functional area) accounts for a certain proportion of the total area of ​​the microelectromechanical system (MEMS), thus guaranteeing the performance of the MEMS.

[0117] In one embodiment of this disclosure, the number of first chambers 5 is greater than the number of second chambers 7. This ensures that the area ratio of the first chambers 5 (functional areas) in the microelectromechanical system is maintained, thus ensuring the functionality of the microelectromechanical system.

[0118] In one embodiment of this disclosure, there are multiple first chambers 5, and each first chamber 5 is interconnected with a second chamber 7. Specifically, the microelectromechanical system includes multiple rows of first chambers 5 arranged in an array and multiple rows of second chambers 7 arranged in an array. Each row of first chambers 5 has multiple first chambers 5, and each row of second chambers 7 has multiple second chambers 7; each first chamber 5 and each second chamber 7 are interconnected.

[0119] In one example, referring to Figure 18, the microelectromechanical system (MEMS) includes multiple functional units. Each functional unit includes a second chamber 7 and multiple first chambers 5 adjacent to the second chamber 7. In this example, there are four first chambers 5. Each second chamber 7 and its four adjacent first chambers 5 are connected via a channel 12. In this example, the channel 12 can be a T-shaped channel 12 (dual channel 12). The first channel 13 of the T-shaped channel 12 connects two adjacent first chambers 5, and the second channel 9 of the T-shaped channel 12 connects the first channel 13 and the second chamber 7, thereby achieving communication between each first chamber 5 and the second chamber 7. In adjacent functional units, adjacent first chambers 5 are connected via a single channel 12, thus achieving mutual communication between all first chambers 5 and all second chambers 7 in the entire MEMS. In other examples, the number of first chambers 5 in a functional unit can be 2, 3, 8, 16, 32, 64, 128, 133, 256, etc. Of course, the number of first chambers 5 may also be other numbers not shown. In this disclosure, the number of first chambers 5 is not limited.

[0120] In another example, referring to Figure 19, the microelectromechanical system (MEMS) includes multiple functional units. Each functional unit includes a second chamber 7 and multiple first chambers 5 adjacent to the second chamber 7. In this example, there are four first chambers 5. Each second chamber 7 and its adjacent first chambers 5 are connected by a channel 12. In this example, the channel 12 can be a T-shaped channel 12 (dual channel 12). The first channel 13 of the T-shaped channel 12 connects two adjacent first chambers 5, and the second channel 9 of the T-shaped channel 12 connects the first channel 13 and the second chamber 7, thereby achieving communication between each first chamber 5 and the second chamber 7. Adjacent functional units share a first chamber 5, which is connected to the two first chambers 5 on both sides by a cross-shaped channel 12. In one example, the number of first chambers 5 in a functional unit can be 2, 3, 8, 16, 32, 64, 128, 133, 256, etc. Of course, the number of first chambers 5 can also be other numbers not shown. In this disclosure, the number of first chambers 5 is not limited.

[0121] In other examples, the functional units can also be connected in other ways not listed above, as long as the first chamber 5 and the second chamber 7 can be interconnected.

[0122] In one embodiment of this disclosure, the size of channel 12 is smaller than the size of the first chamber 5. In other words, channel 12 can be at the same height as the first chamber 5, and the width of the orthographic projection of channel 12 onto the substrate 1 is smaller than the width of the orthographic projection of the first chamber 5 onto the substrate 1. It is understood that, referring to Figures 16a and 16b, along the same direction, the width d1 of channel 12 is smaller than the width d2 of the first chamber 5. Thus, the arrangement of channel 12 does not affect the area ratio of the first chamber 5 (functional area) in the microelectromechanical system, and channel 12 does not interfere with the function of the first chamber 5, thereby not affecting the optical and electromechanical characteristics of the support structure 2. In this example, based on the T-shaped channel 12, the width of the first channel 13 can be greater than the width of the second channel 9, and the size of channel 12 can be adjusted according to the connected chambers.

[0123] In one embodiment of this disclosure, the shape of the first chamber 5 can be rectangular, circular, polygonal, etc. In one example of this disclosure, the shape of the first chamber 5 is a regular octagon. In this example, the shape of the first chamber 5 is different from the shape of the second chamber 7; the shape of the first chamber 5 is a regular octagon, and the shape of the second chamber 7 is a quadrilateral.

[0124] In other examples, the first chamber 5 has the same shape as the second chamber 7.

[0125] In one embodiment of this disclosure, a first sealing structure 8 is used to seal the through hole 6. In one example, the first sealing structure 8 may be provided only at the through hole 6 to seal the through hole 6. In another example, the first sealing structure 8 has a first sub-sealing structure 81, a second sub-sealing structure 82, and a third sub-sealing structure 83 connected in sequence. The first sub-sealing structure 81 is disposed on the inner wall of the second chamber 7, the first chamber 5, and the channel 12; the second sub-sealing structure 82 is disposed at the through hole 6, connecting the first sub-sealing structure 81 and the third sub-sealing structure 83; the third sub-sealing structure 83 is disposed on the side of the support structure 2 away from the substrate 1, and the orthographic projection of the third sub-sealing structure 83 on the substrate 1 is not less than the orthographic projection of the through hole 6 on the substrate 1. Thus, the entire third sub-sealing structure 83 can ensure the sealing of the through hole 6 and guarantee the airtightness. In this example, the first sub-sealing structure 81, the second sub-sealing structure 82, and the third sub-sealing structure 83 are integrally formed.

[0126] In one embodiment of this disclosure, the thickness of the first sub-sealing structure 81 can be reduced by adjusting the size of the through hole 6.

[0127] In one embodiment of this disclosure, the horizontal cross-section of the through hole 6 is circular. In other examples, the shape of the through hole 6 may also be other shapes not listed, and this disclosure does not limit it.

[0128] In one embodiment of this disclosure, the orthographic projection of the third sub-sealing structure 83 on the substrate 1 lies within the orthographic projection of the second chamber 7 and the channel 12 as a whole on the substrate 1. This ensures the performance of the entire support structure 2. In one example, the orthographic projection of the third sub-sealing structure 83 on the substrate 1 lies within the orthographic projection of the second chamber 7 on the substrate 1, and the area of ​​the orthographic projection of the third sub-sealing structure 83 on the substrate 1 is equal to the area of ​​the orthographic projection of the second chamber 7 on the substrate 1. This minimizes the leakage rate of the sealing cavity, ensuring long-term stability without increasing the thickness of the support structure 2.

[0129] In one example, the distance between the edge of the third sub-sealing structure 83 and the center of the through hole 6 is 3-4 times the distance between the edge of the through hole 6 and the center of the through hole 6. This minimizes the leakage rate of the first chamber 5, ensuring long-term stability, without increasing the thickness of the support structure 2.

[0130] In one embodiment of this disclosure, the thickness of the second sub-sealing structure 82 is not less than the thickness of the first sub-sealing structure 81, and the thickness of the third sub-sealing structure 83 is not less than the thickness of the second sub-sealing structure 82.

[0131] In one embodiment of this disclosure, referring to FIG20, the first sealing structure 8 can be fabricated using plasma-enhanced chemical vapor deposition (PECVD) technology. In this example, the diameter of the via 6 is defined as D, and the thickness T of the third sub-sealing structure 83 is defined as... P 1 is greater than 2D, and the maximum thickness T of the second sub-sealing structure 82 is greater than 2D. P 2. The minimum thickness T of the second sub-sealing structure 82 is between 0.25D and 0.3D. P 3 is approximately 0.1D, and the thickness T of the first sub-sealing structure 81 is... P 4. T P 5 is 0.1D, and the minimum thickness of the second sub-sealing structure 82 is basically equal to the thickness of the first sub-sealing structure 81.

[0132] In another embodiment of this disclosure, referring to FIG21, the first sealing structure 8 can be fabricated using low-pressure chemical vapor deposition (LPCVD) technology. In this example, the diameter of the via 6 is defined as D, and the thickness T of the third sub-sealing structure 83 is defined as... L 1. The maximum thickness T of the second sub-sealing structure 82 is not less than 0.9D. L 2 is between 0.45D, and the minimum thickness T of the second sub-sealing structure 82 is between 0.45D and 0.45D. L3 is approximately 0.3D, and the thickness T of the first sub-sealing structure 81 is... L 4 and T L 5 is 0.3D, and the minimum thickness of the second sub-sealing structure 82 is basically equal to the thickness of the first sub-sealing structure 81.

[0133] In one embodiment of this disclosure, the support structure 2 can be a non-conductive insulating material (the support structure 2 is not low-resistivity polysilicon or metal). Then, a plurality of metal conductive structures 4 are disposed on the side of the support structure 2 away from the substrate 1. These metal conductive structures 4 can be electrically connected to form a parallel cascade structure, thus creating a capacitor between the metal conductive structures 4 and the substrate 1. Each metal conductive structure 4 corresponds one-to-one with a first chamber 5, and the orthographic projection of the first chamber 5 onto the substrate 1 lies within the orthographic projection of the metal conductive structure 4 onto the substrate 1. In this example, the resistivity of the metal conductive structure 4 is less than the resistivity of the support structure 2.

[0134] In one embodiment of this disclosure, referring to FIG. 17, the capacitive micromechanical ultrasonic transducer further includes a second sealing structure 10. The second sealing structure 10 is disposed on the side of the first sealing structure 8 away from the substrate 1. The orthographic projection of the third sub-sealing structure 83 on the substrate 1 is within the orthographic projection of the second sealing structure 10 on the substrate 1, and the orthographic projection of the third sub-sealing structure 83 on the substrate 1 is smaller than the orthographic projection of the second sealing structure 10 on the substrate 1. Thus, by using the second sealing structure 10 to cover the third sub-sealing structure 83 for double sealing, a better sealing effect can be achieved. In this example, the thickness of the second sealing structure 10 can be 1 / 3D to 1 / 2D. This thickness ensures a better sealing effect without excessively increasing the thickness of the capacitive micromechanical ultrasonic transducer. For example, the thickness of the second sealing structure 10 can be 1 / 3D. Another example is that the thickness of the second sealing structure 10 can be 2 / 5D. Yet another example is that the thickness of the second sealing structure 10 can be 1 / 2D. In other examples, the thickness of the second sealing structure 10 can be other thicknesses not shown.

[0135] In one embodiment of this disclosure, the microelectromechanical system (MEMS) may further include a drive circuit for providing the MEMS with the required current and voltage.

[0136] Based on the above structure, the fabrication method of the capacitive micromechanical ultrasonic transducer in this disclosure is as follows:

[0137] S021. Referring to Figure 9, a silicon nitride or aluminum oxide layer is deposited on substrate 1 as an insulating dielectric layer 3; in this example, substrate 1 is a low-resistivity silicon substrate 1.

[0138] S022. Referring to Figure 10, a sacrificial layer is deposited on the insulating dielectric layer 3. The sacrificial layer can be silicon oxide or PSG (phosphate glass). A sacrificial structure 11, as shown in Figure 10, is formed using photolithography and dry etching. This sacrificial structure 11 includes a first chamber sacrificial structure 11, a channel sacrificial structure 11, and a second chamber sacrificial structure 11. Depending on the device design, the number of chambers can be 2, 4, 8, 16, 32, 64, 128, 256, or more, or a number between these values. In this embodiment, the number of chambers is 128 to ensure the CMUT has a sufficiently large signal output. After all, the energy of each chamber is limited, and the array arrangement combines the energy of 128 chambers. This effectively increases the output energy without changing the resonant frequency of a single chamber.

[0139] S023, Referring to Figure 11, a layer of low-resistivity polysilicon, metal, or silicon nitride is deposited to form a support structure 2;

[0140] S024. Referring to Figure 12, vias 6 are etched on the support structure 2 using photolithography and dry etching techniques. The vias 6 expose a portion of the second chamber sacrificial structure 11.

[0141] S025. Referring to Figure 13, the sacrificial layer etchant completely corrodes the sacrificial structure 11 through the through hole 6.

[0142] S026. Referring to Figure 14, PECVD or LPCVD is used to complete the sealing. Then, photolithography and dry etching are used to completely remove the sealing material except for the corresponding position of the via 6 slot. The projection size of the remaining sealing material on the silicon substrate 1 plane can be 3 to 4 times or larger than the diameter of the via 6, so as to minimize the leakage rate of the sealing cavity and ensure long-term stability; specifically:

[0143] In one example, referring to Figure 20, a layer of silicon nitride or silicon oxide is deposited using PECVD to seal the via 6. Typically, the silicon nitride deposition temperature can be 400℃~450℃ (for example, silicon nitride deposition temperatures can be 400℃, 410℃, 425℃, 435℃, 450℃, etc.), and the silicon oxide deposition temperature can be 350℃~400℃ (for example, silicon oxide deposition temperatures can be 350℃, 375℃, 385℃, 390℃, 400℃, etc.). Generally, the sealing layer prepared by PECVD defines the diameter of the via 6 as D, and the thickness of the third sub-sealing structure 83 as T. P 1 is greater than 2D, and the maximum thickness T of the second sub-sealing structure 82 is greater than 2D. P 2 is between 0.25D and 0.3D, and the minimum thickness T of the second sub-sealing structure 82 is... P 3 is approximately 0.1D, and the thickness T of the first sub-sealing structure 81 is... P 4. T P5 is 0.1D, the minimum thickness of the second sub-sealing structure 82 is basically equal to the thickness of the first sub-sealing structure 81, and the gap G of the second chamber 7 after sealing. P The height is reduced by approximately 0.2D, and the final support structure has a thickness of 2T. P Increase by approximately 2.1D;

[0144] In another example, referring to Figure 21, a layer of silicon nitride or silicon oxide is deposited using LPCVD to seal the via 6. Generally, the deposition temperature of silicon nitride can be 780℃~850℃ (for example, silicon nitride deposition temperatures can be 780℃, 800℃, 820℃, 840℃, 850℃, etc.), and the deposition temperature of silicon oxide can be 680℃~720℃ (for example, silicon oxide deposition temperatures can be 680℃, 690℃, 700℃, 710℃, 720℃, etc.). Typically, the sealing layer prepared by LPCVD defines the diameter of the via 6 as D, and the thickness of the third sub-sealing structure 83 as T. L 1. The maximum thickness T of the second sub-sealing structure 82 is not less than 0.9D. L 2 is approximately 0.45D, and the minimum thickness T of the second sub-sealing structure 82 is... L 3 is approximately 0.3D, and the thickness T of the first sub-sealing structure 81 is... L 4. T L 5 is 0.3D, and the clearance height G of the second chamber 7 after sealing. L Reducing by approximately 0.6D, the final support structure has a thickness of 2T. L The increase is approximately 1.2D. In this example, compared to the PECVD film deposition sealing method, the LPCVD deposition temperature is higher, but it is still compatible with IC processes; the LPCVD sealing requires a thinner sealing layer, but the gap between the support structure 2 and the substrate 1 is smaller than that of the PECVD sealing method;

[0145] S027. Referring to Figure 15 (Figure 15 is a cross-sectional view of the diagonal of Figure 16), if the support structure 2 is not low-resistivity polysilicon or metal (insulating material), a relative planar capacitor cannot be formed between the support structure 2 and the substrate 1. A metal layer needs to be deposited on the support structure 2. The material of the metal layer can be Al or tungsten, etc. Then, the metal outside the pattern corresponding to the cavity projection on the metal layer is removed by photolithography and dry etching to form multiple spaced metal conductive structures 4. At the same time, each isolated metal conductive structure 4 is connected by wires to form a parallel cascade structure. Compared with a whole metal surface, the patterned parallel metal electrode plates can reduce parasitic capacitance (capacitance that does not change). For the same ultrasonic output energy, the ineffective energy loss of the excitation voltage can be reduced.

[0146] In this disclosure, the via 6 is sealed by depositing silicon nitride or silicon oxide using LPCVD or PECVD. Since the reactive gas does not chemically react with the material of the support structure 2, the generated silicon oxide and silicon nitride are both exogenous materials, so there is no limitation on the material of the support structure 2. Furthermore, some exogenous materials are deposited inside the second chamber 7. The thickness of the deposit can be controlled by selecting a suitable chemical vapor deposition method and the opening size, while the thickness of the inner wall of the traditional thermo-oxidative sealing is difficult to control.

[0147] Compared with existing related sealing vias 6, the method of this invention can reach a minimum temperature of 350°C, has good metal compatibility, and is suitable for MEMS front-end and back-end processes; the method of this invention has no limitation on the release aperture and does not require the object to be sealed to be monocrystalline silicon or polycrystalline silicon, greatly improving the range of applicable materials; the method of this invention is applicable to MEMS devices that require gas sealing, has wide applicability, and is low in cost and high in efficiency.

[0148] The design concepts in this disclosure can be applied to other structures or fields requiring sealing. Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this disclosure are indicated by the appended claims.

Claims

1. A microelectromechanical system, characterized in that, include: Substrate; support structure disposed on one side of the substrate, the support structure having a plurality of first chambers between the support structure and the substrate, the support structure having through holes, the through holes communicating with each of the first chambers through channels, the orthographic projection of the through holes on the substrate and the orthographic projection of the first chambers on the substrate not overlapping each other; A first sealing structure is disposed at the through hole to seal the through hole.

2. The microelectromechanical system according to claim 1, characterized in that, The substrate is made of a conductive material, and the support structure is made of a conductive material; the microelectromechanical system also has an insulating dielectric layer; the insulating dielectric layer is disposed between the substrate and the support structure; the first cavity is formed between the support structure and the insulating dielectric layer.

3. The microelectromechanical system according to claim 2, characterized in that, The support structure is made of insulating material; the microelectromechanical system also has a metal conductive structure, which is disposed on the side of the support structure away from the substrate; the metal conductive structure corresponds one-to-one with the first chamber; the orthographic projection of the first chamber on the substrate is located within the orthographic projection of the metal conductive structure on the substrate; and each of the metal conductive structures is electrically connected to the other.

4. The microelectromechanical system according to claim 1, characterized in that, The substrate is made of conductive material, and the support structure is made of insulating material; electronic components are disposed in the first cavity.

5. The microelectromechanical system according to any one of claims 1-4, characterized in that, The microelectromechanical system further has a second sealing structure; the second sealing structure is disposed on the side of the first sealing structure away from the substrate, and the second sealing structure completely covers the first sealing structure.

6. The microelectromechanical system according to claim 5, characterized in that, The support structure and the substrate also have a second chamber, which is connected to the first chamber through the channel. The orthographic projection of the through hole on the substrate is located within the orthographic projection of the second chamber on the substrate. The orthographic projection of the second chamber onto the substrate does not overlap with the orthographic projection of the first chamber onto the substrate, and the orthographic projection area of ​​the second chamber onto the substrate is smaller than the orthographic projection area of ​​the first chamber onto the substrate.

7. The microelectromechanical system according to claim 6, characterized in that, The first sealing structure has a second sub-sealing structure and a third sub-sealing structure connected in sequence; the second sub-sealing structure is disposed on the inner wall of the through hole; the third sub-sealing structure is disposed on the side of the through hole away from the substrate, and the third sub-sealing structure completely covers the through hole; the second sealing structure completely covers the third sub-sealing structure.

8. The microelectromechanical system according to claim 7, characterized in that, Along the same direction, the distance from the center of the through hole to the edge of the third sub-sealing structure is 3 to 4 times the distance from the center of the through hole to the edge of the through hole.

9. A method for fabricating a microelectromechanical system according to any one of claims 1-8, characterized in that, Includes the following steps: A patterned sacrificial structure is formed on a substrate, the sacrificial structure having interconnected first chamber sacrificial structures and channel sacrificial structures; The support structure is formed on the sacrificial structure, the support structure covering the sacrificial structure and the substrate not covered by the sacrificial structure; a via is formed on the support structure, the via exposing a portion of the channel sacrificial structure, forming a first structure; The first structure is placed in a sacrificial structure etchant to remove the sacrificial structure from the first structure, forming the second structure; A sealing layer is formed on the second structure to seal the through hole; Remove the excess sealing layer from the second structure to form the first sealing structure, thus obtaining the microelectromechanical system.

10. The method for fabricating a microelectromechanical system according to claim 9, characterized in that, A sealing layer is formed on the second structure by PECVD or LPCVD to seal the through hole.

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