Fault detection method and device, electronic equipment and readable storage medium

Abstract

The embodiment of the invention provides a fault detection method and device, electronic equipment and a readable storage medium. The method comprises the following steps: aiming at an analog circuit corresponding to a to-be-detected fault circuit, taking any to-be-detected fault as a target fault, adding the target fault to a to-be-selected fault, and obtaining circuit data corresponding to each acquisition point of the analog circuit under the to-be-selected fault as first data; comparing the first data with the second data and the third data, and if a comparison result shows that at least one abnormal data in the third data is inconsistent with the data of the target acquisition point in the first data, selecting at least one other to-be-detected fault to be added to the to-be-selected fault; and the operation of acquiring the circuit data corresponding to each acquisition point of the analog circuit under the fault to be selected is executed again until the comparison result represents that the target acquisition point in the first data is consistent with the target acquisition point in the third data, and the current fault to be selected is added to the fault set of the fault circuit to be detected, so that the accuracy is improved.

Description

Fault detection methods, devices, electronic equipment and readable storage media Technical Field

[0001] This invention relates to the field of integrated circuit technology, and in particular to a fault detection method, apparatus, electronic device, and readable storage medium. Background Technology

[0002] With the development of integrated circuit technology, scanning tests are often used to diagnose chip faults. This involves replacing flip-flops in the circuit with scanning units and connecting the scanning units end-to-end to form a scanning chain. When the circuit is in test mode, test data can be shifted into the circuit along the scanning chain, or the circuit's internal response can be shifted out through the scanning chain for observation.

[0003] In related technologies, fault diagnosis of scan chains often involves simulating the response of a single faulty unit for testing. This method often does not match the actual faulty circuit, resulting in low accuracy of fault detection. Summary of the Invention

[0004] The purpose of this invention is to provide a fault detection method, apparatus, electronic device, and readable storage medium to solve the problem of low accuracy in fault detection. The specific technical solution is as follows: In a first aspect of this invention, a fault detection method is provided, the method comprising: for an analog circuit corresponding to a faulty circuit to be detected, selecting any fault to be detected as a target fault, adding the target fault to a list of candidate faults, acquiring circuit data corresponding to each acquisition point of the analog circuit under the candidate faults, and using this as first data; comparing the first data with second data and third data respectively, and if the comparison result indicates that at least one abnormal data in the third data is inconsistent with the data of the target acquisition point in the first data, then selecting at least one other fault to be detected and adding it to the list of candidate faults; wherein... The second data is the circuit data corresponding to each acquisition point in the reference circuit corresponding to the fault circuit to be detected, and the third data is the circuit data corresponding to each acquisition point in the fault circuit to be detected; the abnormal data is the acquisition point data that is inconsistent with the second data, and the target acquisition point is the acquisition point corresponding to the abnormal data; the operation of obtaining the circuit data corresponding to each acquisition point of the simulation circuit under the candidate fault is performed again until the comparison result indicates that the target acquisition point in the first data is consistent with the target acquisition point in the third data, then the current candidate fault is added to the fault set of the fault circuit to be detected.

[0005] In a second aspect of the present invention, a fault detection device is also provided. The device includes: a first adding module, configured to, for an analog circuit corresponding to a fault circuit to be detected, select any fault to be detected as a target fault and add the target fault to a list of candidate faults, and acquire circuit data corresponding to each acquisition point of the analog circuit under the candidate faults, as first data; and a comparison module, configured to compare the first data with second data and third data respectively, and if the comparison result indicates that at least one abnormal data in the third data is inconsistent with the data of the target acquisition point in the first data, then at least one other fault to be detected is selected and added to the list of candidate faults; wherein, the... The second data refers to the circuit data corresponding to each acquisition point in the reference circuit corresponding to the fault circuit to be detected, and the third data refers to the circuit data corresponding to each acquisition point in the fault circuit to be detected; the abnormal data refers to the acquisition point data that is inconsistent with the second data, and the target acquisition point is the acquisition point corresponding to the abnormal data; the second adding module is used to perform the operation of obtaining the circuit data corresponding to each acquisition point of the analog circuit under the candidate fault again, until the comparison result indicates that the target acquisition point in the first data is consistent with the target acquisition point in the third data, then the current candidate fault is added to the fault set of the fault circuit to be detected.

[0006] In a third aspect of the present invention, an electronic device is also provided, including a processor, a communication interface, a memory, and a communication bus, wherein the processor, the communication interface, and the memory communicate with each other through the communication bus; the memory is used to store computer programs; and the processor is used to implement the method described in the first aspect when executing the program stored in the memory.

[0007] In a fourth aspect of the invention, a computer-readable storage medium is also provided, wherein instructions are stored therein, which, when executed on a computer, cause the computer to perform the method described in the first aspect.

[0008] In a fifth aspect of the invention, a computer program product comprising instructions is also provided, which, when run on a computer, causes the computer to perform the method described in the first aspect above.

[0009] The fault detection method provided in this invention obtains first data of the analog circuit under a candidate fault, and compares the first data with second data of a reference circuit and third data of the circuit under test to determine whether the candidate fault matches the actual situation of the circuit under test. Furthermore, if at least one abnormal data point in the third data point is inconsistent with the first data, this invention further adds at least one other candidate fault to the candidate fault list, thereby further verifying the possibility of multiple candidate faults in the circuit under test. This can fully verify the existence of multiple candidate faults in the circuit under test, improving the accuracy of fault detection and the quality of fault diagnosis to a certain extent. Attached Figure Description

[0010] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the accompanying drawings used in the description of the embodiments or the prior art will be briefly introduced below.

[0011] Figure 1 is a flowchart of a fault detection method according to an embodiment of the present invention; Figure 2 is a schematic flowchart of another fault detection method according to an embodiment of the present invention; Figure 3 is a schematic diagram of a fault detection scenario according to an embodiment of the present invention; Figure 4 is a schematic diagram of a fault detection device according to an embodiment of the present invention; Figure 5 is a schematic diagram of an electronic device according to an embodiment of the present invention. Detailed Implementation

[0012] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0013] The terms "first," "second," etc., used in the specification and claims of this invention are used to distinguish similar objects and not to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that embodiments of the invention can be implemented in orders other than those illustrated or described herein, and the objects distinguished by "first," "second," etc., are generally of the same class and the number of objects is not limited; for example, the first object can be one or more. Furthermore, the term "and / or" in the specification and claims is used to describe the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A alone, A and B simultaneously, and B alone. The character " / " generally indicates that the preceding and following related objects are in an "or" relationship. In embodiments of this invention, the term "multiple" refers to two or more, and other quantifiers are similar.

[0014] Figure 1 is a flowchart of a fault detection method in an embodiment of the present invention. As shown in Figure 1, the method includes: Step 101: For the analog circuit corresponding to the fault circuit to be detected, any fault to be detected is taken as the target fault, and the target fault is added to the candidate faults. The circuit data corresponding to each collection point of the analog circuit under the candidate fault is obtained as the first data.

[0015] Step 102: Compare the first data with the second data and the third data respectively. If the comparison result indicates that there is at least one abnormal data in the third data that is inconsistent with the data of the target collection point in the first data, then select at least one other fault to be detected and add it to the candidate fault.

[0016] Wherein, the second data is the circuit data corresponding to each acquisition point in the reference circuit corresponding to the fault circuit to be detected, and the third data is the circuit data corresponding to each acquisition point in the fault circuit to be detected; the abnormal data is the acquisition point data that is inconsistent with the second data, and the target acquisition point is the acquisition point corresponding to the abnormal data; step 103, execute the operation of obtaining the circuit data corresponding to each acquisition point of the simulation circuit under the candidate fault again, until the comparison result indicates that the target acquisition point in the first data is consistent with the target acquisition point in the third data, then add the current candidate fault to the fault set of the fault circuit to be detected.

[0017] Regarding steps 101-103 above, embodiments of the present invention can be performed during the chip design stage, before chip tape-out, or even during the chip testing stage; the present invention does not impose any limitations on this. The aforementioned faulty circuit to be tested can be a faulty circuit, referred to as a failed circuit. The aforementioned simulation circuit can be a circuit used to simulate the faulty circuit to be tested, or a virtual circuit pre-built based on a fault simulation tool. In one case, embodiments of the present invention can be applied to Electronic Design Automation (EDA) tools; accordingly, the aforementioned simulation circuit can be built based on EDA.

[0018] The faulty circuit to be detected can be a failed circuit in the scan chain, and the acquisition point can be a scanning unit in the scan chain.

[0019] The aforementioned fault to be detected can be a potential fault in the circuit to be detected. Specifically, the aforementioned fault to be detected can be predetermined based on the scan chain structure of the circuit to be detected. For example, the aforementioned fault to be detected can be a fault in one or more scan units. The number of the aforementioned faults to be detected can be multiple, and this embodiment of the invention does not limit this.

[0020] The circuit data corresponding to the aforementioned acquisition points can be the output data of each scanning unit, and can be 0 or 1. Accordingly, the aforementioned first data can include the circuit data of each acquisition point.

[0021] Specifically, the aforementioned first data can be obtained by simulating candidate faults using analog circuits. The candidate faults can be combinations of faults currently to be detected, which may include one or more faults to be detected.

[0022] Specifically, based on the fault conditions of the candidate fault, corresponding analog values ​​can be set for the analog units in the analog circuit. Specifically, when using EDA tools for simulation, the analog values ​​can be directly imported into the analog circuit based on the candidate fault. For example, taking the candidate fault as scan unit A fixed at 0, the parameter value of the analog unit corresponding to scan unit A in the analog circuit can be set to 0 to simulate the candidate fault.

[0023] Accordingly, after simulating the candidate fault, the circuit data of each simulation unit in the simulation circuit can be read to obtain the circuit data corresponding to each acquisition point of the simulation circuit under the candidate fault, which is used as the first data mentioned above.

[0024] The second data mentioned above refers to the circuit data corresponding to each acquisition point in the reference circuit. The reference circuit can be a fault-free circuit with a completely identical circuit structure to the circuit to be tested, it can be pre-built, or it can be obtained based on EDA simulation; this embodiment of the invention does not impose any restrictions on this. The initial state of the simulation circuit can be consistent with the reference circuit; that is, the initial state of the simulation circuit is a fault-free circuit with a completely identical circuit structure to the circuit to be tested. Correspondingly, the first data mentioned above refers to the acquisition point data obtained by the simulation circuit after simulating the candidate fault. The third data mentioned above refers to the circuit data corresponding to each acquisition point in the circuit to be tested. In this embodiment of the invention, this is equivalent to: for a circuit with a known structure, the first data refers to the circuit data corresponding to each acquisition point when the circuit has a candidate fault, and the third data refers to the circuit data corresponding to each acquisition point when the circuit has an unknown fault.

[0025] The aforementioned abnormal data refers to data collected from points that are inconsistent with the second set of data. In other words, it refers to data collected from points that are inconsistent with the circuit data of the reference circuit. The target data collection points are the data collection points corresponding to the abnormal data.

[0026] Understandably, the second data is the circuit data corresponding to the acquisition point of the reference circuit. Therefore, the second data can be used as the expected value. When the circuit data of a certain acquisition point in the first data or the third data is inconsistent with the circuit data of that acquisition point in the second data, it indicates that there is invalid data and a fault exists in the first data or the third data.

[0027] In this case, embodiments of the present invention can compare the first data with the second data and the third data to obtain a comparison result. The comparison result may include data from collection points where the first data and the second data are inconsistent, and may also include data from collection points where the first data and the third data are inconsistent.

[0028] Understandably, data from acquisition points where the first and second data are inconsistent can indicate that a fault exists at that acquisition point under the candidate fault condition. Data from acquisition points where the first and third data are inconsistent can indicate that the response of that acquisition point in the analog circuit is inconsistent with the response of the circuit to be tested under the candidate fault condition. Therefore, embodiments of the present invention can determine whether the candidate fault exists in the circuit to be tested based on the comparison results.

[0029] The aforementioned abnormal data refers to the data collected at points inconsistent with the second data, and the target data collection point is the data collection point corresponding to the abnormal data. Specifically, if the comparison results indicate that at least one abnormal data point in the third data is inconsistent with the data of the target data collection point in the first data, it indicates that the circuit data of the target data collection point in the faulty circuit to be detected is invalid. However, the circuit data of the target data collection point in the analog circuit is not invalid under the candidate fault. In this case, it indicates that the current candidate fault cannot fully explain the failure of the faulty circuit to be detected, and the faulty circuit to be detected may have multiple faults.

[0030] At this point, the present invention embodiment can further select at least one other fault to be detected and add it to the list of fault candidates. The aforementioned other fault to be detected can be a different fault from the fault already added to the list of fault candidates. Accordingly, at this point, there are at least two faults to be detected among the fault candidates. The present invention embodiment can again perform the operation of acquiring the circuit data corresponding to each acquisition point of the analog circuit under the fault candidates, until the comparison result indicates that the target acquisition point in the first data is consistent with the target acquisition point in the third data. This indicates that the current fault candidate can completely explain the failure of the circuit to be detected, and then the current fault candidate can be added to the fault set of the circuit to be detected.

[0031] The aforementioned fault set can be a pre-set dataset, which can be used to store candidate faults detected by the circuit to be tested.

[0032] Furthermore, the aforementioned fault set can be output to a display component for display, facilitating further testing by relevant testers. It can also be used to evaluate the effectiveness of fault detection; however, this embodiment of the invention does not limit its application.

[0033] It's important to note that scan testing is a typical design-for-test (CBT) technique. Its basic idea is to replace flip-flops in the circuit with scan cells and connect them end-to-end to form a scan chain. When the circuit is in test mode, test data can be shifted into the circuit along the scan chain, and the circuit's internal response can be shifted out for observation. The scan chain improves the observability and testability of the circuit and is the foundation of CBT techniques. Fault diagnosis technology refers to determining the fault location and specific fault behavior of a chip based on the failure response generated during testing. Chip fault diagnosis is a necessary step to improve process yield and process improvement. Scan chain faults account for a relatively high proportion of total chip faults, becoming a significant factor affecting chip yield. Furthermore, due to the unique structure of scan chains compared to logic circuits, diagnosing scan chains is often more difficult.

[0034] Related technologies often employ fault simulation-based scan chain fault diagnosis. The principle is to locate the fault scanning unit by comparing the failure response of the fault to be detected with the failure response of the failed circuit. Fault simulation calculates the failure responses that each fault to be detected can produce. The closer the failure response of a fault to be detected is to the failure response of the failed circuit, the greater the likelihood that the fault to be detected is a real fault. Specifically, the method for evaluating the similarity of failure responses is to calculate a similarity score (TFSF / (TFSF+TFSP+TPSF)) based on three parameters: the number of fault output data bits that the fault to be detected can explain (Tester FailSimulation Fail, TFSF), the number of fault output data bits that the fault to be detected cannot explain (Tester FailSimulation Pass, TFSP), and the number of correct output data bits that the fault to be detected cannot explain (Tester PassSimulation Fail, TPSF). The closer the score is to 100%, the more likely the fault to be detected is a real fault.

[0035] However, this method only considers the case of a single faulty unit. In actual failed circuits, real faults may manifest as intermittent faults, or multiple fault diagnosis units may exist simultaneously in a single failed circuit. In such cases, this method is insufficient to reflect the actual fault situation, resulting in poor diagnostic quality.

[0036] The fault detection method provided in this embodiment of the invention obtains first data of the analog circuit under the candidate fault, and compares the first data with the second data of the reference circuit and the third data of the circuit under test to determine whether the candidate fault matches the actual situation of the circuit under test. Furthermore, if at least one abnormal data point in the third data point is inconsistent with the first data point, this embodiment of the invention adds at least one other candidate fault to the candidate fault list, thereby further verifying the case through the candidate fault. This fully verifies the existence of multiple candidate faults in the circuit under test, which can improve the accuracy of fault detection and the quality of fault diagnosis to a certain extent.

[0037] Optionally, after comparing the first data with the second data and the third data respectively, the embodiments of the present invention may further include: S21, obtaining the intersection of the first collection point and the second collection point based on the comparison result, as a first fault set; the first collection point is the collection point corresponding to the abnormal data in the third data, and the second collection point is the collection point corresponding to the abnormal data in the first data.

[0038] After the above operation of selecting at least one other fault to be detected and adding it to the selected fault, the embodiment of the present invention may further include: S22, modifying the circuit data of the collection point corresponding to the first fault set in the fault circuit to be detected to the target data; the target data is the data of the collection point corresponding to the first fault set in the second data.

[0039] The first acquisition point mentioned above refers to the acquisition point corresponding to the abnormal data in the third data, which is the location of the failure in the faulty circuit. The second acquisition point mentioned above is the acquisition point corresponding to the abnormal data in the first data, which is the location of the failure in the analog circuit.

[0040] Furthermore, by obtaining the intersection of the first and second acquisition points, acquisition points that have failed in both the failed circuit and the analog circuit can be obtained, forming the first fault set. It is understood that the failure data of each acquisition point in the first fault set can be interpreted individually by the candidate faults. In this case, before selecting other faults to be detected and adding them to the candidate faults, and before simulating the candidate faults again, this embodiment of the invention can modify the circuit data of the acquisition points corresponding to the first fault set in the fault circuit to the target data, that is, modify it to the data of the acquisition points corresponding to the first fault set in the second data. In subsequent simulations, the failure states of each acquisition point in the first fault set can no longer be considered.

[0041] In this way, the first set of faults corresponding to the identified candidate faults can be excluded before fault detection is performed again, which can reduce the amount of computation for fault detection and improve fault detection efficiency to a certain extent.

[0042] Optionally, after comparing the first data with the second data and the third data respectively, the method further includes: S31, obtaining the intersection of the first collection point and the third collection point based on the comparison result, as a second fault set; the third collection point is the collection point corresponding to the non-abnormal data in the first data.

[0043] After performing the operation of obtaining the circuit data corresponding to each acquisition point of the analog circuit under the candidate fault again, the embodiment of the present invention may further include: S32, if the previous second fault set belongs to a subset of the current first fault set, then determine that the target acquisition point in the first data is consistent with the target acquisition point in the third data.

[0044] The third acquisition point mentioned above refers to the acquisition point corresponding to the non-abnormal data in the first data, that is: the acquisition point corresponding to the circuit data in the first data that is consistent with the second data.

[0045] Accordingly, the aforementioned second fault set can characterize the acquisition points that have failed in the failed circuit but not in the analog circuit. Here, the aforementioned previous second fault set refers to the second fault set acquired during the previous round of detection. The aforementioned current first fault set refers to the first fault set acquired after re-performing the operation of acquiring the first data based on the new candidate faults.

[0046] Furthermore, after performing the operation of acquiring the first data again, if the previous second fault set belongs to a subset of the current first fault set, it indicates that the failure data that the previous candidate fault could not explain can now be explained by the current candidate fault. This indicates that the combination of faults to be detected contained in the current candidate fault can explain the failure of the circuit to be detected. It can be determined that the target acquisition point in the first data is consistent with the target acquisition point in the third data. At this time, the candidate fault can be directly added to the fault set.

[0047] In this way, by determining the relationship between the previous second fault set and the current first fault set, the combination of multiple faults to be detected can be detected and judged, thereby ensuring that the fault detection is closer to the actual circuit failure and improving the fault detection effect.

[0048] Optionally, if the previous second fault set is not a subset of the current first fault set, it indicates that the current candidate faults still cannot explain all the failure data. In this case, the above steps can be repeated to correct the circuit data of the acquisition point corresponding to the first fault set in the circuit to be detected, correct it to the target data, and select at least one other fault to be detected again to add to the candidate faults until the previous second fault set belongs to a subset of the current first fault set.

[0049] Optionally, after comparing the first data with the second data and the third data respectively, the embodiments of the present invention may further include: S41, if the comparison result indicates that any abnormal data in the first data is consistent with the data of the target collection point in the third data, then the current candidate fault is added to the fault set.

[0050] Specifically, if the comparison results show that any abnormal data in the first data is consistent with the data of the target acquisition point in the third data, it indicates that there is no failure in the circuit to be detected and no failure in the analog circuit. At this time, it can be determined that the current candidate fault can explain the failure of the circuit to be detected, and the current candidate fault can be directly added to the fault set.

[0051] Specifically, embodiments of the present invention can determine whether any abnormal data in the first data is consistent with the data of the target acquisition point in the third data based on the aforementioned second fault set. Specifically, since the first acquisition point is the acquisition point corresponding to the abnormal data in the third data, and the third acquisition point is the acquisition point corresponding to the non-abnormal data in the first data, embodiments of the present invention can obtain the intersection of the first acquisition point and the third acquisition point as the second fault set. When the second fault set is empty, it indicates that there is currently no situation where the circuit to be detected is faulty and the analog circuit is not faulty.

[0052] Accordingly, if the second fault set is not empty, the above steps are performed to select at least one other fault to be detected and add it to the candidate faults.

[0053] In this way, when the abnormal data in the first data is consistent with the third data, it can be directly determined that the candidate fault can explain the failure of the circuit under test, and it can be added to the fault set to ensure the comprehensiveness of the fault detection of the circuit under test.

[0054] Optionally, after comparing the first data with the second data and the third data respectively, the embodiments of the present invention may further include: S51, if the comparison result indicates that there is at least one abnormal data in the first data that is inconsistent with the data of the target acquisition point in the third data, then it is determined that the target fault does not exist in the fault circuit to be detected, the current target fault is removed from the candidate faults, and the operation of taking any fault to be detected as the target fault and adding the target fault to the candidate faults is re-executed.

[0055] Specifically, if there is at least one abnormal data point in the first data that is inconsistent with the data of the target acquisition point in the third data, it indicates that there is a acquisition point that has failed in the circuit to be detected but has not failed in the analog circuit. At this time, it can be determined that the target fault cannot explain the failure of the circuit to be detected, and the current target fault can be directly removed from the candidate faults.

[0056] Furthermore, the fault to be detected can be reselected as the target fault.

[0057] In this way, the consistency between the abnormal data of the first data and the third data can be used to determine whether the fault circuit under test has a target fault, which facilitates the screening of target faults and ensures the effectiveness of the identified candidate faults.

[0058] Optionally, after adding the current candidate fault to the fault set of the fault circuit to be detected, the embodiment of the present invention may further include: S61, if at least one candidate fault is not determined to be the target fault, the operation of adding any candidate fault to the candidate fault and taking any candidate fault as the target fault is executed again for the analog circuit corresponding to the fault circuit to be detected.

[0059] Specifically, in the embodiments of the present invention, if at least one fault to be detected is not identified as a target fault, step 101 above can be executed again to ensure that all faults to be detected in the circuit to be detected are traversed.

[0060] This ensures that no fault is missed, guaranteeing the comprehensiveness and accuracy of fault detection.

[0061] Optionally, the embodiments of the present invention may further include: S71, obtaining the number of times each of the faults to be detected in the fault set is repeated in each of the candidate faults.

[0062] S72. Based on the number of repetitions of each of the faults to be detected, the accuracy of each of the faults to be detected is evaluated.

[0063] Specifically, embodiments of the present invention can statistically analyze the fault set obtained during the above fault detection process. This fault set includes all detectable faults and combinations of detectable faults that can explain the actual failure circuit. In the fault set, a single detectable fault may appear multiple times in several combinations of detectable faults. Embodiments of the present invention can statistically analyze the repetition count of all single detectable faults appearing in the fault set and sort each single detectable fault according to the repetition count. A single detectable fault with a higher repetition count is more likely to actually exist in the actual failure circuit.

[0064] Accordingly, embodiments of the present invention can evaluate the accuracy of each fault to be detected based on the number of repetitions. It is understood that the accuracy evaluation result is positively correlated with the number of repetitions; the more repetitions, the higher the accuracy.

[0065] Thus, by measuring the number of times each fault to be detected is repeated among the candidate faults, the embodiments of the present invention can provide the scan chain fault diagnosis results based on the multi-fault model, thereby improving the accuracy of fault simulation diagnosis.

[0066] For example, Figure 2 is a flowchart of another fault detection method in an embodiment of the present invention. As shown in Figure 2, a failed circuit is selected as the simulation object. First, a suspected fault A is selected and injected into the circuit under test (simulation circuit) to simulate the fault. If a position appears where the failed circuit is not failed but fails in the fault simulation (the position where TPSF is located), that is, TPSF≠0, then it is considered that the suspected fault cannot explain the failed circuit, and the suspected fault is removed. A new suspected fault is selected. Based on this, there are only three comparison situations between the failed circuit response and the suspected fault simulation: both the failed circuit and the fault simulation are failed (i.e., the position where TFSF is located), the failed circuit is failed but not failed in the fault simulation (i.e., the position where TFSP is located), and neither the failed circuit nor the fault simulation is failed, that is: the position where Tester Pass SimulationPass (TPSP) is located.

[0067] If there is no failure on the fault circuit in the fault simulation (i.e., TFSP=0), then the suspected fault is considered to be able to explain the fault circuit on its own and is retained as a candidate fault for the fault circuit.

[0068] If TFSP≠0, then the fault cannot be explained by the failure circuit alone. In this case, consider the case of multiple faults: first modify the state of the failure circuit, correct the fault of the bit where the TFSF of suspected fault A is located (i.e. the failure data that can be correctly simulated in the simulation of suspected fault A) in the failure circuit, no longer consider the bit where the TFSF is located, and only simulate the failure data that cannot be explained by suspected fault A to obtain new parameters.

[0069] A suspected fault B is selected for fault simulation. The circuit data after the injected fault is compared with the unmodified failed circuit data to obtain new TFSF', TFSP', and TPSF'. If TPSF' ≠ 0, a new suspected fault is selected for fault simulation. At this time, if the bit where TFSP is located is a subset of the bit where TFSF' is located, it means that all the failed data that suspected fault A cannot explain can be explained by suspected fault B. It can be considered that the combination of A and B can explain the failed circuit, and the combination of suspected faults A and B is retained as a candidate fault for the failed circuit.

[0070] If the bit containing TFSP is not a subset of the bit containing TFSF', it means that the combination of suspected faults A and B still cannot explain all the failure data. In this case, repeat the above steps, correct the failure data of the bit containing TFSF' in the failed circuit, inject new suspected faults for simulation, until the suspected faults can explain all the failure data in the failed circuit, and retain the set of all suspected faults as a candidate fault.

[0071] The candidate fault set obtained during the above fault simulation process is statistically analyzed. This candidate fault set includes all suspected faults and combinations of suspected faults that can explain the actual failure circuit. In the candidate fault set, a single suspected fault may appear multiple times in several suspected fault combinations. The repetition count of all single suspected faults appearing in the candidate fault set is counted, and each single suspected fault is ranked according to the repetition count. The single suspected fault with a higher repetition count is more likely to actually exist in the actual failure circuit.

[0072] As another example, Figure 3 is a schematic diagram of a fault detection scenario in an embodiment of the present invention. As shown in Figure 3, the faulty circuit is a scanning chain composed of 7 scanning units. By comparing the circuit data when there is no fault (second data) and the data of the faulty circuit (third data), it can be seen that the actual fault of the circuit to be detected generates 4 failure data at A, B, E, and G. Suspected fault 1 is injected into the fault-free circuit (simulated circuit) to simulate the fault, and compared with the faulty circuit. Failure data is generated at A, C, and G. However, since the actual fault does not cause failure at C, the TPSF of suspected fault 1 is 1, and suspected fault 1 is removed from the suspected fault set.

[0073] Furthermore, a fault simulation was performed by injecting suspected fault 2 into the fault-free circuit. Failure data was generated at points A, B, and E. Comparing this with the data from the failed circuit, we found TPSF=0, TFSF=3 (located at points A, B, and E), and TFSP=1 (located at point G). Suspected fault 2 could not explain the failure data of the failed circuit at point G. Therefore, suspected fault 2 was retained, and new faults were continued to be injected.

[0074] The failure data at points A, B, and E in the failed circuit that can be explained by suspected fault 2 are corrected, while the failure data at point G is retained. Suspected fault 3 is re-injected for fault simulation. Comparing the circuit with the previous fault, we find TPSF'=0, TFSF'=2 (located at points E and G), and TFSP'=2 (located at points A and B). The point {G} where TFSP is located is a subset of the point {E,G} where TFSF' is located, meaning that the failure data that cannot be explained by suspected fault 2 can be explained by suspected fault 3. Therefore, suspected fault {2,3} is retained as a candidate fault. If the suspected faults have not been completely traversed, a new suspected fault is injected and the fault simulation is repeated.

[0075] After traversing all suspected faults, we obtain all candidate faults containing {2,3}, where 2 and 3 may exist in multiple candidate faults (candidate faults composed of a single suspected fault or candidate faults composed of a combination of suspected faults). We count and sort the number of times each single suspected fault appears in all candidate faults. The more times it appears, the more likely it is to be a fault in the actual failed circuit. Therefore, we can evaluate the accuracy of each suspected fault based on the number of times it appears.

[0076] Figure 4 is a schematic diagram of a fault detection device according to an embodiment of the present invention. As shown in Figure 4, the device 20 includes: a first adding module 201, used to select any fault to be detected as a target fault for the analog circuit corresponding to the fault to be detected, and add the target fault to the candidate faults, and obtain the circuit data corresponding to each collection point of the analog circuit under the candidate faults as the first data; and a comparison module 202, used to compare the first data with the second data and the third data respectively, and if the comparison result indicates that there is at least one abnormal data in the third data that is inconsistent with the data of the target collection point in the first data, then at least one other fault to be detected is selected and added to the candidate faults. Wherein, the second data is the circuit data corresponding to each acquisition point in the reference circuit corresponding to the fault circuit to be detected, and the third data is the circuit data corresponding to each acquisition point in the fault circuit to be detected; the abnormal data is the acquisition point data that is inconsistent with the second data, and the target acquisition point is the acquisition point corresponding to the abnormal data; the second adding module 203 is used to perform the operation of obtaining the circuit data corresponding to each acquisition point of the analog circuit under the candidate fault again, until the comparison result indicates that the target acquisition point in the first data is consistent with the target acquisition point in the third data, then the current candidate fault is added to the fault set of the fault circuit to be detected.

[0077] Optionally, the device further includes: a first acquisition module, configured to, after the comparison module compares the first data with the second data and the third data respectively, obtain the intersection of the first acquisition point and the second acquisition point based on the comparison result, as a first fault set; the first acquisition point is the acquisition point corresponding to the abnormal data in the third data, and the second acquisition point is the acquisition point corresponding to the abnormal data in the first data; and a first modification module, configured to, after the comparison module selects at least one other fault to be detected and adds it to the candidate faults, modify the circuit data of the acquisition point corresponding to the first fault set in the fault circuit to be detected to target data; the target data is the data of the acquisition point corresponding to the first fault set in the second data.

[0078] Optionally, the device further includes: a second acquisition module, used to obtain the intersection of the first acquisition point and the third acquisition point based on the comparison result after the comparison module compares the first data with the second data and the third data respectively, as a second fault set; the third acquisition point is the acquisition point corresponding to the non-abnormal data in the first data; and a determination module, used to determine that the target acquisition point in the first data is consistent with the target acquisition point in the third data if the previous second fault set belongs to a subset of the current first fault set after the second addition module performs the operation of obtaining the circuit data corresponding to each acquisition point of the analog circuit under the candidate fault again.

[0079] Optionally, the device further includes a third adding module, which is used to add the current candidate fault to the fault set if, after the comparison module compares the first data with the second data and the third data respectively, the comparison result indicates that any abnormal data in the first data is consistent with the data of the target collection point in the third data.

[0080] Optionally, the device further includes: a rejection module, used to determine that the target fault circuit does not have the target fault after the comparison module compares the first data with the second data and the third data respectively, and if the comparison result indicates that at least one abnormal data in the first data is inconsistent with the data of the target acquisition point in the third data, then the current target fault is rejected from the candidate faults, and the operation of taking any target fault as the target fault and adding the target fault to the candidate faults is re-executed.

[0081] Optionally, the apparatus further includes an execution module, configured to, after the second adding module adds the current candidate fault to the fault set of the fault circuit to be detected, if at least one candidate fault is not determined to be the target fault, execute again the operation of the analog circuit corresponding to the fault circuit to be detected, taking any candidate fault as the target fault and adding the target fault to the candidate faults.

[0082] Optionally, the device further includes: a frequency acquisition module, used to acquire the number of times each of the faults to be detected is repeated in each of the candidate faults in the fault set; and an evaluation module, used to evaluate the accuracy of each of the faults to be detected based on the number of times each of the faults to be detected is repeated.

[0083] In summary, the fault detection device provided in this embodiment of the invention acquires first data of the analog circuit under the candidate fault, and compares the first data with the second data of the reference circuit and the third data of the circuit under test to determine whether the candidate fault matches the actual situation of the circuit under test. Furthermore, if at least one abnormal data point in the third data point is inconsistent with the first data, this embodiment of the invention adds at least one other candidate fault to the candidate fault list, thereby further verifying the case through the candidate fault. This fully verifies the presence of multiple candidate faults in the circuit under test, improving the accuracy of fault detection and the quality of fault diagnosis to a certain extent.

[0084] As the device embodiment is basically similar to the method embodiment, the description is relatively simple, and relevant parts can be found in the description of the method embodiment.

[0085] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. The same or similar parts between the various embodiments can be referred to each other.

[0086] Regarding the request processing apparatus in the above embodiments, the specific manner in which each module performs its operations has been described in detail in the embodiments related to the method, and will not be elaborated upon here.

[0087] This invention also provides an electronic device, including: a processor and a memory for storing processor-executable instructions, wherein the processor is configured to execute the above-described fault detection method.

[0088] Referring to Figure 5, which is a schematic diagram of the structure of an electronic device provided in an embodiment of the present invention. As shown in Figure 5, the electronic device includes: a processor, a memory, a communication interface, and a communication bus. The processor, the memory, and the communication interface communicate with each other through the communication bus. The memory is used to store at least one executable instruction, which causes the processor to execute the fault detection method of the aforementioned embodiment.

[0089] It should be noted that the electronic devices in the embodiments of this application include mobile electronic devices and non-mobile electronic devices.

[0090] The processor can be a CPU (Central Processing Unit), a general-purpose processor, a DSP (Digital Signal Processor), an ASIC (Application Specific Integrated Circuit), a FPGA (Field Programmable Gate Array), or other programmable devices, transistor logic devices, hardware components, or any combination thereof. The processor can also be a combination that implements computational functions, such as a combination of one or more microprocessors, or a combination of a DSP and a microprocessor.

[0091] The communication bus may include a path for transmitting information between the memory and the communication interface. The communication bus may be a PCI (Peripheral Component Interconnect) bus or an EISA (Extended Industry Standard Architecture) bus, etc. The communication bus can be divided into address bus, data bus, control bus, etc. For ease of illustration, only one line is used in Figure 3, but this does not mean that there is only one bus or one type of bus.

[0092] The memory may be ROM (Read Only Memory) or other types of static storage devices that can store static information and instructions, RAM (Random Access Memory) or other types of dynamic storage devices that can store information and instructions, or it may be EEPROM (Electrically Erasable Programmable Read Only Memory), CD-ROM (Compact Disk Read Only), magnetic tape, floppy disk and optical data storage devices, etc.

[0093] This invention also provides a non-transitory computer-readable storage medium, which, when the instructions in the storage medium are executed by the processor of an electronic device (server or terminal), enables the processor to execute the fault detection method shown in FIG1.

[0094] This invention also provides a computer program product containing instructions that, when run on a computer, causes the computer to execute the fault detection method shown in FIG1.

[0095] This application also provides a chip, which includes a processor and a communication interface. The communication interface is coupled to the processor. The processor is used to run programs or instructions to implement the various processes of the above-described fault detection method embodiments and can achieve the same technical effect. To avoid repetition, it will not be described again here.

[0096] It should be understood that the chip mentioned in the embodiments of this application may also be referred to as a system-on-a-chip, system chip, chip system, or system-on-a-chip, etc.

[0097] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. The same or similar parts between the various embodiments can be referred to each other.

[0098] Those skilled in the art will understand that embodiments of the present invention can be provided as methods, apparatus, or computer program products. Therefore, embodiments of the present invention can be implemented wholly or partially by software, hardware, firmware, or any combination thereof. When implemented in software, it can be implemented wholly or partially as a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, all or part of the processes or functions described in the embodiments of the present invention are generated. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, the computer instructions can be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via wired (e.g., coaxial cable, fiber optic, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) means. The computer-readable storage medium can be any available medium accessible to a computer or a data storage device such as a server or data center that integrates one or more available media. The available media may be magnetic media (e.g., floppy disks, hard disks, magnetic tapes), optical media (e.g., DVDs), or semiconductor media (e.g., solid state disks (SSDs)).

[0099] Embodiments of the present invention are described with reference to flowchart illustrations and / or block diagrams of methods, terminal devices (systems), and computer program products according to embodiments of the invention. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing terminal device to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing terminal device, create means for implementing the functions specified in one or more blocks of the flowchart illustrations and / or one or more blocks of the block diagrams.

[0100] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing terminal device to operate in a predictive manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means that implement the functions specified in one or more flowcharts and / or one or more block diagrams.

[0101] These computer program instructions may also be loaded onto a computer or other programmable data processing terminal equipment to cause a series of operational steps to be performed on the computer or other programmable terminal equipment to produce a computer-implemented process, such that the instructions, which execute on the computer or other programmable terminal equipment, provide steps for implementing the functions specified in one or more flowcharts and / or one or more block diagrams.

[0102] Although preferred embodiments of the present invention have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of the embodiments of the present invention.

[0103] The various embodiments in this specification are described in a related manner. Similar or identical parts between embodiments can be referred to mutually. Each embodiment focuses on describing the differences from other embodiments. In particular, the system embodiments are basically similar to the method embodiments, so the description is relatively simple; relevant parts can be referred to the descriptions of the method embodiments.

[0104] It should be noted that the various data-related processes in the embodiments of this application are carried out in compliance with the relevant data protection laws and policies of the country where the location is located, and with the authorization granted by the owner of the corresponding device.

[0105] Finally, it should be noted that in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or terminal device that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or terminal device. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or terminal device that includes said element.

[0106] The above provides a detailed description of the fault detection method, apparatus, electronic device, and readable storage medium provided by the present invention. Specific examples have been used to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only for the purpose of helping to understand the method and core ideas of the present invention. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of the present invention. Therefore, the content of this specification should not be construed as a limitation of the present invention.

Claims

1. A fault detection method, characterized in that, The method includes: for the analog circuit corresponding to the faulty circuit to be detected, taking any fault to be detected as a target fault and adding the target fault to the candidate faults; obtaining the circuit data corresponding to each acquisition point of the analog circuit under the candidate faults as first data; comparing the first data with the second data and the third data respectively; if the comparison result indicates that there is at least one abnormal data in the third data that is inconsistent with the data of the target acquisition point in the first data, then selecting at least one other fault to be detected and adding it to the candidate faults; wherein, the second data is the circuit data corresponding to each acquisition point in the reference circuit corresponding to the faulty circuit to be detected, the third data is the circuit data corresponding to each acquisition point in the faulty circuit to be detected; the abnormal data is the acquisition point data that is inconsistent with the second data, and the target acquisition point is the acquisition point corresponding to the abnormal data; repeating the operation of obtaining the circuit data corresponding to each acquisition point of the analog circuit under the candidate faults until the comparison result indicates that the target acquisition point in the first data is consistent with the target acquisition point in the third data, then adding the current candidate fault to the fault set of the faulty circuit to be detected.

2. The method according to claim 1, characterized in that, After comparing the first data with the second data and the third data respectively, the method further includes: obtaining the intersection of the first collection point and the second collection point based on the comparison result, as a first fault set; the first collection point is the collection point corresponding to the abnormal data in the third data, and the second collection point is the collection point corresponding to the abnormal data in the first data; after selecting at least one other fault to be detected and adding it to the candidate faults, the method further includes: modifying the circuit data of the collection point corresponding to the first fault set in the fault circuit to be detected to target data; the target data is the data of the collection point corresponding to the first fault set in the second data.

3. The method according to claim 2, characterized in that, After comparing the first data with the second data and the third data respectively, the method further includes: obtaining the intersection of the first acquisition point and the third acquisition point based on the comparison result, as a second fault set; the third acquisition point is the acquisition point corresponding to the non-abnormal data in the first data; after performing the operation of obtaining the circuit data corresponding to each acquisition point of the analog circuit under the candidate fault again, the method further includes: if the previous second fault set belongs to a subset of the current first fault set, then determining that the target acquisition point in the first data is consistent with the target acquisition point in the third data.

4. The method according to claim 1, characterized in that, After comparing the first data with the second data and the third data respectively, the method further includes: if the comparison result indicates that any abnormal data in the first data is consistent with the data of the target collection point in the third data, then the current candidate fault is added to the fault set.

5. The method according to claim 1, characterized in that, After comparing the first data with the second data and the third data respectively, the method further includes: if the comparison result indicates that there is at least one abnormal data in the first data that is inconsistent with the data of the target acquisition point in the third data, then it is determined that the target fault does not exist in the fault circuit to be detected, the current target fault is removed from the candidate faults, and the operation of taking any fault to be detected as the target fault and adding the target fault to the candidate faults is re-executed.

6. The method according to any one of claims 1-5, characterized in that, After adding the current candidate fault to the fault set of the fault circuit to be detected, the method further includes: if at least one candidate fault is not determined to be the target fault, performing the operation of adding any candidate fault to the candidate fault set for the analog circuit corresponding to the fault circuit to be detected, taking any candidate fault as the target fault, and adding the target fault to the candidate faults.

7. The method according to any one of claims 1-5, characterized in that, The method further includes: obtaining the number of times each of the faults to be detected in the fault set is repeated in each of the candidate faults; and evaluating the accuracy of each of the faults to be detected based on the number of times each of the faults to be detected is repeated.

8. A fault detection device, characterized in that, The device includes: a first adding module, configured to, for an analog circuit corresponding to a faulty circuit to be detected, take any fault to be detected as a target fault and add the target fault to a list of candidate faults, and acquire circuit data corresponding to each acquisition point of the analog circuit under the candidate faults, as first data; a comparison module, configured to compare the first data with second data and third data respectively, and if the comparison result indicates that at least one abnormal data in the third data is inconsistent with the data of the target acquisition point in the first data, then at least one other fault to be detected is selected and added to the list of candidate faults; wherein, the second data is the circuit data corresponding to each acquisition point in the reference circuit corresponding to the faulty circuit to be detected, the third data is the circuit data corresponding to each acquisition point in the faulty circuit to be detected; the abnormal data is the acquisition point data inconsistent with the second data, and the target acquisition point is the acquisition point corresponding to the abnormal data; a second adding module, configured to, again execute the operation of acquiring the circuit data corresponding to each acquisition point of the analog circuit under the candidate faults, until the comparison result indicates that the target acquisition point in the first data is consistent with the target acquisition point in the third data, then add the current candidate fault to the fault set of the faulty circuit to be detected.

9. An electronic device, characterized in that, The system includes a processor, a communication interface, a memory, and a communication bus, wherein the processor, the communication interface, and the memory communicate with each other via the communication bus; the memory is used to store computer programs; and the processor, when executing the program stored in the memory, implements the method described in any one of claims 1-7.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the program is executed by the processor, it implements the method as described in any one of claims 1-7.

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