EUV photomask and manufacturing method thereof

Abstract

The invention relates to an EUV photomask and a manufacturing method thereof. A method of manufacturing a photomask includes forming a reflective multilayer stack over a substrate, and forming a cap layer over the reflective multilayer stack. An absorber layer is formed over the cap layer, and a hard mask is formed over the absorber layer. An opening is formed in the hard mask exposing the absorber layer. The absorber layer is etched using the hard mask as an etch mask. Etching the absorber layer includes applying a first etching gas to the absorber layer; starting bias power and source power; turning off the bias power and the source power; applying a second etching gas to the absorber layer, where the first etching gas and the second etching gas are different; and turning on the source power without turning on the bias power.

Description

Technical Field

[0001] This disclosure relates to EUV photomasks and methods for manufacturing them. Background Technology

[0002] Photolithography is one of the key operations in semiconductor manufacturing. Photolithography techniques include ultraviolet (UV) lithography, deep UV lithography, and extreme UV (EUV) lithography. The photomask is a crucial component in the photolithography process. Fabricating an EUV photomask with high contrast between high-reflectivity and high-absorption regions is essential. Summary of the Invention

[0003] According to one embodiment of this disclosure, a method for manufacturing a photomask is provided, comprising: forming a reflective multilayer stack on a substrate; forming a cap layer on the reflective multilayer stack; forming an absorption layer on the cap layer; forming a hard mask on the absorption layer; forming an opening in the hard mask to expose the absorption layer; and using the hard mask as an etching mask to etch the absorption layer, wherein etching the absorption layer comprises sequentially performing the following operations: applying a first etching gas to the absorption layer; turning on a bias power and a source power; turning off the bias power and the source power; applying a second etching gas to the absorption layer; wherein the first etching gas and the second etching gas are different; and turning on the source power but not the bias power.

[0004] According to one embodiment of this disclosure, a method for manufacturing a reflective photomask is provided, comprising: forming a hard mask layer on a reflective photomask preform, wherein the reflective photomask preform comprises: a reflective multilayer stack disposed on a substrate; a cap layer disposed on the reflective multilayer stack; and an absorption layer disposed on the cap layer; patterning the hard mask layer to form openings in the hard mask layer; and etching the absorption layer in a chamber using the patterned hard mask layer as an etching mask, wherein etching the absorption layer comprises: a) introducing an oxygen-containing gas into the chamber; b) turning on a bias power and a source power for a first time period; c) turning off the bias power and the source power; d) introducing a fluorocarbon gas into the chamber; and e) turning on the source power for a second time period, and not turning on the bias power during the second time period.

[0005] According to one embodiment of this disclosure, a reflective photomask is provided, comprising: a reflective multilayer stack disposed on a substrate; a cap layer disposed on the reflective multilayer stack; a patterned absorption layer including at least one patterned feature disposed on the cap layer; and a sidewall layer disposed on the sidewall of the at least one patterned feature, wherein the sidewall layer comprises CrO. x F yor CrO x Cl y layers, where 0 < x ≤ 10, and 0 < y ≤ 10. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The present disclosure can be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be emphasized that, in accordance with standard practice in the industry, the various features are not drawn to scale and are for illustrative purposes only. Note that, in accordance with standard practice in the industry, the various features are not drawn to scale.

[0007] Figure 1 is a schematic diagram of an EUV lithography system having a laser-produced plasma (LPP) EUV radiation source according to some embodiments of the present disclosure.

[0008] Figure 2 shows a schematic diagram of an extreme ultraviolet lithography tool according to an embodiment of the present disclosure.

[0009] Figure 3A 、 Figure 3B 、 Figure 3C 、 Figure 3D and Figure 3E shows an EUV photomask blank according to an embodiment of the present disclosure.

[0010] Figure 4A 、 Figure 4B 、 Figure 4C 、 Figure 4D 、 Figure 4E and Figure 4F schematically shows a method of manufacturing an EUV photomask according to an embodiment of the present disclosure.

[0011] Figure 5A 、 Figure 5B 、 Figure 5C 、 Figure 5D and Figure 5E schematically shows a method of manufacturing an EUV photomask according to an embodiment of the present disclosure.

[0012] Figure 6 shows an etching cycle according to an embodiment of the present disclosure.

[0013] Figure 7A 、 Figure 7B and Figure 7C schematically shows a method of manufacturing an EUV photomask according to an embodiment of the present disclosure.

[0014] Figure 8A shows a detailed cross-sectional view of an opening formed in an absorption layer of an EUV photomask according to an embodiment of the present disclosure. Figure 8B [[ID=

[0015] Figure 9A , Figure 9B and Figure 9C A detailed cross-sectional view of the sidewall of an opening formed in the absorbent layer according to an embodiment of the present disclosure is shown.

[0016] Figure 10A , Figure 10B , Figure 10C and Figure 10D A method for manufacturing an EUV photomask according to an embodiment of the present disclosure is illustrated schematically.

[0017] Figure 11 A flowchart illustrating the fabrication of an EUV photomask according to an embodiment of the present disclosure is shown.

[0018] Figure 12 A flowchart illustrating the fabrication of an EUV photomask according to an embodiment of the present disclosure is shown.

[0019] Figure 13 A flowchart illustrating the fabrication of an EUV photomask according to an embodiment of the present disclosure is shown.

[0020] Figure 14 A flowchart illustrating the manufacture of a semiconductor device according to an embodiment of the present disclosure is shown.

[0021] Figure 15 A flowchart illustrating the manufacture of a semiconductor device according to an embodiment of the present disclosure is shown.

[0022] Figure 16A , Figure 16B , Figure 16C and Figure 16D The sequential manufacturing operations of a method for manufacturing a semiconductor device according to embodiments of the present disclosure are illustrated. Detailed Implementation

[0023] It is to be understood that the following disclosure provides many different embodiments or examples for implementing various features of the invention. Specific embodiments or examples of components and arrangements are described below to simplify this disclosure. Of course, these are merely examples and not limiting. For example, the dimensions of elements are not limited to the disclosed range or values, but may depend on the device's manufacturing conditions and / or desired properties. Furthermore, forming a first feature on or over a second feature in the following description may include embodiments where the first and second features are formed in direct contact, and may also include embodiments where an additional feature may be formed between the first and second features such that the first and second features do not need to be in direct contact. For simplicity and clarity, various features may be drawn at any scale.

[0024] Furthermore, for ease of description, this document may use spatially related terms such as “below,” “under,” “down,” “above,” “up,” etc., to describe the relationship between one element or feature as shown in the figure and another element(s) or feature(s). In addition to the orientation depicted in the figure, these spatially related terms are also intended to encompass different orientations of the device in use or operation. The device may be oriented in other directions (rotated 90 degrees or in other orientations), and the spatially related descriptors used herein may be interpreted similarly accordingly. Furthermore, the term “made of” may mean “comprising” or “consisting of.” In this disclosure, the phrase “one of A, B, and C” refers to “A, B, and / or C” (A, B, C, A and B, A and C, B and C, or A, B, and C), and unless otherwise stated, does not refer to an element from A, an element from B, and an element from C.

[0025] Embodiments of this disclosure provide a method for manufacturing an EUV photomask. More specifically, this disclosure provides techniques for improving the contours of circuit patterns formed in the absorption layer of an EUV photomask.

[0026] EUV lithography employs a scanner that uses light in the extreme ultraviolet (EUV) region. The mask is a key component of the EUV lithography system. Because optical materials are opaque to EUV radiation, EUV photomasks are reflective masks. Circuit patterns are formed in an absorption layer disposed above the reflective structure. The absorber has low EUV reflectivity, for example, less than 3% to 5%.

[0027] Figure 1 This is a schematic diagram of an EUV lithography system. The EUV lithography system includes: an EUV radiation source device 100 for generating EUV light; an exposure tool 200, such as a scanner; and an excitation laser source device 300. Figure 1 As shown, in some embodiments, the EUV radiation source device 100 and the exposure tool 200 are mounted on the main layer MF of the cleanroom, while the excitation laser source device 300 is mounted in the base layer BF located below the main layer. The EUV radiation source device 100 and the exposure tool 200 are each placed on base plates PP1 and PP2 via shock absorbers DP1 and DP2, respectively. The EUV radiation source device 100 and the exposure tool 200 are coupled to each other by a coupling mechanism, which may include a focusing unit.

[0028] EUV lithography systems are designed to expose resist layers using EUV light (or EUV radiation). The resist layer is a material sensitive to EUV light. The EUV lithography system employs an EUV radiation source device 100 to generate EUV light, for example, EUV light with wavelengths ranging from about 1 nm to about 100 nm. In a specific example, the EUV radiation source 100 generates EUV light with a wavelength centered at about 13.5 nm. In this embodiment, the EUV radiation source 100 utilizes a laser-generated plasma (LPP) mechanism to generate EUV radiation.

[0029] Exposure tool 200 includes various reflective optical components, such as convex mirrors / concave mirrors / plane mirrors, a mask holding mechanism including a mask stage, and a wafer holding mechanism. EUV radiation generated by EUV radiation source 100 is guided by the reflective optical components onto a mask fixed on the mask stage. In some embodiments, the mask stage includes an electrostatic chuck for holding the mask. Because gas molecules absorb EUV light, the lithography system used for EUV lithography patterning is maintained in a vacuum or low-pressure environment to avoid EUV intensity loss.

[0030] Figure 2 This is a schematic diagram detailing an extreme ultraviolet (EUV) lithography tool according to an embodiment of the present disclosure, illustrating the exposure of a photoresist-coated substrate 210 with a patterned EUV beam. The exposure apparatus 200 is an integrated circuit lithography tool, such as a stepper, scanner, step-scan system, direct-write system, or device using contact and / or proximity masks, etc., and is equipped with: one or more optics 205a, 205b, for example, for generating a patterned beam by irradiating a patterned optics 205c (e.g., a mask) with an EUV beam; and one or more reduction projection optics 205d, 205e for projecting the patterned beam onto the substrate 210. Mechanical assemblies (not shown) may be provided for generating controlled relative movement between the substrate 210 and the patterned optics 205c. Figure 2 As further shown, the EUV lithography tool includes an EUV light source 100, which includes plasma that emits EUV light at ZE in a chamber 105. The EUV light is collected by a collector 110 and reflected along a path to an exposure apparatus 200 to illuminate a substrate 210.

[0031] As used herein, the term "optical device" is intended to be interpreted broadly as including, but not limited to, one or more components that reflect and / or transmit and / or manipulate incident light, and includes, but is not limited to: one or more lenses, windows, filters, wedges, prisms, gratings, optical fibers, etalons, diffusers, homogenizers, detectors, and other instrument components, apertures, axial prisms and mirrors including multilayer mirrors, near-normal incident mirrors, grazing incident mirrors, specular reflectors, diffusers, and combinations thereof. Furthermore, unless otherwise stated, the term "optical device" as used herein is not limited to components that operate within one or more specific wavelength ranges (e.g., EUV output light wavelengths, irradiating laser wavelengths, wavelengths suitable for metrological detection, or any other specific wavelength).

[0032] In this disclosure, the terms "mask," "photomask," and "mask plate" are used interchangeably. In this embodiment, the mask is a reflective mask. An exemplary structure of the mask includes a substrate having a suitable material, such as a low thermal expansion material or fused silica. In various examples, the material includes SiO2 doped with TiO2, or other suitable materials having low thermal expansion. The mask includes multiple reflective layers deposited on the substrate. The multiple layers include multiple film pairs, such as molybdenum-silicon (Mo / Si) film pairs (e.g., in each film pair, a molybdenum layer is above or below a silicon layer). Alternatively, the multiple layers may include molybdenum-beryllium (Mo / Be) film pairs, or other suitable materials that can be configured to highly reflect EUV light. The mask may also include a capping layer (e.g., ruthenium (Ru)) disposed on the ML for protection. The mask also includes an absorption layer (e.g., a chromium nitride (CrN) or tantalum boron nitride (TaBN) layer) deposited on the multiple layers. The absorption layer is patterned to define an integrated circuit (IC) layer. Alternatively, another reflective layer can be deposited on top of multiple layers and patterned to define an integrated circuit layer, thereby forming an EUV phase-shift mask.

[0033] In this embodiment, the semiconductor substrate is a semiconductor wafer to be patterned, such as a silicon wafer or other type of wafer. In this disclosure, the semiconductor substrate is coated with a resist layer sensitive to EUV light. Various components (including those described above) are integrated together and operable to perform a photolithography exposure process. The photolithography system may also include other modules or be integrated (or coupled) with other modules.

[0034] like Figure 1As shown, the EUV radiation source 100 includes a target droplet generator 115 and an LPP collector 110 surrounded by a chamber 105. The target droplet generator 115 generates a plurality of target droplets DP. In some embodiments, the target droplets DP are tin (Sn) droplets. In some embodiments, each tin droplet has a diameter of about 30 micrometers (µm). In some embodiments, the tin droplets DP are generated at a rate of about 50-50,000 droplets per second and introduced into the excitation region ZE at a speed of about 70 meters per second (m / s). Other materials may also be used for the target droplets, such as tin-containing liquid materials, such as tin- or lithium (Li) eutectic alloys.

[0035] The excitation laser LR2 generated by the excitation laser source device 300 is a pulsed laser. In some embodiments, the excitation laser includes a preheating laser and a main laser. The preheating laser pulse is used to heat (or preheat) the target droplet to generate a pancake-shaped, low-density target, which is subsequently heated (or reheated) by the main laser pulse to generate emission-enhanced EUV light. In various embodiments, the preheating laser pulse has a spot size of about 100 µm or less, and the main laser pulse has a spot size of about 200-300 µm.

[0036] The laser pulse LR2 is generated by the excitation laser source 300. The laser source 300 may include a laser generator 310, a laser guiding optics 320, and a focusing device 330. In some embodiments, the laser source 310 includes a carbon dioxide (CO2) or neodymium-doped yttrium aluminum garnet (Nd:YAG) laser source. The laser LR1 generated by the laser generator 300 is guided by the laser guiding optics 320 and focused by the focusing device 330 into the excitation laser LR2, which is then introduced into the EUV radiation source 100.

[0037] The laser LR2 is directed into the excitation region ZE through a window (or lens). The window is made of a suitable material that is substantially transparent to the laser beam. The generation of the pulsed laser is synchronized with the generation of the target droplet. As the target droplet moves through the excitation region, it is pre-pulsed and heated, transforming it into a pancake-shaped, low-density target. The delay between the pre-pulse and the main pulse is controlled to allow the pancake-shaped target to form and expand to an optimal size and geometry. When the main pulse heats the pancake-shaped target, a high-temperature plasma is generated. This plasma emits EUV radiation, which is collected by a collecting mirror 110. The collector 110 has a reflective surface that reflects and focuses the EUV radiation for use in photolithography exposure processes. In some embodiments, a droplet trap 116 is mounted opposite the target droplet generator 115. The droplet trap 116 is used to trap excess target droplets. For example, some target droplets may be intentionally missed by the laser pulse.

[0038] Collector 110 includes a suitable coating material and shape for use as an EUV collecting, reflecting, and focusing mirror. In some embodiments, collector 110 is designed to have an elliptical geometry. In some embodiments, the coating material of collector 110 is similar to a reflective multilayer of an EUV mask. In some examples, the coating material of collector 110 includes multiple layers (e.g., multiple Mo / Si film pairs) and may also include a capping layer (e.g., Ru) coated on the multiple layers to substantially reflect EUV light. In some embodiments, collector 110 also includes a grating structure designed to effectively scatter a laser beam directed onto collector 110. For example, in some embodiments, a silicon nitride layer is coated on collector 110 and patterned to have a grating pattern.

[0039] In this EUV radiation source device, plasma induced by the applied laser generates physical debris (e.g., ions, gases, and atoms of droplets) and the desired EUV radiation. It is necessary to prevent material from accumulating on the collector 110, and it is also necessary to prevent physical debris from leaving the chamber 105 and entering the exposure tool 200.

[0040] like Figure 1 As shown, in some embodiments, buffer gas is supplied from a first buffer gas supplier 130 through an orifice in collector 110, through which pulsed laser light is delivered to the tin droplet. In some embodiments, the buffer gas is H2, He, Ar, N2, or another inert gas. In some embodiments, H2 is used as H radicals generated by the ionization of the buffer gas, which can be used for cleaning purposes. Buffer gas can also be supplied towards collector 110 and / or around the edge of collector 110 through one or more second buffer gas suppliers 135. Furthermore, chamber 105 includes one or more gas outlets 140 such that the buffer gas is discharged outside chamber 105. Hydrogen has low absorption to EUV radiation. Hydrogen reaching the coated surface of collector 110 reacts chemically with the metal of the droplet to form hydrides, such as metal hydrides. When tin (Sn) is used as the droplet, stanane (SnH4) is formed, which is a gaseous byproduct of the EUV generation process. The gaseous SnH4 is then pumped out through outlet 140. However, it is difficult to expel all gaseous SnH4 from the chamber and prevent SnH4 from entering the exposure tool 200. In order to capture SnH4 or other debris, one or more debris collection mechanisms or devices 150 are employed in the chamber 105.

[0041] Figure 3A and Figure 3B An EUV reflective photomask blank according to an embodiment of the present disclosure is shown. Figure 3A It's a floor plan (viewed from the top). Figure 3B It is a cross-sectional view along the X direction.

[0042] In some embodiments, an EUV photomask with a circuit pattern is formed from an EUV photomask blank 5. The EUV photomask blank 5 includes a substrate 10, a multilayer Mo / Si stack 15 of alternating layers of silicon and molybdenum, a capping layer 20, a protective layer 22, an absorber layer 25, and a hard mask layer. In some embodiments, the hard mask layer includes a first hard mask layer 30 and a second hard mask layer 32. In other embodiments, the hard mask layer is a single layer. Furthermore, a back conductive layer 45 is formed on the back side of the substrate 10, such as... Figure 3B As shown. In some embodiments, an oxide layer 27 is formed on the top surface of the absorber layer 25, as illustrated. Figure 3B As shown. In other embodiments, no oxide layer is formed on the top surface of the absorber layer 25, as... Figure 3D As shown.

[0043] In some embodiments, the substrate 10 is formed of a low thermal expansion material. In some embodiments, the substrate is a low thermal expansion glass or quartz, such as fused silica or fused silica. In some embodiments, the low thermal expansion glass substrate transmits light having wavelengths including: visible wavelengths, a portion of the infrared wavelengths near the visible spectrum (near-infrared), and a portion of the ultraviolet wavelengths. In some embodiments, the low thermal expansion glass substrate absorbs extreme ultraviolet wavelengths and deep ultraviolet wavelengths near the extreme ultraviolet. In some embodiments, the substrate 10 has dimensions of 152 mm × 152 mm and a thickness of approximately 20 mm. In other embodiments, the substrate 10 has dimensions less than 152 mm × 152 mm and greater than or equal to 148 mm × 148 mm. The substrate 10 is square or rectangular in shape.

[0044] In some embodiments, the functional layer above the substrate (multilayer Mo / Si stack 15, capping layer 20, protective layer 22, absorber layer 25, first hard mask layer 30 and second hard mask layer 32) has a smaller width than the substrate 10. In some embodiments, the size of the functional layer is in the range of about 138 mm × 138 mm to about 142 mm × 142 mm. In some embodiments, the shape of the functional layer is square or rectangular as shown in the plan view.

[0045] In other embodiments, the protective layer 22, the absorber layer 25, the first hard mask layer 30, and the second hard mask layer 32 have smaller dimensions than the substrate 10, the multilayer Mo / Si stack 15, and the cap layer 20, ranging from approximately 138 mm × 138 mm to approximately 142 mm × 142 mm. Figure 3C As shown. When the individual layers are formed, for example by sputtering, a smaller size for one or more functional layers can be formed by using a frame-shaped cap having an opening ranging from about 138 mm × 138 mm to about 142 mm × 142 mm. In other embodiments, all layers above substrate 10 have the same dimensions as substrate 10.

[0046] In some embodiments, the Mo / Si multilayer stack 15 comprises alternating layers of about 30 to about 60 layers each of silicon and molybdenum. In some embodiments, alternating layers of about 40 to about 50 layers each of silicon and molybdenum are formed. In some embodiments, the reflectivity is greater than about 70% for a wavelength of interest (e.g., 13.5 nm). In some embodiments, the silicon and molybdenum layers are formed by chemical vapor deposition (CVD), plasma-enhanced CVD (PECVD), atomic layer deposition (ALD), physical vapor deposition (PVD) (sputtering), or any other suitable film-forming method. Each silicon and molybdenum layer is about 2 nm to about 10 nm thick. In some embodiments, the silicon and molybdenum layers have approximately the same thickness. In other embodiments, the silicon and molybdenum layers have different thicknesses. In some embodiments, each silicon layer is about 4 nm thick, and each molybdenum layer is about 3 nm thick.

[0047] In other embodiments, the multilayer stack 15 comprises alternating layers of molybdenum and beryllium. In some embodiments, the number of layers in the multilayer stack 15 ranges from about 20 to about 100 layers; however, any number of layers is permissible as long as sufficient reflectivity is maintained for imaging the target substrate. In some embodiments, the reflectivity is greater than about 70% for the wavelength of interest (e.g., 13.5 nm). In some embodiments, the multilayer stack 15 comprises about 30 to about 60 alternating layers of Mo and Be. In other embodiments of this disclosure, the multilayer stack 15 comprises about 40 to about 50 alternating layers of Mo and Be.

[0048] In some embodiments, a capping layer 20 is disposed on top of a Mo / Si multilayer 15 to prevent oxidation of the multilayer stack 15. In some embodiments, the capping layer 20 is made of ruthenium, a ruthenium alloy (e.g., RuNb, RuZr, RuZrN, RuRh, RuNbN, RuRhN, RuV, or RuVN), or a ruthenium-based oxide (e.g., RuO2, RuNbO, RuVO, or RuON) and has a thickness in the range of about 2 nm to about 10 nm. In some embodiments, the thickness of the capping layer 20 is in the range of about 2 nm to about 5 nm. In some embodiments, the capping layer 20 has a thickness of 3.5 nm ± 10%. In some embodiments, the capping layer 20 is formed by CVD, PECVD, ALD, PVD (e.g., sputtering), or any other suitable film-forming method. In other embodiments, a Si layer is used as the capping layer 20.

[0049] In some embodiments, a protective (intermediate) layer 22 is formed between the cap layer 20 and the absorber layer 25. In some embodiments, the protective layer 22 protects the cap layer 20. In some embodiments, the protective layer 22 comprises a Ta-based material, such as TaB, TaO, TaBO, or TaBN; silicon; a silicon-based compound (e.g., silicon oxide, silicon nitride, SiON, or MoSi); ruthenium; or a ruthenium-based compound (Ru or RuB). In some embodiments, the protective layer 22 has a thickness of about 2 nm to about 20 nm. In some embodiments, the protective layer 22 is formed by CVD, PECVD, ALD, PVD, or any other suitable film-forming method. In some embodiments, the protective layer 22 serves as an etch stop layer during the patterning operation of the absorber layer.

[0050] In other embodiments, the intermediate layer 22 is a photocatalytic layer that can catalyze hydrocarbon residues formed on the photomask into CO2 and / or H2O using EUV radiation. This performs in-situ self-cleaning of the mask surface. In some embodiments, oxygen and hydrogen are injected into the EUV chamber in the EUV scanner system to maintain chamber pressure (e.g., about 2 Pa). The chamber background gas can be a source of oxygen. In addition to its photocatalytic function, the photocatalytic layer is designed to have sufficient durability and resistance to a variety of chemicals and chemical processes (e.g., cleaning and etching). Ozoned water can be used in subsequent processes to fabricate EUV reflective masks. Ozoned water may damage the cap layer 20 made of Ru, which can lead to a significant decrease in EUV reflectivity. Furthermore, after Ru oxidation, Ru oxide is easily etched away by etchants (e.g., Cl2 or CF4 gas). In some embodiments, the photocatalytic layer comprises one or more of titanium dioxide (TiO2), tin oxide (SnO), zinc oxide (ZnO), and cadmium sulfide (CdS). The thickness of the photocatalytic layer 22 is in the range of about 2 nm to about 10 nm in some embodiments, and in the range of about 3 nm to about 7 nm in other embodiments. When the thickness is too thin, the photocatalytic layer may be insufficient to serve as an etch stop layer. When the thickness is too large, the photocatalytic layer may absorb EUV radiation.

[0051] In some embodiments, the intermediate layer 22 is an antireflective layer. In some embodiments, the antireflective layer 22 is made of silicon oxide and has a thickness of about 2 nm to about 10 nm. In other embodiments, a TaBO layer having a thickness in the range of about 12 nm to about 18 nm is used as the antireflective layer 22. In some embodiments, the thickness of the antireflective layer 22 is in the range of about 3 nm to about 6 nm. In some embodiments, the antireflective layer 22 is formed by CVD, PECVD, ALD, PVD, or any other suitable film-forming method.

[0052] In some embodiments, the absorber layer 25 is disposed above the intermediate (protective) layer 22. In some embodiments, the absorber layer 25 comprises a Cr-based material, such as Cr, CrN, CrON, and / or CrCON. In some embodiments, in the case of CrON or CrCON, the nitrogen content is in the range of about 10 atomic% to about 30 atomic%. In some embodiments, the absorber layer 25 has a multilayer structure of Cr, CrN, CrON, and / or CrCON.

[0053] In some embodiments, the CrN layer is used as absorber layer 25. In some embodiments, when the CrN layer is used, the nitrogen content is in the range of about 16 atomic% to about 40 atomic%. When the nitrogen content is in the range of about 16 atomic% to about 30 atomic%, the CrN absorber layer comprises a Cr phase and a Cr2N phase. When the nitrogen content is in the range of about 30 atomic% to about 33 atomic%, the CrN absorber layer is essentially composed of the Cr2N phase (e.g., greater than 95 vol%). When the nitrogen content is in the range of about 33 atomic% to about 40 atomic%, the CrN absorber layer comprises a Cr2N phase and a CrN phase. These phases can be observed by electron energy loss spectroscopy (EELS), transmission electron microscopy (TEM), and / or X-ray diffraction (XRD) analysis. In some embodiments, the two phases form a solid solution.

[0054] In some embodiments, the nitrogen concentration in the absorber layer 25 is non-uniform. In some embodiments, the nitrogen concentration in the middle or center of the absorber layer 25 is higher than that in the surface region of the absorber layer 25. In some embodiments, the CrN absorber layer includes one or more impurities other than Cr and N, the content of which is less than about 5 atomic%. In some embodiments, the absorber layer 25 also includes one or more elements selected from Co, Te, Hf and / or Ni.

[0055] The thickness of the absorber layer 25 is in the range of about 20 nm to about 50 nm in some embodiments, and in the range of about 35 nm to about 46 nm in other embodiments.

[0056] In some embodiments, the oxide layer 27 comprises one or more of Cr2O3 or CrO2. In some embodiments, the oxide layer 27 is formed during the fabrication operation of the mask preform. In some embodiments, the thickness of the oxide layer 27 is in the range of about 1 nm to about 3 nm. In some embodiments, such as Figure 3D As shown, no oxide layer is formed.

[0057] In some embodiments, a first hard mask layer 30 is disposed on oxide layer 27. In some embodiments, the first hard mask layer 30 is formed on absorber layer 25. In some embodiments, the first hard mask layer 30 is made of a Ta-based material, such as TaB, TaO, TaBO, or TaBN. In other embodiments, the first hard mask layer 30 is made of silicon, a silicon-based compound (e.g., silicon oxide, silicon nitride, SiON, or MoSi), ruthenium, or a ruthenium-based compound (Ru or RuB). In some embodiments, the first hard mask layer 30 is made of the same or similar material as protective layer 22. In some embodiments, the first hard mask layer 30 has a thickness of about 2 nm to about 20 nm. In some embodiments, the first hard mask layer 30 is formed by CVD, PECVD, ALD, PVD, or any other suitable film-forming method.

[0058] In some embodiments, a second hard mask layer 32 is disposed above a first hard mask layer 30. In some embodiments, the second hard mask layer 32 is made of one or more of GaN, CrON, CrCON, silicon oxide, SiCO, and / or yttrium oxide. In some embodiments, the second hard mask layer 32 has a thickness of about 2 nm to about 20 nm. In some embodiments, the thickness of the second hard mask layer 32 is less than or greater than the thickness of the first hard mask layer. In some embodiments, the second hard mask layer 32 is formed by CVD, PECVD, ALD, PVD, or any other suitable film-forming method.

[0059] In some embodiments, for plasmas including chlorine and oxygen, the second hard mask layer 32 is made of a material with an etch rate higher than that of the first hard mask layer 30. In some embodiments, for plasmas including fluorine, the first hard mask layer 30 is made of a material with an etch rate higher than that of the second hard mask layer 32.

[0060] In some embodiments, one or more functional layers above the substrate (multilayer Mo / Si stack 15, capping layer 20, protective layer 22, absorber layer 25, oxide layer 27, first hard mask layer 30 and second hard mask layer 32) have a polycrystalline structure (e.g., nanocrystalline structure) or an amorphous structure.

[0061] In some embodiments, a back conductive layer 45 is disposed on a second main surface of the substrate 10, which is opposite to a first main surface of the substrate 10 on which a Mo / Si multilayer stack 15 is formed. In some embodiments, the back conductive layer 45 is formed of TaB (tantalum boride) or other Ta-based conductive materials. In some embodiments, tantalum boride is crystalline. Crystalline tantalum boride includes TaB, Ta5B6, Ta3B4, and TaB2. In other embodiments, tantalum boride is polycrystalline or amorphous. In other embodiments, the back conductive layer 45 is made of a Cr-based conductive material (CrN or CrON). In some embodiments, the sheet resistance of the back conductive layer 45 is equal to or less than 20 Ω / □. In some embodiments, the sheet resistance of the back conductive layer 45 is equal to or greater than 0.1 Ω / □. In some embodiments, the surface roughness Ra of the back conductive layer 45 is equal to or less than 0.25 nm. In some embodiments, the surface roughness Ra of the back conductive layer 45 is equal to or greater than 0.05 nm. Furthermore, in some embodiments, the flatness of the back conductive layer 45 is equal to or less than 50 nm (within an EUV photomask). In some embodiments, the flatness of the back conductive layer 45 is greater than 1 nm. In some embodiments, the thickness of the back conductive layer 45 is in the range of about 50 nm to about 400 nm. In other embodiments, the back conductive layer 45 has a thickness of about 50 nm to about 100 nm. In some embodiments, the thickness is in the range of about 65 nm to about 75 nm. In some embodiments, the back conductive layer 45 is formed by atmospheric pressure CVD, low pressure CVD, PECVD, laser-enhanced CVD, ALD, molecular beam epitaxy (MBE), PVD (including thermal deposition, pulsed laser deposition, electron beam evaporation, ion beam assisted evaporation, and sputtering), or any other suitable film-forming method. In some embodiments, in the case of CVD, the source gas includes TaCl5 and BCl3.

[0062] In some embodiments, such as Figure 3E As shown, a substrate protective layer 12 is formed between the substrate 10 and the multilayer stack 15. In some embodiments, the substrate protective layer 12 is formed of Ru or a Ru compound (e.g., RuO, RuNb, RuNbO, RuZr, and RuZrO). In some embodiments, the substrate protective layer 12 is formed of the same or a different material as the capping layer 20. In some embodiments, the thickness of the substrate protective layer 12 is in the range of about 2 nm to about 10 nm.

[0063] Figures 4A to 4F as well as Figures 5A to 5E A method for fabricating an EUV photomask for EUV lithography is illustrated schematically. It should be understood that it is possible to... Figures 4A to 5EAdditional operations are provided before, during, and after the process shown, and some of the operations described below may be replaced or eliminated for additional embodiments of the method. The order of operations / processes may be interchanged.

[0064] In some embodiments, such as Figure 4A As shown, in the fabrication of the EUV photomask, a first photoresist layer 35 is formed on the second hard mask layer 32 of the EUV photomask blank 5, and as... Figure 4B As shown, the photoresist layer 35 is selectively exposed to photochemical radiation EB. In some embodiments, the EUV photomask preform is inspected prior to the formation of the first photoresist layer 35. The selectively exposed first photoresist layer 35 is developed to form a pattern 40 including at least one opening in the first photoresist layer 35, as shown. Figure 4C As shown. In some embodiments, the photochemical radiation EB is an electron beam or an ion beam. In some embodiments, pattern 40 corresponds to a pattern of semiconductor device features, which will be formed in subsequent operations using an EUV photomask. In some embodiments, the thickness of the first photoresist layer on the second hard mask layer 32 is in the range of about 500 nm to about 1000 nm.

[0065] Next, as Figure 4D As shown, a pattern 40 in the first photoresist layer 35 is extended into the second hard mask layer 32, thereby forming a pattern 41 in the second hard mask layer 32 including at least one opening that exposes a portion of the first hard mask layer 30. In some embodiments, the pattern 41 extended into the second hard mask layer 32 is formed by etching using a suitable wet or dry etchant selectively applied to the first hard mask layer 30. In some embodiments, the second hard mask layer 32 is patterned using a plasma dry etching operation containing chlorine gas (e.g., Cl2, HCl, BCl, and CCl4) and oxygen gas (e.g., O2). In some embodiments, the material of the first hard mask layer 30 is selected to have high etch resistance (lower etch rate) to plasma dry etching operations using chlorine and oxygen, and the etching essentially stops at the first hard mask layer 30. After forming the pattern 41 in the second hard mask layer 32, the first photoresist layer 35 is removed by a photoresist stripper to expose the upper surface of the second hard mask layer 32, as shown. Figure 4E As shown.

[0066] Next, in some embodiments, the pattern 41 in the second hard mask layer 32, including at least one opening, is extended into the first hard mask layer 30, thereby exposing portions of the oxide layer 27, such as... Figure 4FAs shown. In some embodiments, the pattern 41 extending into the first hard mask layer 30 is formed by etching with a suitable wet or dry etchant that is selective to the oxide layer 27. In some embodiments, a plasma dry etching operation using a fluorine-containing gas (e.g., fluorocarbons (CF4, CHF3, etc.) and SF6) is used to pattern the first hard mask layer 30. In some embodiments, the material of the absorber layer 27 is selected to have high resistance to etch (lower etch rate) in plasma dry etching operations using fluorine, and the etching substantially stops at the oxide layer 27.

[0067] Then, in some embodiments, the pattern 41 in the first hard mask layer 30 and the second hard mask layer 32 is extended into the absorber layer 25, thereby forming the pattern 41 in the absorber layer 25, the pattern 41 exposing a portion of the intermediate layer 22, such as... Figure 5A As shown. The oxide layer 27 and the absorber layer 25 are etched using a suitable wet or dry etchant that is selective for the first hard mask layer 30 and / or the intermediate layer 22. In some embodiments, the material of the intermediate layer 22 is selected to have high etch resistance (lower etch rate) to plasma dry etching operations using chlorine and oxygen, and the etching substantially stops at the intermediate layer 22. In some embodiments, as Figure 5A As shown, the second hard mask layer 32 is removed during the etching of oxide layer 27 and absorber layer 25. Specifically, when the second hard mask layer 32 is made of a Cr-based material (e.g., CrN, CrON, or CrCON), the second hard mask layer 32 is removed during the etching of oxide layer 27 and absorber layer 25. If the second hard mask layer 32 is retained after etching absorber layer 25, in some embodiments, an additional removal operation of the second hard mask layer 32 is performed using suitable wet etching or dry etching.

[0068] Then, remove the portion of the first hard mask layer 30 and the intermediate layer 22 located at the bottom of the pattern opening, such as... Figure 5B As shown. In some embodiments, etching is wet etching and / or dry etching. In some embodiments, a plasma dry etching operation using a fluorine-containing gas (e.g., fluorocarbons (CF4, CHF3, etc.) and SF6) is used to remove the first hard mask layer 30 and the intermediate layer 22. Specifically, when the first hard mask layer 30 is made of the same or similar material as the intermediate layer 22, the first hard mask layer 30 is removed together with the intermediate layer 22. In some embodiments, the material of the cap layer 20 is selected to have high resistance to etching (lower etching rate) in plasma dry etching operations using fluorine, and etching substantially stops at the cap layer 20.

[0069] like Figure 5CAs shown, a second photoresist layer 50 is formed over the oxide layer 27 and the absorption layer 25, thereby filling the pattern 42 in the absorption layer 25. The second photoresist layer 50 is selectively exposed to photochemical radiation, such as an electron beam, ion beam, or UV radiation. The selectively exposed second photoresist layer 50 is developed to form a pattern 55 in the second photoresist layer 50, as shown. Figure 5C As shown. Pattern 55 corresponds to the black boundary surrounding the circuit pattern. The black boundary is a frame-shaped region created by removing all multilayers in the area surrounding the circuit pattern region on the EUV photomask. The black boundary pattern can be generated to prevent exposure of adjacent fields when transferring the EUV photomask onto the wafer. In some embodiments, the width of the black boundary is in the range of about 1 mm to about 5 mm.

[0070] Next, in some embodiments, the pattern 55 in the second photoresist layer 50 is extended into the oxide layer 27, the absorber layer 25, the optional intermediate layer 22, the capping layer 20, and the Mo / Si multilayer 15, thereby forming the pattern 57 in the oxide layer 27, the absorber layer 25, the intermediate layer 22, the capping layer 20, and the Mo / Si multilayer 15 (see...). Figure 5E Pattern 57 exposes a portion of substrate 10, such as Figure 5D As shown. Pattern 57 can be formed by etching using one or more suitable wet or dry etchants that selectively etch each layer. In some embodiments, plasma dry etching is used.

[0071] Then, the second photoresist layer 50 is removed using a suitable photoresist stripper to expose the upper surface of the oxide layer 27, thereby forming a photomask with a circuit pattern 42, such as... Figure 5E As shown. In some embodiments of this disclosure, black boundary patterns 57 in the oxide layer 27, absorber layer 25, intermediate layer 22, cap layer 20, and Mo / Si multilayer 15 define the black boundaries of the photomask. Furthermore, the photomask undergoes cleaning operations, inspection, and repair as needed to provide a finished photomask.

[0072] The etching of the absorber layer 25 according to embodiments of the present disclosure will be explained in further detail. The etching gas used in the etching of the absorber layer includes a mixture of chlorine and oxygen, or a mixture of fluorocarbon gas and oxygen. In some embodiments, the fluorocarbon gas includes C X H Y F Z, where 0 < X ≤ 10, 0 ≤ Y ≤ 12, and 0 < Z ≤ 12. In some embodiments, a plasma dry etching operation using a chlorine-containing gas (e.g., Cl2, HCl, BCl, etc.) and an oxygen-containing gas (e.g., O2) or a fluorine-containing gas (e.g., CF4, CHF3, C2F6, and C4F8) and an oxygen-containing gas is used to pattern the absorption layer 25.

[0073] During the etching of the absorption layer, etching by-products are formed on the sidewalls of the openings formed in the absorption layer. For example, when the absorption layer 25 is made of a Cr-based material (e.g., CrN), various reaction by-products of chromium and the etching gas are formed on the sidewalls of the openings. In some embodiments, the by-products deposited on the sidewalls include CrO x F y or CrO x Cl y layers, where 0 < x ≤ 10 and 0 < y ≤ 10. In addition, when the hard mask layer includes a second hard mask layer made of a Ta-based material (e.g., TaBO or TaBN) and / or includes an intermediate layer made of a Ta-based material, by-products of the etching gas and the Ta-based material can be formed on the sidewalls of the openings in the absorption layer.

[0074] Examples of the reactions of the hard mask layer and the intermediate layer with the etching gas and the by-products formed on the sidewalls of the openings are shown below. The reactions and the by-products formed during the etching are not limited to the following examples: Cr + O2 + 2F → CrO2F2 Cr + O2 → CrO2 CrO2 + 2F → CrO2F2 Cr + O2 + Cl2 → CrO2Cl2 Cr + Cl2 → CrCl2 CrCl2 + O2 → CrO2Cl2 2CF4 + O2 + TaO → TaF x + COF y + CO2, where x + y = 8 2TaBN + 8Cl2 → 2TaCl5 + 2BCl3 + N2.

[0075] The by-product sidewalls may have a shallow substrate inclination angle (e.g., less than about 75°) at the bottom of the openings, thereby further reducing the size of the openings. The etching by-product sidewalls formed during the etching operation may reduce the resolution of the mask and thus deteriorate the pattern formed in the photoresist layer using the mask.

[0076] In embodiments of the present disclosure, the etching gas is circulated during the etching operation to limit the growth of the by-product sidewalls in the openings when etching the absorption layer. The circulation of the applied etching gas according to some embodiments is in Figure 6 Shown in Figure 6 . In step 1, a first etching gas is applied, and in step 2, a first etching gas and a second etching gas are applied. In some embodiments, the cycle of steps 1 and 2 is repeated until the etching operation is completed. In some embodiments, in step 1, the first etching gas is introduced into the etching chamber for a first period of time A, and then in step 1, the source power and the bias power are turned on for a second period of time B. After the first period and the second period, the source power and the bias power are turned off, and then in step 2, the first etching gas and the second etching gas are introduced into the etching chamber for a third period of time C. Next, in step 2, the source power is turned on without turning on the bias power for a fourth period of time D. In some embodiments, an over-etch operation is performed after repeating the etching cycle operation.

[0077] In some embodiments, the first etching gas is an oxygen-containing gas (e.g., O2), and the second etching gas is a chlorine-containing gas (e.g., Cl2) or a fluorine-containing gas (e.g., C X H Y F Z , where 0 < X ≤ 10, 0 ≤ Y ≤ 12, and 0 < Z ≤ 12). In some embodiments, a noble gas or an inert gas (e.g., Ar) is included with the first etching gas and / or the second etching gas to assist in plasma stabilization and control the etching rate and selectivity. In some embodiments, the source power is in the range of about 50 W to about 3000 W, and in other embodiments, the source power is in the range of about 100 W to about 2500 W. In some embodiments, the bias power is in the range of about 5 V to about 500 V, and in other embodiments, the bias power is in the range of about 10 V to about 400 V. At source power and bias power outside the disclosed ranges, there may be under-etching or loss of control over the etching operation, and the resulting etched pattern profile may be unsatisfactory.

[0078] In some embodiments, the first time period A is in the range of 0 to about 100 s, the second time period B is in the range of greater than 0 s to about 100 s, the third time period C is in the range of 0 s to about 100 s, and the fourth time period D is in the range of greater than 0 s to about 100 s. In some embodiments, the first time period A and / or the third time period C is 0 s. In other words, the introduction of the first etching gas occurs substantially simultaneously with the activation of the source power and bias power in step 1, and / or the introduction of the second etching gas occurs substantially simultaneously with the activation of the source power in step 2. In some embodiments, the length of step 1, in which the first etching gas is applied, is in the range of about 3 s to about 30 s; and the length of step 2, in which the first etching gas and the second etching gas are applied, is in the range of about 2 s to about 20 s. In an embodiment, the length of step 1 is 7 ± 2 s, and the length of step 2 is 5 ± 2 s. In some embodiments, the etching operation is performed for a period of time in the range of about 5 s to about 50 s. In an embodiment, the etching operation is performed for 30 ± 2 s. Etching time periods outside the disclosed range may result in insufficient etching or loss of control over the etching operation, and the resulting etched pattern profile may be unsatisfactory.

[0079] In some embodiments, the pressure within the etching chamber is in the range of about 1 mTorr to about 100 mTorr. At etching pressures outside the disclosed range, under-etching or loss of control over the etching operation may occur, and the resulting etched pattern profile may be unsatisfactory.

[0080] Figure 7A , Figure 7B and Figure 7C A detailed view schematically showing the opening 42 formed in the absorption layer 25 is shown. Figure 7A An opening 41 formed in the first hard mask layer 30 and the second hard mask layer 32 is shown. (See diagram.) Figure 7B As shown, the second hard mask layer is removed, and the cyclic etch operation disclosed herein is performed to extend the opening 41 through the absorber layer 25. Then, in some embodiments, the first hard mask layer is removed, and an intermediate layer is etched to form a circuit pattern opening 42 in the mask, as shown. Figure 7C As shown.

[0081] Figure 8A A detailed cross-sectional view of a circuit pattern opening 42 formed in an absorption layer 25 of an EUV photomask according to an embodiment of the present disclosure is shown. As shown, etching byproduct sidewalls 65 are formed on the sidewalls of the opening 42 in the absorption layer. In some embodiments, the etching byproduct sidewalls extend over the upper surface of the absorption layer 25.

[0082] Figure 8BA detailed cross-sectional view is shown of a sidewall formed in an opening 42 in an absorber layer 25 according to an embodiment of the present disclosure. In some embodiments, the sidewall comprises two or more sidewalls, depending on the different etching operations and the amounts of different etching gases used. For example, in some embodiments, the main etching operation cycles through a first oxygen etching step and a second oxygen and C step. X H Y F Z The etching process is as disclosed herein. In this case, the sidewall 65 will be made of CrO2F2. In other embodiments, a main etching operation forms a first sidewall 65a made of CrO2F2. Following the main etching operation is an over-etching using a mixed gas of Cl2 and O2 to obtain a second sidewall 65b made of CrO2Cl2. In some embodiments, the thickness of the first sidewall 65a is in the range of about 1 nm to about 3 nm, and the thickness of the second sidewall 65b is in the range of about 0 nm to about 3 nm. In an embodiment, the thickness of the first sidewall is 2 ± 1 nm, and the thickness of the second sidewall is 1.7 ± 1 nm.

[0083] Figure 9A , Figure 9B and Figure 9C A detailed cross-sectional view of a sidewall 65 formed in an opening 42 in an absorbent layer 25 according to an embodiment of the present disclosure is shown. Figure 9A The etching operation is shown to include an O2 etching step and an O2+C etching step. X H Y F Z An example of an alternating cycle of etching steps. For example... Figure 9A As shown, in this embodiment, a base tilt angle α of 77.8 ± 2° is formed. Figure 9B An embodiment is shown in which the O2 etching step and O2+C X H Y F Z The alternating cycle of etching steps is followed by the use of O2+C X H Y F Z The etching gas mixture is used for over-etching for approximately 30 seconds. (Example: ...) Figure 9B As shown, in this embodiment, a base tilt angle α of 77.4 ± 2° is formed. Figure 9C An embodiment is shown in which the O2 etching step and O2+C X H Y F Z After alternating cycles of etching steps, an over-etching process is performed for approximately 30 seconds using an O2+Cl2 etching gas mixture. Figure 9C As shown, in this embodiment, a base tilt angle α of 88.5 ± 2° is formed.

[0084] Figure 10A , Figure 10B, Figure 10C and Figure 10D A cross-sectional view of a multilayer structure of an absorber layer according to another embodiment of the present disclosure is shown. It should be understood that... Figure 10A-10D Additional operations are provided before, during, and after the illustrated process. In other embodiments of the method, some of the operations described below may be replaced or eliminated. The order of operations / processes may be interchangeable. The materials, configurations, processes, and / or dimensions explained for the foregoing embodiments may be used in the following embodiments, and therefore detailed descriptions of them may be omitted. Figure 10A , Figure 10B and Figure 10C The embodiments are applied to, for example Figure 3D The mask blank shown, in Figure 3D In this case, no oxide layer is formed on the absorber layer 25. Figure 10A The structure after the hard mask layer 30 is patterned is shown, similar to Figure 4F The etching of the first hard mask layer 30 essentially stops at the absorber layer 25.

[0085] Then, the absorber layer 25 is patterned (etched) using a patterned first hard mask layer and a second hard mask layer, as shown. Figure 10B As shown. In some embodiments, as Figure 10B As shown, the second hard mask layer 32 is removed during the etching of the absorber layer 25. In some embodiments, when the intermediate layer 22 is made of the same or similar material as the first hard mask layer 30, the etching substantially stops at the intermediate layer 22. Then, as... Figure 10C As shown, the first hard mask layer 30 and the portion of the intermediate layer 22 at the bottom of the opening pattern of the absorption layer 25 are removed together.

[0086] Figure 10D A cross-sectional view of a finished EUV photomask according to an embodiment of the present disclosure is shown. In some embodiments, such as Figure 10D The EUV photomask with circuit pattern 42 shown includes a substrate 10, a multilayer Mo / Si stack 15 of alternating layers of silicon and molybdenum, a capping layer 20, and a patterned absorption layer 25. Furthermore, a black boundary pattern 57 is formed in the absorption layer 25, the capping layer 20, and the Mo / Si multilayer 15, and a back conductive layer 45 is formed on the back side of the substrate 10. In some embodiments, the patterned absorption layer 25 includes a CrN layer or a nitrogen-rich CrON or CrCON layer, wherein, in some embodiments, the nitrogen content is in the range of about 10 atomic% to about 30 atomic%.

[0087] Typically, Cr-based materials (CrN, CrON, or CrCON) have high EUV absorption (extinction) coefficients, k. For example, CrN has a k value of 0.0387, which is higher than that of TaBN (0.031) and TaBO (0.027). Therefore, the thickness of the absorption layer can be reduced (e.g., from 70 nm for TaBN to 46 nm for CrN), which can suppress the three-dimensional effects of the patterned absorption layer. However, CrN layers or nitrogen-rich CrON or CrCON layers are difficult to etch due to their low etching rates. In some embodiments, two hard mask layers are used to pattern the absorption layer to help control the pattern profile of the etched pattern. Therefore, the resolution of EUV lithography can be further improved, and masks with higher EUV absorption coefficients can be provided.

[0088] Figure 11 A flowchart of a method 1100 for manufacturing an EUV photomask according to an embodiment of the present disclosure is shown. In operation S1105, a reflective multilayer stack 15 is formed on a substrate 10. In operation S1110, a capping layer 20 is formed on the reflective multilayer stack 15. Then, in operation S115, an absorption layer 25 is formed on the capping layer 20, and in operation S1120, hard masks 30 and 32 are formed on the absorption layer 25. In operation S1125, an opening 41 is formed in the hard masks 30 and 32, thereby exposing the absorption layer 25 in operation S1125. In operation S1130, the absorption layer is etched using the hard masks 30 and 32 as etch masks. In operation S1130, etching the absorption layer 25 sequentially includes: operation S1135, applying a first etching gas to the absorption layer; operation S1140, turning on the bias power and source power; operation S1145, turning off the bias power and source power; operation S1150, applying a second etching gas to the absorption layer, wherein the first etching gas and the second etching gas are different; and operation S1155, turning on the source power but not the bias power. In some embodiments, before forming the absorption layer in operation S1115, an anti-reflective layer 22 is formed on top of the cap layer in operation S1160.

[0089] Figure 12A flowchart of a method 1200 for manufacturing an EUV photomask according to an embodiment of the present disclosure is shown. In operation S1205, hard mask layers 30 and 32 are formed on a reflective photomask blank 5. The reflective photomask blank 5 includes: a reflective multilayer stack 15 disposed on a substrate 10; a cap layer 20 disposed on the reflective multilayer stack 15; and an absorption layer 25 disposed on the cap layer 20. In operation S1210, the hard mask layers 30 and 32 are patterned to form openings 41 in the hard mask layers. In operation S1215, the patterned hard mask layers are used as etching masks to etch the absorption layer 25 in a chamber. Etching the absorber layer in operation S1215 includes the following operations: operation S1220, a) introducing oxygen-containing gas into the chamber; operation S1225, b) turning on the bias power and source power for a first time period; operation S1230, c) turning off the bias power and source power; operation S1235, d) introducing fluorocarbon gas into the chamber; and operation S1240, e) turning on the source power for a second time period, and not turning on the bias power during the second time period. In some embodiments, method 1200 includes repeating operation S1245 of operations a) to e).

[0090] Figure 13 A flowchart of a method 1300 for manufacturing an EUV photomask according to an embodiment of the present disclosure is shown. Method 1300 includes operation S1305, in which a hard mask layer 30, 32 comprising a first tantalum compound is formed on a photomask preform 5. The photomask preform includes: a reflective multilayer stack 15 disposed on a substrate 10; a capping layer 20 disposed on the reflective multilayer stack 15; an intermediate layer 22 comprising a second tantalum compound disposed on the capping layer 20; and an absorption layer 25 disposed on the intermediate layer 22. In operation S1310, the hard mask layers 30, 32 are patterned by photolithography to expose portions of the absorption layer 25. In operation S1315, the patterned hard mask layers are used as an etching mask to etch the absorption layer in a chamber to form an opening 42 in the absorption layer 25. Etching the absorber layer in operation S1315 includes the following operations: S1320, a) introducing oxygen-containing gas into the chamber; S1325, b) turning on the bias power and source power for a first time period; S1330, c) turning off the bias power and source power; S1335, d) introducing a fluorocarbon gas into the chamber; S1340, e) turning on the source power for a second time period, and not turning on the bias power during the second time period; and S1345, f) forming a sidewall layer comprising the reaction products of the oxygen-containing gas, the fluorocarbon gas, and the absorber layer on the sidewall of the opening. In some embodiments, method 1300 includes repeating operations a), b), c), d), and e) in operation S1350. In some embodiments, method 1300 includes performing an over-etching operation using an over-etching gas in operation S1355.

[0091] Figure 14 FIG. 1400 is a flow chart of a method of manufacturing a semiconductor device according to an embodiment of the present disclosure. In operation S1405, a hard mask layer 30, 32 is formed over a photomask blank 5. The photomask blank 5 includes: a reflective multi-layer stack 15 disposed over a substrate 10; a cap layer 20 disposed over the reflective multi-layer stack 15; and an absorption layer 25 disposed over the cap layer 20. In operation S < 1410>, an opening 41 is formed in the hard mask layer, and the opening 41 exposes the absorption layer 25. In operation S1415, the absorption layer 25 is etched using the hard mask layer as an etch mask to form a patterned photomask. The etching of the absorption layer includes the following operations: S1420, introducing a first etch gas into a chamber containing the photomask blank 5; S1425, turning on a bias power and a source power for a first period of time; S1430, turning off the bias power and the source power after the first period of time; S1435, introducing a second etch gas into the chamber after turning off the bias power and the source power, wherein the first etch gas and the second etch gas are different; and S1440, after introducing the second etch gas, turning on the source power for a second period of time without turning on the bias power. In operation S1445, a pattern is formed in a photoresist layer disposed over a semiconductor substrate using the patterned photomask. In some embodiments, forming a pattern in the photoresist layer using the patterned photomask includes operations S1450, directing actinic radiation towards the patterned photomask such that the actinic radiation is reflected from the patterned photomask and directing the reflected actinic radiation towards the photoresist layer to form a latent pattern in the photoresist layer; and operation S1455, developing the latent pattern to form a pattern in the photoresist layer.

[0092] Figure 15 FIG. 1500 is a flow chart of a method of manufacturing a semiconductor device according to an embodiment of the present disclosure. In operation S1505, actinic radiation is directed from an actinic radiation source towards a reflective photomask. The reflective photomask includes: a reflective multi-layer stack 15 disposed over a substrate 10; a cap layer 20 disposed over the reflective multi-layer stack 15; a patterned absorption layer 25 disposed over the cap layer, including at least one pattern feature; and a sidewall layer disposed over a sidewall of the at least one pattern feature. The sidewall includes CrO x F y or CrO x Cl y layer, where 0 < x ≤ 10 and 0 < y ≤ 10. In operation S1510, the patterned actinic radiation reflected from the reflective photomask is directed towards a semiconductor substrate coated with a photoresist layer to form a latent pattern in the photoresist layer. Then, in operation S1515, a developer is applied to the photoresist layer to develop the latent pattern and form a pattern in the photoresist layer.

[0093] Figure 16A , Figure 16B , Figure 16C and Figure 16D The sequential manufacturing operations of a method for manufacturing a semiconductor device according to embodiments of the present disclosure are illustrated. A semiconductor substrate or other suitable substrate is provided, which will be patterned to form an integrated circuit thereon. In some embodiments, the semiconductor substrate comprises silicon. Alternatively or additionally, the semiconductor substrate comprises germanium, silicon-germanium, or other suitable semiconductor materials, such as group III-V semiconductor materials.

[0094] like Figure 16A As shown, a target layer (TL) to be patterned is formed on a semiconductor substrate. In some embodiments, the target layer is the semiconductor substrate. In some embodiments, the target layer includes a conductive layer such as a metal layer or a polysilicon layer; a dielectric layer such as silicon oxide, silicon nitride, SiON, SiOC, SiOCN, SiCN, hafnium oxide, or aluminum oxide; or a semiconductor layer such as an epitaxially formed semiconductor layer. In some embodiments, the target layer is formed on an underlying structure (e.g., an isolation structure), transistor, or wiring. Figure 16A As shown, a photoresist layer PR is formed on the target layer TL. The photoresist layer is sensitive to radiation from the exposure source during subsequent photolithography processes. In this embodiment, the photoresist layer is sensitive to EUV light used in the photolithography process. The photoresist layer can be formed on the target layer by spin coating or other suitable techniques. The coated photoresist layer can be further baked to remove solvent from the photoresist layer.

[0095] The photoresist layer was then patterned using an EUV reflective mask as described above, such as... Figure 16B As shown, patterning of the photoresist layer involves performing a photolithography process using an EUV mask through an EUV exposure system. During the exposure process, an integrated circuit (IC) design pattern defined on the EUV mask is imaged onto the photoresist layer to form a latent pattern thereon.

[0096] Patterning of the photoresist layer also includes: developing and exposing the photoresist layer to form a patterned photoresist layer with one or more openings, such as... Figure 16C As shown. In one embodiment where the photoresist layer is a positive photoresist layer, the exposed portions of the photoresist layer are removed during the development process. Patterning of the photoresist layer may also include other process steps, such as various baking steps at different stages. For example, a post-exposure baking (PEB) process may be performed after the photolithography exposure process and before the development process.

[0097] like Figure 16CAs shown, a patterned photoresist layer is used as an etching mask to pattern the target layer TL. In some embodiments, patterning the target layer includes applying an etching process to the target layer using the patterned photoresist layer as an etching mask. A portion of the target layer exposed within an opening in the patterned photoresist layer is etched, while the remaining portion is not etched. Furthermore, the patterned photoresist layer can be removed by wet stripping or plasma ashing, such as... Figure 16D As shown.

[0098] In some embodiments, two hard mask layers 30, 32 are used to pattern the absorber layer 25. When using a chromium-based absorber layer, using two thinner hard mask layers provides improved control over the pattern profile of the etched pattern, in contrast to a single, thicker hard mask layer. Cr-based absorber layers (e.g., CrN or nitrogen-rich CrON or CrCON layers) have a higher EUV absorption coefficient than other absorber layers. The higher EUV absorption coefficient allows for the use of absorber layers with reduced thickness, which in turn suppresses three-dimensional effects in EUV lithography.

[0099] The cyclic etching operation of the absorber layer disclosed herein provides a reduction in the thickness of the etching byproduct sidewalls 65 on the openings 42 in the absorber layer 25. In some embodiments, the etching byproduct sidewalls are reduced by about 40% to about 66% compared to an absorber etching operation that does not include the cyclic etching operation disclosed herein. In other embodiments, the etching byproduct sidewalls are reduced by about 45% to about 55%. In some embodiments, the substrate tilt angle α of the etching byproduct sidewalls is increased to more than 75°, and in other embodiments to more than 88°. In some embodiments, the substrate tilt angle α is in the range of about 77° to about 90°. In some embodiments, the cyclic etching operation of the absorber layer disclosed herein provides improved resolution of the circuit pattern 42 formed in the absorber layer 25. Embodiments of this disclosure provide improved mask critical dimension (CD) uniformity and prevent mask-induced CD and profile attenuation. Embodiments of this disclosure also prevent undercutting due to the absorber layer etching operation. Embodiments of this disclosure are performed with the same etching tools currently used for etching absorber layers. Therefore, no new tools are required to practice the disclosed methods.

[0100] It is understood that not all advantages need to be discussed herein, no particular advantage is necessary for all embodiments or examples, and other embodiments or examples may provide different advantages.

[0101] According to an embodiment of the present disclosure, a method of manufacturing a photomask includes: forming a reflective multi-layer stack over a substrate, and forming a cap layer over the reflective multi-layer stack. An absorption layer is formed over the cap layer, and a hard mask is formed over the absorption layer. An opening is formed in the hard mask to expose the absorption layer. The absorption layer is etched using the hard mask as an etch mask. Etching the absorption layer sequentially includes: applying a first etch gas to the absorption layer; turning on the bias power and the source power; turning off the bias power and the source power; applying a second etch gas to the absorption layer, wherein the first etch gas and the second etch gas are different; and turning on the source power without turning on the bias power. In an embodiment, forming the reflective multi-layer stack includes: forming a plurality of alternating molybdenum layers and silicon layers. In an embodiment, the reflective multi-layer stack includes 20 to 60 pairs of molybdenum layers and silicon layers. In an embodiment, the cap layer includes ruthenium. In an embodiment, the first etch gas includes oxygen. In an embodiment, the second etch gas includes chlorine. In an embodiment, the second etch gas includes C X H Y F Z , where 0 ≤ x ≤ 10, 0 ≤ y ≤ 12, and 0 ≤ z ≤ 12, and for a given second etch gas, only one of x, y, and z can be 0. In an embodiment, during the application of the second etch gas to the absorption layer, a mixture of the first etch gas and the second etch gas is applied. In an embodiment, the method includes: forming an anti-reflection layer over the cap layer before forming the absorption layer. In an embodiment, the anti-reflection layer includes a tantalum compound.

[0102] According to another embodiment of the present disclosure, a method of manufacturing a reflective photomask includes: forming a hard mask layer over a reflective photomask blank. The reflective photomask blank includes: a reflective multi-layer stack disposed over a substrate; a cap layer disposed over the reflective multi-layer stack; and an absorption layer disposed over the cap layer. The hard mask layer is patterned to form an opening in the hard mask layer. The absorption layer is etched in a chamber using the patterned hard mask layer as an etch mask. Etching the absorption layer includes the following operations: a) introducing an oxygen-containing gas into the chamber, b) turning on the bias power and the source power for a first period of time, c) turning off the bias power and the source power, d) introducing a fluorocarbon gas into the chamber, and e) turning on the source power for a second period of time, and not turning on the bias power during the second period of time. In an embodiment, the fluorocarbon gas is represented as C X H Y F Z , where 0 < x ≤ 10, 0 ≤ y ≤ 12, and 0 < z ≤ 12. In an embodiment, the method includes repeating operations a) to e). In an embodiment, the absorption layer includes chromium. In an embodiment, the hard mask layer includes a tantalum compound.

[0103] Another embodiment of the present disclosure is a method of manufacturing a photomask, comprising: forming a hard mask layer including a first tantalum compound on a photomask blank. The photomask blank includes: a reflective multilayer stack disposed on a substrate; a cap layer disposed on the reflective multilayer stack; an intermediate layer including a second tantalum compound disposed on the cap layer; and an absorption layer disposed on the intermediate layer. The hard mask layer is patterned by lithography to expose a portion of the absorption layer, and the patterned hard mask layer is used as an etch mask to etch the absorption layer in a chamber to form an opening in the absorption layer. Etching the absorption layer includes the following operations: a) introducing an oxygen-containing gas into the chamber; b) turning on the bias power and the source power for a first period of time; c) turning off the bias power and the source power; d) introducing a fluorocarbon gas into the chamber; e) turning on the source power for a second period of time and not turning on the bias power during the second period of time; and f) forming a sidewall layer including a reaction product of the oxygen-containing gas, the fluorocarbon gas, and the absorption layer on the sidewalls of the opening. In an embodiment, the method includes repeating operations a), b), c), d), and e). In an embodiment, the method includes performing an overetch operation using an overetch gas. In an embodiment, the overetch gas includes a mixed gas of oxygen and chlorine. In an embodiment, the sidewall layer includes CrO x F y or CrO x Cl y layer, where 0 < x ≤ 10 and 0 < y ≤ 10.

[0104] Another embodiment of the present disclosure is a method of manufacturing a semiconductor device, including forming a hard mask layer over a photomask blank. The photomask blank includes: a reflective multilayer stack disposed over a substrate; a cap layer disposed over the reflective multilayer stack; and an absorption layer disposed over the cap layer. An opening is formed in the hard mask layer, and the opening exposes the absorption layer. The absorption layer is etched using the hard mask layer as an etch mask to form a patterned photomask. Etching the absorption layer includes: introducing a first etch gas into a chamber containing the photomask blank, turning on a bias power and a source power for a first period of time; turning off the bias power and the source power after the first period of time; after turning off the bias power and the source power, introducing a second etch gas into the chamber, wherein the first etch gas and the second etch gas are different; and after introducing the second etch gas, turning on the source power for a second period of time without turning on the bias power. The patterned photomask is used to form a pattern in a photoresist layer disposed over a semiconductor substrate. In an embodiment, using the patterned photomask to form a pattern in the photoresist layer includes: directing actinic radiation toward the patterned photomask such that the actinic radiation is reflected by the patterned photomask, and directing the reflected actinic radiation toward the photoresist layer to form a latent pattern in the photoresist layer, and developing the latent pattern to form a pattern in the photoresist layer. In an embodiment, the actinic radiation is extreme ultraviolet radiation. In an embodiment, the reflective multilayer stack includes 20 to 60 pairs of molybdenum layers and silicon layers. In an embodiment, the cap layer includes ruthenium. In an embodiment, the first etch gas includes oxygen. In an embodiment, the second etch gas includes chlorine. In an embodiment, the second etch gas includes C X H Y F Z , where \(0 \lt x \leq 10\), \(0 \leq y \leq 12\), and \(0 \lt z \leq 12\). In an embodiment, the photomask blank includes an intermediate layer including a tantalum compound disposed between the cap layer and the absorption layer.

[0105] Another embodiment of the present disclosure is a method of manufacturing a semiconductor device, including: directing actinic radiation from an actinic radiation source to a reflective photomask. The reflective photomask includes: a reflective multilayer stack disposed over a substrate; a cap layer disposed over the reflective multilayer stack; a patterned absorption layer including at least one pattern feature disposed over the cap layer; and a sidewall layer disposed over the sidewalls of the at least one pattern feature, wherein the sidewall includes CrO x F y or CrO x Cl ya layer, where 0 < x ≤ 10 and 0 < y ≤ 10. The patterned actinic radiation reflected from the reflective photomask is directed towards a semiconductor substrate coated with a photoresist layer to form a latent pattern in the photoresist layer. Then, a developer is applied to the photoresist layer to develop the latent pattern and form a pattern in the photoresist layer. In an embodiment, the patterned absorption layer includes chromium. In an embodiment, the actinic radiation is extreme ultraviolet radiation.

[0106] In an embodiment, the reflective multilayer stack includes 20 to 60 pairs of molybdenum layers and silicon layers. In an embodiment, the cap layer includes ruthenium.

[0107] Another embodiment of the present disclosure is a reflective photomask that includes a reflective multilayer stack disposed on a substrate and a cap layer disposed on the reflective multilayer stack. A patterned absorption layer including at least one pattern feature is disposed on the cap layer, and a sidewall layer is disposed on the sidewalls of the at least one pattern feature. The sidewall layer includes CrO x F y or CrO x Cl y layer, where 0 < x ≤ 10 and 0 < y ≤ 10. In an embodiment, the reflective multilayer stack includes 20 to 60 pairs of molybdenum layers and silicon layers. In an embodiment, the cap layer includes ruthenium. In an embodiment, the absorption layer includes chromium. In an embodiment, the absorption layer includes chromium nitride. In an embodiment, the reflective photomask includes an intermediate layer disposed between the cap layer and the absorption layer. In an embodiment, the intermediate layer is an antireflection layer. In an embodiment, the intermediate layer is made of a tantalum compound. In an embodiment, the thickness of the sidewall layer is in the range of 0.5 nm to 5 nm. In an embodiment, the thickness of the sidewall layer is in the range of 1 nm to 3 nm.

[0108] The foregoing disclosure outlines the features of several embodiments or examples, enabling those skilled in the art to better understand the aspects of the present disclosure. Those skilled in the art should understand that they can readily use the present disclosure as a basis for designing or modifying other processes and structures to implement the same purposes and / or achieve the same advantages as the embodiments or examples described herein. Those skilled in the art should appreciate that they can readily use the present disclosure as a basis for designing or modifying other processes and structures for performing the same purposes and / or achieving the same advantages as the embodiments or examples introduced herein

[0109] Example 1 is a method for manufacturing a photomask, comprising: forming a reflective multilayer stack on a substrate; forming a cap layer on the reflective multilayer stack; forming an absorption layer on the cap layer; forming a hard mask on the absorption layer; forming an opening in the hard mask to expose the absorption layer; and using the hard mask as an etching mask to etch the absorption layer, wherein etching the absorption layer comprises performing the following operations in sequence: applying a first etching gas to the absorption layer; turning on a bias power and a source power; turning off the bias power and the source power; applying a second etching gas to the absorption layer; wherein the first etching gas and the second etching gas are different; and turning on the source power but not the bias power.

[0110] Example 2 is the method described in Example 1, wherein forming the reflective multilayer stack includes forming a plurality of alternating molybdenum layers and silicon layers.

[0111] Example 3 is the method described in Example 2, wherein the reflective multilayer stack comprises 20 to 60 pairs of molybdenum layers and silicon layers.

[0112] Example 4 is the method described in Example 1, wherein the cap layer comprises ruthenium.

[0113] Example 5 is the method described in Example 1, wherein the first etching gas includes oxygen.

[0114] Example 6 is the method described in Example 1, wherein the second etching gas includes chlorine.

[0115] Example 7 is the method described in Example 1, wherein the second etching gas includes C X H Y F Z , where 0≤x≤10, 0≤y≤12, and 0≤z≤12, and for a given second etching gas, only one of x, y, and z can be 0.

[0116] Example 8 is the method of Example 1, wherein a mixture of the first etching gas and the second etching gas is applied during the application of the second etching gas to the absorption layer.

[0117] Example 9 is the method of Example 1, further comprising: forming an anti-reflective layer on top of the cap layer prior to forming the absorbent layer.

[0118] Example 10 is the method described in Example 9, wherein the antireflective layer comprises a tantalum compound.

[0119] Example 11 is a method of manufacturing a reflective photomask, including: forming a hard mask layer on a reflective photomask blank, wherein the reflective photomask blank includes: a reflective multi-layer stack disposed on a substrate; a cap layer disposed on the reflective multi-layer stack; and an absorption layer disposed on the cap layer; patterning the hard mask layer to form an opening in the hard mask layer; and using the patterned hard mask layer as an etching mask to etch the absorption layer in a chamber, wherein etching the absorption layer includes the following operations: a) introducing an oxygen-containing gas into the chamber; b) turning on the bias power and the source power for a first period of time; c) turning off the bias power and the source power; d) introducing a fluorocarbon gas into the chamber; and e) turning on the source power for a second period of time, and not turning on the bias power during the second period of time.

[0120] Example 12 is the method according to Example 11, wherein the fluorocarbon gas is represented as C X H Y F Z , where 0 < X ≤ 10, 0 ≤ Y ≤ 12, and 0 < Z ≤ 12.

[0121] Example 13 is the method according to Example 11, further including repeating operations a) to e).

[0122] Example 14 is the method according to Example 11, wherein the absorption layer includes chromium.

[0123] Example 15 is the method according to Example 11, wherein the hard mask layer includes a tantalum compound.

[0124] Example 16 is a reflective photomask, including: a reflective multi-layer stack disposed on a substrate; a cap layer disposed on the reflective multi-layer stack; a patterned absorption layer including at least one pattern feature disposed on the cap layer; and a sidewall layer disposed on the sidewalls of the at least one pattern feature, wherein the sidewall layer includes CrO x F y or CrO x Cl y layer, where 0 < x ≤ 10, and 0 < y ≤ 10.

[0125] Example 17 is the reflective photomask according to Example 16, wherein the reflective multi-layer stack includes 20 to 60 pairs of molybdenum layers and silicon layers.

[0126] Example 18 is the reflective photomask according to Example 16, wherein the cap layer includes ruthenium.

[0127] Example 19 is the reflective photomask according to Example 16, wherein the absorption layer includes chromium.

[0128] Example 20 is the reflective photomask described in Example 16, wherein the absorption layer comprises chromium nitride.

Claims

1. A method for manufacturing a photomask, comprising: A reflective multilayer stack is formed on the substrate; A cap layer is formed on the reflective multilayer stack; An absorbent layer is formed on top of the cap layer; A hard mask is formed on the absorption layer; An opening is formed in the hard mask to expose the absorption layer; as well as The hard mask is used as an etching mask to etch the absorption layer. Etching the absorber layer includes performing the following operations in sequence: A first etching gas is applied to the absorption layer; Enable bias power and source power; Turn off the bias power and the source power; A second etching gas is applied to the absorption layer; Wherein, the first etching gas and the second etching gas are different; and Turn on the source power but not the bias power.

2. The method according to claim 1, wherein, Forming the reflective multilayer stack includes forming multiple alternating molybdenum and silicon layers.

3. The method according to claim 2, wherein, The reflective multilayer stack comprises 20 to 60 pairs of molybdenum and silicon layers.

4. The method according to claim 1, wherein, The cap layer includes ruthenium.

5. The method according to claim 1, wherein, The first etching gas includes oxygen.

6. The method according to claim 1, wherein, The second etching gas includes chlorine.

7. The method according to claim 1, wherein, The second etching gas includes C X H Y F Z , where 0≤x≤10, 0≤y≤12, and 0≤z≤12, and for a given second etching gas, only one of x, y, and z can be 0.

8. The method according to claim 1, wherein, During the application of the second etching gas to the absorption layer, a mixture of the first etching gas and the second etching gas is applied.

9. A method for manufacturing a reflective photomask, comprising: A hard mask layer is formed on top of a reflective photomask preform. The reflective photomask blank includes: Reflective multilayer stacks are disposed on a substrate; A cap layer is disposed on the reflective multilayer stack; and An absorbent layer is disposed on the cap layer; Pattern the hard mask layer to form openings in the hard mask layer; and The absorber layer is etched in the chamber using a patterned hard mask layer as an etching mask. Etching the absorber layer includes the following operations: a) Introducing oxygen-containing gas into the chamber; b) Enable bias power and source power continuously for the first time period; c) Turn off the bias power and the source power; d) Introducing fluorocarbon gas into the chamber; and e) The source power is turned on for a second time period, and the bias power is not turned on during the second time period.

10. A reflective photomask, comprising: Reflective multilayer stacks are disposed on a substrate; A cap layer is placed on top of a reflective multilayer stack; A patterned absorption layer, including at least one patterned feature, is disposed on the cap layer; as well as A sidewall layer is disposed on the sidewall of the at least one pattern feature. Among them, the side wall layer includes CrO x F y or CrO x Cl y layer, where 0 < x ≤ 10 and 0 < y ≤ 10.

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