PCIe (Peripheral Component Interconnect Express) dynamic degradation type link resetting method and system

Abstract

The invention relates to the technical field of PCIe (Peripheral Component Interconnect Express), in particular to a PCIe dynamic degradation type link resetting method and system. Comprising the following steps: S1, continuously reading the LTSSM state of a PCIe link, recording the duration of an abnormal state, and when the duration exceeds a preset threshold value, judging that timeout abnormity exists; s2, after the abnormal early warning is received, a dynamic degradation reset instruction for the NVMe controller is initiated; s3, the state machine control unit takes over the reset link initialization process and follows the physical layer priority gt; the link layer is preferentially gt; a priority strategy is simplified by a transaction layer, and a centralized resource guide link rapidly completes training and enters an L0 state. Compared with the prior art, the method has strict protocol compliance, the reset efficiency is improved, and the overall stability and performance of the system are optimized.

Description

A PCIe dynamic degradation link reset method and system Technical Field

[0001] This invention relates to the field of PCIe technology, specifically to a PCIe dynamic degradation link reset method and system. Background Technology

[0002] Existing PCIe systems typically employ a Full Link Reset (FLR) or a hardware reset mechanism relying on external pins (such as PERST#) to handle link state anomalies, such as link training or recovery timeouts. The FLR mechanism requires resetting all functional modules in the link, including non-core units (such as various controller caches and complex interrupt controllers), resulting in a reset process that generally takes more than 100 milliseconds (ms). This violates the constraints of the PCIe fundamental protocol on link recovery time and directly leads to a severe degradation in system I / O performance.

[0003] The problem is particularly pronounced in high-performance NVMe SSD applications. The NVMe controller's own reset process typically includes time-consuming non-core initialization steps, such as firmware loading, complete I / O commit and complete queue (SQ / CQ) reconstruction and configuration, interrupt vector table remapping, cache consistency maintenance, and deep power management state initialization. These steps, superimposed on the PCIe link reset, cause the overall reset time to far exceed the 100ms protocol safety window, resulting in significant performance bottlenecks and system response latency.

[0004] Current technologies lack timing awareness of the reset process, making it impossible to dynamically assess reset progress and risks within the time window specified in the protocol. Furthermore, existing solutions lack dynamic degradation mechanisms, failing to intelligently skip specific non-core initialization steps to compress reset time based on real-time risks. Whether relying on software-based in-band resets or hardware-based pin resets, their reset range and timing are fixed and coarse-grained, failing to meet the sub-millisecond-level rapid fault recovery requirements of modern high-performance devices. Summary of the Invention

[0005] To overcome the shortcomings of the prior art, this invention provides a PCIe dynamic degradation link reset method and system, which achieves a closed-loop dynamic reset control of "perception-decision-execution" through the collaborative work of a hardware monitoring unit and an intelligent state machine.

[0006] To achieve the above objectives, a PCIe dynamic degradation link reset method is designed, including the following steps: S1, Status monitoring and risk prediction: Continuously read the PCIe link LTSSM status and record the duration of abnormal states. When the duration exceeds a preset threshold, a timeout anomaly is determined, triggering step S2; S2, Reset strategy decision and execution: After receiving an anomaly warning, initiate a dynamic degradation reset command for the NVMe controller; skip non-core initialization processes and execute core process reset instead, executing the core logic reset of the PCIe controller in parallel or with priority; S3, Link recovery control: The state machine control unit takes over the link initialization process after reset, following a priority strategy of physical layer priority > link layer priority > transaction layer simplification, concentrating resources to guide the link to quickly complete training and enter the L0 state.

[0007] The specific method of step S1 includes: reading the LTSSM status in real time through the status register access module, configuring timer logic to monitor the duration of abnormal status changes, triggering the reset strategy of step S2 if the timeout occurs, and continuing to monitor if the timeout does not occur.

[0008] In step S2, the current device type is determined by the state machine, and a preset degradation reset strategy is selected.

[0009] In step S2, the non-core initialization process includes firmware reloading, I / O queue reconstruction, interrupt controller deep configuration, full cache refresh, and power management deep initialization; the core process reset includes resetting the NVMe controller's configuration space register, the queue manager's pointer, and the exception status register.

[0010] The skipping firmware reload process specifically involves: retaining the existing running firmware image and context, and not performing the firmware reload and initialization process from storage medium to memory, which takes ≥50ms; skipping the I / O queue reconstruction process, specifically retaining the allocated queue memory resources and structure, and only resetting the head and tail pointers of the queue, rather than destroying and recreating all I / O queues; skipping the interrupt controller deep configuration process, specifically keeping the mapping relationship between the interrupt vector table and the CPU unchanged, and only clearing the pending interrupt status bits to avoid time-consuming operations such as reallocating interrupt numbers; skipping the full cache refresh process, specifically abandoning the time-consuming full cache write-back and invalidation operations while ensuring data consistency, and only restoring the cache function by resetting the relevant control bits; and skipping the power management deep initialization process, specifically maintaining the current power state and clock frequency, bypassing the time-consuming power state traversal and clock phase-locked loop relocking process.

[0011] To achieve the above objectives, a PCIe dynamic degradation link reset system is designed to implement the aforementioned PCIe dynamic degradation link reset method. The system includes: a hardware monitoring unit integrated within the PCIe controller or SoC, comprising a status register read interface and a programmable timer, used to perform real-time monitoring tasks and generate interrupts or level signals when a timeout risk occurs; a reset strategy decision module, using a microcontroller or finite state machine, used to receive alarm signals from the hardware monitoring unit, with built-in decision logic capable of generating control signals containing degradation reset instructions based on the current system context; a degradation reset execution circuit connected to the NVMe controller and PCIe controller, which, upon receiving a degradation reset instruction, skips non-core initialization processes and directly performs a reset operation on the core registers by writing a sequence to the registers; and a link recovery state machine, a hardware state machine, which actively intervenes in the link training process after the degradation reset is executed to ensure the optimal recovery path and prioritizes meeting the timing requirements of L0 state recovery.

[0012] Compared with the prior art, the present invention has the following beneficial effects: 1. Strict protocol compliance: Through proactive timing awareness and risk prediction, it ensures that even in the case of link anomalies, the recovery process can be strictly limited to the 100ms time window specified by the PCIe protocol, thus completely avoiding the risk of link degradation or disconnection due to timeout.

[0013] 2. Significant improvement in reset efficiency: Targeting the critical bottleneck of the NVMe controller, by dynamically skipping 5 key non-core initialization steps such as firmware loading and queue reconstruction, the complex reset process, which may have exceeded 150ms, is compressed to less than 100ms, improving the reset efficiency by more than 30% compared to the traditional FLR mechanism.

[0014] 3. Overall system stability and performance optimization: While achieving rapid reset, the use of intelligent degradation rather than brute-force full reset reduces the impact on other parts of the system, such as host memory management and interrupt subsystems, ensuring the immediacy and high reliability of data transmission after link recovery, and significantly improving the overall service quality and response speed of NVMe SSD storage systems, high-speed network equipment and data center servers. Attached Figure Description

[0015] Figure 1 is a schematic diagram of the process of the present invention.

[0016] Figure 2 is a schematic diagram of the architecture of the present invention. Detailed Implementation

[0017] The present invention will now be further described with reference to the accompanying drawings.

[0018] As shown in Figure 1, this embodiment provides a PCIe dynamic degradation link reset method, including the following steps: S1, Status monitoring and risk prediction: Continuously read the PCIe link LTSSM status and record the duration of abnormal status. When the duration exceeds a preset threshold, it is determined that there is a timeout abnormality, triggering step S2; S2, Reset strategy decision and execution: After receiving the abnormality warning, initiate a dynamic degradation reset command for the NVMe controller; skip the non-core initialization process and instead execute the core process reset, and execute the core logic reset of the PCIe controller in parallel or with priority, ensuring that the physical link layer enters the ready state first.

[0019] S3, Link Recovery Control: The state machine control unit takes over the link initialization process after reset, following the priority strategy of physical layer priority > link layer priority > transaction layer simplification. It concentrates resources to guide the link to quickly complete training and enter the L0 state. The entire composite reset process, that is, the total time from risk detection to L0 recovery, is forcibly constrained to within 100ms.

[0020] The specific method of step S1 includes: reading the LTSSM status in real time through the status register access module, configuring timer logic to monitor the duration of abnormal status changes, triggering the reset strategy of step S2 if the timeout occurs, and continuing to monitor if the timeout does not occur.

[0021] In step S2, the current device type is determined through the state machine, and a preset degradation reset strategy is selected. The preliminary judgment step of step S2, namely identifying the current device type, is a prerequisite for executing the subsequent differentiated strategy.

[0022] In step S2, under the risk of timeout, the dynamic degradation reset instruction skips the initialization steps that are not essential for function recovery but are time-consuming, and only resets the core functions, rather than performing a full reset as default. The non-core initialization process includes the firmware reload process, the I / O queue reconstruction process, the interrupt controller deep configuration process, the full cache refresh process, and the power management deep initialization process; the core process reset includes the reset of the NVMe controller's configuration space register, the queue manager pointer, and the exception status register.

[0023] Specifically, skipping the firmware reload process involves preserving the existing running firmware image and context, and avoiding the firmware reload and initialization process from storage medium to memory, which takes ≥50ms. Skipping the I / O queue reconstruction process involves preserving the allocated queue memory resources and structure, only resetting the head and tail pointers of the queues, such as the SQ head pointer and CQ tail pointer, instead of destroying and recreating all I / O queues. Skipping the interrupt controller deep configuration process involves maintaining the mapping relationship between the interrupt vector table and the CPU, only clearing the status bits of pending interrupts, avoiding time-consuming operations such as reallocating interrupt numbers. Skipping the full cache refresh process involves abandoning time-consuming full cache write-back and invalidation operations while ensuring data consistency, restoring cache functionality only by resetting relevant control bits. Skipping the power management deep initialization process involves maintaining the current power state and clock frequency, bypassing the time-consuming power state traversal and clock phase-locked loop relocking process.

[0024] In practical use, depending on the different device types, corresponding degradation reset strategies are preset, that is, the types of non-core initialization processes and core processes are selected, and the range of reset processes is flexibly configured to achieve rapid recovery and realize dynamic degradation reset.

[0025] In step S3, a dedicated state machine is used to strictly control the recovery priority of the link after reset. The primary goal of the state machine is to guide the link to recover to the L0 state via the shortest path, and in this process, the initialization order and dependencies of each sub-module are dynamically managed.

[0026] As shown in Figure 2, the system used to implement the above-mentioned PCIe dynamic degradation link reset method includes: a hardware monitoring unit, integrated inside the PCIe controller or SoC, including a status register read interface and a programmable timer, used to perform real-time monitoring tasks and generate interrupts or level signals when timeout risks occur; a reset strategy decision module, using a microcontroller or finite state machine, used to receive alarm signals from the hardware monitoring unit, with built-in decision logic, capable of generating control signals containing degradation reset instructions based on the current system context; a degradation reset execution circuit, connected to the NVMe controller and the PCIe controller, which, upon receiving a degradation reset instruction, does not send a global reset signal to the NVMe controller, but instead skips the non-core initialization process by writing a sequence to the registers, and directly performs a reset operation on the core registers; and a link recovery state machine, using a hardware state machine, which actively intervenes in the link training process after the degradation reset is executed, ensuring the optimal recovery path and prioritizing the timing requirements of L0 state recovery.

[0027] In this embodiment, the system is designed and operated with a 100ms protocol timeout as a hard constraint. All reset logic design and decision-making threshold settings are verified and optimized with this constraint in mind, ensuring that reset operations do not exceed this timeout under any circumstances. The system minimizes the computational, memory, and I / O resource consumption of reset operations through dynamic degradation reset. After rapid link recovery, the system can immediately resume full-performance operation. Skipped non-core initialization steps can be completed in the background when necessary or during idle periods, achieving a balance between performance and security.

[0028] This invention enables real-time monitoring of the PCIe link state (LTSSM) and proactive prediction of reset timeout risks, fundamentally avoiding protocol violations caused by reset timeouts. For complex devices such as NVMe controllers, a dynamic degradation reset strategy is provided, intelligently skipping non-core initialization processes and significantly reducing the overall reset time to less than 100ms. While ensuring protocol compliance, it guarantees the PCIe link's rapid and stable recovery to full-speed operating state (L0 state), thereby comprehensively improving system performance and reliability under high loads.

[0029] In practical applications, this invention is suitable for scenarios with stringent requirements for rapid PCIe link recovery, such as high-performance computing, NVMe solid-state drives (SSDs), servers, and network equipment. When applied to high-performance NVMe SSDs in data centers and high-end PCs, if an SSD enters Recovery mode due to momentary link interference, the method of this invention ensures rapid recovery within the protocol time limit, avoiding I / O interruptions and guaranteeing high availability and low latency of the storage system. When applied to servers and storage arrays requiring rapid startup, the method of this invention can significantly shorten the PCIe device enumeration and initialization time during server startup or device hot-swapping, accelerating system readiness. When applied to highly reliable network equipment and smart network interface cards (NICs), in network switching equipment and DPU / IPUs requiring continuous high bandwidth and low latency, the method of this invention can minimize packet loss and transmission interruptions caused by link-layer error recovery, ensuring the continuity of network services.

Claims

1. A PCIe dynamic degradation link reset method, characterized in that: The process includes the following steps: S1, Status Monitoring and Anomaly Detection: Continuously read the PCIe link LTSSM status and record the duration of abnormal states. When the duration exceeds a preset threshold, a timeout anomaly is determined, triggering step S2; S2, Reset Strategy Decision and Execution: Upon receiving an anomaly warning, initiate a dynamic degradation reset command for the NVMe controller; skip non-core initialization processes and execute core process resets instead, executing the core logic reset of the PCIe controller in parallel or with priority; S3, Link Recovery Control: The state machine control unit takes over the link initialization process after the reset, following a priority strategy of physical layer priority > link layer priority > transaction layer simplification, concentrating resources to guide the link to quickly complete training and enter the L0 state.

2. The PCIe dynamic degradation link reset method according to claim 1, characterized in that: The specific method of step S1 includes: reading the LTSSM status in real time through the status register access module, configuring timer logic to monitor the duration of abnormal status changes, triggering the reset strategy of step S2 if the timeout occurs, and continuing to monitor if the timeout does not occur.

3. The PCIe dynamic degradation link reset method according to claim 1, characterized in that: In step S2, the current device type is determined by the state machine, and a preset degradation reset strategy is selected.

4. The PCIe dynamic degradation link reset method according to claim 1, characterized in that: In step S2, the non-core initialization process includes firmware reloading, I / O queue reconstruction, interrupt controller deep configuration, full cache refresh, and power management deep initialization; the core process reset includes resetting the NVMe controller's configuration space register, the queue manager's pointer, and the exception status register.

5. A PCIe dynamic degradation link reset method according to claim 4, characterized in that: The skipping firmware reload process specifically involves: retaining the existing running firmware image and context, and not performing the firmware reload and initialization process from storage medium to memory, which takes ≥50ms; skipping the I / O queue reconstruction process, specifically retaining the allocated queue memory resources and structure, and only resetting the head and tail pointers of the queue, rather than destroying and recreating all I / O queues; skipping the interrupt controller deep configuration process, specifically keeping the mapping relationship between the interrupt vector table and the CPU unchanged, and only clearing the pending interrupt status bits to avoid time-consuming operations such as reallocating interrupt numbers; skipping the full cache refresh process, specifically abandoning the time-consuming full cache write-back and invalidation operations while ensuring data consistency, and only restoring the cache function by resetting the relevant control bits; and skipping the power management deep initialization process, specifically maintaining the current power state and clock frequency, bypassing the time-consuming power state traversal and clock phase-locked loop relocking process.

6. A PCIe dynamic degradation link reset system, used to implement the PCIe dynamic degradation link reset method according to any one of claims 1-5, characterized in that, The system includes: a hardware monitoring unit, integrated within the PCIe controller or SoC, including a status register read interface and a programmable timer, for performing real-time monitoring tasks and generating interrupts or level signals when timeout risks occur; a reset strategy decision module, using a microcontroller or finite state machine, for receiving alarm signals from the hardware monitoring unit, with built-in decision logic, capable of generating control signals containing degraded reset instructions based on the current system context; a degraded reset execution circuit, connected to the NVMe controller and PCIe controller, which, upon receiving a degraded reset instruction, skips non-core initialization processes and directly performs reset operations on core registers by writing a sequence to the registers; and a link recovery state machine, using a hardware state machine, which actively intervenes in the link training process after the degraded reset is executed, ensuring the optimal recovery path and prioritizing the timing requirements of L0 state recovery.

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