Data processing device and method, equipment and medium

Abstract

The invention provides a data processing device and method, equipment and a medium, and relates to the technical field of computers. The data processing device comprises a register and a load storage unit. Wherein the register is used for storing operation data of each operation thread in the thread bundle; the loading storage unit is connected with the register and is used for responding to a data processing instruction sent for the thread bundle, reading operation data corresponding to each operation thread in the thread bundle from the register, and based on the data processing instruction, using at least one hardware function module in the loading storage unit to load the operation data corresponding to each operation thread in the thread bundle; and executing corresponding data processing operation on the operation data. According to the scheme, the data processing instruction is completed by loading the hardware function module in the storage unit, so that the hardware overhead in the data processing process is reduced.

Description

Data processing apparatus, methods, equipment and media Technical Field

[0001] This disclosure relates to the field of computer technology, and more specifically, to a data processing apparatus, method, device, and medium. Background Technology

[0002] In parallel processing architectures, to support different multi-threaded data processing operations, existing technologies typically configure dedicated processing circuits within the chip for each type of data processing operation. However, these circuits often require large-scale multi-path interconnect structures, with numerous signal paths, large device sizes, and high wiring complexity, leading to a significant increase in hardware footprint and implementation costs. As the number of threads continues to increase, the scale of related circuits expands exponentially, not only consuming a large amount of chip resources but also potentially affecting the overall performance of the chip. Therefore, how to reduce hardware overhead while ensuring the reliability of data processing functions has become a pressing technical problem in data processing technology. Summary of the Invention

[0003] The purpose of this disclosure is to provide a data processing apparatus, a data processing method, an electronic device, and a computer-readable storage medium that can complete data processing instructions by utilizing the hardware functional modules inside the loading storage unit, thereby reducing hardware overhead during the data processing process.

[0004] Other features and advantages of this disclosure will become apparent from the following detailed description, or may be learned in part from practice of this disclosure.

[0005] According to a first aspect of the present disclosure, a data processing apparatus is provided, the apparatus comprising: a register for storing operation data of each operation thread in a thread bundle; and a loading storage unit connected to the register, the loading storage unit being configured to, in response to a data processing instruction sent for the thread bundle, read operation data corresponding to each operation thread in the thread bundle from the register, and, based on the data processing instruction, perform corresponding data processing operations on the operation data using at least one hardware functional module within the loading storage unit.

[0006] In some example embodiments of this disclosure, based on the foregoing scheme, the data processing instruction includes a data shuffling instruction, and the operation data corresponding to each operation thread in the thread bundle includes the data to be exchanged corresponding to each operation thread and the thread number of the target thread corresponding to each operation thread; the loading storage unit includes a crossbar switch, which includes multiple input terminals and multiple output terminals, with each operation thread corresponding to one input terminal and one output terminal; when the data processing instruction is the data shuffling instruction, the loading storage unit is used to: input the data to be exchanged corresponding to each operation thread to the multiple input terminals of the crossbar switch respectively; use the crossbar switch to map the data to be exchanged on the input terminal corresponding to the thread number to the output terminal corresponding to the operation thread corresponding to the target thread; and write the shuffling result data output by the multiple output terminals back to the storage location in the register corresponding to each operation thread.

[0007] In some example embodiments of this disclosure, based on the foregoing scheme, the cross switch includes: a data writing switch, the data writing switch including a plurality of first input terminals and a plurality of first output terminals, each operation thread corresponding to a first input terminal and a first output terminal; the loading storage unit is used to: input the data to be exchanged corresponding to each operation thread to the plurality of first input terminals of the data writing switch respectively.

[0008] In some example embodiments of this disclosure, based on the foregoing scheme, the cross switch further includes: a data return switch, the data return switch including a plurality of second input terminals and a plurality of second output terminals; each operation thread corresponds to a second input terminal and a second output terminal; the loading storage unit is used to: establish a data path between the plurality of first output terminals and the plurality of second input terminals based on the correspondence between the first output terminals, the second input terminals and the operation threads; use the thread number as a control signal for the data write switch or the data return switch; and use the data write switch, the data return switch and the data path to map the data to be exchanged on the first input terminal corresponding to the thread number to the second output terminal corresponding to the operation thread corresponding to the target thread.

[0009] In some example embodiments of this disclosure, based on the foregoing scheme, when the thread number is used as the control signal for the data write switch, the loading storage unit is configured to: use the data write switch to map the data to be exchanged on the first input terminal corresponding to the thread number to the first output terminal corresponding to the operation thread corresponding to the target thread; transmit the data to be exchanged on the first output terminal to the corresponding second input terminal through the data path; and based on the correspondence between the second input terminal, the second output terminal, and the operation thread, map the data to be exchanged on the second input terminal to the second output terminal corresponding to the operation thread through the data return switch.

[0010] In some example embodiments of this disclosure, based on the foregoing scheme, when the thread number is used as the control signal for the data return switch, the loading storage unit is configured to: based on the correspondence between the first input terminal, the first output terminal, and the operating thread, map the data to be exchanged on the first input terminal to the first output terminal corresponding to the operating thread through the data write switch; transmit the data to be exchanged on the first output terminal to the corresponding second input terminal through the data path; and use the data return switch to map the data to be exchanged on the second input terminal corresponding to the thread number to the second output terminal corresponding to the operating thread corresponding to the target thread.

[0011] In some example embodiments of this disclosure, based on the foregoing scheme, the data processing instruction includes a data matching instruction, and the operation data corresponding to each operation thread in the thread bundle includes the data to be matched corresponding to each operation thread; the loading storage unit includes: an address merging subunit, used to compare the data to be matched and obtain a comparison result; when the data processing instruction is the data matching instruction, the loading storage unit is used to: generate a mask corresponding to each operation thread according to the comparison result; and write the mask corresponding to each operation thread back to the storage location in the register corresponding to each operation thread.

[0012] In some example embodiments of this disclosure, based on the foregoing scheme, the address merging subunit is used to: convert the data to be matched into address format data for address comparison; and compare the address format data corresponding to each of the operation threads to obtain the comparison result.

[0013] In some example embodiments of this disclosure, based on the foregoing scheme, the mask includes multiple mask bits, with each operation thread corresponding to one mask bit; the loading storage unit is configured to: in response to the address format data corresponding to the reference operation thread and the matching operation thread being the same, write the mask bit corresponding to the matching operation thread into the mask corresponding to the reference operation thread as a first preset identifier; the reference operation thread and the matching operation thread are any two different operation threads in the thread bundle; in response to the address format data corresponding to the reference operation thread and the matching operation thread being different, write the mask bit corresponding to the matching operation thread into the mask corresponding to the reference operation thread as a second preset identifier; the second preset identifier is different from the first preset identifier.

[0014] In some example embodiments of this disclosure, based on the foregoing scheme, the loading storage unit includes a crossbar switch, which further includes a data write switch and a data return switch; the data processing device further includes a shared memory connected to the loading storage unit, which is used to perform data processing operations according to the access request of the loading storage unit; the shared memory is configured with multiple computing units, and each operation thread corresponds to one computing unit; the loading storage unit realizes data interaction with the shared memory through the data write switch and the data return switch; the data processing instruction includes a data reduction instruction, and the operation data corresponding to each operation thread in the thread bundle includes the data to be reduced corresponding to each operation thread; when the data processing instruction is the data reduction instruction, the loading storage unit is used to: based on the correspondence between the computing unit and the operation thread, use the data write switch to send the data to be reduced to the corresponding computing unit; when the computing unit completes the reduction operation, use the data return switch to write the reduction result data output by each computing unit back to the storage location in the register corresponding to each operation thread.

[0015] In some example embodiments of this disclosure, based on the foregoing scheme, the loading storage unit includes: a crossbar switch, the crossbar switch including a data write switch and a data return switch; the data write switch includes multiple first input terminals and multiple first output terminals; each operation thread corresponds to one first input terminal and one first output terminal; the data processing device further includes: shared memory connected to the loading storage unit, the shared memory including multiple storage banks; each first output terminal of the data write switch corresponds to one storage bank; the loading storage unit realizes data interaction with the shared memory through the data write switch and the data return switch; the data processing instructions include data loading instructions. The operation data corresponding to each operation thread in the thread bundle includes the load address corresponding to each operation thread; when the data processing instruction is the data loading instruction, the load storage unit is used to: generate a first strobe signal based on the load address; according to the first strobe signal, use the data write switch to complete the strobe configuration between the plurality of first input terminals and the plurality of first output terminals, map each load address to the first storage bank among the plurality of storage banks, and send a data loading instruction to each of the first storage banks; use the data return switch to receive the load data output by each of the first storage banks, and write the load data back to the storage location in the register corresponding to each operation thread.

[0016] In some example embodiments of this disclosure, based on the foregoing scheme, the loading storage unit includes: a crossbar switch, the crossbar switch including a data write switch, the data write switch including multiple first input terminals and multiple first output terminals; each operation thread corresponds to one first input terminal and one first output terminal; the data processing device further includes: shared memory connected to the loading storage unit, the shared memory including multiple storage banks; each first output terminal of the data write switch corresponds to one storage bank; the loading storage unit realizes data interaction with the shared memory through the data write switch; the data processing instruction includes a data storage instruction, and the operation data corresponding to each operation thread in the thread bundle includes the storage data and storage address corresponding to each operation thread; when the data processing instruction is the data storage instruction, the loading storage unit is used to: generate a second strobe signal based on the storage address; according to the second strobe signal, use the data write switch to complete the strobe configuration between the multiple first input terminals and the multiple first output terminals, map each storage address to a second storage bank among the multiple storage banks, and send corresponding storage data and data storage instructions to each second storage bank; the data storage instruction is used to trigger the second storage bank to perform a write operation on the storage data.

[0017] In some example embodiments of this disclosure, based on the foregoing scheme, the loading storage unit includes: a cross switch, the cross switch including a data write switch and a data return switch, the data write switch including multiple first input terminals and multiple first output terminals; each operation thread corresponds to one first input terminal and one first output terminal; the data processing device further includes: shared memory, connected to the loading storage unit, the shared memory including multiple storage banks; each first output terminal of the data write switch corresponds to one storage bank; multiple computing units are configured in the shared memory, each operation thread corresponds to one computing unit; the loading storage unit realizes data interaction with the shared memory through the data write switch and the data return switch; the data processing instructions include atomic operation instructions, and the operation data corresponding to each operation thread in the thread bundle includes the data corresponding to each operation thread. Atomic operation data and access addresses; when the data processing instruction is the atomic operation instruction, the loading storage unit is configured to: generate a third strobe signal based on the access address; according to the third strobe signal, use the data write switch to complete the strobe configuration between the plurality of first input terminals and the plurality of first output terminals, map each access address to a third storage bank among the plurality of storage banks, and send corresponding atomic operation data and atomic operation instructions to each of the third storage banks; according to the atomic operation instruction, use the arithmetic unit to perform arithmetic processing on the atomic operation data to obtain atomic operation result data; in response to the atomic operation instruction requesting data return, use the data return switch to receive the atomic operation result data output by each of the third storage banks, and write the atomic operation result data back to the storage location in the register corresponding to each of the operation threads.

[0018] According to a second aspect of the present disclosure, a data processing method is provided, applied to a loading storage unit; the loading storage unit is connected to a register, the register being used to store operation data of each operation thread in a thread bundle; the method includes: in response to a data processing instruction sent for the thread bundle, reading operation data corresponding to each operation thread in the thread bundle from the register; and, based on the data processing instruction, performing a corresponding data processing operation on the operation data using at least one hardware functional module inside the loading storage unit.

[0019] In some example embodiments of this disclosure, based on the foregoing scheme, the loading storage unit is configured with a crossbar switch, which includes multiple input terminals and multiple output terminals, with each operation thread corresponding to one input terminal and one output terminal; the data processing instruction includes a data shuffling instruction, and the operation data corresponding to each operation thread in the thread bundle includes the data to be exchanged corresponding to each operation thread and the thread number of the target thread corresponding to each operation thread; the step of performing corresponding data processing operations on the operation data using at least one hardware functional module inside the loading storage unit based on the data processing instruction includes: when the data processing instruction is the data shuffling instruction, inputting the data to be exchanged corresponding to each operation thread to the multiple input terminals of the crossbar switch respectively; using the crossbar switch to map the data to be exchanged on the input terminal corresponding to the thread number to the output terminal corresponding to the operation thread corresponding to the target thread; and writing the shuffling result data output by the multiple output terminals back to the storage location in the register corresponding to each operation thread.

[0020] In some example embodiments of this disclosure, based on the foregoing scheme, the cross switch includes a data writing switch; the data writing switch includes a plurality of first input terminals and a plurality of first output terminals; each operation thread corresponds to a first input terminal and a first output terminal; the step of inputting the data to be exchanged corresponding to each operation thread to the plurality of input terminals of the cross switch respectively includes: inputting the data to be exchanged corresponding to each operation thread to the plurality of first input terminals of the data writing switch respectively.

[0021] In some example embodiments of this disclosure, based on the foregoing scheme, the cross switch further includes a data return switch; the data return switch includes multiple second input terminals and multiple second output terminals; each operation thread corresponds to one second input terminal and one second output terminal; the step of using the cross switch to map the data to be exchanged on the input terminal corresponding to the thread number to the output terminal corresponding to the operation thread corresponding to the target thread includes: establishing a data path between the multiple first output terminals and the multiple second input terminals based on the correspondence between the first output terminal, the second input terminal and the operation thread; using the thread number as the control signal of the data write switch or the data return switch; using the data write switch, the data return switch and the data path to map the data to be exchanged on the first input terminal corresponding to the thread number to the second output terminal corresponding to the operation thread corresponding to the target thread.

[0022] In some example embodiments of this disclosure, based on the foregoing scheme, when the thread number is used as the control signal for the data write switch, the step of mapping the data to be exchanged on the first input terminal corresponding to the thread number to the second output terminal corresponding to the operation thread corresponding to the target thread using the data write switch, the data return switch, and the data path includes: mapping the data to be exchanged on the first input terminal corresponding to the thread number to the first output terminal corresponding to the operation thread corresponding to the target thread using the data write switch; transmitting the data to be exchanged on the first output terminal to the corresponding second input terminal through the data path; and mapping the data to be exchanged on the second input terminal to the second output terminal corresponding to the operation thread through the data return switch based on the correspondence between the second input terminal, the second output terminal, and the operation thread.

[0023] In some example embodiments of this disclosure, based on the foregoing scheme, when the thread number is used as the control signal for the data return switch, the step of mapping the data to be exchanged on the first input terminal corresponding to the thread number to the second output terminal corresponding to the operation thread corresponding to the target thread using the data write switch, the data return switch, and the data path includes: based on the correspondence between the first input terminal, the first output terminal, and the operation thread, mapping the data to be exchanged on the first input terminal to the first output terminal corresponding to the operation thread through the data write switch; transmitting the data to be exchanged on the first output terminal to the corresponding second input terminal through the data path; and using the data return switch to map the data to be exchanged on the second input terminal corresponding to the thread number to the second output terminal corresponding to the operation thread corresponding to the target thread.

[0024] In some example embodiments of this disclosure, based on the foregoing scheme, the loading storage unit is further configured with an address merging subunit for merging operations based on access addresses; the data processing instruction includes a data matching instruction, and the operation data corresponding to each operation thread in the thread bundle includes the data to be matched corresponding to each operation thread; the step of performing corresponding data processing operations on the operation data using at least one hardware functional module inside the loading storage unit based on the data processing instruction includes: when the data processing instruction is the data matching instruction, comparing the data to be matched using the address merging subunit to obtain a comparison result; generating a mask corresponding to each operation thread based on the comparison result; and writing the mask corresponding to each operation thread back to the storage location in the register corresponding to each operation thread.

[0025] In some example embodiments of this disclosure, based on the foregoing scheme, the step of comparing the data to be matched using the address merging subunit to obtain a comparison result includes: converting the data to be matched into address format data for address comparison; and using the address merging subunit to compare the address format data corresponding to each of the operation threads to obtain a comparison result.

[0026] In some example embodiments of this disclosure, based on the foregoing scheme, the mask includes multiple mask bits, with each operation thread corresponding to one mask bit; generating the mask corresponding to each operation thread based on the comparison result includes: in response to the address format data corresponding to the reference operation thread and the matching operation thread being the same, writing the mask bit corresponding to the matching operation thread into the mask corresponding to the reference operation thread as a first preset identifier; the reference operation thread and the matching operation thread are any two different operation threads in the thread bundle; in response to the address format data corresponding to the reference operation thread and the matching operation thread being different, writing the mask bit corresponding to the matching operation thread into the mask corresponding to the reference operation thread as a second preset identifier; the second preset identifier is different from the first preset identifier.

[0027] In some example embodiments of this disclosure, based on the aforementioned scheme, the loading storage unit is configured with a crossbar switch; the crossbar switch further includes a data write switch and a data return switch; the loading storage unit is also connected to shared memory, and the loading storage unit realizes data interaction with the shared memory through the data write switch and the data return switch; the shared memory is used to perform data processing operations according to the access request of the loading storage unit; the shared memory is configured with multiple computing units, and each operation thread corresponds to one computing unit; the data processing instruction includes a data reduction instruction, and the operation data corresponding to each operation thread in the thread bundle includes the data to be reduced corresponding to each operation thread; the step of performing corresponding data processing operations on the operation data based on the data processing instruction and using at least one hardware functional module inside the loading storage unit includes: when the data processing instruction is the data reduction instruction, using the data write switch to send the data to be reduced to the corresponding computing unit; when the computing unit completes the reduction operation, using the data return switch to write the reduction result data output by each computing unit back to the storage location in the register corresponding to each operation thread.

[0028] In some example embodiments of this disclosure, based on the foregoing scheme, the loading storage unit is configured with a cross switch, which includes a data write switch and a data return switch. The data write switch includes multiple first input terminals and multiple first output terminals; each operation thread corresponds to one first input terminal and one first output terminal; the loading storage unit is also connected to shared memory, and the loading storage unit realizes data interaction with the shared memory through the data write switch and the data return switch; the shared memory includes multiple storage banks; each first output terminal of the data write switch corresponds to one storage bank; the data processing instruction includes a data loading instruction, and the operation data corresponding to each operation thread in the thread bundle includes the loading data corresponding to each operation thread. Load address; the step of performing corresponding data processing operations on the operation data using at least one hardware functional module inside the load storage unit based on the data processing instruction includes: when the data processing instruction is the data load instruction, generating a first strobe signal based on the load address; according to the first strobe signal, using the data write switch to complete the strobe configuration between the plurality of first input terminals and the plurality of first output terminals, mapping each load address to a first storage bank among the plurality of storage banks, and sending a data load instruction to each first storage bank; using the data return switch to receive the load data output by each first storage bank, and writing the load data back to the storage location in the register corresponding to each operation thread.

[0029] In some example embodiments of this disclosure, based on the foregoing scheme, the loading storage unit is configured with a crossbar switch, the crossbar switch including a data write switch, the data write switch including multiple first input terminals and multiple first output terminals; each operation thread corresponds to one first input terminal and one first output terminal; the loading storage unit is also connected to shared memory, and the loading storage unit realizes data interaction with the shared memory through the data write switch; the shared memory includes multiple storage banks; each first output terminal of the data write switch corresponds to one storage bank; the data processing instruction includes data storage instruction, and the operation data corresponding to each operation thread in the thread bundle includes the storage corresponding to each operation thread. Data and storage address; the step of performing corresponding data processing operations on the operation data using at least one hardware functional module inside the loading storage unit based on the data processing instruction includes: when the data processing instruction is the data storage instruction, generating a second strobe signal based on the storage address; according to the second strobe signal, using the data write switch to complete the strobe configuration between the plurality of first input terminals and the plurality of first output terminals, mapping each storage address to a second storage bank among the plurality of storage banks, and sending corresponding storage data and data storage instructions to each second storage bank; the data storage instruction is used to trigger the second storage bank to perform a write operation on the storage data.

[0030] In some example embodiments of this disclosure, based on the foregoing scheme, the loading storage unit is configured with a crossbar switch, the crossbar switch including a data write switch and a data return switch, the data write switch including multiple first input terminals and multiple first output terminals; each operation thread corresponds to one first input terminal and one first output terminal; the loading storage unit is also connected to shared memory, and the loading storage unit realizes data interaction with the shared memory through the data write switch and the data return switch; the shared memory includes multiple storage banks; each first output terminal of the data write switch corresponds to one storage bank; multiple computing units are configured in the shared memory, and each operation thread corresponds to one computing unit; the data processing instructions include atomic operation instructions, and the operation data corresponding to each operation thread in the thread bundle includes the atomic operation data and access address corresponding to each operation thread; based on the data processing instructions, using the At least one hardware functional module within the loading storage unit performs corresponding data processing operations on the operation data, including: when the data processing instruction is the atomic operation instruction, generating a third strobe signal based on the access address; according to the third strobe signal, using the data write switch to complete the strobe configuration between the plurality of first input terminals and the plurality of first output terminals, mapping each access address to a third storage bank among the plurality of storage banks, and sending corresponding atomic operation data and atomic operation instructions to each of the third storage banks; according to the atomic operation instruction, using the arithmetic unit to perform arithmetic processing on the atomic operation data to obtain atomic operation result data; in response to the atomic operation instruction requesting data return, using the data return switch to receive the atomic operation result data output by each of the third storage banks, and writing the atomic operation result data back to the storage location in the register corresponding to each of the operation threads.

[0031] According to a third aspect of the present disclosure, an electronic device is provided, comprising: a processor; and a memory storing computer-readable instructions that, when executed by the processor, implement the data processing method as described in the second aspect.

[0032] According to a fourth aspect of the present disclosure, a computer-readable storage medium is provided having a computer program stored thereon, which, when executed by a processor, implements the data processing method as described in the second aspect.

[0033] The technical solutions provided in this disclosure include the following beneficial effects: The data processing method in the example embodiments of this disclosure, on the one hand, utilizes at least one hardware functional module within the loading storage unit to execute data processing operations corresponding to data processing instructions. This allows different data processing operations to reuse existing hardware capabilities within the loading storage unit, thereby avoiding the need for additional dedicated hardware configuration for inter-thread data processing operations. On the other hand, different hardware functional modules within the loading storage unit can be used to complete different types of data processing instructions, enabling the loading storage unit to directly call the corresponding hardware functional module to process the operation data when receiving different types of data processing instructions. Based on the above solution, inter-thread data processing operations can be implemented through registers and the loading storage unit, thereby reducing hardware overhead while ensuring the reliability of the data processing function.

[0034] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description

[0035] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure. It is obvious that the drawings described below are merely some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0036] Figure 1 schematically illustrates a flowchart of a data processing method according to some embodiments of the present disclosure.

[0037] Figure 2 schematically illustrates the structural composition of a data processing apparatus according to some embodiments of the present disclosure.

[0038] Figure 3 schematically illustrates a process diagram of data shuffling operations according to some embodiments of the present disclosure.

[0039] Figure 4 schematically illustrates the interaction relationship of data processing apparatus during data shuffling operations according to some embodiments of the present disclosure.

[0040] Figure 5 schematically illustrates the interaction relationship of the data processing apparatus during a data shuffling operation according to some other embodiments of the present disclosure.

[0041] Figure 6 schematically illustrates a flowchart of a data matching operation according to some embodiments of the present disclosure.

[0042] Figure 7 schematically illustrates the interaction relationship of data processing apparatuses during data matching operations according to some embodiments of the present disclosure.

[0043] Figure 8 schematically illustrates a flowchart of data reduction operations according to some embodiments of the present disclosure.

[0044] Figure 9 schematically illustrates the interaction relationship of a data processing apparatus during data reduction operations according to some embodiments of the present disclosure.

[0045] Figure 10 schematically illustrates the interaction relationship of a data processing apparatus during data access operations according to some embodiments of the present disclosure.

[0046] Figure 11 schematically illustrates the structure of a data processing apparatus according to some other embodiments of the present disclosure.

[0047] Figure 12 schematically illustrates the structural diagram of a computer system of an electronic device according to some embodiments of the present disclosure.

[0048] In the accompanying drawings, the same or corresponding reference numerals indicate the same or corresponding parts. Detailed Implementation

[0049] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numerals in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this specification. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this specification as detailed in the appended claims.

[0050] The terminology used in this specification is for the purpose of describing particular embodiments only and is not intended to be limiting of this specification. The singular forms “a,” “the,” and “the” as used in this specification and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the term “and / or” as used herein refers to and includes any and all possible combinations of one or more of the corresponding listed items.

[0051] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this disclosure will be more thorough and complete, and will fully convey the concept of the exemplary embodiments to those skilled in the art.

[0052] Furthermore, the described features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. Numerous specific details are provided in the following description to give a thorough understanding of embodiments of this disclosure. However, those skilled in the art will recognize that the technical solutions of this disclosure can be practiced without one or more of the specific details, or other methods, components, apparatuses, steps, etc., can be employed. In other instances, well-known methods, apparatuses, implementations, or operations are not shown or described in detail to avoid obscuring various aspects of this disclosure.

[0053] Furthermore, the accompanying drawings are for illustrative purposes only and are not necessarily drawn to scale. The block diagrams shown in the drawings are merely functional entities and do not necessarily correspond to physically independent entities. That is, these functional entities can be implemented in software, in one or more hardware modules or integrated circuits, or in different network and / or processor devices and / or microcontroller devices.

[0054] In parallel processing architectures such as GPUs and NPUs, there are typically load storage units (LSUs) with crossbar switches and registers. However, during parallel data processing, only the load storage units and registers are used for routine data reading, writing, and basic arithmetic operations. Data processing operations between threads often rely on dedicated circuitry. As the number of threads increases, this dedicated circuitry needs to support larger-scale multi-path interconnects, which not only consumes significant hardware resources but also makes it difficult to integrate inter-thread data interactions, such as data shuffling operations, into the existing architecture at a lower cost.

[0055] In view of this, the inventors of this application conceived of incorporating the data operation process between threads into the existing loading memory units and register working paths of the data processing device, so that data processing operations no longer need to rely on separately set dedicated circuits. Thus, the data interaction of thread bundles can be completed within existing hardware components, significantly reducing hardware overhead while ensuring the reliability of data processing operations.

[0056] In this embodiment, a data processing method is first provided, which can be applied to a loading storage unit. The loading storage unit is connected to a register, which is used to store the operation data of each operation thread in a thread bundle.

[0057] Furthermore, the load storage unit and registers can be components of a data processing device, which can represent a processing architecture supporting multi-threaded parallel execution, capable of scheduling thread bundles to complete data processing operations within the same execution cycle. In this embodiment, the execution carrier of the data processing device can be various processing architectures supporting parallel computing, such as a Graphics Processing Unit (GPU), a Neural Processing Unit (NPU), a Field-Programmable Gate Array (FPGA), and a Tensor Processing Unit (TPU). Registers can represent high-speed storage resources within the data processing device, providing temporary storage and fast access capabilities for operation data to each thread within the thread bundle, thereby ensuring the immediate availability of data during instruction processing. The load storage unit (LSU) can represent a functional unit for receiving and processing data access requests from the thread bundle. It can interact with registers and perform data input, exchange, and write-back operations based on internally configured crossbar switches, thereby realizing the loading and storage of data in the processing path.

[0058] Figure 1 schematically illustrates a flowchart of a data processing method according to some embodiments of the present disclosure. Referring to Figure 1, the data processing method may include the following steps: step S110, in response to a data processing instruction sent for a thread bundle, reading operation data corresponding to each operation thread in the thread bundle from a register; step S120, based on the data processing instruction, performing corresponding data processing operations on the operation data using at least one hardware functional module inside the loading storage unit.

[0059] According to the data processing method in this example embodiment, on the one hand, by utilizing at least one hardware functional module within the loading storage unit to execute data processing operations corresponding to data processing instructions, different data processing operations can reuse existing hardware capabilities within the loading storage unit, thereby avoiding the need for additional dedicated hardware to implement inter-thread data processing operations. On the other hand, different hardware functional modules within the loading storage unit can be used to complete different types of data processing instructions, enabling the loading storage unit to directly call the corresponding hardware functional module to process the operation data when receiving different types of data processing instructions. Based on the above scheme, inter-thread data processing operations can be implemented through registers and the loading storage unit, thereby reducing hardware overhead while ensuring the reliability of data processing functions.

[0060] The data processing method in this example embodiment will be further explained below.

[0061] In step S110, in response to the data processing instruction sent for the thread bundle, the operation data corresponding to each operation thread in the thread bundle is read from the register.

[0062] In this context, a warp can represent a fixed-size collection of threads in a data processing device. These threads execute instruction streams synchronously in hardware and share the same execution cycle. Operational data can represent thread-level data content used or generated by the operation threads within the warp during data processing, including numerical data, status data, or intermediate result data used for computation, exchange, or transmission. Operational threads can represent threads within the warp that participate in data processing operations. Each operation thread stores its corresponding operational data in a register and participates in the data processing process according to instructions. Data processing instructions can represent control instructions used to instruct the loading storage unit to perform preset data processing operations on the operational data corresponding to each operation thread in the warp. For example, data processing instructions may include data shuffling instructions, data matching instructions, data reduction instructions, data loading instructions, data storage instructions, and other suitable instruction types such as atomic operation instructions.

[0063] In step S120, based on the data processing instructions, at least one hardware function module inside the loading storage unit is used to perform corresponding data processing operations on the operation data.

[0064] The hardware functional module can represent a circuit unit configured within the loading storage unit and used to perform a preset processing procedure on the operation data after receiving a data processing instruction. For example, the hardware functional module may include a crossbar switch, an address merging subunit, etc. The data processing operation can represent the processing procedure specified by the data processing instruction and performed on the operation data by the hardware functional module. For example, the data processing operation may include data shuffling operations, data matching operations, data reduction operations, data loading operations, data storage operations, and atomic operations, etc.

[0065] Further, referring to FIG2, the data processing apparatus in this embodiment may include a loading storage unit 201, a register 202, and a shared memory 203, wherein the loading storage unit 201 is capable of data interaction with the register 202 and the shared memory 203 respectively. In related technologies, when performing data processing operations, the crossbar switch in the loading storage unit is typically only used to map the access address provided by the thread bundle to the corresponding storage location in the shared memory 203, or to map the storage data returned by the shared memory 203 to the storage location corresponding to the target operation thread in the register 202, so as to complete data loading or data writing.

[0066] However, the inventors of this application recognized that the crossbar switch in the load storage unit is configured with multiple input terminals and multiple output terminals corresponding to each operating thread in the thread bundle, and its internal signal path structurally possesses the ability to redirect data between threads. Therefore, in addition to performing conventional data access operations, it can also transfer data from one operating thread to another operating thread via the crossbar switch based on the mapping relationship between the input terminals and output terminals, realizing data exchange between threads. In other words, by controlling the connection relationship between each input terminal and each output terminal in the crossbar switch, a data transfer path between threads can be constructed on the internal path of the load storage unit 201, enabling the thread bundle to complete the data shuffling operation without relying on additional switching circuits, thereby reducing the hardware overhead of the data processing device.

[0067] Therefore, in some embodiments, a crossbar switch inside the loading storage unit can be used to perform the data shuffling operation. The crossbar switch includes multiple inputs and multiple outputs, with each operation thread corresponding to one input and one output. The data processing instruction is a data shuffling instruction, and the operation data includes the data to be exchanged and the thread number of the target thread corresponding to each operation thread.

[0068] Specifically, the data shuffle instruction can represent a control instruction used to trigger data exchange between threads within a thread bundle. This instruction instructs the load storage unit to map the operation data corresponding to the target thread to the corresponding operation thread. The data to be exchanged can represent the data that each operation thread needs to exchange with other threads when executing the data shuffle instruction. This data is read from a register and input to the crossbar switch for reallocation. The operation thread receives operation data from the corresponding target thread when executing the data shuffle instruction. The load storage unit can determine the data source that each operation thread should obtain based on its thread number and stores the mapped data in its corresponding register location after shuffling. The target thread can represent the thread unit that provides data to the operation threads during the data shuffle process. The data to be exchanged stored in its register will be mapped to the corresponding operation thread according to its thread number. The thread number can represent a marker information used to identify the target thread. This number is read by the operation thread and used as a data redirection control signal for the crossbar switch, instructing the crossbar switch to obtain the data to be exchanged from the input of the corresponding target thread and transmit it to the output of the current operation thread. For operation threads that do not need to participate in data exchange, their corresponding thread number can be specified as the thread's own number to keep the original data unchanged.

[0069] In response to a data processing instruction sent to a thread bundle, the operation data corresponding to each operation thread in the thread bundle is read from the register, including: in response to a data shuffling instruction sent to a thread bundle, the data to be exchanged corresponding to each operation thread in the thread bundle and the thread number of the target thread corresponding to each operation thread are read from the register.

[0070] Furthermore, the registers in this embodiment can be vector registers, scalar registers, or other register types suitable for parallel processing. When the register is a vector register, its storage structure is organized according to the thread bundle dimension. During the data shuffling process, it can read the data to be exchanged from each operation thread in parallel in a vector manner, and write it back to the register in vector form after the mapping is completed. This is suitable for execution modes that drive data flow in a wide vector manner. When the register is a scalar register, the data corresponding to each operation thread is stored in independent scalar register entries. The loading storage unit can access these scalar register entries in parallel within the same processing cycle, and after the cross switch completes the mapping, it writes the corresponding shuffling results back to their respective scalar register entries in parallel.

[0071] By reading the data to be exchanged from each operating thread and its corresponding target thread number from the register, the load memory unit can obtain the complete mapping information required for data exchange between threads in one go. Since these data and numbers directly correspond to the input and output terminals of the crossbar switch, the subsequent data shuffling process can be completed on the internal path of the load memory unit without introducing additional addressing steps or memory access operations.

[0072] Further, referring to Figure 3, in some embodiments, the data processing instruction includes a data shuffling instruction, and the operation data corresponding to each operation thread in the thread bundle includes the data to be exchanged corresponding to each operation thread and the thread number of the target thread corresponding to each operation thread. Then, based on the data processing instruction, at least one hardware function module inside the loading storage unit is used to perform the corresponding data processing operation on the operation data, specifically including the following technical steps: Step S310, when the data processing instruction is a data shuffling instruction, the data to be exchanged corresponding to each operation thread is respectively input to the multiple input terminals of the cross switch.

[0073] Specifically, after the loading memory unit finishes reading the data to be exchanged from the register, it sends the data to be exchanged for each operating thread to its corresponding input terminal based on the one-to-one correspondence between the operating threads and the crossbar switch input terminals, so that each input terminal carries data content from different operating threads. Through the above processing, the crossbar switch can establish a mapping relationship between the input terminals and output terminals based on the thread number in subsequent steps.

[0074] Step S320: Use a crossbar switch to map the data to be exchanged on the input terminal corresponding to the thread number to the output terminal corresponding to the operation thread corresponding to the target thread.

[0075] Specifically, the loading storage unit uses the thread number of each operating thread as the control signal for the crossbar switch. The crossbar switch selects the input terminal from multiple input terminals to carry the data to be exchanged by the target thread, based on the target thread location indicated by the thread number. Subsequently, a data path is established within the crossbar switch from this input terminal to the corresponding output terminal of the current operating thread. This allows the data provided by the target thread to be transmitted to the corresponding output terminal of the current operating thread via the data path, thus completing the data exchange between threads. Through this process, the crossbar switch can directly obtain the data to be exchanged from the target thread based on the thread number and deliver it to the corresponding operating thread, thereby reducing additional data forwarding paths and lowering the hardware resource consumption during the data shuffling process between threads.

[0076] Step S330: Write the shuffle result data output from multiple output terminals back to the storage location corresponding to each operation thread in the register.

[0077] The shuffling result data can represent the data provided by the target thread and transmitted to the corresponding operation thread after the crossbar switch establishes the mapping relationship between the input and output terminals. It serves as the output data for inter-thread data exchange. Specifically, after the crossbar switch completes the mapping between the input and output terminals, the loading storage unit acquires the shuffling result data output from each output terminal. Based on the one-to-one correspondence between the operation thread and the register storage location, it sends each shuffling result data to the corresponding thread storage location in the register, ensuring that each operation thread receives the final exchange data provided by its target thread.

[0078] The specific details of the steps in the above embodiments will be described in detail below.

[0079] In some embodiments, referring to FIG4, the crossbar switch includes a data write switch. The data write switch includes a plurality of first inputs and a plurality of first outputs; each operation thread corresponds to one first input and one first output.

[0080] The data write switch can represent a switch structure applied in the load memory unit. It is typically used to route data output from a register to a bank in shared memory corresponding to the target address, based on address information provided by the operating thread. In related technologies, this switch is usually only used to perform the address-to-bank mapping operation during the data write process. In this embodiment, in addition to performing the above mapping function, the data write switch is also used to construct data exchange paths between operating threads in a thread bundle, enabling data shuffling between threads via the load memory unit without the need for independent switching circuits.

[0081] Furthermore, the first input terminal can represent an input interface configured on the data write switch, with each first input terminal corresponding to an operation thread in the thread bundle, used to receive the data to be written or exchanged corresponding to that operation thread. The first output terminal can represent an output interface configured on the data write switch, used to send the input data to the corresponding target storage in the shared memory after the data write switch has completed mapping, or to send the data to the corresponding second input terminal during data shuffling.

[0082] When the cross switch includes a data write switch, the data to be exchanged corresponding to each operation thread is respectively input to multiple input terminals of the cross switch, including: the data to be exchanged corresponding to each operation thread is respectively input to multiple first input terminals of the data write switch.

[0083] In other words, the data to be exchanged read from the register by each operation thread in the thread bundle can be sent to multiple first input terminals of the data write switch according to the one-to-one correspondence between the operation thread and the first input terminal. Specifically, the loading storage unit determines the corresponding port number of each operation thread in the data write switch based on the structure of the current thread bundle, and loads the data to be exchanged from different operation threads sequentially to their matching first input terminals based on this correspondence, so that each first input terminal receives the data to be exchanged from a unique operation thread. In this way, the data to be exchanged from each operation thread can be accurately allocated to multiple first input terminals of the data write switch, providing a clear port basis for subsequent input and output terminal mapping based on thread number, enabling data exchange between threads to be completed in a more accurate and lower-overhead manner.

[0084] Furthermore, referring to Figure 4, the crossbar switch also includes a data return switch; the data return switch includes multiple second input terminals and multiple second output terminals; each operation thread corresponds to one second input terminal and one second output terminal. Data exchange during the data shuffling process can be completed using the data write switch and the data return switch. Specifically, using the crossbar switch to map the data to be exchanged on the input terminal corresponding to the thread number to the output terminal corresponding to the operation thread corresponding to the target thread includes: establishing a data path between multiple first output terminals and multiple second input terminals based on the correspondence between the first output terminal, the second input terminal, and the operation thread; using the thread number as the control signal for the data write switch or the data return switch; and using the data write switch, the data return switch, and the data path to map the data to be exchanged on the first input terminal corresponding to the thread number to the second output terminal corresponding to the operation thread corresponding to the target thread. Thus, data exchange between threads can be directly achieved through the port mapping relationship within the crossbar switch, avoiding the hardware overhead of building an independent switching structure.

[0085] The data return switch can represent another switch structure applied in the load memory unit, which is typically used to route data returned from shared memory back to the register according to the access relationship of the thread bundle. In related technologies, this switch is usually only used to return data output from shared memory to the register according to a predetermined thread order. In this embodiment, the data return switch, while maintaining the original data return function, is further used to send the redirected inter-thread exchange result back to the corresponding operation thread, so that data from other target threads can be correctly written back to the storage location in the register corresponding to the operation thread.

[0086] Furthermore, the second input terminal can represent an input interface configured on the data return switch, used to receive return data from shared memory, or to receive data to be exchanged forwarded by the corresponding first output terminal through the data path during the data shuffling process. The second output terminal can represent an output interface configured on the data return switch, with each second output terminal corresponding to an operation thread in the thread bundle, used to write the returned data or exchanged data into the register at the storage location corresponding to that operation thread.

[0087] A data path can represent a logical connection path established between the first output of a data write switch and the second input of a data return switch for forwarding data to be exchanged. This path is dynamically established based on a fixed correspondence between the first output, the second input, and the operating thread, allowing data to be exchanged from the first input, after its first mapping by the data write switch, to be transmitted along this path to the data return switch and enter the second input corresponding to the target thread. The establishment of the data path enables data forwarding between threads to reuse the existing port structure within the loading memory unit without constructing additional physical wiring or switching circuits. Control signals can represent switch control information generated by the thread number and used to instruct the data write switch or data return switch to select ports. This control information determines which first input, first output, second input, or second output participates in the current data mapping process, allowing the data to be exchanged to be transmitted along the crossbar switch according to the index path determined by the target thread.

[0088] Furthermore, a data path is established between multiple first output terminals and multiple second input terminals, including: based on the correspondence between the first output terminals, second input terminals and operation threads, a data write switch selects the first output terminal corresponding to the target thread, and a data return switch selects the second input terminal corresponding to the target thread; using the path construction module set in the loading storage unit, the preset connection structure from the first output terminal to the second input terminal is selected, so that the data to be exchanged from the first output terminal can be transmitted to the corresponding second input terminal along the selected connection structure, thereby forming a data path functionally used for data exchange between threads.

[0089] Referring to Figure 4, when the thread number is used as the control signal for the data write switch, the data to be exchanged on the first input terminal corresponding to the thread number is mapped to the second output terminal corresponding to the operation thread corresponding to the target thread using the data write switch, data return switch, and data path. This includes: using the data write switch to map the data to be exchanged on the first input terminal corresponding to the thread number to the first output terminal corresponding to the operation thread corresponding to the target thread; transmitting the data to be exchanged on the first output terminal to the corresponding second input terminal through the data path; and based on the correspondence between the second input terminal, the second output terminal, and the operation thread, mapping the data to be exchanged on the second input terminal to the second output terminal corresponding to the operation thread through the data return switch.

[0090] Specifically, in the data shuffling process shown in Figure 4, the data to be exchanged first enters the write data path of the loading storage unit and is received by the data write switch. At this time, the thread number is used as a control signal input to the internal switch node of the data write switch, causing the switch node to select between multiple first input terminals and multiple first output terminals. Thus, the data write switch maps the data to be exchanged on the first input terminal corresponding to the thread number to the first output terminal corresponding to the operation thread corresponding to the target thread. After the mapping result is generated at the first output terminal, the data to be exchanged on the first output terminal is transmitted to the corresponding second input terminal using the data path between the first output terminal and the second input terminal. Since the data path is constructed internally by the loading storage unit, the data does not pass through shared memory during transmission. When the data arrives at the second input terminal, the data return switch selects according to the fixed correspondence between the second input terminal and the second output terminal, and its internal switch node maps the data to be exchanged from the second input terminal to the second output terminal corresponding to the operation thread. Thus, the operation thread obtains the data provided by the target thread, forming the shuffling result data corresponding to that operation thread. The entire process is completed within the loading storage unit, without going through shared memory or introducing external interaction paths, thus enabling data shuffling between threads using the existing structure.

[0091] Referring to Figure 5, when the thread number is used as the control signal for the data return switch, the data to be exchanged on the first input terminal corresponding to the thread number is mapped to the second output terminal corresponding to the operation thread corresponding to the target thread using the data write switch, the data return switch, and the data path. This includes: based on the correspondence between the first input terminal, the first output terminal, and the operation thread, mapping the data to be exchanged on the first input terminal to the first output terminal corresponding to the operation thread using the data write switch; transmitting the data to be exchanged on the first output terminal to the corresponding second input terminal through the data path; and using the data return switch to map the data to be exchanged on the second input terminal corresponding to the thread number to the second output terminal corresponding to the operation thread corresponding to the target thread.

[0092] Specifically, in the data shuffling process shown in Figure 5, the data to be exchanged first enters the write data path of the loading storage unit and is received by the data write switch. Based on the correspondence between the first input, first output, and operation thread, the data write switch maps the data to be exchanged on the first input to the first output corresponding to the operation thread. Subsequently, the data to be exchanged on the first output is transmitted to the corresponding second input via the data path inside the loading storage unit, without passing through shared memory. After the thread number is input to the data return switch, the switch node of the data return switch selects between the second input and the second output corresponding to the target thread based on the thread number, and maps the data to be exchanged on the second input to the second output corresponding to the operation thread corresponding to the target thread, thereby generating the shuffling result data corresponding to the operation thread.

[0093] In some embodiments, the load storage unit is further configured with an address merging subunit capable of merging operations based on access addresses. The address merging subunit can represent a hardware unit configured within the load storage unit, used to compare and merge the access addresses of multiple operation threads, and capable of generating corresponding shared memory access requests based on the address merging results. In related technologies, the address processing logic of the load storage unit is mainly used to merge thread requests with the same access address within a thread bundle to reduce the number of shared memory accesses; when data matching operations are required, an independent comparator must be additionally configured for the thread bundle to compare the operation data, resulting in significant hardware resource consumption. However, the inventors of this application have conceived of utilizing the inherent address comparison capability of the address merging subunit to complete data matching operations between threads, so that data matching no longer depends on an independent comparator, but reuses the existing address merging subunit of the load storage unit, thereby reducing hardware overhead.

[0094] In response to a data processing instruction sent to a thread bundle, the system reads the operation data corresponding to each operation thread in the thread bundle from the register, including: in response to a data matching instruction sent to the thread bundle, reading the data to be matched corresponding to each operation thread in the thread bundle from the register. The data matching instruction can represent a control instruction used to trigger data comparison operations within the thread bundle, instructing the load storage unit to initiate a processing flow for matching and analyzing data from multiple operation threads. The data to be matched can represent data stored in registers corresponding to each operation thread in the thread bundle, which is used to input to the address merging subunit for comparison processing after the data matching instruction is triggered.

[0095] Further, referring to Figure 6, in some embodiments, the data processing instruction includes a data matching instruction, and the operation data corresponding to each operation thread in the thread bundle includes the data to be matched corresponding to each operation thread. Therefore, based on the data processing instruction, when the data processing instruction is a data matching instruction and the operation data includes the data to be matched, performing the corresponding data processing operation on the operation data using at least one hardware functional module inside the loading storage unit may include the following technical steps: Step S610, when the data processing instruction is a data matching instruction, comparing the data to be matched using the address merging subunit to obtain a comparison result.

[0096] Specifically, referring to the data matching operation process shown in Figure 7, when the data matching operation is performed in the loading storage unit, the data to be matched first enters the loading storage unit through the write data path and is then input to the address merging subunit. The address merging subunit uses its internal address comparison circuit to compare the data to be matched from multiple operation threads one by one. During the comparison process, the address merging subunit can perform bit-by-bit or field-by-field comparison operations on the data to be matched based on internally preset comparison rules, and generate comparison results corresponding to each operation thread.

[0097] Step S620: Generate a mask corresponding to each operation thread based on the comparison results.

[0098] The mask can represent the identification data generated by the address merging subunit based on the comparison results of the data to be matched, and is used to characterize the consistency or difference relationship between the operation threads on the data to be matched.

[0099] Step S630: Write the mask corresponding to each operation thread back to the storage location in the register corresponding to each operation thread. Specifically, after generating the mask corresponding to each operation thread based on the comparison result, the mask corresponding to each operation thread is written back to the corresponding storage location in the register via the return data path of the loaded storage unit, so that each operation thread can obtain its own corresponding data matching result.

[0100] In some embodiments, the step S610 above, which uses the address merging subunit to compare the data to be matched and obtain a comparison result, specifically includes the following technical steps: converting the data to be matched into address format data for address comparison; and using the address merging subunit to compare the address format data corresponding to each operation thread to obtain a comparison result.

[0101] The address format data can represent an address field generated from the data to be matched, with the same bit width as the address comparison input of the address merging subunit. This address format data satisfies the input requirements of the address comparison circuit inside the address merging subunit, enabling data from different operation threads to participate in the comparison process with a unified address expression format. The comparison result can represent the comparison information output by the address merging subunit after completing the address format data comparison process. It is used to characterize the equality or inequality relationship between the address format data corresponding to each operation thread in the thread bundle. For example, the comparison result can include identical or different results.

[0102] Specifically, converting the data to be matched into address format data for address comparison can be done through the following steps: extracting the valid fields for comparison from the data to be matched; adjusting the bit width of the valid fields based on the address field width of the address merging subunit to obtain the address format data. Here, the valid fields can represent the data content extracted from the data to be matched for address comparison. The address field width can represent the field width corresponding to the address comparison input of the address merging subunit. For example, taking the binary data "1101011010110011" as the data to be matched for a certain operation thread, if the valid field is the lower 8 bits, the extracted valid field is "10110011". When the address field width is 12 bits, the valid field is adjusted to 12 bits according to a preset alignment rule, for example, by padding the high bits of the valid field with 4 bits "0", resulting in the address format data "000010110011". Of course, in other embodiments of this disclosure, the valid field can also be selected from the middle bit segment or high bit segment of the data to be matched according to a preset field selection rule, and processed in the same bit width adjustment method as described above. Through the above conversion, the original data to be matched is semantically mapped into an input field that can be used for address comparison, so that it can be directly sent into the comparison path of the address merging subunit to participate in the matching process.

[0103] In some embodiments, the mask includes multiple mask bits, with each operation thread corresponding to one mask bit; the step S630 above, generating the mask corresponding to each operation thread based on the comparison result, specifically includes the following technical steps: in response to the same address format data corresponding to the reference operation thread and the matching operation thread, the mask bit corresponding to the matching operation thread is written into the mask corresponding to the reference operation thread as a first preset identifier; the reference operation thread and the matching operation thread are any two different operation threads in the thread bundle; in response to different address format data corresponding to the reference operation thread and the matching operation thread, the mask bit corresponding to the matching operation thread is written into the mask corresponding to the reference operation thread as a second preset identifier; the second preset identifier is different from the first preset identifier.

[0104] The number of bits in the mask can be equal to the number of operating threads in the thread bundle, thus allowing the data matching results between each operating thread and other operating threads within the thread bundle to be fully expressed through the same mask. Furthermore, a first preset identifier can be written into the mask bits representing the operating thread itself to indicate that the matching relationship between the thread and itself is always satisfied. The reference operating thread can represent the thread selected as the comparison benchmark during mask generation to determine its data matching relationship with other operating threads within the thread bundle. The matching operating thread can represent the target thread whose data matching result will be written into the mask corresponding to the reference operating thread after data comparison with the reference operating thread.

[0105] Furthermore, the mask bits can represent bit units in the mask used to indicate whether there is a data match between the reference operation thread and a specific matching operation thread, and are used to carry the corresponding matching identifier. The first preset identifier can represent a flag value used to indicate that the matching relationship is established, for example, it can be configured as 1; the second preset identifier can represent a flag value used to indicate that the matching relationship is not established, for example, it can be configured as 0, and this identifier is different from the first preset identifier. Of course, in other embodiments of this disclosure, the first preset identifier can also be configured as 0, and the second preset identifier can be configured as 1. Thus, each operation thread in the thread bundle can accurately reflect its data matching relationship with other threads through its own corresponding mask. For example, for a thread bundle containing 32 operation threads, the number of bits in the mask is also 32. If the first preset identifier is 1 and the second preset identifier is 0, taking the operation thread with thread number 0 as the reference operation thread as an example, its corresponding mask can be represented as: 1001000000000000000000000000001. In this design, bit 0 of the mask corresponds to the reference operation thread itself, and this bit is written with the first preset identifier 1. Bits 3 and 31, corresponding to the mask bits, are also written with the first preset identifier 1, indicating that the reference operation thread and the operation threads with thread numbers 3 and 31 have the same data to be matched. The remaining mask bits are written with the second preset identifier 0, indicating that the reference operation thread and the corresponding operation thread have different data to be matched. Furthermore, in data processing devices, the loading storage unit is usually equipped with shared memory, and the shared memory often has a pre-configured arithmetic unit capable of performing atomic operations. Related technologies generally only utilize this arithmetic unit to complete atomic operations, requiring a separate dedicated reduction circuit to be configured when performing data reduction, resulting in increased hardware overhead. The inventors of this application conceived that reduction operations and atomic operations are essentially both aggregation processing of multi-threaded data, thus reusing the existing arithmetic units in shared memory to execute the computational logic required for the reduction process, thereby eliminating the need for additional dedicated reduction hardware, achieving reduction processing with the existing structure and reducing overall hardware overhead.

[0106] Therefore, in some embodiments of this application, the data processing apparatus further includes shared memory, and a loading storage unit is also connected to the shared memory. The loading storage unit interacts with the shared memory through a data write switch and a data return switch. The shared memory is used to perform data processing operations according to the access request of the loading storage unit. Multiple processing units are configured in the shared memory, and each operation thread corresponds to one processing unit. In response to a data processing instruction sent to a thread bundle, the operation data corresponding to each operation thread in the thread bundle is read from the register, including: in response to a data reduction instruction sent to the thread bundle, the data to be reduced corresponding to each operation thread in the thread bundle is read from the register.

[0107] The data reduction instruction can be a control instruction used to initiate a multi-threaded data aggregation processing flow. It instructs the load memory unit to aggregate multiple data items to be reduced from registers to the arithmetic unit within shared memory for performing addition, minimum value, maximum value, or other reduction operations. The data to be reduced can represent data stored in registers and corresponding to each operating thread in the thread bundle. This data is sent to the load memory unit after the data reduction instruction is triggered, so that the arithmetic unit in shared memory can perform reduction processing.

[0108] Referring to Figure 8, in some embodiments, the data processing instruction includes a data reduction instruction, and the operation data corresponding to each operation thread in the thread bundle includes the data to be reduced corresponding to each operation thread. Then, based on the data processing instruction, at least one hardware functional module inside the loading storage unit is used to perform the corresponding data processing operation on the operation data, specifically including the following technical steps: Step S810, when the data processing instruction is a data reduction instruction, based on the correspondence between the arithmetic unit and the operation thread, the data to be reduced is sent to the corresponding arithmetic unit using a data write switch.

[0109] The arithmetic unit can refer to a hardware execution unit configured inside shared memory for performing arithmetic or logical operations on data from multiple operation threads. In atomic operation processing, it is usually used to handle basic operations such as addition and bitwise operations. In this application, it is reused for multi-threaded data aggregation operations in reduction operations.

[0110] In step S820, after the arithmetic unit completes the reduction operation, the reduction result data output by each arithmetic unit is written back to the storage location corresponding to each operation thread in the register using the data return switch.

[0111] The reduction result data can represent the data output by the arithmetic unit after completing the reduction operation. This data corresponds to the result of performing an aggregation operation on multiple data to be reduced, and is written back to the storage location in the register corresponding to each operation thread under the forwarding of the data return switch.

[0112] Specifically, referring to the data reduction operation process shown in Figure 9, after the data reduction instruction is triggered, the data to be reduced corresponding to multiple operation threads in the register is received by the loading storage unit and input to the data write switch via the write data path. The data write switch, based on the preset correspondence between the arithmetic unit and the operation thread, performs input-to-output gating on the data to be reduced from each thread, ensuring that each piece of data to be reduced is delivered to its corresponding arithmetic unit. The arithmetic unit performs reduction-type operations on the received data and generates reduction result data, which is input to the data return switch via the return data path. The data return switch, based on the fixed correspondence between the second input and the second output, maps the reduction result data from the arithmetic unit to the register location corresponding to each operation thread, so that the final reduction result is written back to the register and retrieved by each operation thread. Thus, multi-threaded data reduction processing can be completed through the loading storage unit and shared memory, without the need for additional independent reduction hardware units.

[0113] In other embodiments of this disclosure, referring to FIG10, a data loading operation from shared memory can also be performed using a loading storage unit. The shared memory includes multiple memory banks, each first output terminal of the data write switch corresponds to one memory bank, the data processing instruction includes a data loading instruction, and the operation data corresponding to each operation thread in the thread bundle includes the loading address corresponding to each operation thread. Based on the data processing instruction, at least one hardware functional module within the loading storage unit is used to perform corresponding data processing operations on the operation data, specifically including the following technical steps: when the data processing instruction is a data loading instruction, a first strobe signal is generated based on the loading address; according to the first strobe signal, the data write switch is used to complete the strobe configuration between multiple first input terminals and multiple first output terminals, mapping each loading address to a first memory bank among the multiple memory banks, and sending a data loading instruction to each first memory bank; the data return switch is used to receive the loaded data output from each first memory bank, and the loaded data is written back to the storage location in the register corresponding to each operation thread.

[0114] Specifically, a bank can represent an independent storage unit configured within shared memory for storing data and responding to read / write requests from load storage units. Each bank has an independent address space and access port, enabling multiple operation threads to perform data access operations in parallel across different banks. A data load instruction can represent a control instruction used to trigger the load storage unit to execute a data reading process. It instructs the load storage unit to read data from the shared memory at the addresses corresponding to multiple operation threads and return the read results to a register. The load address can represent the address information provided by each operation thread to determine the target read location in shared memory.

[0115] Furthermore, the first strobe signal can represent control information generated based on the load address to instruct the internal switch node of the data write switch to perform strobe operations. It can characterize the correspondence between each load address and multiple first output terminals, enabling the data write switch to complete strobe configuration among multiple first input terminals and multiple first output terminals. The first memory bank can represent the target memory bank in the memory bank set that matches the load address corresponding to each operation thread and is selected to perform the data loading operation. It is determined based on the mapping result of the data write switch and is used to receive load instructions and output the corresponding load data. The load data can represent the data output by the first memory bank after responding to the data load instruction.

[0116] In the specific implementation process, during the data loading operation, firstly, a data loading instruction is used to instruct the loading storage unit to initiate the reading process of shared memory. Based on this, the loading storage unit obtains the loading address corresponding to each operation thread from the register, ensuring that the target reading location of each operation thread is clearly identified. Subsequently, a first strobe signal is generated based on the mapping relationship between the loading address and the first memory bank. This enables the data write switch to complete the selection configuration among multiple first input terminals and multiple first output terminals based on the first strobe signal, and issues a data loading instruction to the first memory bank to trigger the shared memory reading operation. When the first memory bank outputs loaded data, the data return switch receives data from each first memory bank according to its internally fixed second input terminal, second output terminal, and operation thread correspondence, and writes the loaded data back to the storage location in the register corresponding to each operation thread, thereby completing the thread bundle's data loading process for shared memory. Through the above steps, a parallel data reading process can be completed among multiple memory banks using the data write switch and data return switch in the loading storage unit.

[0117] In other embodiments of this disclosure, referring to FIG10, a loading storage unit can also be used to complete data storage (store) operations on shared memory. The data processing instructions include data storage instructions, and the operation data corresponding to each operation thread in the thread bundle includes the storage data and storage address corresponding to each operation thread. Based on the data processing instructions, at least one hardware functional module within the loading storage unit is used to perform corresponding data processing operations on the operation data. Specifically, this includes the following technical steps: when the data processing instruction is a data storage instruction, a second strobe signal is generated based on the storage address; according to the second strobe signal, a data write switch is used to complete the strobe configuration between multiple first input terminals and multiple first output terminals, mapping each storage address to a second storage bank among multiple storage banks, and sending corresponding storage data and data storage instructions to each second storage bank; the data storage instruction is used to trigger the second storage bank to perform a write operation on the stored data.

[0118] The data storage instruction can represent a control instruction used to initiate a shared memory write process. This instruction is received by the loading storage unit and triggers it to write data to the second storage bank according to the storage address. The stored data can represent the data corresponding to each operation thread in a register, which is sent to the second storage bank as the write content after the data storage instruction is triggered. The storage address can represent the target write location identifier recorded in a register, used to instruct the loading storage unit to write the operation thread's data to the corresponding area in the shared memory. The second strobe signal can represent strobe control information determined by the storage address. This strobe control information characterizes the strobe relationship between each storage address and multiple first outputs of the data write switch, and is used to drive the data write switch to complete the strobe configuration between multiple first inputs and multiple first outputs, so that the storage address is mapped to its corresponding second storage bank. The second storage bank can represent the target storage bank in the shared memory used to perform the write operation, which completes the writing of stored data after receiving the write request forwarded by the loading storage unit.

[0119] Specifically, data storage operations can be performed by loading the storage unit. Upon receiving a data storage instruction, the loading storage unit first reads the storage data and storage address corresponding to each operation thread from the register. Subsequently, a second strobe signal is generated based on the correspondence between the storage address and the second storage bank. The data write switch is configured to be selected between multiple first input terminals and multiple first output terminals according to the second strobe signal, so that the storage address is mapped to its corresponding second storage bank, and the corresponding storage data and data storage instruction are sent to the second storage bank. After the second storage bank receives the data storage instruction, its internal write logic is triggered, and the input storage data is written, thereby completing the data update on the shared memory side. Through the above process, the process of writing thread-side data to shared memory can be directly completed using the loading storage unit.

[0120] In other embodiments of this disclosure, referring to FIG10, atomic operations can also be performed using a loading storage unit and shared memory. The data processing instructions include atomic operation instructions, and the operation data corresponding to each operation thread in the thread bundle includes atomic operation data and access addresses corresponding to each operation thread. Based on the data processing instructions, at least one hardware functional module within the loading storage unit is used to perform corresponding data processing operations on the operation data. Specifically, this includes the following technical steps: when the data processing instruction is an atomic operation instruction, a third strobe signal is generated based on the access address; according to the third strobe signal, a data write switch is used to complete the strobe configuration between multiple first input terminals and multiple first output terminals, mapping each access address to a third storage bank among multiple storage banks, and sending corresponding atomic operation data and atomic operation instructions to each third storage bank; according to the atomic operation instructions, an arithmetic unit is used to process the atomic operation data to obtain atomic operation result data; in response to the atomic operation instruction requesting data return, a data return switch is used to receive the atomic operation result data output by each third storage bank, and the atomic operation result data is written back to the register at the storage location corresponding to each operation thread.

[0121] Here, atomic operation instructions can represent control instructions used to trigger logical operations in the loaded memory unit. These instructions specify the target operation type, such as addition, minimum value, maximum value, bitwise operation, etc., and require the arithmetic unit to perform atomic processing on the corresponding data within shared memory. Atomic operation data can represent data stored in registers and used by each operation thread to participate in atomic operations. Access addresses can represent address information used to identify the location of the atomic operation data in the target memory within shared memory. The third strobe signal can represent strobe control information generated based on the access address. This strobe control information characterizes the strobe relationship between the access address and multiple first outputs of the data write switch, and is used to drive the data write switch to complete the strobe configuration between multiple first inputs and multiple first outputs, so that each access address is mapped to its corresponding third memory. The third memory can represent the memory in shared memory used to receive atomic operation data and cooperate with the arithmetic unit to perform atomic operations. Atomic operation result data can represent the result data output and written back to the register by the arithmetic unit after completing the atomic operation.

[0122] Specifically, during atomic operation processing, firstly, after the atomic operation instruction is issued, the loading memory unit receives the instruction and extracts the atomic operation data and access address corresponding to each operation thread from the register. Subsequently, the data write switch generates a third strobe signal based on the correspondence between the access address and the third memory bank. The data write switch then configures the selection between multiple first input terminals and multiple first output terminals according to the third strobe signal, so that each access address is mapped to its corresponding third memory bank. The atomic operation data and atomic operation instructions of each operation thread are then sent to their respective third memory banks to trigger the internal arithmetic units to perform atomic-level operations. After the arithmetic units complete the arithmetic operations on the atomic operation data based on the atomic operation instructions, they generate atomic operation result data. When the atomic operation instruction requests a return data, the data return switch forwards the atomic operation result data to the storage location in the register corresponding to each operation thread, based on the fixed correspondence path between the third memory bank and the register, so that each operation thread can obtain its corresponding atomic operation result. If the atomic operation instruction does not require a return data, the atomic operation result data can be retained in the corresponding third memory bank. By utilizing the address mapping capability of the loading memory unit and the computing units in shared memory through the above steps, atomic operations can be performed in parallel in a multi-threaded environment, thereby improving the processing efficiency of atomic operations.

[0123] Furthermore, referring to Figure 10, when using the load memory unit for data loading, data storage, and atomic operations, the access addresses of each thread can be merged through the address merging subunit. Specifically, the address merging subunit receives multiple access addresses from registers and identifies access requests with consistent access targets through internal address comparison logic, generating corresponding merged addresses. These merged addresses are then sent to the data write switch and data return switch, respectively, as the selection criteria for their internal switch nodes. Specifically, the data write switch node performs selection based on the correspondence between the merged address and the memory bank, mapping multiple access requests to the target memory bank in a merged form. Correspondingly, when data needs to be returned, the data return switch node also uses the merged address as a selection condition to uniformly select the data path returned from shared memory, forwarding the data output from the memory bank to the location in the register corresponding to the corresponding operation thread according to the merged access relationship. Through address merging, the data write switch and data return switch can perform switch node selection based on a unified merged address, thereby reducing duplicate accesses, lowering access conflicts, and improving shared memory access efficiency.

[0124] It should be noted that the data shuffling instructions, data matching instructions, data reduction instructions, data loading instructions, data storage instructions, and atomic operation instructions in the above embodiments can be issued individually or collaboratively by other instruction issuing units such as the thread bundle scheduling unit, command processing unit, and front-end control unit.

[0125] Furthermore, this disclosure also provides a data processing apparatus. Referring to FIG11, the data processing apparatus 1100 includes a loading storage unit 201 and a register 202. The register 202 is used to store operation data of each operation thread in a thread bundle; the loading storage unit 201 is connected to the register 202, and the loading storage unit 201 is used to read the operation data corresponding to each operation thread in the thread bundle from the register 202 in response to a data processing instruction sent for the thread bundle, and to perform corresponding data processing operations on the operation data based on the data processing instruction using at least one hardware functional module inside the loading storage unit 201.

[0126] Please refer to Figure 11.

[0127] In some example embodiments of this disclosure, based on the foregoing scheme, the data processing instruction includes a data shuffling instruction, and the operation data corresponding to each operation thread in the thread bundle includes the data to be exchanged corresponding to each operation thread and the thread number of the target thread corresponding to each operation thread.

[0128] The loading storage unit 201 includes a crossbar switch, which has multiple input terminals and multiple output terminals, with each operation thread corresponding to one input terminal and one output terminal.

[0129] When the data processing instruction is a data shuffling instruction, the loading storage unit 201 is used to: input the data to be exchanged corresponding to each operation thread to the multiple input terminals of the crossbar switch respectively; use the crossbar switch to map the data to be exchanged on the input terminal corresponding to the thread number to the output terminal corresponding to the operation thread corresponding to the target thread; and write the shuffling result data output from the multiple output terminals back to the storage location corresponding to each operation thread in the register 202.

[0130] In some example embodiments of this disclosure, based on the foregoing scheme, the cross switch includes: a data write switch 2011, which includes a plurality of first input terminals and a plurality of first output terminals, with each operation thread corresponding to a first input terminal and a first output terminal.

[0131] The loading storage unit 201 is used to input the data to be exchanged corresponding to each operation thread to the multiple first input terminals of the data writing switch 2011.

[0132] In some example embodiments of this disclosure, based on the foregoing scheme, the cross switch further includes: a data return switch 2012, which includes a plurality of second input terminals and a plurality of second output terminals; each operation thread corresponds to a second input terminal and a second output terminal.

[0133] The loading storage unit 201 is used to: establish a data path between multiple first output terminals and multiple second input terminals based on the correspondence between the first output terminal, the second input terminal and the operation thread; use the thread number as the control signal for the data write switch 2011 or the data return switch 2012; and use the data write switch 2011, the data return switch 2012 and the data path to map the data to be exchanged on the first input terminal corresponding to the thread number to the second output terminal corresponding to the operation thread corresponding to the target thread.

[0134] In some example embodiments of this disclosure, based on the foregoing scheme, when the thread number is used as the control signal for the data write switch 2011, the loading storage unit 201 is used to: map the data to be exchanged on the first input terminal corresponding to the thread number to the first output terminal corresponding to the operation thread corresponding to the target thread using the data write switch 2011; transmit the data to be exchanged on the first output terminal to the corresponding second input terminal through the data path; and based on the correspondence between the second input terminal, the second output terminal, and the operation thread, map the data to be exchanged on the second input terminal to the second output terminal corresponding to the operation thread through the data return switch 2012.

[0135] In some example embodiments of this disclosure, based on the foregoing scheme, when the thread number is used as the control signal for the data return switch 2012, the loading storage unit 201 is used to: based on the correspondence between the first input terminal, the first output terminal, and the operating thread, map the data to be exchanged on the first input terminal to the first output terminal corresponding to the operating thread through the data writing switch 2011; transmit the data to be exchanged on the first output terminal to the corresponding second input terminal through the data path; and use the data return switch 2012 to map the data to be exchanged on the second input terminal corresponding to the thread number to the second output terminal corresponding to the operating thread corresponding to the target thread.

[0136] In some example embodiments of this disclosure, based on the aforementioned scheme, the data processing instruction includes a data matching instruction, and the operation data corresponding to each operation thread in the thread bundle includes the data to be matched corresponding to each operation thread; the loading storage unit 201 includes: an address merging subunit 2013, used to compare the data to be matched and obtain a comparison result.

[0137] When the data processing instruction is a data matching instruction, the loading storage unit 201 is used to: generate a mask corresponding to each operation thread based on the comparison result; and write the mask corresponding to each operation thread back to the storage location corresponding to each operation thread in the register 202.

[0138] In some example embodiments of this disclosure, based on the aforementioned scheme, the address merging subunit 2013 is used to: convert the data to be matched into address format data for address comparison; and compare the address format data corresponding to each operation thread to obtain the comparison result.

[0139] In some example embodiments of this disclosure, based on the aforementioned scheme, the mask includes multiple mask bits, and each operation thread corresponds to one mask bit; the loading storage unit 201 is used to: in response to the same address format data corresponding to the reference operation thread and the matching operation thread, write the mask bit corresponding to the matching operation thread into the mask corresponding to the reference operation thread as a first preset identifier; the reference operation thread and the matching operation thread are any two different operation threads in the thread bundle; in response to different address format data corresponding to the reference operation thread and the matching operation thread, write the mask bit corresponding to the matching operation thread into the mask corresponding to the reference operation thread as a second preset identifier; the second preset identifier is different from the first preset identifier.

[0140] In some exemplary embodiments of this disclosure, based on the foregoing scheme, the loading storage unit 201 includes a crossbar switch, which further includes a data write switch 2011 and a data return switch 2012; the data processing device 1100 further includes a shared memory 203 connected to the loading storage unit 201, the shared memory 203 being used to perform data processing operations according to the access requests of the loading storage unit 201; the shared memory 203 is configured with multiple computing units, each operation thread corresponding to one computing unit; the loading storage unit 201 is implemented through the data write switch 2011 and the data return switch 2012. Data interaction with shared memory 203; data processing instructions include data reduction instructions, and the operation data corresponding to each operation thread in the thread bundle includes the data to be reduced corresponding to each operation thread; when the data processing instruction is a data reduction instruction, the loading storage unit 201 is used to: based on the correspondence between the arithmetic unit and the operation thread, use the data write switch 2011 to send the data to be reduced to the corresponding arithmetic unit; when the arithmetic unit completes the reduction operation, use the data return switch 2012 to write the reduction result data output by each arithmetic unit back to the storage location corresponding to each operation thread in the register 202.

[0141] In some example embodiments of this disclosure, based on the foregoing scheme, the loading storage unit 201 includes: a cross switch, which includes a data write switch 2011 and a data return switch 2012; the data write switch 2011 includes a plurality of first input terminals and a plurality of first output terminals; each operation thread corresponds to a first input terminal and a first output terminal.

[0142] The data processing device 1100 further includes: a shared memory 203 connected to the loading storage unit 201, the shared memory 203 including multiple storage banks; each first output terminal of the data write switch 2011 corresponds to one storage bank.

[0143] The loading storage unit 201 realizes data interaction with the shared memory 203 through the data write switch 2011 and the data return switch 2012; the data processing instructions include data loading instructions, and the operation data corresponding to each operation thread in the thread bundle includes the loading address corresponding to each operation thread.

[0144] When the data processing instruction is a data loading instruction, the loading memory unit 201 is used to: generate a first strobe signal based on the loading address; according to the first strobe signal, use the data write switch 2011 to complete the strobe configuration between multiple first input terminals and multiple first output terminals, map each loading address to the first memory bank among multiple memory banks, and send the data loading instruction to each first memory bank; use the data return switch 2012 to receive the loading data output by each first memory bank, and write the loading data back to the storage location in the register 202 corresponding to each operation thread.

[0145] In some example embodiments of this disclosure, based on the foregoing scheme, the loading storage unit 201 includes: a cross switch, the cross switch including a data write switch 2011, the data write switch 2011 including a plurality of first input terminals and a plurality of first output terminals; each operation thread corresponds to a first input terminal and a first output terminal.

[0146] The data processing device 1100 further includes: a shared memory 203 connected to the loading storage unit 201, the shared memory 203 including multiple storage banks; each first output terminal of the data write switch 2011 corresponds to one storage bank.

[0147] The loading storage unit 201 realizes data interaction with the shared memory 203 through the data write switch 2011; the data processing instructions include data storage instructions, and the operation data corresponding to each operation thread in the thread bundle includes the storage data and storage address corresponding to each operation thread.

[0148] When the data processing instruction is a data storage instruction, the loading storage unit 201 is used to: generate a second strobe signal based on the storage address; according to the second strobe signal, use the data write switch 2011 to complete the strobe configuration between multiple first input terminals and multiple first output terminals, map each storage address to a second storage bank among multiple storage banks, and send corresponding storage data and data storage instructions to each second storage bank; the data storage instruction is used to trigger the second storage bank to perform a write operation on the storage data.

[0149] In some example embodiments of this disclosure, based on the foregoing scheme, the loading storage unit 201 includes: a cross switch, the cross switch including a data write switch 2011 and a data return switch 2012, the data write switch 2011 including a plurality of first input terminals and a plurality of first output terminals; each operation thread corresponds to a first input terminal and a first output terminal.

[0150] The data processing device 1100 further includes: a shared memory 203 connected to the loading storage unit 201, the shared memory 203 including multiple storage banks; each first output terminal of the data write switch 2011 corresponds to a storage bank; the shared memory 203 is configured with multiple arithmetic units, such as arithmetic unit 0, arithmetic unit 1, arithmetic unit 2 to arithmetic unit n, and each operation thread corresponds to a arithmetic unit.

[0151] The loading storage unit 201 realizes data interaction with the shared memory 203 through the data write switch 2011 and the data return switch 2012; the data processing instructions include atomic operation instructions, and the operation data corresponding to each operation thread in the thread bundle includes the atomic operation data and access address corresponding to each operation thread.

[0152] When the data processing instruction is an atomic operation instruction, the load memory unit 201 is used to: generate a third strobe signal based on the access address; according to the third strobe signal, use the data write switch 2011 to complete the strobe configuration between multiple first input terminals and multiple first output terminals, map each access address to a third memory bank among multiple memory banks, and send the corresponding atomic operation data and atomic operation instruction to each third memory bank; according to the atomic operation instruction, use the arithmetic unit to perform arithmetic processing on the atomic operation data to obtain atomic operation result data; in response to the atomic operation instruction requesting data return, use the data return switch 2012 to receive the atomic operation result data output by each third memory bank, and write the atomic operation result data back to the storage location corresponding to each operation thread in the register 202.

[0153] The specific details of each module of the above data processing device have been described in detail in the corresponding data processing methods, so they will not be repeated here.

[0154] It should be noted that although several modules or units of the data processing apparatus have been mentioned in the detailed description above, this division is not mandatory. In fact, according to embodiments of this disclosure, the features and functions of two or more modules or units described above can be embodied in one module or unit. Conversely, the features and functions of one module or unit described above can be further divided and embodied by multiple modules or units.

[0155] Furthermore, in an exemplary embodiment of this disclosure, an electronic device capable of implementing the above-described data processing method is also provided.

[0156] Those skilled in the art will understand that various aspects of this disclosure can be implemented as a system, method, or program product. Therefore, various aspects of this disclosure can be embodied in the following forms: a completely hardware embodiment, a completely software embodiment (including firmware, microcode, etc.), or an embodiment combining hardware and software aspects, collectively referred to herein as a "circuit," "module," or "system."

[0157] An electronic device 1200 according to such an embodiment of the present disclosure will now be described with reference to FIG12. The electronic device 1200 shown in FIG12 is merely an example and should not impose any limitation on the functionality and scope of use of the embodiments of the present disclosure.

[0158] As shown in Figure 12, the electronic device 1200 is presented in the form of a general-purpose computing device. The components of the electronic device 1200 may include, but are not limited to: at least one processing unit 1210, at least one storage unit 1220, a bus 1230 connecting different system components (including the storage unit 1220 and the processing unit 1210), and a display unit 1240. Furthermore, the processing unit 1210 can be a parallel processing architecture, such as any one or more of a graphics processor, a neural network processing unit, a programmable logic device, and a tensor processing unit. In addition, the processing unit 1210 is configured with registers, shared memory, and a load memory unit configured with a crossbar switch and an address merging subunit. The shared memory is configured with multiple memory banks and multiple arithmetic units.

[0159] The storage unit stores program code that can be executed by the processing unit 1210, causing the processing unit 1210 to perform the steps described in the "Exemplary Methods" section above according to various exemplary embodiments of this disclosure.

[0160] Storage unit 1220 may include readable media in the form of volatile storage units, such as random access memory (RAM) 1221 and / or cache memory 1222, and may further include read-only memory (ROM) 1223.

[0161] Storage unit 1220 may also include a program / utility 1224 having a set (at least one) program module 1225, such program module 1225 including but not limited to: operating system, one or more application programs, other program modules and program data, each or some combination of these examples may include an implementation of a network environment.

[0162] Bus 1230 can represent one or more of several types of bus structures, including a memory cell bus or memory cell controller, a peripheral bus, a graphics acceleration port, a processing unit, or a local bus using any of the various bus structures.

[0163] Electronic device 1200 can also communicate with one or more external devices 1270 (e.g., keyboard, pointing device, Bluetooth device, etc.), and with one or more devices that enable a user to interact with electronic device 1200, and / or with any device that enables electronic device 1200 to communicate with one or more other computing devices (e.g., router, modem, etc.). This communication can be performed via input / output (I / O) interface 1250. Furthermore, electronic device 1200 can also communicate with one or more networks (e.g., local area network (LAN), wide area network (WAN), and / or public networks, such as the Internet) via network adapter 1260. As shown, network adapter 1260 communicates with other modules of electronic device 1200 via bus 1230. It should be understood that, although not shown in the figures, other hardware and / or software modules can be used in conjunction with electronic device 1200, including but not limited to: microcode, device drivers, redundant processing units, external disk drive arrays, RAID systems, tape drives, and data backup storage systems.

[0164] In exemplary embodiments of this disclosure, a computer-readable storage medium is also provided, on which a program product capable of implementing the methods described above is stored. In some possible embodiments, various aspects of this disclosure may also be implemented as a program product including program code that, when the program product is run on a terminal device, causes the terminal device to perform the steps described in the "Exemplary Methods" section of this specification according to various exemplary embodiments of this disclosure.

[0165] In the embodiments of this disclosure, the program product used to implement the above-described data processing method may employ a portable compact disc read-only memory (CD-ROM) and include program code, and may run on a terminal device, such as a personal computer. However, the program product of this disclosure is not limited thereto. In this document, the readable storage medium may be any tangible medium containing or storing a program that may be used by or in conjunction with an instruction execution system, apparatus, or device.

[0166] The program product may employ any combination of one or more readable media. A readable medium may be a readable signal medium or a readable storage medium. A readable storage medium may be, for example, but not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination thereof. More specific examples of readable storage media (a non-exhaustive list) include: an electrical connection having one or more wires, a portable disk, a hard disk, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination thereof.

[0167] Computer-readable signal media may include data signals propagated in baseband or as part of a carrier wave, carrying readable program code. Such propagated data signals may take various forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination thereof. A readable signal medium may also be any readable medium other than a readable storage medium, capable of sending, propagating, or transmitting programs for use by or in conjunction with an instruction execution system, apparatus, or device.

[0168] The program code contained on the readable medium may be transmitted using any suitable medium, including but not limited to wireless, wired, optical fiber, RF, etc., or any suitable combination thereof.

[0169] Program code for performing the operations of this disclosure can be written in any combination of one or more programming languages, including object-oriented programming languages ​​such as Java and C++, and conventional procedural programming languages ​​such as C or similar languages. The program code can execute entirely on the user's computing device, partially on the user's computing device, as a standalone software package, partially on the user's computing device and partially on a remote computing device, or entirely on a remote computing device or server. In cases involving remote computing devices, the remote computing device can be connected to the user's computing device via any type of network, including a local area network (LAN) or a wide area network (WAN), or it can be connected to an external computing device (e.g., via the Internet using an Internet service provider).

[0170] Furthermore, the above figures are merely illustrative of the processes included in the method according to exemplary embodiments of this disclosure and are not intended to be limiting. It is readily understood that the processes shown in the above figures do not indicate or limit the temporal order of these processes. Additionally, it is readily understood that these processes may be executed synchronously or asynchronously, for example, in multiple modules.

[0171] From the above description of the embodiments, those skilled in the art will readily understand that the exemplary embodiments described herein can be implemented by software or by combining software with necessary hardware. Therefore, the technical solutions according to the embodiments of this disclosure can be embodied in the form of a software product, which can be stored in a non-volatile storage medium (such as a CD-ROM, USB flash drive, external hard drive, etc.) or on a network, including several instructions to cause a computing device (such as a personal computer, server, touch terminal, or network device, etc.) to execute the methods according to the embodiments of this disclosure.

[0172] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and embodiments are to be considered exemplary only, and the true scope and spirit of this disclosure are indicated by the claims.

[0173] It should be understood that this disclosure is not limited to the precise structures described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of this disclosure is limited only by the appended claims.

Claims

1. A data processing apparatus, characterized in that, The device includes: a register for storing operation data of each operation thread in a thread bundle; and a loading storage unit connected to the register, wherein the loading storage unit is configured to read operation data corresponding to each operation thread in the thread bundle from the register in response to a data processing instruction sent for the thread bundle, and to perform corresponding data processing operations on the operation data based on the data processing instruction using at least one hardware function module inside the loading storage unit.

2. The data processing apparatus according to claim 1, characterized in that, The data processing instruction includes a data shuffling instruction. The operation data corresponding to each operation thread in the thread bundle includes the data to be exchanged corresponding to each operation thread and the thread number of the target thread corresponding to each operation thread. The loading storage unit includes a crossbar switch, which includes multiple input terminals and multiple output terminals. Each operation thread corresponds to one input terminal and one output terminal. When the data processing instruction is the data shuffling instruction, the loading storage unit is used to: input the data to be exchanged corresponding to each operation thread to the multiple input terminals of the crossbar switch respectively; use the crossbar switch to map the data to be exchanged on the input terminal corresponding to the thread number to the output terminal corresponding to the operation thread corresponding to the target thread; and write the shuffling result data output by the multiple output terminals back to the storage location in the register corresponding to each operation thread.

3. The data processing apparatus according to claim 2, characterized in that, The cross switch includes: a data write switch, which includes multiple first input terminals and multiple first output terminals, with each operation thread corresponding to one first input terminal and one first output terminal; the loading storage unit is used to: input the data to be exchanged corresponding to each operation thread to the multiple first input terminals of the data write switch respectively.

4. The data processing apparatus according to claim 3, characterized in that, The cross switch further includes: a data return switch, which includes multiple second input terminals and multiple second output terminals; each operation thread corresponds to one second input terminal and one second output terminal; the loading storage unit is used to: establish a data path between the multiple first output terminals and the multiple second input terminals based on the correspondence between the first output terminals, the second input terminals and the operation threads; use the thread number as a control signal for the data write switch or the data return switch; and use the data write switch, the data return switch and the data path to map the data to be exchanged on the first input terminal corresponding to the thread number to the second output terminal corresponding to the operation thread corresponding to the target thread.

5. The data processing apparatus according to claim 4, characterized in that, When the thread number is used as the control signal for the data write switch, the loading storage unit is used to: use the data write switch to map the data to be exchanged on the first input terminal corresponding to the thread number to the first output terminal corresponding to the operation thread corresponding to the target thread; Through the data path, the data to be exchanged on the first output terminal is transmitted to the corresponding second input terminal; based on the correspondence between the second input terminal, the second output terminal, and the operation thread, the data to be exchanged on the second input terminal is mapped to the second output terminal corresponding to the operation thread through the data return switch.

6. The data processing apparatus according to claim 4, characterized in that, When the thread number is used as the control signal for the data return switch, the loading storage unit is configured to: based on the correspondence between the first input terminal, the first output terminal, and the operating thread, map the data to be exchanged on the first input terminal to the first output terminal corresponding to the operating thread through the data write switch; transmit the data to be exchanged on the first output terminal to the corresponding second input terminal through the data path; and use the data return switch to map the data to be exchanged on the second input terminal corresponding to the thread number to the second output terminal corresponding to the operating thread corresponding to the target thread.

7. The data processing apparatus according to claim 1, characterized in that, The data processing instruction includes a data matching instruction, and the operation data corresponding to each operation thread in the thread bundle includes the data to be matched corresponding to each operation thread; the loading storage unit includes an address merging subunit, used to compare the data to be matched and obtain a comparison result; when the data processing instruction is the data matching instruction, the loading storage unit is used to: generate a mask corresponding to each operation thread according to the comparison result; and write the mask corresponding to each operation thread back to the storage location in the register corresponding to each operation thread.

8. The data processing apparatus according to claim 7, characterized in that, The address merging subunit is configured to: convert the data to be matched into address format data for address comparison; and compare the address format data corresponding to each of the operation threads to obtain the comparison result.

9. The data processing apparatus according to claim 8, characterized in that, The mask includes multiple mask bits, with each operation thread corresponding to one mask bit; the loading storage unit is used to: in response to the address format data corresponding to the reference operation thread and the matching operation thread being the same, write the mask bit corresponding to the matching operation thread into the mask corresponding to the reference operation thread as a first preset identifier; the reference operation thread and the matching operation thread are any two different operation threads in the thread bundle; In response to the difference in address format data between the reference operation thread and the matching operation thread, a second preset identifier is written into the mask corresponding to the matching operation thread in the mask corresponding to the reference operation thread; the second preset identifier is different from the first preset identifier.

10. The data processing apparatus according to claim 1, characterized in that, The loading storage unit includes a crossbar switch, which further includes a data write switch and a data return switch. The data processing device further includes shared memory connected to the loading storage unit. The shared memory is used to perform data processing operations according to the access request of the loading storage unit. The shared memory is configured with multiple computing units, and each operation thread corresponds to one computing unit. The loading storage unit interacts with the shared memory through the data write switch and the data return switch. The data processing instruction includes a data reduction instruction, and the operation data corresponding to each operation thread in the thread bundle includes the data to be reduced corresponding to each operation thread. When the data processing instruction is the data reduction instruction, the loading storage unit is used to: based on the correspondence between the computing unit and the operation thread, use the data write switch to send the data to be reduced to the corresponding computing unit; when the computing unit completes the reduction operation, use the data return switch to write the reduction result data output by each computing unit back to the storage location in the register corresponding to each operation thread.

11. The data processing apparatus according to claim 1, characterized in that, The loading storage unit includes a crossbar switch, which includes a data write switch and a data return switch; the data write switch includes multiple first input terminals and multiple first output terminals; each operation thread corresponds to one first input terminal and one first output terminal; the data processing device further includes a shared memory connected to the loading storage unit, the shared memory including multiple storage banks; each first output terminal of the data write switch corresponds to one storage bank; the loading storage unit realizes data interaction with the shared memory through the data write switch and the data return switch; the data processing instruction includes a data loading instruction, and each operation thread in the thread bundle... The operation data corresponding to the process includes the load address corresponding to each operation thread; when the data processing instruction is the data loading instruction, the load storage unit is used to: generate a first strobe signal based on the load address; according to the first strobe signal, use the data write switch to complete the strobe configuration between the plurality of first input terminals and the plurality of first output terminals, map each load address to the first storage bank among the plurality of storage banks, and send a data loading instruction to each first storage bank; use the data return switch to receive the load data output by each first storage bank, and write the load data back to the storage location in the register corresponding to each operation thread.

12. The data processing apparatus according to claim 1, characterized in that, The loading storage unit includes a crossbar switch, which includes a data write switch. The data write switch includes multiple first input terminals and multiple first output terminals. Each operation thread corresponds to one first input terminal and one first output terminal. The data processing device further includes a shared memory connected to the loading storage unit. The shared memory includes multiple memory banks. Each first output terminal of the data write switch corresponds to one memory bank. The loading storage unit interacts with the shared memory through the data write switch. The data processing instruction includes a data storage instruction. The operation data corresponding to each operation thread in the thread bundle includes the storage data and storage address corresponding to each operation thread. When the data processing instruction is the data storage instruction, the loading storage unit is used to: generate a second strobe signal based on the storage address; according to the second strobe signal, use the data write switch to complete the strobe configuration between the multiple first input terminals and the multiple first output terminals, map each storage address to a second memory bank among the multiple memory banks, and send corresponding storage data and data storage instructions to each second memory bank. The data storage instruction is used to trigger the second memory bank to perform a write operation on the storage data.

13. The data processing apparatus according to claim 1, characterized in that, The loading storage unit includes a crossbar switch, which includes a data write switch and a data return switch. The data write switch includes multiple first input terminals and multiple first output terminals. Each operation thread corresponds to one first input terminal and one first output terminal. The data processing device further includes a shared memory connected to the loading storage unit. The shared memory includes multiple memory banks. Each first output terminal of the data write switch corresponds to one memory bank. The shared memory is configured with multiple arithmetic units, and each operation thread corresponds to one arithmetic unit. The loading storage unit interacts with the shared memory through the data write switch and the data return switch. The data processing instructions include atomic operation instructions, and the operation data corresponding to each operation thread in the thread bundle includes the atomic operation data and access address corresponding to each operation thread. Address; when the data processing instruction is the atomic operation instruction, the loading storage unit is configured to: generate a third strobe signal based on the access address; according to the third strobe signal, use the data write switch to complete the strobe configuration between the plurality of first input terminals and the plurality of first output terminals, map each access address to a third storage bank among the plurality of storage banks, and send corresponding atomic operation data and atomic operation instructions to each of the third storage banks; according to the atomic operation instruction, use the arithmetic unit to perform arithmetic processing on the atomic operation data to obtain atomic operation result data; in response to the atomic operation instruction requesting data return, use the data return switch to receive the atomic operation result data output by each of the third storage banks, and write the atomic operation result data back to the storage location in the register corresponding to each of the operation threads.

14. A data processing method, characterized in that, The method is applied to a load storage unit; the load storage unit is connected to a register, the register being used to store operation data of each operation thread in a thread bundle; the method includes: in response to a data processing instruction sent for the thread bundle, reading operation data corresponding to each operation thread in the thread bundle from the register; and, based on the data processing instruction, performing a corresponding data processing operation on the operation data using at least one hardware function module inside the load storage unit.

15. The data processing method according to claim 14, characterized in that, The loading storage unit is configured with a crossbar switch, which includes multiple input terminals and multiple output terminals. Each operation thread corresponds to one input terminal and one output terminal. The data processing instruction includes a data shuffling instruction. The operation data corresponding to each operation thread in the thread bundle includes the data to be exchanged corresponding to each operation thread and the thread number of the target thread corresponding to each operation thread. Based on the data processing instruction, the operation data is processed using at least one hardware functional module inside the loading storage unit. This includes: when the data processing instruction is the data shuffling instruction, inputting the data to be exchanged corresponding to each operation thread to the multiple input terminals of the crossbar switch; using the crossbar switch to map the data to be exchanged on the input terminal corresponding to the thread number to the output terminal corresponding to the operation thread corresponding to the target thread; and writing the shuffling result data output by the multiple output terminals back to the storage location in the register corresponding to each operation thread.

16. The data processing method according to claim 15, characterized in that, The cross switch includes a data write switch; the data write switch includes multiple first input terminals and multiple first output terminals; each operation thread corresponds to one first input terminal and one first output terminal; the step of inputting the data to be exchanged corresponding to each operation thread to the multiple input terminals of the cross switch includes: inputting the data to be exchanged corresponding to each operation thread to the multiple first input terminals of the data write switch.

17. The data processing method according to claim 16, characterized in that, The cross switch further includes a data return switch; the data return switch includes multiple second input terminals and multiple second output terminals; each operation thread corresponds to one second input terminal and one second output terminal; the step of using the cross switch to map the data to be exchanged on the input terminal corresponding to the thread number to the output terminal corresponding to the operation thread corresponding to the target thread includes: establishing a data path between the multiple first output terminals and the multiple second input terminals based on the correspondence between the first output terminal, the second input terminal and the operation thread; using the thread number as the control signal of the data write switch or the data return switch; and using the data write switch, the data return switch and the data path to map the data to be exchanged on the first input terminal corresponding to the thread number to the second output terminal corresponding to the operation thread corresponding to the target thread.

18. The data processing method according to claim 17, characterized in that, When the thread number is used as the control signal for the data write switch, the step of mapping the data to be exchanged on the first input terminal corresponding to the thread number to the second output terminal corresponding to the operation thread corresponding to the target thread using the data write switch, the data return switch, and the data path includes: mapping the data to be exchanged on the first input terminal corresponding to the thread number to the first output terminal corresponding to the operation thread corresponding to the target thread using the data write switch; transmitting the data to be exchanged on the first output terminal to the corresponding second input terminal through the data path; and mapping the data to be exchanged on the second input terminal to the second output terminal corresponding to the operation thread based on the correspondence between the second input terminal, the second output terminal, and the operation thread using the data return switch.

19. The data processing method according to claim 17, characterized in that, When the thread number is used as the control signal for the data return switch, the step of mapping the data to be exchanged on the first input terminal corresponding to the thread number to the second output terminal corresponding to the operation thread corresponding to the target thread using the data write switch, the data return switch, and the data path includes: based on the correspondence between the first input terminal, the first output terminal, and the operation thread, mapping the data to be exchanged on the first input terminal to the first output terminal corresponding to the operation thread using the data write switch; transmitting the data to be exchanged on the first output terminal to the corresponding second input terminal through the data path; and using the data return switch to map the data to be exchanged on the second input terminal corresponding to the thread number to the second output terminal corresponding to the operation thread corresponding to the target thread.

20. The data processing method according to claim 14, characterized in that, The loading storage unit is configured with an address merging subunit for merging operations based on access addresses; the data processing instruction includes a data matching instruction, and the operation data corresponding to each operation thread in the thread bundle includes the data to be matched corresponding to each operation thread; the step of performing corresponding data processing operations on the operation data based on the data processing instruction and utilizing at least one hardware functional module inside the loading storage unit includes: when the data processing instruction is the data matching instruction, comparing the data to be matched using the address merging subunit to obtain a comparison result; generating a mask corresponding to each operation thread based on the comparison result; and writing the mask corresponding to each operation thread back to the storage location in the register corresponding to each operation thread.

21. The data processing method according to claim 20, characterized in that, The step of comparing the data to be matched using the address merging subunit to obtain a comparison result includes: converting the data to be matched into address format data for address comparison; and using the address merging subunit to compare the address format data corresponding to each of the operation threads to obtain the comparison result.

22. The data processing method according to claim 21, characterized in that, The mask includes multiple mask bits, with each operation thread corresponding to one mask bit; generating the mask corresponding to each operation thread based on the comparison result includes: in response to the same address format data corresponding to the reference operation thread and the matching operation thread, writing the mask bit corresponding to the matching operation thread into the mask corresponding to the reference operation thread as a first preset identifier; the reference operation thread and the matching operation thread are any two different operation threads in the thread bundle; in response to different address format data corresponding to the reference operation thread and the matching operation thread, writing the mask bit corresponding to the matching operation thread into the mask corresponding to the reference operation thread as a second preset identifier; the second preset identifier is different from the first preset identifier.

23. The data processing method according to claim 14, characterized in that, The loading storage unit is configured with a crossbar switch; the crossbar switch further includes a data write switch and a data return switch; the loading storage unit is also connected to shared memory, and the loading storage unit realizes data interaction with the shared memory through the data write switch and the data return switch; the shared memory is used to perform data processing operations according to the access request of the loading storage unit; the shared memory is configured with multiple computing units, and each operation thread corresponds to one computing unit; the data processing instruction includes a data reduction instruction, and the operation data corresponding to each operation thread in the thread bundle includes the data to be reduced corresponding to each operation thread; the step of performing corresponding data processing operations on the operation data based on the data processing instruction and using at least one hardware functional module inside the loading storage unit includes: when the data processing instruction is the data reduction instruction, based on the correspondence between the computing unit and the operation thread, using the data write switch to send the data to be reduced to the corresponding computing unit; when the computing unit completes the reduction operation, using the data return switch to write the reduction result data output by each computing unit back to the storage location in the register corresponding to each operation thread.

24. The data processing method according to claim 14, characterized in that, The loading storage unit is configured with a crossbar switch, which includes a data write switch and a data return switch. The data write switch includes multiple first input terminals and multiple first output terminals. Each operation thread corresponds to one first input terminal and one first output terminal. The loading storage unit is also connected to shared memory, and the loading storage unit realizes data interaction with the shared memory through the data write switch and the data return switch. The shared memory includes multiple storage banks. Each first output terminal of the data write switch corresponds to one storage bank. The data processing instruction includes a data loading instruction, and the operation data corresponding to each operation thread in the thread bundle includes the loading address corresponding to each operation thread. The data processing instruction includes a data loading instruction. According to the processing instruction, at least one hardware functional module inside the loading storage unit is used to perform corresponding data processing operations on the operation data, including: when the data processing instruction is the data loading instruction, generating a first strobe signal based on the loading address; according to the first strobe signal, using the data write switch to complete the strobe configuration between the plurality of first input terminals and the plurality of first output terminals, mapping each loading address to a first storage bank among the plurality of storage banks, and sending a data loading instruction to each first storage bank; using the data return switch to receive the loading data output by each first storage bank, and writing the loading data back to the storage location in the register corresponding to each operation thread.

25. The data processing method according to claim 14, characterized in that, The loading storage unit is configured with a crossbar switch, which includes a data write switch. The data write switch includes multiple first input terminals and multiple first output terminals. Each operation thread corresponds to one first input terminal and one first output terminal. The loading storage unit is also connected to shared memory, and the loading storage unit interacts with the shared memory through the data write switch. The shared memory includes multiple memory banks. Each first output terminal of the data write switch corresponds to one memory bank. The data processing instructions include data storage instructions, and the operation data corresponding to each operation thread in the thread bundle includes the storage data and storage address corresponding to each operation thread. In response to the data processing instruction, at least one hardware functional module within the loading storage unit is used to perform a corresponding data processing operation on the operation data, including: when the data processing instruction is the data storage instruction, generating a second strobe signal based on the storage address; according to the second strobe signal, using the data write switch to complete the strobe configuration between the plurality of first input terminals and the plurality of first output terminals, mapping each storage address to a second storage bank among the plurality of storage banks, and sending corresponding storage data and data storage instruction to each second storage bank; the data storage instruction is used to trigger the second storage bank to perform a write operation on the storage data.

26. The data processing method according to claim 14, characterized in that, The loading storage unit is configured with a crossbar switch, which includes a data write switch and a data return switch. The data write switch includes multiple first input terminals and multiple first output terminals. Each operation thread corresponds to one first input terminal and one first output terminal. The loading storage unit is also connected to shared memory, and the loading storage unit realizes data interaction with the shared memory through the data write switch and the data return switch. The shared memory includes multiple storage banks. Each first output terminal of the data write switch corresponds to one storage bank. The shared memory is configured with multiple computing units, and each operation thread corresponds to one computing unit. The data processing instructions include atomic operation instructions, and the operation data corresponding to each operation thread in the thread bundle includes the atomic operation data and access address corresponding to each operation thread. Based on the data processing instructions, at least the internal memory of the loading storage unit... A hardware functional module performs corresponding data processing operations on the operation data, including: when the data processing instruction is the atomic operation instruction, generating a third strobe signal based on the access address; according to the third strobe signal, using the data write switch to complete the strobe configuration between the plurality of first input terminals and the plurality of first output terminals, mapping each access address to a third memory bank among the plurality of memory banks, and sending corresponding atomic operation data and atomic operation instructions to each of the third memory banks; according to the atomic operation instruction, using the arithmetic unit to perform arithmetic processing on the atomic operation data to obtain atomic operation result data; in response to the atomic operation instruction requesting data return, using the data return switch to receive the atomic operation result data output by each of the third memory banks, and writing the atomic operation result data back to the register at the storage location corresponding to each of the operation threads.

27. An electronic device, characterized in that, include: processor; and a memory for storing executable instructions of the processor; wherein the processor is configured to perform the data processing method of any one of claims 14-26 by executing the executable instructions.

28. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by a processor, it implements the data processing method according to any one of claims 14-26.

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