Memory management method, memory management device, electronic device and storage medium

Abstract

At least one embodiment of the invention provides a memory management method, a memory management device, an electronic device and a storage medium. The memory management method comprises the steps that a page table is created on a memory management layer, and the page table is used for translating a virtual address into a physical address; in response to a first base page allocated at the hardware architecture layer with a first size value, the page table is allocated with a second base page of a second size value, where the second size value is N times the first size value, N being a positive integer, and such that each page entry of the page table corresponds to N consecutive first base pages of a corresponding next-level page. According to the memory management method, the memory occupation overhead caused by the physical page metadata can be reduced.

Description

Technical Field

[0001] Embodiments of this disclosure relate to memory management methods, memory management devices, electronic devices, and storage media. Background Technology

[0002] Common operating systems (such as Linux) use virtual memory to provide independent memory space for programs (processes). Under virtual memory, programs access memory through virtual addresses, avoiding address conflicts and data security issues that occur when different programs use absolute physical addresses to access memory.

[0003] Virtual memory mechanisms can be implemented through paging. The page table is a key component of paging memory management, enabling the operating system to effectively manage memory resources while providing programs with independent address spaces. The page table is created and maintained by the operating system kernel. Under paging, physical memory is divided into several fixed-size physical pages. The operating system provides each program with a page table, and each page table entry (or page table entry) corresponds to a page in the virtual address space. The entry contains the physical address information of that page (usually the base address of the physical page frame), used to translate the virtual page addresses used by the program into physical page addresses. Summary of the Invention

[0004] At least one embodiment of this disclosure provides a memory management method, comprising: creating a page table at a memory management layer, wherein the page table is used to translate virtual addresses into physical addresses; in response to allocating a first base page of a first size value at a hardware architecture layer, allocating a second base page of a second size value to the page table, such that each page table entry corresponds to N consecutive first base pages of the corresponding next-level page, wherein the second size value is N times the first size value, and N is a positive integer.

[0005] At least one embodiment of this disclosure provides a memory management apparatus, including: a page table creation unit configured to: create a page table at a memory management layer, wherein the page table is used to translate virtual addresses into physical addresses; and, in response to a first base page having a first size value allocated at a hardware architecture layer, allocate a second base page having a second size value to the page table, such that each page table entry corresponds to N consecutive first base pages of the corresponding next-level page, wherein the second size value is N times the first size value, and N is a positive integer.

[0006] At least one embodiment of this disclosure provides an electronic device including at least one processing unit and a memory; wherein the memory stores computer-readable instructions and is communicatively connected to at least one processing unit; the at least one processing unit is configured to execute the computer-readable instructions stored in the memory to implement the memory management method described above.

[0007] At least one embodiment of this disclosure provides a computer-readable storage medium storing computer-readable instructions that, when executed by a processor, implement the memory management method described above. Attached Figure Description

[0008] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the accompanying drawings of the embodiments of this disclosure will be briefly described below. Clearly, the drawings described below only relate to some embodiments of this disclosure and are not intended to limit the scope of this disclosure.

[0009] Figure 1 A schematic diagram illustrating an exemplary hierarchical page table and MMU address translation process is shown.

[0010] Figure 2 A schematic diagram illustrating an exemplary 2MB large-page MMU page table translation process is shown.

[0011] Figure 3 A schematic diagram of an example 64K MMU page table translation process is shown;

[0012] Figure 4 A flowchart of a memory management method according to at least one embodiment of the present disclosure is shown;

[0013] Figure 5 A schematic diagram of a memory management apparatus according to at least one embodiment of the present disclosure is shown;

[0014] Figure 6A A schematic diagram of a page table design for a 64K base page based on a 4K MMU according to at least one embodiment of the present disclosure is shown;

[0015] Figure 6B A schematic diagram illustrating the mapping relationship between pgd_t / pmd_t and 64K base pages according to at least one embodiment of the present disclosure is shown;

[0016] Figure 7 A schematic diagram is shown illustrating TLB space / hit rate optimization under the Svnapot feature according to at least one embodiment of the present disclosure;

[0017] Figure 8 A schematic diagram of an optimized design for page table entries based on Svnapot according to at least one embodiment of the present disclosure is shown;

[0018] Figure 9 A schematic diagram of an electronic device according to at least one embodiment of the present disclosure is shown;

[0019] Figure 10 A schematic diagram of a computer-readable storage medium according to at least one embodiment of the present disclosure is shown;

[0020] Figure 11 A schematic diagram of another electronic device according to at least one embodiment of the present disclosure is shown. Detailed Implementation

[0021] Reference will now be made in detail to specific embodiments of the present disclosure, examples of which are illustrated in the accompanying drawings. Although the present disclosure will be described in conjunction with specific embodiments, it will be understood that it is not intended to limit the present disclosure to the described embodiments. Rather, it is intended to cover variations, modifications, and equivalents included within the spirit and scope of the present disclosure as defined by the appended claims. It should be noted that the method operations described herein can be implemented by any functional block or functional arrangement, and any functional block or functional arrangement can be implemented as a physical entity or a logical entity, or a combination of both.

[0022] To enable those skilled in the art to better understand this disclosure, the disclosure will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0023] Note that the examples described below are merely specific examples and are not intended to limit the embodiments of this disclosure to the specific shapes, hardware, connections, operations, values, conditions, data, sequences, etc., shown and described. Those skilled in the art can utilize the concepts of this disclosure to construct further embodiments not mentioned herein by reading this specification.

[0024] The terminology used in this disclosure is that which is currently widely used in the art in consideration of the functionality of this disclosure; however, these terms may vary depending on the intent, precedent, or new technology of those skilled in the art. Furthermore, specific terms may be chosen by the applicant, and in such cases, their detailed meanings will be described in the detailed description of this disclosure. Therefore, the terminology used in this specification should not be construed as simple names, but rather based on the meaning of the terms and the overall description of this disclosure.

[0025] This disclosure uses flowcharts to illustrate the operations performed by the system according to embodiments of this application. It should be understood that the preceding or following operations are not necessarily performed in exact order. Instead, various steps can be processed in reverse order or simultaneously, as needed. Furthermore, other operations can be added to these processes, or one or more steps can be removed from them.

[0026] First, the abbreviations and related terms involved in this application are defined and explained.

[0027] The Memory Management Unit (MMU) is used to map virtual addresses to physical addresses and to provide hardware mechanisms for memory access authorization.

[0028] The Translation Lookaside Buffer (TLB), also known as the page table cache or address-bypass cache, is a type of cache used by the CPU's memory management unit to improve the translation speed from virtual addresses to physical addresses.

[0029] A page table is a data structure used by the operating system to store the mapping between virtual addresses and physical addresses. Generally, each process has its own page table, which manages the relationship between its virtual address space and physical memory.

[0030] A page table page is a physical memory page that stores page tables.

[0031] A data page is a physical memory page primarily used to store process data. This data can be variables, arrays, objects, and other actual content used by the program at runtime.

[0032] A base page refers to the smallest unit of memory management and allocation as perceived by the software. For example, in a traditional RISC-V kernel, the base page size is 4KB.

[0033] The basic physical page refers to the granularity of memory pages managed by hardware (e.g., MMU). For example, the MMU of the RISC-V architecture uses 4K as the smallest memory page granularity, meaning the basic physical page is 4K.

[0034] It is understood that the terms defined above are merely exemplary definitions in specific application scenarios to better understand this application, and this disclosure is not limited thereto. For example, the terms described above for a specific processor architecture (e.g., RISC-V) can be extended to other types of processor architectures (e.g., x86, RAM, etc.).

[0035] As mentioned above, to avoid address conflicts and data security issues when different programs access memory using absolute physical addresses, a virtual memory mechanism was introduced. The virtual memory mechanism can be implemented through paging, thus translating access to virtual addresses into access to physical addresses.

[0036] When a processor (such as a CPU) actually accesses memory, the processor's memory management unit (MMU) translates the access to a virtual address into an access to a physical address by querying the page table of the current program.

[0037] For example, when the CPU attempts to access a virtual address, it performs the following steps to look up the physical address using the page table.

[0038] First, address splitting is performed. The CPU splits the virtual address into three parts: the page directory index, the page table index, and the offset within the page. The specific size of these parts depends on the system architecture and the page table hierarchy.

[0039] Next, the page directory is searched. The CPU uses the page directory index to find the corresponding page table base address in the first-level page directory.

[0040] Next, the page table is searched. Based on the page table base address and page table index, the CPU searches for the specific page table entry in the second-level page table.

[0041] Next, the physical address can be obtained. If the valid bit in the page table entry is 1 (indicating that the page is valid), the CPU can obtain the base address of the physical page frame from that entry, and then add this base address to the page offset in the virtual address to obtain the final physical address.

[0042] Finally, the CPU accesses physical memory. After obtaining the physical address, it can directly access the data in physical memory.

[0043] If an invalid page table entry is found during the page table lookup process (i.e., the page is not in physical memory), a page fault exception will occur. The operating system kernel will then intervene, reading the page from disk into physical memory, updating the page table, and retrying the original access instruction. This entire process utilizes the hardware TLB to accelerate the translation from virtual to physical addresses, reducing the overhead of looking up the page table on every access. The TLB caches recently used page table entries, enabling rapid translation of frequently accessed addresses and improving memory access speed.

[0044] Figure 1 A schematic diagram of an exemplary hierarchical page table and MMU address translation process is shown.

[0045] See Figure 1 Corresponding to the exemplary 39-bit virtual address, it may include fields such as the page global directory offset (pgd offset, bits 30-38), the page middle directory offset (pmd offset, bits 21-29), the page table entry offset (pte offset, bits 12-20), and the address offset within the page (data offset, bits 0-11).

[0046] The page table base address can be used to determine the page global directory (also known as a first-level page table page). The corresponding pgd_t can be found in the page global directory using the pgd offset. The pgd_t typically includes a data structure representing each entry in the page global directory (or page global directory entry), which can point to a specific intermediate page directory (also known as an intermediate-level page table page).

[0047] You can use `pgd_t` in conjunction with `pmd offset` to find the corresponding `pmd_t` in the intermediate page table. `pmd_t` typically includes a data structure representing each entry in the intermediate page table (or intermediate page table entry), which can point to a specific page table entry page (also known as the last-level page table page).

[0048] You can use `pmd_t` in conjunction with `pte_offset` to look up the corresponding `pte_t` in a page table entry. `pmd_t` typically includes a data structure representing each entry (or page table entry page entry) in the page table entry, which can point to a specific data page.

[0049] The final physical address can be calculated using `pte_t` in conjunction with the data offset. For example, physical address = physical address in `pte_t` + data offset.

[0050] In the example above, the page table base address and multiple offsets help the operating system to effectively manage and access virtual memory, correctly mapping the corresponding locations in physical memory to the virtual address space.

[0051] It is understood that the fields of the virtual address described above are merely examples, and the number of bits of the virtual address fields or the number of offsets can be set as needed.

[0052] In the example above involving multi-level page tables, the MMU's page table translation process involves multiple memory accesses, which is too slow relative to the CPU's execution speed. Therefore, the CPU typically also includes a Translation Lookahead (TLB) to cache the MMU's lookup results and quickly retrieve the translation result from the TLB on the next memory access, saving the performance overhead of the MMU looking up page tables. However, the TLB's cache capacity is limited. When a TLB cache miss occurs, it is still necessary to use, for example, see [link to example]. Figure 1 The page table can be queried in this way.

[0053] Currently, operating systems (such as Linux) typically use a default physical page size of 4KB for their paging mechanism. In server scenarios with a large amount of physical memory, such as servers, a 4KB physical page size can present the following problems.

[0054] On the one hand, the actual memory space used by the program is much larger than 4K, and there are many TLB misses during the operation, which results in a large performance overhead from the MMU page table lookup operations.

[0055] On the other hand, in memory management mechanisms such as Linux, each basic physical page has a corresponding basic page structure (struct page) for managing that physical page. For example, the basic page structure may contain information related to the physical page, such as page number, page status, and page content. When the total amount of physical memory is large and the number of basic physical pages is relatively small, the number of basic page structures increases relatively. Since the basic page structures occupy actual physical memory, this leads to a relatively large memory overhead.

[0056] For example, there are generally two solutions to improve TLB hit rate and reduce MMU page table query overhead: one is a big page solution based on merging basic physical pages; the other is a hardware solution based on larger basic physical pages.

[0057] First, we will introduce the large-page scheme for merging basic physical pages.

[0058] For example, Linux provides two big page mechanisms: Hugetlb and Transparent Huge Page (THP). The core idea of ​​both is to allow programs to map larger contiguous physical memory, merge multiple physical pages into one big page, and each big page occupies only one entry in the TLB, reducing TLB space usage, thereby improving TLB hit rate and reducing the number of page table translation query levels and performance overhead.

[0059] Figure 2 A schematic diagram of an exemplary 2MB large-page MMU page table translation process is shown.

[0060] See Figure 2 An exemplary 39-bit virtual address may include various address parts such as the pgd offset (bits 30-38), the pmd offset (bits 21-29), and the data offset (bits 0-20) within the page. Figure 1 Similarly, the page table base address and multiple offsets help the operating system to effectively manage and access virtual memory, correctly mapping the corresponding locations in physical memory within the virtual address space.

[0061] and Figure 1 The difference is, Figure 2 The underlying physical page is a 2MB big page, not... Figure 1 The 4K small pages in the middle. Because large pages were used, Figure 2 Virtual addresses do not include Figure 1 The pte offset in the pte is directly mapped to a big page using pmd_t.

[0062] It is understood that the fields of the virtual address described above are merely examples, and the number of bits of the virtual address fields or the number of offsets can be set as needed.

[0063] The inventors of this disclosure recognized that while the big page mechanism reduces the probability of TLB misses, it also introduces new problems. First, the big page mechanism allocates and maps large contiguous blocks of physical memory for programs. When the system's free contiguous physical memory is insufficient, data migration and page merging operations are required on several underlying physical pages that are currently in use (e.g., transferring data from one page to another). Figure 1 The 4K base physical pages in the middle are merged into, for example Figure 2 The 2MB big page in the code introduces new performance overhead. Secondly, the big page mechanism does not change the underlying physical page size (e.g., it remains 2MB). Figure 1 The 4K base physical page does not address the memory overhead of the base physical page's metadata structure.

[0064] The following section introduces a hardware solution based on a larger base physical page.

[0065] Some CPU architectures' MMUs support base physical pages larger than 4K, including up to 64K. Each 64K of physical memory occupies one item in the TLB, reducing TLB space usage and the probability of TLB misses compared to 4K physical pages. Simultaneously, larger base physical pages reduce the number of physical page metadata structures, lowering memory overhead.

[0066] Figure 3 A schematic diagram of an example 64K MMU page table translation process is shown.

[0067] See Figure 3 In the corresponding CPU architecture, the virtual address consists of different parts (e.g., different fields), each part corresponding to a different level of address translation. For example, the virtual address includes TTBR select (Translation Table Base Register Select), level 2 index, level 3 index, and data offset, as well as other optional parts.

[0068] In the CPU architecture described above, the TTBR is the Translation Table Base Address Register, used to store the base address of the page table for the current process. TTBR select can be used to select the correct TTBR (TTBRx), thereby locating the correct page table. Level 2 Index and Level 3 Index can be used to locate specific page table entries or segment table entries within the page table (e.g., level2 pte_t, level3 pte_t). Data offset is used to determine the offset within the physical page, used to find the specific location of data within the data page.

[0069] See Figure 3 In the CPU architecture, each physical page is 64K in size.

[0070] It is understood that the fields of the virtual address described above are merely examples, and the number of bits of the virtual address fields or the number of offsets can be set as needed.

[0071] The inventors of this disclosure recognized that supporting different sizes of base physical pages increases the complexity of MMU hardware design. Therefore, not all CPU architectures support larger base physical pages; for example, x86 architecture and RISC-V architecture currently only support 4K physical base pages.

[0072] At least one embodiment of the present invention provides a memory management method, a memory management device, an electronic device, and a storage medium, which can be implemented in one or more of the following aspects, such as providing a larger physical base page mechanism when the hardware MMU does not support a larger physical base page (e.g., 64K), thereby reducing the memory overhead caused by physical page metadata; or reducing the probability of TLB misses and improving operating performance; or avoiding the large page merging overhead in the large page mechanism.

[0073] Figure 4 A flowchart of a memory management method according to at least one embodiment of the present disclosure is shown. See also Figure 4 The memory management method 400 described herein and its additional aspects can be found below. Figure 5 The memory management device 500, electronic device, hardware structure, software structure, or hardware structure and software structure described are implemented.

[0074] See Figure 4 The memory management method 400 includes steps S410 to S420.

[0075] In step S410, page tables are created in the memory management layer. These page tables are used to translate virtual addresses into physical addresses.

[0076] The memory management layer is a component that implements memory management. For example, the memory management layer can be part of the operating system, such as the operating system kernel, used to efficiently allocate and reclaim memory resources to ensure that multiple processes can run safely and efficiently. For example, the "memory management layer" here includes the software or firmware part of the processor used to implement memory management, which may include the memory subsystem.

[0077] In step S420, in response to a first base page with a first size value allocated at the hardware architecture layer, a second base page with a second size value is allocated to the page table, such that each page table entry corresponds to N consecutive first base pages of the corresponding next-level page. Here, the second size value is N times the first size value, and N is a positive integer.

[0078] The “hardware architecture layer” here includes the hardware portion of the processor used to implement memory management, which may include, for example, a memory management unit (MMU), and may further include a translation back buffer (TLB).

[0079] It can be understood that the next level page of a first-level page table can be a second-level page table, and the next level page of the last-level page table can be a data page. Therefore, each page table entry can correspond to N consecutive first base pages of the corresponding next-level page table or data page.

[0080] As described above, the memory management method according to at least one embodiment of the present disclosure can implement a physical base page mechanism with a second size N times the first size at the memory management layer, provided that the hardware architecture layer supports a base page of a first size value. This can reduce the memory overhead caused by physical page metadata.

[0081] The following describes some exemplary additional aspects of a memory management method according to at least one embodiment of the present disclosure.

[0082] For example, according to at least one embodiment of the memory management method of this disclosure, creating a page table in the memory management layer includes: setting the base page in the memory management subsystem of the memory management layer to a second size value.

[0083] Thus, the memory management method according to at least one embodiment of this disclosure can allocate a base page to a second size value in software for the base page in the memory management subsystem of an operating system (e.g., Linux), thereby reducing the new performance overhead introduced by data migration and page merging operations of the base physical pages required in existing big-page schemes.

[0084] For example, in a memory management method according to at least one embodiment of the present disclosure, the first size value corresponds to the size of the underlying physical pages supported by the memory management unit (MMU) in the hardware architecture layer.

[0085] Thus, the memory management method according to at least one embodiment of this disclosure can implement a physical base page mechanism with a second size value that is N times the size of the first size value under the requirement or constraint of the size of the base physical page supported by the memory management unit, thereby reducing the memory overhead caused by physical page metadata.

[0086] For example, in a memory management method according to at least one embodiment of the present disclosure, the second size is 64K, the first size is 4K, and N=16.

[0087] Thus, the memory management method according to at least one embodiment of the present disclosure can implement a physical base page mechanism of N times the first size value in a specific architecture, thereby reducing the memory overhead caused by physical page metadata.

[0088] For example, a specific architecture could be RISC-V, x86, ARM, or MIPS. Based on this embodiment, the memory management layer can provide an abstraction of 64K basic physical pages, while the actual hardware architecture layer that maps memory still maps physical memory in 4K granularity.

[0089] For example, in the memory management method according to at least one embodiment of the present disclosure, each page table entry includes N page table sub-entries (also called page table sub-entries), and each page table sub-entry corresponds to one of the N consecutive first base pages of the corresponding next-level page.

[0090] Thus, the memory management method according to at least one embodiment of this disclosure can realize the mapping from the previous page to the next page by setting the data structure of the specific page table entries. The data structure of the specific page table entries can make each page table sub-entry correspond exactly to the size of the basic physical page supported by the hardware architecture layer, thereby enabling the setting of the minimum number of page table sub-entries under the requirement of the size of the basic physical page supported by the hardware architecture layer, and reducing the corresponding memory occupation overhead.

[0091] For example, the memory management method according to at least one embodiment of the present disclosure further includes: encoding N page table sub-items included in each page table entry of the last-level page table page of the page table to the same value.

[0092] Thus, the memory management method according to at least one embodiment of the present disclosure can cache only one page table sub-entry in the TLB for the physical memory corresponding to N page table sub-entries, saving TLB space and reducing TLB misses.

[0093] Of course, the embodiments are not limited to this. For example, in some embodiments, a portion of the N page table sub-entries included in each page table entry may be encoded with the same value.

[0094] For example, in a memory management method according to at least one embodiment of the present disclosure, the same value and a data offset corresponding to the target physical address are used to obtain the target physical address.

[0095] Thus, the memory management method according to at least one embodiment of the present disclosure can obtain the target physical address from the data page using the same value and the corresponding data offset.

[0096] For example, in a memory management method according to at least one embodiment of the present disclosure, the same value indicates the starting address of a page consisting of N consecutive first base pages of the corresponding next-level page.

[0097] For example, 16 consecutive 4K base pages can form a 64K page, and the same value can indicate the starting address of this 64K page.

[0098] Thus, the memory management method according to at least one embodiment of this disclosure can map to the corresponding next-level page using the starting address and the offset relative to the starting address.

[0099] Of course, the embodiments are not limited to this. For example, the same value can indicate the end address or other address of a page consisting of N consecutive first base pages of the corresponding next-level page, as long as it can be mapped to the corresponding next-level page through the corresponding offset.

[0100] For example, according to at least one embodiment of the memory management method of this disclosure, the physical memory of N consecutive first base pages of the corresponding next-level page has the same mapping permissions.

[0101] For example, mapping permissions can include read-only, writable, executable, user-mode, and kernel-mode. Read-only means that the physical memory region can only read data, not write to it. Writable means that the physical memory region can both read and write data. Executable means that the physical memory region can execute the code stored within it. User-mode and kernel-mode mean that the physical memory region may only be accessible to user programs (user mode) or the operating system (kernel mode). The same mapping permissions can provide consistent access control, making memory management more efficient and simpler.

[0102] Thus, the memory management method according to at least one embodiment of the present disclosure can implement the mapping to data pages in a more efficient and simpler manner.

[0103] Corresponding to the memory management method 400 according to at least one embodiment of the present disclosure, at least one embodiment of the present disclosure also provides a memory management device.

[0104] Figure 5 A schematic diagram of a memory management device 500 according to at least one embodiment of the present disclosure is shown.

[0105] See Figure 5 The memory management device 500 includes a page table creation unit 510.

[0106] Page table creation unit 510 is configured to create page tables at the memory management layer. These page tables are used to translate virtual addresses into physical addresses.

[0107] Page table creation unit 510 is further configured to allocate a second base page with a second size value to the page table in response to a first base page with a first size value allocated at the hardware architecture layer, such that each page table entry corresponds to N consecutive first base pages of the corresponding next-level page. Here, the second size value is N times the first size value, and N is a positive integer.

[0108] As described above, the memory management device according to at least one embodiment of the present disclosure can implement a physical base page mechanism with a second size N times the first size, provided that the hardware architecture layer supports a base page of a first size, thereby reducing the memory overhead caused by physical page metadata.

[0109] The additional aspects of the memory management device 500 according to at least one embodiment of the present disclosure can correspond to the additional aspects of the memory management method 400 according to at least one embodiment of the present disclosure. Therefore, the technical effects of the additional aspects of the memory management method 400 according to at least one embodiment of the present disclosure can also be mapped to the additional aspects of the memory management device 500 according to at least one embodiment of the present disclosure, which will not be repeated here.

[0110] The following describes some exemplary additional aspects of a memory management apparatus according to at least one embodiment of the present disclosure.

[0111] For example, in a memory management apparatus according to at least one embodiment of the present disclosure, each page table entry includes N page table sub-entries, each page table sub-entry corresponding to one of N consecutive first base pages of the corresponding next-level page, and the memory management apparatus further includes an encoding unit configured to encode the N page table sub-entries included in each page table entry of the last-level page table page of the page table to the same value.

[0112] For example, in a memory management device according to at least one embodiment of the present disclosure, the second size is 64K, the first size is 4K, and N=16.

[0113] For example, in a memory management device according to at least one embodiment of the present disclosure, the same value indicates the starting address of a page consisting of N consecutive first base pages of the corresponding next-level page.

[0114] The following describes the above combination with an example application scenario. Figure 4 and Figure 5 One or more exemplary aspects are described. It is understood that the exemplary application scenarios described below are merely examples and not limitations, intended to achieve the above combinations in specific application scenarios. Figure 4 and Figure 5 One or more aspects, and the aspects described below in conjunction with exemplary application scenarios can be combined with the above. Figure 4 and Figure 5One or more aspects are combined.

[0115] In this exemplary application scenario, an exemplary solution for 64K base pages in a RISC-V architecture is provided. Based on the SVnapot hardware features of the RISC-V architecture, it provides a 64K base page mechanism when the hardware MMU does not support 64K base pages. This can reduce the probability of TLB misses, improve processor performance, reduce physical page metadata memory usage, and avoid introducing the big page merging overhead in big page mechanisms.

[0116] In this embodiment, the size of the basic physical page in the memory management subsystem of an operating system (e.g., Linux) is updated to 64K (e.g., corresponding to the second size value mentioned above), and memory is managed and allocated with a granularity of 64K, thereby reducing the memory overhead caused by physical page metadata.

[0117] Furthermore, this scheme manages and allocates memory with a page granularity of 64KB, with both page table pages and data pages (excluding big pages) being 64KB. Meanwhile, the hardware MMU still treats the underlying physical page as 4KB during virtual memory translation (e.g., corresponding to the first size value mentioned above). Therefore, in the actual page table configuration process, page table entries are still configured using 4KB physical pages.

[0118] Figure 6A A schematic diagram of a page table design for a 64K base page based on a 4K MMU according to at least one embodiment of the present disclosure is shown. Figure 6B A schematic diagram is shown illustrating the mapping relationship between pgd_t / pmd_t and 64K base pages according to at least one embodiment of the present disclosure.

[0119] The following is combined Figure 6A and Figure 6B These are exemplary steps for designing the page table for the base page.

[0120] (1) When applying for the root page table (i.e., the first-level page table) 602, the base page obtained is 64K.

[0121] In some embodiments, see Figure 6A Due to MMU hardware limitations (e.g., the MMU only parses 39 bits of the virtual address and does not identify information in other bits), the MMU can use bits 34-38 of the 39-bit virtual address as the pgd offset. In this case, the page table base address points to the first 4KB physical page, and the page table content is filled only, for example, the first 4KB; meanwhile, the root page table page 602 may include 60KB of unused memory. Additionally, this 60KB of unused memory can store other data.

[0122] Of course, the above embodiments are not limited to this. For example, depending on the MMU hardware limitations, 64K in the root page table 602 may be used partially or entirely.

[0123] (2) When allocating and mapping the next-level page table pages 604 / 606 (i.e., intermediate-level page table page 604 and the last-level page table page 606), the allocated base page is 64K. At the memory management layer, this scheme still maps one pgd_t / pmd_t concept (e.g., corresponding to the page table entry above) to an entire 64K physical page. Similarly, at the hardware architecture layer, since the MMU can only see 4K physical pages, 16 page table sub-entries (each page table sub-entry corresponding to a 4K physical page) are used to map a 64K physical page. Therefore, each pgd_t in page table page 602 and / or each pmd_t in page table page 604 contains 16 page table sub-entries (e.g., corresponding to N=16 above).

[0124] See Figure 6A For example, the pmd offset and pte offset both correspond to 9 bits (i.e., the pmd offset corresponds to bits 25-33 of the 39-bit virtual address, and the pte offset corresponds to bits 16-24 of the 39-bit virtual address), indicating that there are 2^9 page table entries (i.e., pmd_t / pte_t). Additionally, since pmd_t / pte_t also contains 16 page table sub-entries, there are a total of (2^9)*16 page table sub-entries, each corresponding to a 64K next-level page table page or data page.

[0125] For example, the software can use pmd offset / pte offset to look up each pmd_t / pte_t page table entry in the 64K page table pages.

[0126] See Figure 6B Each pgd_t / pmd_t can contain 16 page table sub-entries, each page table sub-entry maps to a 4K physical page, and the 16 page table sub-entries can map to 16 consecutive 4K physical pages, thus realizing the mapping of each pgd_t / pmd_t to a 64K base page.

[0127] For example, the MMU actually sees the sub-items of pgd_t / pmd_t, and the mapping granularity is still 4K. That is, it is still translated according to the 4K granularity (corresponding to one of the 16 page table sub-items in pgd_t / pmd_t), except that the 4K physical pages mapped by each of the 16 sub-items are connected to each other (therefore corresponding to a 64K page).

[0128] (3) The actual data page mapping is filled in the last-level page table page 606, and the data page 608 is a 64K base page. In this embodiment, the concept of a pte_t (for example, corresponding to the page table entry mentioned above) is still mapped to an entire 64K physical page. Each pte_t contains 16 page table sub-entries, and 16 page table sub-entries are used to map a 64K physical page. The 4K physical pages mapped by these 16 sub-entries are all connected to each other.

[0129] In this way, the memory management layer can provide an abstraction of 64K basic physical pages, while the hardware architecture layer that actually maps memory still maps physical memory in 4K granularity.

[0130] The following describes an example of TLB space / hit rate optimization based on Svnapot hardware features. The embodiments disclosed herein are not limited to Svnapot hardware features, and other means with similar encoding effects are also applicable.

[0131] This embodiment optimizes TLB hit rate based on the SVnapot hardware features of the RISC-V architecture. The SVnapot feature optimizes leaf pte (leaf node page table entry in a multi-level page table structure, i.e., the lowest-level page table entry, directly pointing to a physical memory page). For contiguous physical memory larger than 4K with the same mapping permissions (naturally aligned power-of-2 granularity size, NAPOT), the corresponding leaf pte can be encoded with the same value (hereinafter referred to as napot pte). The napot pte points to the starting physical address (i.e., the starting address) of the NAPOT. When the TLB or MMU translates the virtual address, it obtains the starting physical address of the NAPOT based on the napot pte, and then adds the offset (i.e., the data offset) in the virtual address (VA) to obtain the actual physical address (PA).

[0132] Figure 7 A schematic diagram illustrating TLB space / hit rate optimization under the Svnapot feature according to at least one embodiment of the present disclosure is shown. Figure 8 A schematic diagram of an Svnapot-based page table entry optimization design according to at least one embodiment of the present disclosure is shown.

[0133] Figure 7 The top of the graph shows the occupancy of 4K base pages in the TLB, and the bottom of the graph shows the occupancy of 64K base pages in the TLB.

[0134] See Figure 7The tag in the virtual address can be used to index the tag in the TLB. A tag is a portion of the virtual address used to identify a TLB entry, helping the processor quickly find and identify whether a specific virtual address is cached in the TLB. Typically, the tag contains the high-order bits of the virtual address for matching. If the tag in the virtual address matches the tag in an entry in the TLB (a hit), the corresponding physical page frame number (PFN) of the hit entry can be obtained. The PPFN indicates the actual storage location in physical memory. Then, the actual physical address can be obtained based on the PPFN and the data offset.

[0135] Taking 64K NAPOT as an example, in Figure 7 In the scenario shown above, with 4K base pages, each 4K base page requires one TLB entry. Therefore, for 64K of contiguous physical memory, 16 TLB entries are needed.

[0136] In comparison, taking 64K NAPOT as an example, in Figure 7 The lower part of the diagram illustrates a scenario with 64K base pages. Each 64K contiguous physical memory contains 16 contiguous 4K physical pages, corresponding to 16 PTEs. These PTEs are encoded with the same value, all pointing to the starting address of the 64K contiguous physical memory. For example, see... Figure 8 Each `pte_t` contains 16 page table entries, each encoded as the same `napot pte`, all pointing to the starting address of a contiguous 64KB physical memory. The TLB or MMU obtains this address from the `napot pte` and adds the address offset corresponding to bits [15:0] in the virtual address to get the actual physical address. In this way, only one entry needs to be cached in the TLB for the 64KB contiguous physical memory, thus saving TLB space and reducing TLB misses.

[0137] For example, when mapping data pages in the last-level page table, this embodiment uses the Svnapot feature to encode the pte_t of the mapped data page, so that the 16 page table sub-entries contained therein are encoded with the same napot pte, all pointing to the starting address of the 64K physical page, thereby reducing the space occupied by the TLB and reducing the probability of TLB miss.

[0138] Of course, the embodiments disclosed herein are not limited to this. For example, at least a portion of the 16 page table sub-entries contained in pte_t can be encoded as the same napot pte, thereby reducing the space occupied by the TLB and lowering the probability of TLB misses. Alternatively, the same napot pte can point to other addresses within the 64K physical page (e.g., the end address or a middle address), as long as the actual physical address is obtained through the corresponding offset.

[0139] In the above exemplary application scenarios, several effects can be achieved. For example, by using software, even when the hardware architecture only supports 4K granular physical pages, an abstraction of 64K basic physical pages can be provided to the memory management layer (or memory management subsystem). Another example is that by using SVNApot hardware features, each page table sub-entry corresponding to the 64K basic physical page can be encoded with the same value, reducing TLB space usage and improving TLB hit rate.

[0140] It is understood that the above exemplary application scenarios are merely illustrative, intended to illustrate one or more aspects of this disclosure in specific processor architectures and specific physical page sizes. These exemplary application scenarios can be extended to other processor architectures and specific physical page sizes, such as providing a base page of a certain size when the hardware architecture managing memory (e.g., RAM) does not support it. For example, the processor architecture may also include x86 or other suitable processor architectures. Furthermore, the 4K supported by the hardware architecture may be other sizes, such as 8K, 16K, 64K, etc. Similarly, a 64K physical page may be other sizes, such as 16K, 64K, 128K, etc. Moreover, the virtual address bit length and the fields for each offset are merely exemplary; different bit lengths of virtual addresses, different bit lengths of fields for virtual addresses, or more or fewer offsets can be set as needed.

[0141] Figure 9 A schematic diagram of an electronic device 900 according to at least one embodiment of the present disclosure is shown.

[0142] like Figure 9 As shown, the electronic device 900 includes at least one processing unit 920 and a memory 910. The electronic device 900 can run an operating system (e.g., Linux) for implementing a memory management method and its additional aspects according to at least one embodiment of the present disclosure. The memory 910 is, for example, RAM, which stores computer-readable instructions and is communicatively connected to the processing unit 920. The processing unit 920 executes the computer-readable instructions stored in the memory 910 to implement the memory management method and its additional aspects according to at least one embodiment of the present disclosure.

[0143] For example, the memory 910 and the processing unit 920 can communicate with each other directly or indirectly. For example, in some examples, such as... Figure 9As shown, the electronic device 900 may also include a system bus 930, through which the memory 910 and the processing unit 920 can communicate with each other. For example, the processing unit 920 can access the memory 910 through the system bus 930. For example, in other examples, components such as the memory 910 and the processing unit 920 can communicate through a network on-chip (NOC) connection.

[0144] For example, the processing unit 920 can control other components in the electronic device 900 to perform desired functions. The processing unit 920 can be a device with data processing and / or program execution capabilities, such as a central processing unit (CPU), tensor processor (TPU), network processor (NP), or graphics processor (GPU), or it can be a digital signal processor (DSP), application-specific integrated circuit (ASIC), field-programmable gate array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc.

[0145] For example, memory 910 may include any combination of one or more computer program products, which may include various forms of computer-readable storage media, such as volatile memory and / or non-volatile memory. Volatile memory may include, for example, random access memory (RAM) and / or cache memory. Non-volatile memory may include, for example, read-only memory (ROM), hard disk, erasable programmable read-only memory (EPROM), portable compact disc read-only memory (CD-ROM), USB memory, flash memory, etc.

[0146] For example, one or more computer-readable instructions can be stored on the memory 910, and the processing unit 920 can execute the computer-readable instructions to perform various functions. Various application programs and various data, such as instruction processing code and various data used and / or generated by the application programs, can also be stored in the computer-readable storage medium.

[0147] For example, when some computer instructions stored in memory 910 are executed by processing unit 920, they can perform one or more steps in the memory management method described above.

[0148] For example, such as Figure 9 As shown, the electronic device 900 may further include an input interface 940 that allows external devices to communicate with the electronic device 900. For example, the input interface 940 may be used to receive instructions from external computer devices, users, etc. The electronic device 900 may also include an output interface 950 that enables the electronic device 900 to connect to one or more external devices. For example, the electronic device 900 can communicate via the output interface 950, etc.

[0149] It should be noted that the electronic device 900 according to at least one embodiment of the present disclosure is exemplary and not restrictive. Depending on the actual application needs, the electronic device 900 may also include other conventional components or structures. For example, in order to realize the necessary functions of the electronic device, those skilled in the art can set other conventional components or structures according to the specific application scenario. The embodiments of the present disclosure do not limit this.

[0150] At least one embodiment of this disclosure also provides a computer-readable storage medium. Figure 10 A schematic diagram of a computer-readable storage medium 1000 according to at least one embodiment of the present disclosure is shown.

[0151] For example, such as Figure 10 As shown, the computer-readable storage medium 1000 stores computer-readable instructions 1010, which, when executed by a computer (including a processor), can implement a memory management method and its additional aspects according to at least one embodiment of the present disclosure.

[0152] For example, one or more computer-readable instructions may be stored on the computer-readable storage medium 1000. Some of the computer-readable instructions stored on the computer-readable storage medium 1000 may be, for example, instructions for implementing one or more steps in the memory management method described above.

[0153] For example, a computer-readable storage medium may include the storage component of a tablet computer, a hard disk of a personal computer, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM), optical disc read-only memory (CD-ROM), flash memory, or any combination of the above computer-readable storage media, or other suitable storage media. For example, computer-readable storage medium 1000 may include the memory 910 in the electronic device 900 described above.

[0154] At least some embodiments of this disclosure also provide an electronic device. Figure 11 A schematic diagram of another electronic device 1100 according to at least one embodiment of the present disclosure is shown.

[0155] The electronic device according to at least one embodiment of the present disclosure can be implemented as, but is not limited to, mobile terminals such as mobile phones, laptops, digital broadcast receivers, PDAs (personal digital assistants), PADs (tablet computers), PMPs (portable multimedia players), in-vehicle terminals (e.g., in-vehicle navigation terminals), and fixed terminals such as digital TVs, desktop computers, etc.

[0156] Figure 11 The electronic device 1100 shown is merely an example and should not be construed as limiting the functionality and scope of use of the embodiments disclosed herein.

[0157] For example, such as Figure 11 As shown, in some examples, electronic device 1100 includes processor 1101, which may include the processor of any of the above embodiments (e.g., an SMT processor), which can perform various appropriate actions and processes according to a program stored in read-only memory (ROM) 1102 or a program loaded from storage device 1108 into random access memory (RAM) 1103. Various programs and data required for the operation of the computer system are also stored in RAM 1103. Processor 1101, ROM 1102, and RAM 1103 are connected via bus 1104. Input / output (I / O) interface 1105 is also connected to bus 1104.

[0158] For example, the following components can be connected to I / O interface 1105: input devices 1106 including, for example, touchscreens, touchpads, keyboards, mice, cameras, microphones, accelerometers, gyroscopes, etc.; output devices 1107 including, for example, liquid crystal displays (LCDs), speakers, vibrators, etc.; storage devices 1108 including, for example, magnetic tapes, hard disks, etc.; and communication devices 1109, such as network interface cards like LAN cards and modems, etc. Communication device 1109 allows electronic device 1100 to communicate wirelessly or wiredly with other devices to exchange data and perform communication processing via networks such as the Internet. Drive 1110 is also connected to I / O interface 1105 as needed. Removable media 1111, such as disks, optical discs, magneto-optical discs, semiconductor memories, etc., are installed on drive 1110 as needed so that computer programs read from them can be installed into storage device 1108 as needed. Although Figure 11 An electronic device 1100 including various means is shown; however, it should be understood that implementation or inclusion of all the means shown is not required. More or fewer means may be implemented or included alternatively.

[0159] For example, the electronic device 1100 may further include a peripheral interface (not shown). This peripheral interface can be of various types, such as a USB interface, a Lightning interface, etc. The communication device 1109 can communicate wirelessly with a network and other devices, such as the Internet, an intranet, and / or a wireless network such as a cellular telephone network, a wireless local area network (LAN), and / or a metropolitan area network (MAN). Wireless communication can use any of a variety of communication standards, protocols, and technologies, including but not limited to Global System for Mobile Communications (GSM), Enhanced Data GSM Environment (EDGE), Wideband Code Division Multiple Access (W-CDMA), Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Bluetooth, Wi-Fi (e.g., based on IEEE 802.11a, IEEE 802.11b, IEEE 802.11g, and / or IEEE 802.11n standards), Voice over Internet Protocol (VoIP), Wi-MAX, protocols for email, instant messaging, and / or Short Message Service (SMS), or any other suitable communication protocol.

[0160] The following examples are merely illustrative and may be combined without limitation with other embodiments or aspects of the teachings described herein.

[0161] Example 1. A memory management method, comprising:

[0162] A page table is created in the memory management layer, wherein the page table is used to translate virtual addresses into physical addresses;

[0163] In response to allocating a first base page with a first size value at the hardware architecture layer, allocating a second base page with a second size value to the page table, such that each page table entry corresponds to N consecutive first base pages of the corresponding next-level page.

[0164] Wherein, the second size value is N times the first size value, and N is a positive integer.

[0165] Example 2. The memory management method according to Example 1, wherein creating a page table in the memory management layer includes:

[0166] Set the base page in the memory management subsystem of the memory management layer to the second size value.

[0167] Example 3. The memory management method according to Example 1, wherein the first size value corresponds to the size of the underlying physical page supported by the memory management unit in the hardware architecture layer.

[0168] Example 4. The memory management method according to Example 1, wherein the second size is 64K, the first size is 4K, and N = 16.

[0169] Example 5. The memory management method according to Example 1, wherein each page table entry includes N page table sub-entries, and each page table sub-entry corresponds to one of the N consecutive first base pages of the corresponding next-level page.

[0170] Example 6. The memory management method according to Example 5 further includes:

[0171] Each page table entry in the last-level page table of the page table includes N page table sub-entries that are encoded with the same value.

[0172] Example 7. The memory management method according to Example 6, wherein the same value and the data offset corresponding to the target physical address are used to obtain the target physical address.

[0173] Example 8. The memory management method according to Example 6, wherein the same value indicates the starting address of the page consisting of N consecutive first base pages of the corresponding next-level page.

[0174] Example 9. The memory management method according to Example 6, wherein the physical memory of N consecutive first base pages of the corresponding next-level page has the same mapping permissions.

[0175] Example 10. A memory management device, comprising:

[0176] The page table creation cell is configured as follows:

[0177] A page table is created at the memory management layer, wherein the page table is used to translate virtual addresses into physical addresses; and

[0178] In response to allocating a first base page with a first size value at the hardware architecture layer, allocating a second base page with a second size value to the page table, such that each page table entry corresponds to N consecutive first base pages of the corresponding next-level page.

[0179] Wherein, the second size value is N times the first size value, and N is a positive integer.

[0180] Example 11. The memory management apparatus according to Example 10, wherein each page table entry includes N page table sub-entries, each page table sub-entry corresponding to one of N consecutive first base pages of the corresponding next-level page, and the memory management apparatus further includes:

[0181] The encoding unit is configured to encode the N page table sub-items included in each page table entry of the last-level page table page of the page table into the same value.

[0182] Example 12. The memory management device according to Example 10, wherein the second size is 64K, the first size is 4K, and N = 16.

[0183] Example 13. The memory management apparatus according to Example 11, wherein the same value indicates the starting address of a page consisting of N consecutive first base pages of the corresponding next-level page.

[0184] Example 14. An electronic device comprising at least one processing unit and a memory, wherein,

[0185] The memory stores computer-readable instructions and is communicatively connected to the at least one processing unit;

[0186] The at least one processing unit is configured to execute the computer-readable instructions stored in the memory to implement the memory management method according to any one of Examples 1-9.

[0187] Example 15. A non-transitory computer-readable storage medium, wherein computer-readable instructions are stored in the computer-readable storage medium.

[0188] When the processor executes the computer-readable instructions, it implements the memory management method according to any one of Examples 1-9.

[0189] In addition to the exemplary descriptions above, the following points should be noted regarding this disclosure:

[0190] (1) The accompanying drawings of the embodiments of this disclosure only involve the structures involved in the embodiments of this disclosure. Other structures can be referred to the general design.

[0191] (2) Where there is no conflict, the embodiments of this disclosure and the features in the embodiments can be combined with each other to obtain new embodiments.

[0192] The above description is merely an exemplary embodiment of this disclosure and is not intended to limit the scope of protection of this disclosure, which is determined by the appended claims.

Claims

1. A memory management method, comprising: A page table is created in the memory management layer, wherein the page table is used to translate virtual addresses into physical addresses; In response to allocating a first base page with a first size value at the hardware architecture layer, allocating a second base page with a second size value to the page table, such that each page table entry corresponds to N consecutive first base pages of the corresponding next-level page. Wherein, the second size value is N times the first size value, and N is a positive integer.

2. The memory management method according to claim 1, wherein, The creation of page tables in the memory management layer includes: Set the base page in the memory management subsystem of the memory management layer to the second size value.

3. The memory management method according to claim 1, wherein, The first size value corresponds to the size of the underlying physical page supported by the memory management unit in the hardware architecture layer.

4. The memory management method according to claim 1, wherein, The second size is 64K, the first size is 4K, and N = 16.

5. The memory management method according to claim 1, wherein, Each page table entry includes N page table sub-entries, and each page table sub-entry corresponds to one of the N consecutive first base pages of the corresponding next-level page.

6. The memory management method according to claim 5 further includes: Each page table entry in the last-level page table of the page table includes N page table sub-entries with the same value.

7. The memory management method according to claim 6, wherein, The same value and the data offset corresponding to the target physical address are used to obtain the target physical address.

8. The memory management method according to claim 6, wherein, The same value indicates the starting address of the page consisting of N consecutive first base pages of the corresponding next-level page.

9. The memory management method according to claim 6, wherein, The physical memory of the N consecutive first base pages of the corresponding next-level page has the same mapping permissions.

10. A memory management device, comprising: The page table creation cell is configured as follows: A page table is created at the memory management layer, wherein the page table is used to translate virtual addresses into physical addresses; and In response to allocating a first base page with a first size value at the hardware architecture layer, allocating a second base page with a second size value to the page table, such that each page table entry corresponds to N consecutive first base pages of the corresponding next-level page. Wherein, the second size value is N times the first size value, and N is a positive integer.

11. The memory management device according to claim 10, wherein, Each page table entry includes N page table sub-entries, each page table sub-entry corresponding to one of the N consecutive first base pages of the corresponding next-level page, and the memory management device further includes: The encoding unit is configured to encode the N page table sub-items included in each page table entry of the last-level page table page of the page table into the same value.

12. The memory management device according to claim 10, wherein, The second size is 64K, the first size is 4K, and N = 16.

13. The memory management device according to claim 11, wherein, The same value indicates the starting address of the page consisting of N consecutive first base pages of the corresponding next-level page.

14. An electronic device comprising at least one processing unit and a memory, wherein, The memory stores computer-readable instructions and is communicatively connected to the at least one processing unit; The at least one processing unit is configured to execute the computer-readable instructions stored in the memory to implement the memory management method according to any one of claims 1-9.

15. A non-transitory computer-readable storage medium, wherein, The computer-readable storage medium stores computer-readable instructions. When the processor executes the computer-readable instructions, it implements the memory management method according to any one of claims 1-9.

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