Chip interconnection interface system for 3DIC packaging and 3DIC packaging chip

Abstract

The invention provides a chip interconnection interface system for 3DIC (three-dimensional integrated circuit) packaging and a 3DIC packaging chip. The system comprises an interface sending module located in a computing chip and used for converting write data with original bit width into write data with reduced bit width and sending the write data to a storage chip through a hybrid bonding interface; the interface receiving module is positioned in the storage chip and is used for receiving the write data with the reduced bit width, recovering the write data to the original bit width and providing the write data to the storage controller; wherein the reduced bit width of the write data is smaller than the bit width of the read data so as to adapt to the access characteristic that the read-write bandwidth of the computing chip to the storage chip is asymmetric. According to the invention, the periodicity of the signal can be effectively reduced, and the receiving chip restores the original data through descrambling; the confidentiality and the anti-interference capability of data transmission are enhanced, and the system stability of a chip interconnection interface of 3DIC packaging can be improved.

Description

Chip interconnect interface system for 3DIC packaging and 3DIC packaged chip Technical Field

[0001] This invention belongs to the field of semiconductor technology, and particularly relates to a chip interconnect interface system for 3DIC packaging and a 3DIC package chip. Background Technology

[0002] In existing 3DIC packaged chips, given the high computing power applications of AI and HPC, more AXI4 support is needed to support higher bandwidth memory access requirements. If the number of paths is N=8, then the total number of AXI traces is 2497. 8 = 19976 bits of traces, of which 19976 lines are only data, address and control lines, excluding clock and reset, as well as power and ground traces.

[0003] With tens of thousands of data traces, the sheer number of traces and the numerous factors to consider make the design extremely complex, occupying a significant amount of chip area. If hybrid bonding interconnects from 3D process technology are used, assuming a bonding pad size of 2.5µm and a pitch of 5µm, the occupied area would be approximately 382.5µm x 382.5µm, roughly equal to 146306µm. 2 Its area is 146306um. 2 This only includes the area of ​​the data, address, and control lines, not including the clock, reset, power, and ground lines. Therefore, a single AXI trace will be much larger than 146306um. 2 If it's an 8-channel AXI trace, the trace size will be greater than 1180000um. 2 .

[0004] With more traces, more trace area is occupied, and more crosstalk between traces, chip design and packaging design become more difficult and challenging. Summary of the Invention

[0005] Therefore, the purpose of this invention is to solve the practical problems of complex wiring and severe crosstalk in the prior art.

[0006] This invention provides a chip interconnect interface system for 3DIC packaging, comprising: an interface transmitting module located within a computing chip, used to convert original bit-width write data into reduced bit-width write data and transmit it to a memory chip via a hybrid bonding interface; and an interface receiving module located within the memory chip, used to receive the reduced bit-width write data, restore it to its original bit-width, and provide it to a memory controller; wherein the reduced bit-width of the write data is smaller than the bit-width of the read data to adapt to the asymmetric access characteristics of the computing chip to the memory chip's read / write bandwidth.

[0007] Furthermore, preferably, in the chip interconnect interface system for 3DIC packaging described in this invention, the interface sending module includes a bit width reduction unit for proportionally reducing the original bit width of write data to the reduced bit width; the interface receiving module includes a bit width recovery unit for restoring the received reduced bit width data to the original bit width.

[0008] Furthermore, preferably, in the chip interconnect interface system for 3DIC packaging described in this invention, the original bit width is 1024 bits, and the reduced bit width is 384 bits or 512 bits.

[0009] Furthermore, preferably, in the chip interconnect interface system for 3DIC packaging described in this invention, the system further includes a data scrambling and descrambling module, which, on the transmitting side, scrambles at least one of the address, data, and control signals transmitted through the hybrid bonding interface; and on the receiving side, descrambles the received signals accordingly to restore the original signals.

[0010] Furthermore, preferably, in the chip interconnect interface system for 3DIC packaging described in this invention, the system further includes an error correction coding module. On the transmitting side, an error correction code is generated for the data transmitted through the AXI protocol channel based on the BCH algorithm, and the error correction code is placed in the User field of the AXI protocol for transmission. On the receiving side, the data is checked and corrected according to the received error correction code.

[0011] Furthermore, preferably, in the chip interconnect interface system for 3DIC packaging described in this invention, the error correction coding module is configured to support the correction of at least two-bit errors and the detection of multi-bit errors.

[0012] Furthermore, preferably, in the chip interconnect interface system for 3DIC packaging described in this invention, the system further includes a redundancy repair module, and the interconnect traces of the hybrid bonding interface include redundant lines; the redundancy repair module is configured to: when a fault is detected in a signal line, use a redundant line to replace the faulty line for signal transmission through a shift operation.

[0013] Furthermore, preferably, in the chip interconnect interface system for 3DIC packaging described in this invention, the redundancy repair module configures redundant lines in units of 64 bits, that is, 1 redundant line is configured for every 64-bit signal lines.

[0014] Furthermore, preferably, in the chip interconnect interface system for 3DIC packaging described in this invention, the computing chip and the memory chip are three-dimensionally stacked and integrated through hybrid bonding technology, and the interconnect interface system achieves interconnection through bonding pads on the hybrid bonding surface.

[0015] Furthermore, preferably, the present invention also provides a 3DIC packaged chip, comprising any of the above-mentioned chip interconnect interface systems for 3DIC packaging.

[0016] Using this invention, the periodicity of signals can be effectively reduced, and the receiving chip can restore the original data by descrambling; the confidentiality and anti-interference ability of data transmission are enhanced, and the system stability of the chip interconnect interface of 3DIC package can be improved. Attached Figure Description

[0017] Figure 1 is a schematic diagram illustrating the interconnection structure of a computing chip and a memory chip in a 3DIC according to a preferred embodiment of the present invention.

[0018] Figure 2 is a schematic diagram showing a cross-sectional view of a 3DIC package according to a preferred embodiment of the present invention. Figure 3 is a schematic diagram showing a top view of a 3DIC package according to a preferred embodiment of the present invention. Figure 4 is a schematic diagram showing the interconnection interface between a computing chip and a memory chip according to a preferred embodiment of the present invention.

[0019] Figure 5 is a schematic diagram showing the interconnection interface between the computing chip and the storage chip with verification information according to a preferred embodiment of the present invention.

[0020] Figure 6 is a schematic diagram illustrating the repair of the interconnection interface between the computing chip and the memory chip according to a preferred embodiment of the present invention. Detailed Implementation

[0021] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of the embodiments. Other embodiments or modifications obtained by those skilled in the art based on the embodiments of this application without creative effort are all within the scope of protection of this application.

[0022] The interconnection structure between the computing chip and the memory chip is as follows: As shown in Figure 1 above, in existing 3D DRAM chips, the computing chip (also called the logic die) and the memory chip (also called the 3D DRAM die) are directly connected via AXI4, which consists of five channels: WDC (Write Data Channel), WAC (Write Address Channel), RAC (Read Address Channel), RDC (Read Data Channel), and WRC (Write Response Channel). To ensure high-bandwidth transmission, the data width is set to 1024 bits or higher. Therefore, the AXI4 data width is 1024 bits, and the five channels are shown in Tables 1-1 to 1-5 below.

[0023] Table 1-1 WDC: WriteData Channel, totaling 1188 bits. Table 1-2 WAC: WriteAddressChannel (Write Address Channel) totals 105 bits. Table 1-3 RAC: ReadAddressChannel (read address channel) totals 105 bits. Table 1-4 RDC: ReadDataChannel (read channel) totals 1076 bits. Table 1-5 WRC: WriteResponseChannel (Write Response Channel) - 23 bits in total The total number of bits for the above AXI channel is 2497 bits.

[0024] Figure 2 shows the 3DIC package configuration, a cross-sectional view of which is highlighted in red. The computing chip and the 3D DRAM memory chip are interconnected closely via hybrid bonding, and the chips are interconnected via AXI4. The interconnect interface optimization addresses the issue that NPU / GPU / AI chips or CPU chips access memory differently during read and write operations. 70%–80% of the time is spent reading data from memory, while 30%–20% is spent writing data, resulting in a read / write ratio of approximately 7:3. Therefore, the read bandwidth is significantly greater than the write bandwidth. To accommodate this read / write bandwidth discrepancy, read operations utilize full bandwidth, while write operations can use half the read bandwidth or even less. The improvement methods are as follows: 1. Ensure bandwidth performance and reduce interconnect traces.

[0025] 1) If the data width for reading data is kept at 1024 bits, then the data width for writing data can be reduced to 384 bits or lower; this can save more than 30% of data traces, see Tables 2-1, 2-2, 2-3, 2-4, and 2-5.

[0026] Adding a small amount of logic overhead within the chip saves more than 29.3% of the data lines in the chip interconnection and reduces the number of bonding pads in the hybrid bonding of computing and memory chips.

[0027] 2. Reliability-enhancing design.

[0028] 1) By performing an XOR operation between the data stream and the pseudo-random sequence using Scramble, the data is randomly distributed, thereby reducing the periodicity of the signal, enhancing the confidentiality and anti-interference capability of data transmission, and improving system stability; 2) An ECC check bit is added to the User field of each AXI channel. ECC technology is used to perform single-bit error correction and multi-bit error detection on the data, thereby ensuring system stability; 3) Redundancy is added to the interconnects. When a line fails, it can be repaired through the redundancy mechanism, ensuring system reliability and improving chip yield.

[0029] The above points can ensure the reliability of interconnection and transmission between chips.

[0030] Table 2-1 WDC: WriteData Channel (457 bits in total) Table 2-2 WAC: WriteAddressChannel (Write Address Channel) totals 105 bits. Table 2-3 RAC: ReadAddressChannel (read address channel) totals 105 bits. Table 2-4 RDC: ReadDataChannel (read channel) totals 1076 bits. Table 2-5 WRC: WriteResponseChannel (Write Response Channel) - 23 bits in total The total number of bits for the above AXI channel is 1766 bits; if the number of channels N=8, then the total number of AXI traces is 1766. 8 = 14128 bits of traces; compared to the existing interconnect interface with 19976 bits of traces, it has saved 5848 bits of traces, which is a 29.3% reduction in traces.

[0031] The inter-chip interconnection interface is shown in Figure 4. When the computing chip writes data to the storage chip, the downsize module reduces the data width from 1024 bits to 384 bits. This change in data width is imperceptible to the GPU / NPU Matrix / CPU computing modules. When the storage chip receives data, the received 384-bit data is upsized back to 1024 bits. This change in data width is also imperceptible to the Memory Controller.

[0032] In addition, the data, address, and control signals in the AXI channel of the computing chip are scrambled before being transmitted to the memory chip. The memory chip then descrambles and restores the original data, address, and control signals, which enhances the confidentiality and anti-interference capabilities of data transmission and improves system stability. Similarly, when the computing chip reads data from the memory chip, the data, address, and control signals from the memory chip are scrambled before being transmitted to the computing chip. After receiving the data, the computing chip descrambles and restores the original data, address, and control signals.

[0033] Because there are many interconnecting signal lines and the wiring is dense, crosstalk between lines is severe. The transmitting chip uses a scramble function to XOR the data stream with a pseudo-random sequence to scramble the data, making the data randomly distributed, thereby reducing the periodicity of the signal. The receiving chip then descrambles the data to restore the original data. This enhances the confidentiality and anti-interference capability of data transmission and improves system stability.

[0034] In addition, to ensure error prevention during inter-chip transmission, error detection and correction logic has been added to improve the data error rate. Verification information for each AXI channel has been added, as shown in Figure 5. The process from the computing chip to the storage chip involves passing through the ECC Gen and generating ECC verification information using the BCH algorithm. This information is then sent to the storage chip via the AXI4 user field of the computing chip. The storage chip's ECCCheck performs error detection and correction. If the error is less than or equal to 2 bits, error correction is performed. If the error is greater than 2 bits, an error is reported, generating a bus error, which is transmitted to the computing chip via the AXI response channel for processing or retransmission.

[0035] Similarly, in the process of reading data from a memory chip to a computing chip, the memory chip needs to pass through ECCGen and generate ECC check information using the BCH algorithm. This information is then sent to the computing chip via the AXI4 user field of the memory chip. The computing chip's ECC Check performs error detection and correction. If the error is less than or equal to 2 bits, error correction is performed. If the error is greater than 2 bits, the read operation is initiated again. If the read error exceeds the upper limit, it is reported to the computing chip system for processing.

[0036] In addition, the interconnection traces between chips are dense, and hybrid bonding cannot guarantee 100% that the traces are fault-free. When a trace is faulty, it needs to be repaired. The operation is shown in Figure 6. The repair mechanism is to right-shift and repair when one of the lower 32 bits is faulty; when one of the higher 32 bits is faulty, it is still performed by left-shifting, as follows: when bit[0] is faulty, R (Redundancy) is right-shifted once, and bit0 is filled in R; when bit[1] is faulty, R (Redundancy) is right-shifted twice, bit0 is filled in R, and bit1 is filled in the original bit0; and so on.

[0037] When bit

[63] is faulty, R (Redundancy) is shifted left by 1 time, and bit 63 is filled with R bit; when bit

[62] is faulty, R (Redundancy) is shifted left by 1 time, bit 63 is filled with R bit, and bit 62 is filled with the original bit 63 bit; and so on.

[0038] When the logic die detects a pin fault, it synchronizes with the memory die for repair.

[0039] Similarly, when the memory die detects a pin fault, it synchronizes with the logic die for repair.

[0040] In principle, 1 redundant line is used for repairing 64-bit lines. If there are 128-bit lines, 2 redundant lines are required.

[0041] If there are 256-bit lines, 4-bit redundant lines are needed.

[0042] If there are 384-bit lines, 6-bit redundant lines are needed.

[0043] If there are 512-bit lines, 8 bits of redundancy are required.

[0044] If there are 1024-bit lines, 16-bit redundancy is required.

[0045] And so on.

[0046] If there are fewer than 64 bits, use 1 redundant bit to repair it.

[0047] The embodiments of the present invention have the following advantages: Since the memory access methods of GPU chips / AI chips or CPU chips are different when reading and writing memory, 70% to 80% of the time is spent reading data from the memory, while 30% to 20% of the time is spent writing data into the memory, the ratio of reading to writing is about 7:3.

[0048] Therefore, the read bandwidth is much greater than the write bandwidth. To accommodate this inconsistency between read and write bandwidth, reads are at full bandwidth, while writes can be half or even less of the read bandwidth.

[0049] The improvements based on the above implementation method are as follows: 1. Guarantee bandwidth performance and reduce interconnection traces 1) If the data bit width for reading data remains in the original position (if the original position is 1024 bits), then the data bit width for writing data can be reduced to one-third of the original (384 bits); this can save more than 30% of data traces.

[0050] Adding a tiny amount of logic overhead within the chip saves more than 30% of the data lines in the chip interconnection and reduces the number of bonding pads in the hybrid bonding of computing and memory chips.

[0051] 2. Reliability Enhancement Design: 1) Due to the high-speed and dense interconnection of the chip, the data stream is XORed with the pseudo-random sequence through Scramble, so that the data is randomly distributed, thereby reducing the periodicity of the signal, enhancing the confidentiality and anti-interference ability of data transmission, and improving system stability.

[0052] 2) Add an ECC check bit to the User field of each AXI channel. Use ECC technology to perform double-bit error correction and multi-bit error detection on the data to ensure system stability.

[0053] 3) The interconnect hybrid bonding traces increase redundancy. When a trace fails, it can be repaired through the redundancy mechanism, which ensures system reliability and improves chip yield.

[0054] The above points can ensure the reliability of interconnection and transmission between chips.

[0055] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0056] The various embodiments in this specification are described in a related manner. The same or similar parts between the various embodiments can be referred to each other. Each embodiment focuses on describing the differences from other embodiments.

[0057] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

[0058] The above embodiments of the present invention are merely examples for clearly illustrating the present invention and are not intended to limit the implementation of the present invention. Those skilled in the art will recognize that other variations or modifications can be made based on the above description. It is neither necessary nor possible to exhaustively describe all possible implementations here. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included within the scope of protection of the claims of the present invention.

Claims

1. A chip interconnect interface system for 3DIC packaging, characterized in that, include: An interface transmitting module located within the computing chip is used to convert the original bit-width write data into reduced bit-width write data and send it to the memory chip through a hybrid bonding interface; an interface receiving module located within the memory chip is used to receive the reduced bit-width write data, restore it to the original bit-width, and provide it to the memory controller; wherein, the reduced bit-width of the write data is smaller than the bit-width of the read data, in order to adapt to the asymmetric access characteristics of the computing chip to the read and write bandwidth of the memory chip.

2. The chip interconnect interface system for 3DIC packaging according to claim 1, characterized in that, The interface sending module includes a bit width reduction unit, used to proportionally reduce the original bit width of the write data to the reduced bit width; the interface receiving module includes a bit width recovery unit, used to restore the received reduced bit width data to the original bit width.

3. The chip interconnect interface system for 3DIC packaging according to claim 2, characterized in that, The original bit width is 1024 bits, and the reduced bit width is 384 bits or 512 bits.

4. The chip interconnect interface system for 3DIC packaging according to claim 1, characterized in that, The system also includes a data scrambling and descrambling module: on the transmitting side, at least one of the address, data and control signals transmitted through the hybrid bonding interface is scrambled; on the receiving side, the received signal is descrambled accordingly to restore the original signal.

5. The chip interconnect interface system for 3DIC packaging according to claim 1, characterized in that, The system also includes an error correction coding module: on the transmitting side, an error correction code is generated for the data transmitted through the AXI protocol channel based on the BCH algorithm, and the error correction code is placed in the User field of the AXI protocol for transmission; on the receiving side, the data is detected and corrected according to the received error correction code.

6. The chip interconnect interface system for 3DIC packaging according to claim 5, characterized in that, The error correction coding module is configured to support the correction of at least two-bit errors and the detection of multi-bit errors.

7. The chip interconnect interface system for 3DIC packaging according to claim 1, characterized in that, The system also includes a redundancy repair module, and the interconnect traces of the hybrid bonding interface include redundant lines; the redundancy repair module is configured to: when a fault is detected in a signal line, use a redundant line to replace the faulty line for signal transmission through a shift operation.

8. The chip interconnect interface system for 3DIC packaging according to claim 7, characterized in that, The redundancy repair module configures redundant lines in units of 64 bits, that is, 1 redundant line is configured for every 64-bit signal lines.

9. The chip interconnect interface system for 3DIC packaging according to any one of claims 1 to 8, characterized in that, The computing chip and the memory chip are integrated in three dimensions by hybrid bonding technology, and the interconnect interface system is interconnected through bonding pads on the hybrid bonding surface.

10. A 3DIC packaged chip, characterized in that, A chip interconnect interface system for 3DIC packaging as described in any one of claims 1 to 9.

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