Interrupt processing method, interrupt processing circuit, storage medium and program product
By setting independent signal switches to control the connection between each processor and the interrupt handler in a multi-core heterogeneous device system, direct connection reduces intermediate forwarding links, solves the problems of untimely interrupt processing and interrupt loss, and achieves efficient interrupt signal processing.
Patent Information
- Application Number
- CN202511788134.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-11-28
- Publication Date
- 2026-05-01
AI Technical Summary
In multi-core heterogeneous device systems, existing interrupt handling methods are prone to problems such as untimely interrupt handling and interrupt loss in time-sensitive or high-frequency interrupt triggering scenarios.
By setting independent signal switches to control the connection between each processor and the interrupt handler, the multi-core central processing unit can flexibly control the interrupt signals. Direct connection reduces intermediate forwarding links, and hardware-level signal switch control replaces software arbitration.
It reduces signal transmission latency, improves the real-time performance and accuracy of interrupt handling, simplifies the interrupt handling process, avoids the delay and interrupt loss problems caused by traditional arbitration mechanisms, and improves the overall processing efficiency of the system.
Smart Images
Figure CN121958155A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of electronic circuit technology, and in particular to an interrupt handling method, an interrupt handling circuit, a storage medium, and a program product. Background Technology
[0002] Interrupt mechanisms are a key technology for electronic devices to achieve multitasking and real-time response. With the development of technology and the diversification of user needs, the interrupt handler of electronic devices receives interrupt signals from different external devices, sorts these requests according to certain priority rules, and passes them to the central processing unit (CPU) for processing. In order to adapt to a wider range of application scenarios, different CPUs in multi-core heterogeneous device systems may reuse some of the same external devices. In actual operation, an interrupt signal may require different CPUs to execute.
[0003] Therefore, in time-sensitive or high-frequency interruption scenarios, interrupt handling may be delayed or interrupts may be lost, and existing interrupt handling methods still need improvement. Summary of the Invention
[0004] This application provides an interrupt handling method, an interrupt handling circuit, a storage medium, and a program product. By setting independent signal switches to control the connection between each processor and the interrupt handler, it can directly realize the flexible control of interrupt signals by a multi-core central processing unit, avoiding the delay and interrupt loss problems caused by traditional arbitration mechanisms, and avoiding the problems of untimely interrupt handling and interrupt loss in time-sensitive or interrupt-triggered scenarios.
[0005] To address the aforementioned technical problems, the first aspect of this application provides an interrupt handling method, characterized in that the interrupt handling method is applied to an interrupt handling circuit, the interrupt handling circuit including an interrupt processor and at least two central processing units (CPUs), each CPU being connected to the interrupt processor via a signal switch; the interrupt handling method includes: in response to receiving a set signal through the interrupt processor, the interrupt processor generates an interrupt signal; the interrupt processor sends the interrupt signal to the corresponding CPU via the signal switch; and the CPU whose function matches the type of the set signal executes the interrupt process corresponding to the interrupt signal, specifically including: if the number of CPUs whose function matches the type of the set signal is at least two, each matched CPU processes the interrupt process simultaneously.
[0006] The step of the central processing unit (CPU) executing the interrupt process corresponding to the interrupt signal by matching its own function with the type of the set signal further includes: the CPU receiving the interrupt signal and determining whether the type of the set signal matches its own function; if the type of the set signal matches its function, the CPU executes the interrupt process; if the type of the set signal does not match its function, the CPU discards the interrupt signal.
[0007] The central processing units (CPUs) are interconnected. After receiving an interrupt signal and determining whether the type of the set signal matches its own function, the CPU also sends the determination result to other CPUs.
[0008] The step of discarding an interrupt signal if the type of the signal does not match its function includes: disconnecting the signal switch connected to its central processing unit.
[0009] Prior to the step of the interrupt processor generating an interrupt signal in response to receiving a setting signal through the interrupt processor, the method further includes: in response to receiving an initialization signal or a reset signal, each central processing unit sends a control signal to control the closed signal switch.
[0010] The interrupt processor is also used to connect to external devices, including on-chip devices or external devices including on-chip devices and external devices. The on-chip devices are connected to the interrupt controller, and the external devices are connected through the on-chip devices. The step of the interrupt processor generating an interrupt signal in response to receiving a setting signal through the interrupt processor includes: receiving a setting signal sent from the on-chip device through the interrupt processor; wherein the setting signal is a setting signal of the external device forwarded by the on-chip device, or / and a setting signal generated by the on-chip device itself.
[0011] The interrupt handling circuit further includes a storage medium connected to both the interrupt processor and the central processing unit (CPU). The storage medium stores interrupt numbers and the corresponding interrupt processes. The step of the interrupt processor generating an interrupt signal in response to receiving a set signal includes: identifying the set signal and determining its type; querying the corresponding interrupt number from the storage medium based on the set signal type and generating the interrupt signal; and executing the interrupt process corresponding to the interrupt signal using a CPU whose function matches the set signal type, including: querying the interrupt process corresponding to the interrupt number from the storage medium based on the interrupt number and executing the interrupt process.
[0012] The steps of querying the interrupt process corresponding to the interrupt number from the storage medium by the central processing unit (CPU) based on the interrupt number and executing the interrupt process include: the CPU obtaining its own function type; determining the corresponding process based on the function type and the interrupt number; and executing the interrupt process.
[0013] To address the aforementioned technical problems, a second aspect of this application provides an interrupt processing circuit, comprising: an interrupt processor for generating an interrupt signal upon receiving a set signal; at least two central processing units (CPUs), each CPU being connected to the interrupt processor via a signal switch; and CPUs for executing an interrupt process corresponding to the interrupt signal when the type of the set signal matches its own function.
[0014] The central processing units (CPUs) are interconnected. Each CPU sends control signals to the signal switches connected to it based on its own and / or other CPUs' functions, in order to control the signal switches to be turned on or off.
[0015] To address the aforementioned technical problems, a third aspect of this application provides a computer-readable storage medium / computer program product, characterized in that the computer-readable storage medium stores computer program instructions, which can be executed by a processor to implement any of the aforementioned interrupt handling methods; the computer program product includes computer program instructions, which, when executed by a processor, implement any of the aforementioned interrupt handling methods. Unlike existing technologies, this application provides an interrupt handling method, interrupt handling circuit, storage medium, and program product. By setting independent signal switches to control the connection between each processor and the interrupt handler, it can directly realize flexible control of interrupt signals by a multi-core CPU. The direct connection between the interrupt handler and each CPU reduces intermediate forwarding links and lowers signal transmission latency. The CPU that executes the corresponding interrupt process based on its own function and the type of the set signal can also realize parallel processing of interrupt processes, thus optimizing the interrupt handling architecture. By replacing software arbitration with hardware-level signal switch control, the interrupt handling process is simplified, system complexity is reduced, and the delay and interrupt loss problems caused by traditional arbitration mechanisms are avoided. This also prevents the problems of untimely interrupt handling and interrupt loss that are prone to occur in time-sensitive or high-interrupt-triggered scenarios. Attached Figure Description
[0016] Figure 1 This is a schematic diagram of one embodiment of the interrupt handling circuit of this application; Figure 2 This is a flowchart illustrating the steps of one implementation method of the interruption handling method of this application; Figure 3 This is a schematic diagram of the second embodiment of the interrupt handling circuit of this application; Figure 4 This is a schematic diagram of the third embodiment of the interrupt handling circuit of this application; Figure 5 This is a flowchart illustrating the steps of the third embodiment of the interruption handling method of this application; Figure 6 This is a schematic diagram of one embodiment of the computer-readable storage medium of this application. Detailed Implementation
[0017] The embodiments of this application will be described in detail below with reference to the accompanying drawings. The specific connection structure is based on the structure in actual production. In the following description, specific details such as particular system structures, interfaces, and technologies are set forth for illustration rather than limitation in order to provide a thorough understanding of this application.
[0018] To solve the above-mentioned technical problems, the first aspect of this application provides an interrupt handling method for an interrupt handling circuit.
[0019] Please see Figure 1 , Figure 1 This is a schematic diagram of the first embodiment of the interrupt handling circuit of this application. The interrupt handling method is applied to the interrupt handling circuit. The interrupt handling circuit 100 includes an interrupt processor 102 and at least two central processing units 101. Each central processing unit 101 is connected to the interrupt processor 102 through a signal switch 103.
[0020] Interrupt handler 102 is the hardware responsible for responding to received interrupt requests and coordinating the work between the central processing unit 101 and external devices 104. When a preset signal is received, the central processing unit 101 can quickly trigger a preset interrupt mechanism, breaking the current execution flow of the central processing unit 101 to prioritize the handling of interrupt requests. The central processing unit 101 is used to execute the interrupt process corresponding to the interrupt signal when the type of the preset signal matches its own function.
[0021] Please refer to Figure 2 , Figure 2 This is a flowchart illustrating the steps of the first embodiment of the interruption handling method of this application. The interruption handling method includes: S101: In response to receiving a setting signal through the interrupt processor 102, the interrupt processor 102 generates an interrupt signal.
[0022] In some embodiments, the interrupt processor 102 is connected to the external device 104 via physical circuitry. When the external device 104 sends a setting signal to trigger an interrupt, the interrupt processor 102 generates an interrupt signal according to a preset rule and transmits it to the target central processing unit 101 through the activated signal switch 103.
[0023] The setting signal of external device 104 can refer to various external devices 104, such as keyboard, mouse, hard drive, printer, sensor or brain-computer interface, etc. When a specific operation is completed or the central processing unit 101 needs to intervene, the electrical or data signal issued according to the hardware protocol and system preset rules is issued. For example, when a key is pressed on the keyboard, the keyboard controller will convert the key code into a signal that conforms to the interrupt specification; after the hard drive completes data reading and writing, it will send an "operation completed" status signal to the interrupt processor 102; when the sensor detects that the environmental parameters exceed the threshold, it will also issue an alarm signal that needs to be processed by the central processing unit 101. These signals will be received and accurately identified by the interrupt processor 102 and then an interrupt signal will be generated.
[0024] An interrupt signal is a control signal with a priority identifier and interrupt source information. It can include a request to suspend the current task of the central processing unit 101, or it can transmit information that enables the central processing unit 101 to quickly locate the corresponding interrupt service routine, so as to achieve an immediate response to sudden demands.
[0025] When multiple processors need to respond to the same interrupt simultaneously to achieve collaborative interrupt event processing, multiple signal switches 103 can be configured to be turned on at the same time to receive interrupt signals synchronously, avoiding concurrency problems caused by timing differences and providing parallel processing capabilities.
[0026] Alternatively, by using signal switches 103 configured independently for each processor, interrupt signals can be transmitted according to their orientation. The independent on / off state configuration of signal switches 103 allows different processors to receive interrupts as needed, avoiding the transmission of unnecessary interrupt signals to the central processing unit 101.
[0027] It can also be configured through software to enable different processors to respond to the same interrupt in a time-sharing manner, avoid resource contention, and communicate with other central processing units 101, and configure the signal switches 103 of other central processing units 101 to remain closed.
[0028] When the interrupt processor 102 receives multiple set signals and generates an interrupt signal, it determines the priority of the interrupt signal and sends the interrupt signal to the central processing unit 101 based on the priority.
[0029] External device 104 is connected to the corresponding pin of interrupt processor 102, and external device 104 sends interrupt signals to interrupt processor 102 through the pin of interrupt processor 102. Interrupt processor 102 sorts multiple simultaneous interrupts according to a preset priority rule, maintains an interrupt queue, and sends interrupt signals in priority order to ensure that high-priority interrupts are processed first.
[0030] S102: The interrupt signal is sent to the corresponding central processing unit 101 via the signal switch 103 through the interrupt processor 102.
[0031] Signal switch 103 serves as a physical circuit connecting the central processing unit 101 and the interrupt processor 102. When the switch is on, interrupt signal transmission is allowed; when it is off, signal transmission is blocked. The logic for generating control signals can be based on the operating state, load condition, or preset priority rules of the central processing unit 101. For example, it can automatically turn on the corresponding switch when a certain central processing unit 101 is in operation, or dynamically adjust the switch state according to the interrupt event type. The control of signal switch 103 can be implemented using hardware logic circuits or programmable registers. For example, the on / off state of the switch can be set through a configuration register, or the switch switching can be triggered by real-time monitoring of changes in the state of other processors.
[0032] The signal switch 103 can be an electronic component such as a register, flip-flop, latch, memory, or logic gate, used to control the on / off state of the path for transmitting interrupt signals. The signal switch 103 controls the path to be turned on or off according to the control signal of the corresponding central processing unit 101, thereby determining whether the interrupt signal is transmitted to the designated processor. Multiple signal switches 103 can be set, and each switch independently controls the interrupt signal path of the corresponding central processing unit 101. In some embodiments, the central processing unit 101 can output a control signal to control the corresponding signal to be turned on according to the actual operating conditions, during initialization, or when the connected external device 104 is connected or when the operating function is switched.
[0033] One output interface of the interrupt signal output terminal of the interrupt processor 102 is connected to multiple signal switches 103. Each processor controls its connection with the interrupt processor 102 by setting an independent signal switch 103, which directly realizes the flexible control of the interrupt signal by the multi-core central processing unit 101. By directly establishing a physical connection between the central processing unit 101 and the interrupt processor 102, the delay caused by the arbitration mechanism is avoided.
[0034] Each type of setting signal has its corresponding characteristics, such as high or low level, pulse width or data format, and corresponds to the system's preset interrupt number, ensuring that the central processing unit 101 can accurately identify the interrupt signal as representing the interrupt source device and the interrupt process queried. After receiving the interrupt signal, the central processing unit 101 will jump to interrupt mode and decide whether to execute the interrupt process.
[0035] S103: The central processing unit 101, whose own function matches the type of the set signal, executes the interrupt process corresponding to the interrupt signal.
[0036] In a multi-core heterogeneous device system, different central processing units 101 may reuse some of the same external devices 104. In actual operation, an interrupt signal may require different central processing units 101 to execute.
[0037] In multi-core systems, multiple interfaces are needed to connect external devices 104, such as I2C (Inter-Integrated Circuit), GPIO (General Purpose Input / Output), Display, Audio, and Camera. These are typically not exclusively handled by a single central processing unit 101. For example, in vehicle systems, when an I2C interface connects to a camera device for reversing functionality, the central processing unit 101 responsible for reversing may be needed to handle the process. In other applications, when an I2C interface connects to a display device, the central processing unit 101 responsible for display functionality needs to handle the process.
[0038] The direct connection between the interrupt handler 102 and each central processing unit 101 reduces intermediate forwarding links and lowers signal transmission latency. After receiving an interrupt signal, the central processing unit 101 will jump to interrupt mode and decide whether to execute the interrupt process.
[0039] The functions of the central processing unit 101 can include its own role allocation, load level, power status, interrupt masking status, interrupt process affinity, and hardware capabilities. The central processing unit 101 can set any value related to its own functions during initialization, and can also switch its own functions based on communication between the central processing units 101.
[0040] If there are at least two central processing units 101 whose functions match the type of the set signal, each matching central processing unit 101 will process the interrupt process simultaneously.
[0041] The central processing unit 101 processes the interrupt signal, obtains the cause of the interrupt or the corresponding interrupt process based on the interrupt signal, and then determines the time to execute the interrupt process.
[0042] Multiple CPUs 101 can simultaneously receive the same interrupt signal, enabling them to execute corresponding interrupt processes concurrently. The direct connection between the interrupt handler 102 and each CPU 101 reduces intermediate forwarding steps, lowers signal transmission latency, and improves overall system processing efficiency. Alternatively, in other embodiments, at least two CPUs 101 execute interrupt processes sequentially at different set times based on the interrupt signal. By setting different time points for sequential execution of interrupt processes, resource contention when multiple CPUs 101 handle the same interrupt simultaneously can be avoided, ensuring priority execution of critical tasks. Alternatively, since the same interrupt process has different priorities among the two CPUs 101, one CPU 101 executes the interrupt process first, while the other CPU 101 checks whether the interrupt process has already been processed by other cores. If it has, it ignores the interrupt, reducing resource consumption.
[0043] When multiple processors receive interrupts simultaneously, their respective interrupt service routines can be executed in parallel, improving overall system processing efficiency, enhancing the real-time performance and accuracy of interrupt handling, and reducing the computational power required by the central processing unit 101 to decide whether to execute the received interrupt signal. Hardware-level signal switch 103 controls the interrupt handling process instead of software arbitration, simplifying the interrupt handling process and reducing system complexity. This avoids the latency and interrupt loss issues associated with traditional arbitration mechanisms, making it particularly suitable for time-sensitive scenarios.
[0044] In some embodiments, when multiple central processing units 101 need to process the same interrupt simultaneously, all relevant switches are set to the ON state, so that the interrupt signal arrives at each central processing unit 101 at the same time. Alternatively, software configuration can be used to implement time-sharing responses to the same interrupt by different processors to avoid resource contention. Or, when a processor needs to receive a specific interrupt, the corresponding switch can be configured to ON through the central processing unit 101, enabling communication with other central processing units 101, while configuring the signal switches 103 of the other central processing units 101 to remain OFF.
[0045] By setting independent signal switches 103 to control the connection between each processor and the interrupt handler 102, the multi-core CPU 101 can directly and flexibly control interrupt signals. The direct connection between the interrupt handler 102 and each CPU 101 reduces intermediate forwarding steps, eliminating the need for virtual machine distribution or inter-core communication forwarding, thus reducing signal transmission latency. When multiple processors receive interrupts simultaneously, they can execute their respective interrupt service routines in parallel, improving overall system processing efficiency. Furthermore, the independent on / off state configuration of the signal switches 103 allows different processors to receive interrupts on demand, avoiding the transmission of unnecessary interrupt signals to the CPU 101, improving the real-time performance and accuracy of interrupt handling. It also reduces the computational burden on the CPU 101 to decide whether to execute received interrupt signals. Replacing software arbitration with hardware-level signal switch 103 control simplifies the interrupt handling process and reduces system complexity. It avoids the latency and interrupt loss problems associated with traditional arbitration mechanisms, making it particularly suitable for time-sensitive scenarios.
[0046] In one optional implementation, step S103, where the central processing unit 101 whose function matches the type of the set signal executes the interrupt process corresponding to the interrupt signal, may include: the central processing unit 101 receiving the interrupt signal and determining whether the type of the set signal matches its own function; if the type of the set signal matches its function, the central processing unit 101 executes the interrupt process; if the type of the set signal does not match its function, the central processing unit 101 discards the interrupt signal.
[0047] The central processing unit 101 can discard the interrupt signal, or it can be aware of the interrupt signal transmission but choose not to process it. When an interrupt occurs, if the type of the set signal does not match its function, the central processing unit 101 will not process the interrupt signal, but other matching central processing units 101 will process the interrupt signal to ensure the interrupt proceeds normally.
[0048] In one alternative implementation, the step of discarding an interrupt signal if the type of the set signal does not match its function includes: disconnecting the signal switch 103 connected to its central processing unit 101.
[0049] When external device 104 is replaced, removed, or reconfigured, the central processing unit 101 will detect that the type of the set signal does not match its function. To ensure the safety of the central processing unit 101, the signal switch 103 connected to it will be disconnected to avoid system crashes or abnormal behavior. Alternatively, the interrupt path to one central processing unit 101 can be turned off first, and then the path to another central processing unit 101 can be turned on, allowing the same peripheral device to be called by multiple central processing units 101, thus avoiding resource conflicts.
[0050] In one optional implementation, the central processing units 101 are interconnected (not shown in the figure). After receiving an interrupt signal and determining whether the type of the setting signal matches its own function, the central processing unit 101 further includes sending the determination result to other central processing units 101.
[0051] The central processing units 101 interact with each other via signal connections, generating control signals based on their own or other processors' operating states to adjust the on or off state of the signal switch 103. Multiple heterogeneous central processing units 101 are directly connected to the interrupt processor 102 via physical circuitry. Each central processing unit 101 can be configured to be turned on and off via an independent signal switch 103 to control the signal transmission of a specific interrupt number.
[0052] By directly controlling the signal switch 103 based on its own or other processor states, the central processing unit 101 can achieve real-time dynamic management of interrupt signal transmission, avoiding the delays and interrupt loss problems of traditional arbitration mechanisms. This direct control method reduces the processing overhead of intermediate links, making interrupt response faster and more reliable, especially suitable for time-sensitive scenarios. Simultaneously, the independent configuration of the signal switch 103 allows different central processing units 101 to flexibly choose whether to receive specific interrupts according to their own needs. This supports multiple cores responding to the same interrupt event simultaneously, and also avoids resource contention through software-level time-division multiplexing, improving the overall processing efficiency and resource utilization of multi-core heterogeneous systems. This hardware-level interrupt path management mechanism makes interrupt allocation more precise, effectively reducing system complexity and potential failure points caused by arbitration.
[0053] In other embodiments, hardware logic circuits can be used to implement state judgment. For example, by obtaining the operating mode or resource status of one or more central processing units 101, the state of its own signal switch 103 can be dynamically adjusted. Alternatively, the corresponding signal path can be enabled or disabled by configuring registers in software. The interrupt handling circuit 100 can also support dynamic configuration, which can flexibly adjust the interrupt allocation strategy according to different application scenarios, significantly reducing the probability of interrupt loss and improving the overall reliability of the system.
[0054] In some embodiments, taking temperature detection as an example, the signal path of the interrupt signal generated by the interrupt processor 102 is turned on by a dedicated low-power processor. At this time, the main application processor does not process the interrupt, and the simple and periodic interrupt is handed over to the low-power processor. After a period of time, the main application processor turns on the interrupt signal path, processes the interrupt of the current temperature sensor, and performs more complex data analysis, such as summarizing or predicting based on a batch of stored temperature data. While achieving the predetermined function, the overall energy consumption of the system is significantly reduced, and efficient allocation of responsibilities is achieved, thereby optimizing energy efficiency.
[0055] In some embodiments, taking the application scenario of automobile braking as an example, the interrupt signal is handled by one central processing unit 101 by default, while another backup central processing unit 101 with the same function exists as a monitoring role and does not directly respond to the interrupt. When the central processing unit 101, which is mainly responsible for this function, fails, the switching mechanism of the signal switch 103 is triggered, and the backup central processing unit 101 receives the interrupt signal and takes over the processing. This effectively avoids the coordination problems and complexities that may be caused by the dual cores processing the interrupt at the same time, and ensures functional safety.
[0056] One output interface of the interrupt signal output terminal of the interrupt processor 102 can be connected to multiple signal switches 103 to achieve simultaneous output of interrupt signals. By directly establishing a physical connection between the central processing unit 101 and the interrupt processor 102, the latency caused by the arbitration mechanism is avoided. When multiple processors need to respond to the same interrupt simultaneously to achieve collaborative interrupt event processing, multiple switches can be configured to be turned on simultaneously to synchronously acquire interrupt signals, avoiding concurrency problems caused by timing differences and realizing parallel processing capabilities. Alternatively, through the signal switches 103 configured independently for each processor, the interrupt signal can be transmitted according to the direction. This ensures that the central processing units 101 of different architectures can control the shared external device 104, and can also block invalid interrupts through hardware signal switches 103, reducing unnecessary interrupt processing overhead, significantly improving interrupt response efficiency, reducing the risk of interrupt loss, and simplifying the interrupt management complexity of multi-core systems. In some embodiments, the signals of the interrupt processor 102 are connected to the signal bus through an interface, and then connected to each central processing unit 101 through the signal bus.
[0057] In one alternative implementation, prior to the step of the interrupt processor 102 generating an interrupt signal in response to receiving a setting signal through the interrupt processor 102, the method further includes: in response to receiving an initialization signal or a reset signal, each central processing unit 101 sends a control signal to control the closed signal switch 103.
[0058] The initialization signal restores the interrupt handling circuit 100 or the entire system of the electronic device to its initial state, resetting all interrupt paths to the default disabled state at the hardware level. Alternatively, the reset signal resets the path between the central processing unit 101 and the interrupt processor 102, re-establishing the path between them. This ensures correct and corresponding interrupt path configuration and accurate entry into interrupt mode, guaranteeing the reliability, determinism, and consistency of interrupt handling.
[0059] Please refer to Figure 3 , Figure 3 This is a schematic diagram of the second embodiment of the interrupt handling circuit of this application.
[0060] In some embodiments, the external device 104 connected to the interrupt handling circuit 100 includes an on-chip device 1041, or includes an on-chip device 1041 and an external device 104, at least the on-chip device 1041 is connected to the external device 104; the on-chip device 1041 is connected to the interrupt processor 102; the interrupt processor 102 receives interrupt signals from the on-chip device 1041 and / or the external device 104 through the on-chip device 1041, and the interrupt processor 102 generates an interrupt signal in response to receiving a setting signal through the interrupt processor 102, the step of the interrupt processor 102 generating an interrupt signal includes: receiving a setting signal sent from the on-chip device 1041 through the interrupt processor 102; wherein, the setting signal is a setting signal of the external device 1042 forwarded by the on-chip device 1041, or / and a setting signal generated by the on-chip device 1041 itself.
[0061] In one embodiment, the interrupt processor 102 is also used to connect to an external device 104 and generate an interrupt signal when the external device 104 issues a setting signal; the external device 104 includes an on-chip device 1041 and an external device 1042, the on-chip device 1041 is connected to the interrupt controller, and the external device 1042 is connected through the on-chip device 1041.
[0062] Interrupt handling circuit 100 includes an interrupt processor 102 connected to an external device 104. Upon receiving a setting signal from the external device 104, the interrupt processor 102 queries and determines the corresponding interrupt number and transmits it to multiple central processing units 101. The connection between the interrupt processor 102 and the external device 104 can be a direct physical circuit connection or data transmission via a bus protocol. Each central processing unit 101 controls the enable state of a signal switch 103 through independently configured registers. When the signal switch 103 is enabled, the interrupt signal is transmitted to the corresponding central processing unit 101 through a preset physical path. In specific implementations, the interrupt number lookup process can be implemented based on hardware logic circuits or through firmware or software algorithms. The interrupt signal transmission path can adopt a parallel bus structure or a time-division multiplexed serial bus structure. The interrupt enable configuration of each central processing unit 101 can be implemented through dedicated registers or a unified configuration memory. The configuration method can be direct hardware writing or dynamic adjustment through software instructions.
[0063] By directly querying and distributing interrupt numbers, the latency and interrupt loss risks associated with traditional arbitration controllers are avoided, enabling multiple CPUs (101) to process requests from different interrupt sources in parallel. Independent interrupt number enabling configuration allows processors with different architectures to selectively receive interrupts according to their needs, improving resource utilization in heterogeneous multi-core systems. The combination of the physical transmission path of interrupt signals and the independent configuration of processors ensures real-time interrupt response while simplifying communication complexity between multiple cores, reducing overall system interrupt handling latency. This design is particularly suitable for scenarios requiring multi-core collaborative processing of complex tasks, significantly improving system concurrency and response efficiency.
[0064] In some embodiments, the external device 104 connected to the interrupt handling circuit 100 consists only of the on-chip device 1041. In some embodiments, the external device 1041 includes both the on-chip device 1041 and an external device 1042. The on-chip device 1041 is connected to the external device 104; the on-chip device 1041 is connected to the interrupt processor 102; and the interrupt processor 102 receives interrupt signals from the on-chip device 1041 and / or the external device 1042 through the on-chip device 1041. In some embodiments, the external device 104 may include the on-chip device 1041 and a combination of the on-chip device 1041 and the external device 1042, wherein the on-chip device 1041 is directly connected to the interrupt processor 102, and the interrupt processor 102 receives a setting signal through the on-chip device 1041, which may originate from the on-chip device 1041 itself or from the external device 104 connected to it. The interrupt processor 102 has the capability to handle multiple interrupts from the central processing unit 101 simultaneously and is physically connected to each central processing unit 101.
[0065] In one specific embodiment, the interrupt may include scenarios such as an interrupt triggered by the completion of DMA (Direct Memory Access) buffer filling or an interrupt triggered by a GPIO level change. The interrupt processor 102 identifies the set signal source and queries the interrupt number through a preset physical signal channel or physical pin.
[0066] The ability of multiple CPUs 101 to simultaneously receive interrupt signals allows them to process different interrupt events in parallel, improving overall system efficiency. By establishing a fixed correspondence between interrupt numbers and external devices 104, the interrupt handling logic is simplified, reducing the complexity of interrupt signal processing in multi-core heterogeneous systems. The signal switch 103 is autonomously controlled by each CPU 101, ensuring accurate interrupt signal transmission while dynamically controlling the signal switch 103 to reduce unnecessary interrupt handling overhead and optimize resource utilization.
[0067] In some embodiments, the setting information when connecting different external devices 1042 may also be different. The specific external device 1042 type or setting signal can be recorded in the internal status register, converted into a setting signal type that conforms to the system interrupt specification, and transmitted to the interrupt processor 102.
[0068] Please see Figure 4 , Figure 4 This is a schematic diagram of the third embodiment of the interrupt handling circuit of this application.
[0069] In one embodiment, the interrupt handling circuit 100 further includes a storage medium 105, which is connected to the interrupt processor 102 and the central processing unit 101 respectively; wherein, the storage medium 105 stores the interrupt number and the interrupt process corresponding to the interrupt number.
[0070] In specific embodiments, in some cases, the storage medium 105 can be memory, flash memory, registers, or network storage that stores interrupt numbers, interrupt process methods, and a mapping relationship between interrupt numbers and corresponding interrupt processes. The interrupt processor 102 has a query logic module internally, and the central processing unit 101 interacts with the storage medium 105 through a bus interface. By integrating the storage medium 105 internally into the interrupt processor 102 to achieve direct mapping between interrupt numbers and interrupt processes, the latency problem caused by traditional arbitration mechanisms is avoided. This allows the multi-core heterogeneous central processing unit 101 to acquire the interrupt processes they need in parallel, effectively resolving the interrupt allocation conflict in the scenario of external device 104 multiplexing.
[0071] Please participate Figure 5 , Figure 5 This is a flowchart illustrating the steps of the third embodiment of the interruption handling method of this application.
[0072] In one alternative implementation, the step of interrupt processor 102 generating an interrupt signal in response to receiving a setting signal through interrupt processor 102 includes S201: identifying the setting signal through interrupt processor 102 and determining the type of interrupt signal.
[0073] The storage medium 105 is directly connected to the interrupt processor 102. When a setting signal is received, the interrupt processor 102 obtains the corresponding interrupt number by querying the pre-stored data in the storage medium 105. In some embodiments, there is a fixed correspondence between the interrupt number and the external device 104, thereby ensuring that the interrupt processor 102 accurately processes the interrupt signal.
[0074] The steps of executing the interrupt process corresponding to the interrupt signal by the central processing unit 101 matching its own function with the type of the set signal include S202: the central processing unit 101 queries the storage medium 105 for the interrupt process corresponding to the interrupt number according to the interrupt number.
[0075] The central processing unit 101 maintains a connection with the storage medium 105 and can retrieve the corresponding interrupt process from the storage medium 105 based on the interrupt number. Each central processing unit 101 can be independently configured to turn on a corresponding switch to control the signal transmission of a specific interrupt number.
[0076] In some embodiments, the central processing unit 101, signal switch 103, interrupt processor 102, on-chip device 1041, and storage medium 105 may be integrated inside the SoC (System on Chip), and the external device 104 transmits interrupt signals through connection with the on-chip device 1041.
[0077] In some embodiments, the storage medium 105 can be memory, flash memory, registers, or network storage that stores interrupt numbers, interrupt process methods, and their mapping relationships. The interrupt handler 102 has a polling logic module internally, and the central processing unit 101 interacts with the storage medium 105 through a bus interface. By integrating the storage medium 105 internally into the interrupt handler 102 to achieve direct mapping between interrupt numbers and interrupt processes, the latency problem caused by traditional arbitration mechanisms is avoided. This allows the multi-core heterogeneous central processing unit 101 to acquire the interrupt processes they need in parallel, effectively resolving the interrupt allocation conflict in the scenario of external device 104 multiplexing.
[0078] In one optional implementation, after the central processing unit 101 queries the interrupt process corresponding to the interrupt number from the storage medium 105 according to the interrupt number, the step of executing the interrupt process includes S203: the central processing unit 101 obtains its own function type.
[0079] In some embodiments, in addition to storing interrupt numbers, interrupt process methods, and system software that maps interrupt numbers to corresponding interrupt processes, storage medium 105 may also store the identifier and functions of central processing unit 101. Each central processing unit 101 can use this identifier to maintain and retrieve its dynamic "function" information. Its own function type may include: its own role assignment, load level, power state, interrupt masking state, interrupt process affinity, and hardware capabilities, etc. The central processing unit 101 can set any value related to its own functions during initialization, and can also switch its own functions based on communication between central processing units 101.
[0080] In other embodiments, the central processing unit 101 may use its own identifier to query its own functions and use the interrupt number to query interrupt requests during initialization or normal process execution.
[0081] S204: The central processing unit 101 determines the corresponding interrupt process based on the function type and interrupt number.
[0082] S205: The central processing unit 101 executes the interrupt process.
[0083] In one specific embodiment, an input peripheral sends a setting signal requesting input data. After the interrupt handler 102 generates an interrupt signal and transmits it to multiple central processing units 101, each central processing unit 101 finds that this interrupt can run on multiple central processing units 101, but the required load is high. One central processing unit 101 determines that its own function meets the interrupt process affinity of the interrupt signal, but its role is assigned to data computation and it is in a high-load state, which does not match the requirements of the interrupt requested by the setting signal, so it decides not to execute the interrupt process. Another central processing unit 101 meets the interrupt process affinity of the interrupt signal, its role is assigned to process input and it is in an idle state, which highly matches the requirements of interrupt handling. Therefore, it decides to execute the complete interrupt process and process the input data of this peripheral. In other embodiments, other central processing units 101 can act as cooperating executors around the main central processing unit 101 that handles the interrupt process, also deciding to respond to the interrupt signal based on their own identity and function type, and starting to execute the part of the work process assigned to them by the main central processing unit 101.
[0084] In some embodiments, the central processing unit 101, signal switch 103, interrupt processor 102, on-chip device 1041, and storage medium 105 may be integrated inside the system on chip, and the external device 104 transmits interrupt signals through connection with the on-chip device 1041.
[0085] The above embodiments provide an interrupt handling method. By setting independent signal switches to control the connection between each processor and the interrupt handler, it is possible to directly realize flexible control of interrupt signals by a multi-core CPU. The direct connection between the interrupt handler and each CPU reduces intermediate forwarding links and lowers signal transmission latency. When multiple processors receive interrupts simultaneously, they can execute their respective interrupt service routines in parallel, improving the overall system processing efficiency. Furthermore, the independent on / off state configuration of the signal switches allows different processors to receive interrupts on demand, avoiding the transmission of unnecessary interrupt signals to the CPU, improving the real-time performance and accuracy of interrupt handling. It also reduces the CPU's computational burden in deciding whether to execute received interrupt signals. By replacing software arbitration with hardware-level signal switch control, the interrupt handling process is simplified, and system complexity is reduced. It avoids the latency and interrupt loss problems caused by traditional arbitration mechanisms, making it particularly suitable for time-sensitive scenarios.
[0086] Please refer to this again. Figure 1 , Figure 1 This is a schematic diagram of one embodiment of the interrupt handling circuit of this application. The interrupt handling circuit 100 includes: an interrupt processor 102, used to generate an interrupt signal upon receiving a set signal; Interrupt handler 102 is the hardware responsible for responding to received interrupt requests and coordinating the work between the central processing unit 101 and external devices 104. When a set signal is received, the central processing unit 101 can quickly trigger a preset interrupt mechanism to break the current execution flow of the central processing unit 101 in order to prioritize the interrupt request.
[0087] In some embodiments, the interrupt processor 102 is connected to the external device 104 via physical circuitry. When the external device 104 sends a setting signal to trigger an interrupt, the interrupt processor 102 generates an interrupt signal according to a preset rule and transmits it to the target central processing unit 101 through the activated signal switch 103.
[0088] The setting signal of external device 104 can refer to various external devices 104, such as keyboard, mouse, hard disk, printer, sensor, etc. When a specific operation is completed or when the central processing unit 101 needs to intervene, the electrical signal or data signal issued according to the hardware protocol and system preset rules will be received and accurately identified by the interrupt processor 102 and then an interrupt signal will be generated.
[0089] An interrupt signal is a control signal with a priority identifier and interrupt source information. It can include a request to suspend the current task of the central processing unit 101, or it can transmit information that enables the central processing unit 101 to quickly locate the corresponding interrupt service routine, so as to achieve an immediate response to sudden demands.
[0090] At least two central processing units 101 are provided, and each central processing unit 101 is connected to an interrupt processor 102 via a signal switch 103. The central processing unit 101 is used to execute the interrupt process corresponding to the interrupt signal when the type of the set signal matches its own function.
[0091] The signal switch 103 can be an electronic component such as a register, flip-flop, latch, memory, or logic gate, used to control the on / off state of the path for transmitting interrupt signals. The signal switch 103 controls the path to be turned on or off according to the control signal of the corresponding central processing unit 101, thereby determining whether the interrupt signal is transmitted to the designated processor. Multiple signal switches 103 can be set, and each switch independently controls the interrupt signal path of the corresponding central processing unit 101. In some embodiments, the central processing unit 101 can output a control signal to control the corresponding signal to be turned on according to the actual operating conditions, during initialization, or when the connected external device 104 is connected or when the operating function is switched.
[0092] In a multi-core heterogeneous device system, different central processing units (CPUs) 101 may reuse some of the same external devices 104. In actual operation, an interrupt signal may require different CPUs 101 to execute. External devices 104 require multiple interface connections, such as I2C, GPIO, Display, Audio, and Camera, which are usually not exclusively handled by a single CPU 101. For example, in vehicle equipment, when an I2C interface is used to connect a camera device for reversing functions, the CPU 101 responsible for reversing functions may need to handle the process. In other applications, when an I2C interface is used to connect a display device, the CPU 101 responsible for display functions needs to handle the process.
[0093] Each type of setting signal has its corresponding characteristics, such as high or low level, pulse width or data format, and corresponds to the system's preset interrupt number, ensuring that the central processing unit 101 can accurately identify the interrupt signal as representing the interrupt source device and the interrupt process queried. After receiving the interrupt signal, the central processing unit 101 will jump to interrupt mode and decide whether to execute the interrupt process.
[0094] The functions of the central processing unit 101 can include its own role allocation, load level, power status, interrupt masking status, interrupt process affinity, and hardware capabilities. The central processing unit 101 can set any value related to its own functions during initialization, and can also switch its own functions based on communication between the central processing units 101.
[0095] In one alternative implementation, the central processing units 101 are interconnected, and the central processing unit 101 is used to send control signals to the signal switches 103 connected thereto according to its own and / or other central processing units 101's functions, so as to control the signal switches 103 to be turned on or off.
[0096] The central processing units 101 interact with each other via signal connections, generating control signals based on their own or other processors' operating states to adjust the on or off state of signal switches 103. Multiple central processing units 101 are directly connected to interrupt processors 102 via physical circuits, and each central processing unit 101 can be independently configured to turn on its corresponding switch, controlling the signal transmission of a specific interrupt number.
[0097] The status judgment can be implemented by hardware logic circuits. For example, by obtaining the operating mode or resource status of one or more central processing units 101, the status of its own signal switch 103 can be dynamically adjusted. Alternatively, the corresponding signal path can be opened or closed by configuring the register in software.
[0098] The interrupt handling circuit 100 can also support dynamic configuration, which can flexibly adjust the interrupt allocation strategy according to different application scenarios, significantly reduce the probability of interrupt loss, and improve the overall reliability of the system.
[0099] In one embodiment, an output interface of the interrupt signal output terminal of the interrupt processor 102 can be connected to at least multiple signal switches 103 to achieve simultaneous output of interrupt signals. By directly establishing a physical connection between the central processing unit 101 and the interrupt processor 102, the latency caused by the arbitration mechanism is avoided. When multiple processors need to respond to the same interrupt simultaneously to achieve collaborative interrupt event processing, multiple switches can be configured to be turned on simultaneously to synchronously acquire interrupt signals, avoiding concurrency problems caused by timing differences and achieving parallel processing capabilities. Alternatively, through the signal switches 103 configured independently for each processor, the interrupt signal can be transmitted according to the direction, which not only ensures the control of the shared external device 104 by the central processing units 101 with different architectures, but also blocks invalid interrupts through hardware signal switches 103, reduces unnecessary interrupt processing overhead, significantly improves interrupt response efficiency, reduces the risk of interrupt loss, and simplifies the interrupt management complexity of multi-core systems. In some embodiments, the signal of the interrupt processor 102 is connected to the signal bus through an interface, and then connected to each central processing unit 101 through the signal bus.
[0100] Please refer to it again. Figure 3 , Figure 3 This is a schematic diagram of the second embodiment of the interrupt handling circuit of this application.
[0101] In some embodiments, the external device 104 connected to the interrupt handling circuit 100 consists only of the on-chip device 1041. In some embodiments, the external device 1041 includes both the on-chip device 1041 and an external device 1042. The on-chip device 1041 is connected to the external device 104; the on-chip device 1041 is connected to the interrupt processor 102; and the interrupt processor 102 receives interrupt signals from the on-chip device 1041 and / or the external device 1042 through the on-chip device 1041. In some embodiments, the external device 104 may include the on-chip device 1041 and a combination of the on-chip device 1041 and the external device 1042, wherein the on-chip device 1041 is directly connected to the interrupt processor 102, and the interrupt processor 102 receives a setting signal through the on-chip device 1041, which may originate from the on-chip device 1041 itself or from the external device 104 connected to it. The interrupt processor 102 has the capability to handle multiple interrupts from the central processing unit 101 simultaneously and is connected to each central processing unit 101 via physical circuitry.
[0102] In one specific embodiment, the interrupt may include scenarios such as an interrupt triggered by the completion of DMA buffer filling or an interrupt triggered by a change in GPIO level. The interrupt processor 102 identifies and sets the signal source and queries the interrupt number through a preset physical signal channel or physical pin.
[0103] The ability of multiple CPUs 101 to simultaneously receive interrupt signals allows them to process different interrupt events in parallel, improving overall system efficiency. By establishing a fixed correspondence between interrupt numbers and external devices 104, the interrupt handling logic is simplified, reducing the complexity of interrupt signal processing in multi-core heterogeneous systems. The signal switch 103 is autonomously controlled by each CPU 101, ensuring accurate interrupt signal transmission while dynamically controlling the signal switch 103 to reduce unnecessary interrupt handling overhead and optimize resource utilization.
[0104] Please refer to it again. Figure 4 , Figure 4 This is a schematic diagram of the third embodiment of the interrupt handling circuit of this application.
[0105] In one embodiment, the interrupt handling circuit 100 further includes a storage medium 105, which is connected to both the interrupt processor 102 and the central processing unit 101. The storage medium 105 stores an interrupt number and the interrupt process corresponding to the interrupt number. The interrupt processor 102 queries the storage medium 105 for the corresponding interrupt number according to the type of a set signal, generates an interrupt signal, and sends the interrupt signal and the interrupt number to the active central processing unit 101. The central processing unit 101 queries the storage medium 105 for the interrupt process corresponding to the interrupt number and executes the interrupt process.
[0106] Storage medium 105 is used to store the mapping relationship between interrupt numbers and corresponding interrupt processes. Storage medium 105 is directly connected to interrupt processor 102. When a setting signal is received, interrupt processor 102 obtains the corresponding interrupt number by querying the pre-stored data in storage medium 105. Central processing unit 101 maintains a connection with storage medium 105 and can extract the corresponding interrupt process from storage medium 105 based on the interrupt number. In some embodiments, central processing unit 101, signal switch 103, interrupt processor 102, on-chip device 1041, and storage medium 105 can be integrated inside SoC (System on Chip). External device 104 transmits interrupt signals through connection with on-chip device 1041.
[0107] In some embodiments, the storage medium 105 can be memory, flash memory, registers, or network storage that stores interrupt numbers, interrupt process methods, and their mapping relationships. The interrupt handler 102 has a polling logic module internally, and the central processing unit 101 interacts with the storage medium 105 through a bus interface. By integrating the storage medium 105 internally into the interrupt handler 102 to achieve direct mapping between interrupt numbers and interrupt processes, the latency problem caused by traditional arbitration mechanisms is avoided. This allows the multi-core heterogeneous central processing unit 101 to acquire the interrupt processes they need in parallel, effectively resolving the interrupt allocation conflict in the scenario of external device 104 multiplexing.
[0108] Understandable. Figure 1 , Figure 3 and Figure 4 The central processing unit 101 and external device 104 shown in the structural diagram can be the same or different models or functions of the central processing unit 101 or external device 104. The specific structure is based on production and actual application.
[0109] The above method provides an interrupt handling circuit. By setting independent signal switches 103 to control the connection between each processor and the interrupt handler 102, the multi-core CPU 101 can directly and flexibly control interrupt signals. The direct connection between the interrupt handler 102 and each CPU 101 reduces intermediate forwarding links, lowers signal transmission latency, and optimizes the interrupt handling architecture. The interrupt handler 102 supports interrupt instructions from CPUs 101 with various architectures and can simultaneously initiate interrupt events to multiple CPUs 101, causing each CPU 101 to execute the interrupt process corresponding to the interrupt number. When multiple processors receive interrupts simultaneously, they can execute their respective interrupt service routines in parallel, improving the overall system processing efficiency. Furthermore, the independent on / off state configuration of the signal switches 103 allows different processors to receive interrupts on demand, avoiding the transmission of unnecessary interrupt signals to the CPU 101, improving the real-time performance and accuracy of interrupt handling, and reducing the computational power required by the CPU 101 to decide whether to execute the received interrupt signal. By using hardware-level signal switch 103 control instead of software arbitration, the interrupt handling process is simplified, and system complexity is reduced. It avoids the delays and interruptions caused by traditional arbitration mechanisms, and is especially suitable for time-sensitive scenarios.
[0110] A third aspect of this application provides a computer-readable storage medium or a computer program product.
[0111] Please refer to Figure 6 , Figure 6 This is a schematic diagram of one embodiment of the computer-readable storage medium of this application. The computer-readable storage medium 200 of this embodiment stores computer program instructions 201, which can be executed using any of the interrupt handling methods described above. The computer-readable storage medium 200 can be a read / write storage device such as a hard disk, memory chip, SD card, or optical disk, either internal to or connected to an interrupt handling circuit.
[0112] Based on the above embodiments, the technical solution of this application, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a computer software product stored in a computer-readable storage medium 200.
[0113] The computer program product of this embodiment (not shown) includes computer program instructions 201, which, when executed by a processor, implement the interrupt handling method of any of the preceding claims. This computer program product, as a separate product, is stored in a computer-readable storage medium when sold or used, and enables some or one or more of the computer program instructions 201 of the computer program product to be runnable.
[0114] In the several embodiments provided in this application, it should be understood that the disclosed systems and devices can be implemented in other ways. Regarding the technical solutions in the embodiments of this application, it is obvious that the described embodiments are only a part of the embodiments of this application, and not all of them. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application. For example, the device implementation methods described above are merely illustrative. For example, the division of modules or units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the displayed or discussed mutual coupling or direct coupling or communication connection may be through some interfaces, indirect coupling or communication connection of devices or units, and may be electrical, mechanical, or other forms.
[0115] It should be noted that if the embodiments of this application involve directional indicators (such as up, down, left, right, front, back, etc.), the directional indicators are only used to explain the relative positional relationship and movement of each component in a certain specific posture (as shown in the figure). If the specific posture changes, the directional indicators will also change accordingly.
[0116] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "coupled," "connected," "linked," "set up," and "installed" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.
[0117] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment, depending on actual needs.
[0118] Furthermore, the technical solutions of the various embodiments can be combined with each other, but only if they are based on the ability of those skilled in the art to implement them. When the combination of technical solutions is contradictory or cannot be implemented, it should be considered that such combination of technical solutions does not exist and is not within the scope of protection claimed in this application.
[0119] The above description is merely an embodiment of this application and does not limit the patent scope of this application. Any equivalent structural or procedural transformations made using the content of this application's specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of this application.
Claims
1. An interrupt handling method, characterized in that, The interrupt handling method is applied to an interrupt handling circuit, which includes an interrupt processor and at least two central processing units (CPUs), each of which is connected to the interrupt processor via a signal switch. The interrupt handling method includes: In response to receiving a setting signal via the interrupt processor, the interrupt processor generates an interrupt signal; The interrupt processor sends the interrupt signal to the corresponding central processing unit via the signal switch. The interrupt process corresponding to the interrupt signal is executed by a central processing unit whose function matches the type of the set signal. Specifically, if there are at least two central processing units whose function matches the type of the set signal, each of the matched central processing units processes the interrupt process simultaneously.
2. The interrupt handling method according to claim 1, characterized in that, The step of the central processing unit, whose own functions match the type of the set signal, executing the interrupt process corresponding to the interrupt signal further includes: The central processing unit receives the interrupt signal and determines whether the type of the set signal matches its own function. If the type of the set signal matches its function, the central processing unit executes the interrupt process; If the type of the set signal does not match its function, the central processing unit discards the interrupt signal.
3. The interrupt handling method according to claim 2, characterized in that, The central processing units are interconnected. After receiving the interrupt signal and determining whether the type of the set signal matches its own function, the process further includes: The judgment result is sent to other central processing units.
4. The interrupt handling method according to claim 2, characterized in that, The step of discarding the interrupt signal if the type of the set signal does not match its function includes: Disconnect the signal switch connected to its central processing unit.
5. The interrupt handling method according to claim 1, characterized in that, Prior to the step of the interrupt processor generating an interrupt signal in response to receiving a set signal through the interrupt processor, the method further includes: In response to receiving an initialization signal or a reset signal, each of the central processing units sends a control signal to control the closing of the signal switch.
6. The interrupt handling method according to claim 1, characterized in that, The interrupt processor is also configured to connect to an external device, the external device including an on-chip device or the external device including the on-chip device and an external device, the on-chip device being connected to the interrupt controller, and the external device being connected through the on-chip device; the step of the interrupt processor generating an interrupt signal in response to receiving a set signal through the interrupt processor includes: The interrupt processor receives a setting signal sent from the on-chip device; wherein the setting signal is a setting signal of an external device forwarded by the on-chip device, or / and a setting signal generated by the on-chip device itself.
7. The interrupt handling method according to claim 1, characterized in that, The interrupt handling circuit further includes a storage medium, which is connected to both the interrupt processor and the central processing unit; wherein the storage medium stores an interrupt number and the interrupt process corresponding to the interrupt number. The step of the interrupt processor generating an interrupt signal in response to receiving a set signal through the interrupt processor includes: identifying the set signal through the interrupt processor to determine the type of the interrupt signal; and querying the corresponding interrupt number from the storage medium according to the type of the set signal to generate an interrupt signal. The step of the central processing unit (CPU) matching the type of the set signal by its own function to execute the interrupt process corresponding to the interrupt signal includes: the CPU querying the interrupt process corresponding to the interrupt number from the storage medium according to the interrupt number, and executing the interrupt process.
8. The interrupt handling method according to claim 7, characterized in that, The step of querying the interrupt process corresponding to the interrupt number from the storage medium by the central processing unit based on the interrupt number, and executing the interrupt process, includes: The central processing unit obtains its own function type; The corresponding process is determined based on the function type and the interrupt number; Execute the interrupted process.
9. An interrupt handling circuit, characterized in that, The interrupt handling circuit includes: An interrupt handler is used to generate an interrupt signal when a set signal is received. At least two central processing units, each of which is connected to the interrupt processor via a signal switch; The central processing unit is used to execute the interrupt process corresponding to the interrupt signal when the type of the set signal matches its own function.
10. The interrupt handling circuit according to claim 9, characterized in that, The central processing units are interconnected, and each central processing unit is used to send control signals to the signal switches connected to it according to its own and / or other central processing units’ functions, so as to control each signal switch to be turned on or off.
11. A computer-readable storage medium / computer program product, characterized in that, The computer-readable storage medium stores computer program instructions that can be executed by a processor to implement the interrupt handling method as described in any one of claims 1 to 8. The computer program product includes computer program instructions that, when executed by a processor, implement the interrupt handling method as described in any one of claims 1 to 8.