Automatic layout and synthesis method and system for analog circuit layout based on sample driving

Abstract

The invention discloses an automatic layout and synthesis method and system for an analog circuit layout based on sample driving, and is suitable for a circuit design platform of a unified working area. A plurality of sub-layouts are divided in a circuit in advance, and an independent layout analysis mechanism is introduced, so that a design closed loop with layout legality control and artificial intelligence agent model optimization deep fusion is constructed. The system further decouples different analysis mechanisms through multi-level circuit connection relation standardization (performance analysis, layout analysis and coupling analysis). A random sampling + real-time sub-layout layout verification mechanism is adopted, and it is ensured that a training sample has geometric conflict-free and electrical high-fidelity characteristics. The layout constraint is used as a hard condition to be embedded into optimization result judgment through an online iteration or rapid reasoning mode, so that the layout conforming to the layout rule of each sub-layout is directly generated while optimization exploration pursues high-performance circuit parameters, and the design automation level and the result reliability in a complex environment are remarkably improved.

Description

A Sample-Driven Automatic Placement and Synthesis Method and System for Analog Circuit Layout Technical Field

[0001] This invention relates to the field of electronic design automation (EDA) technology, and particularly to the automated layout design of analog, radio frequency, and millimeter-wave integrated circuits. Specifically, it relates to a sample-driven automatic layout and synthesis method and system for analog circuits. Background Technology

[0002] In the field of analog integrated circuit design, the intelligent integration of layout and circuit performance has become a key path to overcome design efficiency bottlenecks and improve product performance. Traditional EDA systems generally adopt the "unified work area" design paradigm: after defining component connection relationships in the schematic environment, the system automatically generates initial layout coordinates based on component attributes and topology. However, this mechanical automatic stitching method has two significant structural defects.

[0003] First, there is a lack of a pre-judgment mechanism for the legality of the layout. In complex circuits, geometric overlap between components (such as DRC violations) occurs frequently, and the existing framework can neither detect such conflicts in real time during the layout generation stage nor provide automated repair strategies. This forces designers to repeatedly adjust the position parameters manually, which severely restricts the speed of design iteration.

[0004] Secondly, the physical field coupling effect is deeply disconnected from the layout design process. Even if a non-overlapping layout is generated, traditional processes still cannot automatically take into account the influence of physical field factors such as electromagnetic and thermal fields. Especially in radio frequency, microwave and millimeter wave circuits, interconnect coupling, matching structure and shielding layout directly affect circuit performance, but current methods lack the ability to embed these effects into the optimization closed loop.

[0005] Furthermore, with the integration of artificial intelligence (AI) technology and EDA, many machine learning-based optimization methods have emerged. However, most existing methods are still limited to parameter tuning at the schematic level. In the layout generation and optimization stages, they still heavily rely on human experience, and time-consuming high-precision physical field simulation is usually treated as an isolated post-verification step. This results in the failure to form an efficient collaborative closed loop among layout generation, physical field coupling modeling, and circuit performance optimization. In summary, there is an urgent need in this field for an innovative design method that can deeply embed layout compliance verification and physical field effect awareness into a data-driven automated optimization process, thereby achieving integrated intelligent synthesis from circuit parameters to a manufacturable layout. Summary of the Invention

[0006] To address the aforementioned shortcomings of existing technologies, this invention provides a sample-driven automatic placement and synthesis method and system for analog circuit layout. The core of this invention lies in constructing a collaborative design closed loop that deeply integrates layout validity control with artificial intelligence proxy model optimization.

[0007] The core concept of this invention is as follows: During the data acquisition (sample generation) phase, deep integration layout compliance checks and high-precision physical field simulations are performed to ensure that each sample used to train the surrogate model has no component overlap and a high-fidelity electrical response (including parasitic and coupling effects). The surrogate model trained in this way encodes layout constraints and physical laws in its input-output mapping relationship. During the optimization phase, when exploring the design space using this model, the layout legality of each candidate solution is judged in real time to ensure that it still meets geometric layout constraints while considering the influence of physical fields, thereby achieving the simultaneous completion of "parameter optimization" and "feasible layout generation".

[0008] To realize the above concept and adapt to the efficiency and accuracy requirements of different scenarios, this invention is specifically embodied through the following closely related implementation scheme: a sample-driven automatic placement and synthesis method and system for analog circuit layout. This scheme emphasizes online iteration and closed-loop verification. During the optimization process, it dynamically generates samples, updates the surrogate model, and performs placement and simulation verification at each iteration point, forming a self-evolving closed loop of "optimization-verification-learning," ultimately outputting a rigorously verified globally optimal solution.

[0009] A sample-driven, fast automatic placement and synthesis method and system for analog circuit layout: This approach focuses on offline modeling and rapid inference. It pre-builds and stores a high-quality surrogate model library. When encountering a new design task, it performs one-time prediction and placement verification by quickly matching and calling the pre-trained model, obtaining a high-quality solution that meets the requirements in a very short time (e.g., seconds), making it suitable for scenarios with high real-time requirements.

[0010] A collaborative analysis and application method for performance and layout based on design identifier stripping in hybrid circuit design: This scheme is the underlying supporting technology that enables the efficient implementation of the aforementioned two schemes in complex EDA design environments. Through innovative "design identifier stripping" and "hierarchical standardization of connection relationships" techniques, it completely decouples the circuit's performance analysis, layout analysis, and physical field coupling analysis processes, ensuring that the analysis used for layout does not interfere with the solution used for performance; simultaneously, it makes the analysis results independent of specific design naming or schematic location coordinates, thereby achieving efficient reuse of samples and data.

[0011] To ensure the accuracy of the surrogate model's learning, the cornerstone of this invention lies in the generation of high-quality samples. By deeply coupling layout legality determination and high-precision physics simulation in the sample acquisition process, each training sample is guaranteed to simultaneously meet the two conditions of "geometric feasibility" and "electrical fidelity." This fundamentally eliminates the interference of illegal layout data on model learning and enables the model to accurately capture the precise input-output mapping relationship containing complex physical field effects.

[0012] Based on this, this invention constructs a dynamic optimization closed loop of "design-verification-learning" built on layout control. In the optimization iteration, each candidate design point generated by the surrogate model automatically undergoes a verification process of "layout generation and overlap check → physical field simulation." Only samples that pass verification are added to the training set to update and enhance the surrogate model. This closed-loop mechanism ensures that the optimization process always takes place within a compliant layout space and continuously corrects the model using the latest simulation data, ultimately leading to a reliable solution that satisfies all layout constraints and achieves optimal performance.

[0013] Furthermore, this invention constructs a fully closed-loop verification chain from "optimized output → layout verification → simulation feedback → model update". Each optimization iteration generates candidate solutions that undergo rigorous layout splicing and overlap detection, retaining only solutions with legal layouts; and precise simulation verification is performed using a numerical solver. The results are used to continuously update the AI ​​proxy model, forming a dynamically evolving learning mechanism. This closed-loop structure ensures that the final output optimal circuit solution always meets the dual objectives of layout compliance and performance optimization.

[0014] This invention effectively overcomes the shortcomings of existing AI-assisted EDA technologies in layout integration and physical perception, providing intelligent closed-loop optimization capabilities for traditional design processes. It deeply integrates schematic design, layout generation, and performance verification, significantly reducing manual intervention in layout and synthesis, and greatly improving the automation level, efficiency, and reliability of analog, RF, and millimeter-wave integrated circuit design.

[0015] The specific content of this invention unfolds through the following four implementation stages. Scheme 1 and Scheme 2 inherit each other's technical concepts, together forming a complete technical system that progressively meets users' needs at different levels. Scheme 3 is an integration and best practice of the methods proposed in Schemes 1 and 2 within the specific application context of a 'unified workspace design system'. Together, these three schemes constitute a logically rigorous and complete solution from method to application. Given the high degree of inheritance and consistency among the three schemes in their core technical principles and implementation processes, to avoid duplication, this document describes the common foundational parts of the three schemes uniformly in each implementation stage, only providing specific explanations and distinctions when addressing key differences or unique features of each scheme.

[0016] This invention consists of a layout controller, a circuit numerical solver, an MLAO optimization engine, a sample library, and a holographic model library. The execution steps are divided into a circuit standardization analysis stage, a sampling and layout control stage, a sample generation stage, and an optimization iteration stage.

[0017] The method described in this invention is applicable to a wide range of electronic design objects. Specifically, its application includes hybrid design circuits that simultaneously incorporate schematic and layout elements, as well as antenna arrays composed of multiple patch antenna elements in a specific topology or complete antenna circuits containing matching networks. This definition ensures that the method of this invention can cover the entire design spectrum from low-level integrated passive devices to high-level RF system modules.

[0018] Phase 1, Circuit Standardization Analysis Phase: Step 1 of Phase 1: Receive the input design circuit, which includes schematic and / or layout elements and their connections; simultaneously, receive the user-specified optimization variables, optimization objectives, and their upper and lower bounds. The optimization variables act on the attributes of any element in the circuit; the attributes include layout geometric attributes and schematic electrical attributes.

[0019] More preferably, in addition to schematic elements and layout elements, the design circuit may also include user-defined coupling blocks. The coupling block is characterized in that it is a local circuit unit comprised of multiple interconnected layout elements specified in the circuit.

[0020] Phase 1, Step 2: Using the components in the circuit as vertices and the electrical connection lines as edges, construct an undirected graph representing the overall topology of the circuit, and generate the corresponding undirected graph adjacency list. This establishes the first-level connection relationship. Combine this connection relationship with a predefined first feature field identifier to generate standardized component port names, which serve as the ports of the undirected graph for circuit performance analysis.

[0021] Further preferredly, for circuits with a hybrid schematic and layout design, the circuit is divided into several sub-layouts, using interconnected layout components as units. Within each sub-layout, an undirected graph is constructed with components as vertices and connecting lines as edges, generating a corresponding adjacency list and establishing a second-level connection relationship. This relationship is combined with a predefined second feature field identifier to generate standardized component port names, which serve as ports for the layout control undirected graph.

[0022] Further preferably, for coupled block elements contained in the circuit, which are composed of interconnected layout elements, an undirected graph is constructed using each element within the coupled block as a vertex and the connecting lines as edges, and an adjacency list is generated to establish a third-level connection relationship. This relationship is combined with a predefined third feature field identifier to generate standardized internal element port names, which serve as ports in the undirected graph for coupling analysis. Here, the coupled block, as a whole element, has its external ports defined by the first-level connection relationship.

[0023] The significance of this stage lies in the decoupling of the circuit analysis object from user-specific design identifiers by introducing a connection relationship analysis method based on undirected graphs. By constructing a multi-level undirected graph model and assigning standardized hierarchical names to component ports based on the node information of each layer, the three processes—circuit performance analysis, physical field coupling analysis, and layout analysis—can operate independently at their corresponding connection relationship levels without interference. Simultaneously, this standardization method ensures that the analysis process and results do not depend on any temporary, user-defined design identifiers, thus making the results of each analysis reusable at the connection relationship level.

[0024] The rationale for hierarchical analysis lies in the fact that layout, electrical performance, and coupling effects are user concerns at different levels. At the layout level, users focus on whether there are geometric conflicts between components or interconnects, a global consideration. However, at the level of electrical performance and physical coupling, especially for microwave / millimeter-wave circuits, under limited computing resources, users often adopt a local priority strategy, focusing on local circuit modules that may generate strong coupling. Therefore, this invention allows users to define any local layout circuit as a "coupled block" element for independent analysis. This method fundamentally solves a structural defect of the "unified workspace" design pattern: the difficulty in directly and efficiently analyzing and quantifying the physical coupling effects between the icons of various layout elements within the workspace.

[0025] Furthermore, as the core backend processing layer of the sample-driven design platform, this method needs to establish standardized processes in circuit analysis, layout generation, and numerical solution to generate standardized, reusable samples and models. In various design scenarios, parameters such as the name of design instances vary depending on the specific case, making it difficult to directly reuse the generated samples. This method, based on user-provided connection relationships, forms a standardized component port naming framework. Within this framework, the topology of different samples can be checked for graph isomorphism, serving as a crucial basis for determining whether circuit samples are reusable, thus providing fundamental support for the efficient reuse of circuit samples.

[0026] Phase 2, Sampling and Layout Control Phase: Step 1 of Phase 2: Random sampling is performed within the design space defined by the upper and lower bounds of the user-specified optimization variables to generate a set of parameter combinations as candidate sample features.

[0027] Phase 2, Step 2: Assign the sampled data to the corresponding optimization variables and their corresponding component attributes to obtain a circuit instance where all layout component attributes are known values.

[0028] Phase 2, Step 3: Based on the layout geometry attributes of each element, calculate and generate the layout drawing coordinate points and the coordinate point data structure of the outline graphic of the element.

[0029] Phase 2, Step 4: Based on the layout analysis of the undirected graph ports containing connection relationship information of each layout element obtained in Phase 1, Step 2, and the coordinate point data structure generated in Step 3, the coordinate points of each layout element are spliced ​​together to obtain the coordinate point data structure of the overall layout circuit, as well as the outline coordinate data structure of each element after splicing.

[0030] Phase 2, Step 5: Perform pairwise overlap determination on all component contour coordinate data structures after stitching. If the overlap area of ​​any two contour figures exceeds a preset threshold, the candidate sample feature is deemed invalid, and steps 1 to 5 are re-executed until a valid sample is collected in a layout generated based on the feature, where the overlap area between all component contours is less than the preset threshold.

[0031] Phase 2, Step 6: Repeat steps 1 to 5 above until the number of qualified samples collected reaches the specified value.

[0032] Phase 2 defensive steps: If a sample that meets the criteria cannot be obtained after a sufficient number of sampling attempts, an alarm message is sent to the user to indicate that there may be unreasonable circuit design constraints or errors in the optimization space definition.

[0033] The advantages of this stage are as follows: This invention proposes a "random sampling plus real-time filtering" method to generate samples. This method can reliably generate a sufficient number of layout samples with reasonable layout using relatively simple logic. At the same time, it constructs a framework that integrates the layout sampling space and the performance optimization space, thereby concisely and effectively solving the two traditionally separate problems of layout compliance and circuit performance optimization.

[0034] Phase 3, Sample Generation Phase: Step 1 of Phase 3: Using the layout element coordinate point data structure generated for each qualified sample in Steps 1 to 4 of Phase 2, generate layout files (such as GDSII) for each element. Subsequently, using the undirected graph ports of each element's circuit analysis (containing standardized connection information), and with the external ports of the circuit as signal excitation ports, call the numerical solver to perform performance simulation on the circuit to obtain circuit performance analysis results.

[0035] Further preferably, when coupling blocks exist in the circuit, the circuit performance analysis includes two levels: The first level (coupling block analysis): For each coupling block element, the integrated layout coordinates of the entire coupling block are calculated based on its undirected graph ports used in the coupling analysis as the electrical connection basis. Using the external ports of the coupling block as excitation ports, a numerical solver is called to perform simulation to obtain the equivalent performance model (such as an S-parameter file) of the coupling block considering the physical field coupling effect between internal components.

[0036] Second level (overall circuit analysis): The equivalent performance models of each coupled block obtained in the first level are used as "black box" components and substituted into the circuit. Then, the overall circuit simulation is performed according to the circuit analysis method based on the first-level connection relationship described in the first paragraph of step 1 of stage 3 to obtain the final circuit performance analysis results.

[0037] Phase 3, Step 2: Using the simulation result data corresponding to each sample, calculate the electrical performance index value corresponding to the optimization target input by the user, and form the sample label for that sample.

[0038] In a further preferred embodiment, the information such as the ports of the undirected graph generated in step 2 of stage 1, the attributes of each component after substituting the optimized variable values, and the simulation result file path are encapsulated together into structured sample description data and stored in the sample library.

[0039] Phase 3 Optimization Steps (Sample Loading): Phase 3 Optimization Step 1: Based on the undirected graph ports of the current circuit generated in Phase 1 Step 2, perform graph isomorphism checks on the samples in the sample library and screen out candidate samples that are isomorphic to the current circuit design topology.

[0040] Phase 3 Optimization Step 2: Compare the component attributes (static attributes) in the candidate samples obtained in Step 1 with the non-optimized attributes of the current design circuit one by one, and select samples with consistent static attributes and whose dynamic attribute (optimization parameter) values ​​fall within the upper and lower bounds of the user input optimization. These samples can be directly reused or used for initialization in this phase.

[0041] Specifically, the application method corresponding to Scheme 3 includes a method of sampling or loading layout component samples in conjunction with the current circuit layout environment: Step 1: Receive the hybrid design circuit input by the user; Step 2: Locate the sub-layout where the component to be loaded is located, and receive the sample feature data to be loaded or sampled; Step 3: Assign the sample feature data to the component to be loaded one by one, and based on the second layer connection relationship and layout analysis method, determine and filter out the sample feature data that will not cause component overlap in its sub-layout.

[0042] This phase establishes a dynamic ecosystem of sample and model libraries. This invention not only solves the problems of automatic layout and synthesis, but also constructs a complete collaborative ecosystem to improve overall design efficiency: optimization tasks drive numerical solvers to generate new data; numerical solvers add high-quality samples to the sample library; the sample library provides training data for the construction of the model library; the model library provides fast surrogate model predictions ("distilled samples") for optimization iterations, thereby accelerating optimization efficiency; simultaneously, the sample library itself can also provide a high-quality initial sample set for new optimization tasks.

[0043] Phase 4, Model Construction and Optimization Iteration Phase: Pre-definition: This invention defines an electro-holographic model group (hereinafter referred to as "holographic model", as shown in Figure 4): In the field of intelligent microwave or AI combined with radio frequency circuits, a proxy model group that meets the following characteristics: The model group can map the sample features (input variables) of a circuit to a set of basic electrical responses (such as the frequency points and component data of the S-parameter matrix); Under the preset engineering approximation conditions, based solely on the basic electrical responses output by the model group, all key performance parameters of the circuit (such as gain, isolation, group delay, etc.) can be derived through publicly available and mature circuit theories or formulas (such as network parameter conversion).

[0044] For example, taking an on-chip two-port RF filter circuit as an example, an electro-holographic model set takes the layout properties of each component of the circuit as input and outputs the real and imaginary parts of S11, S21, and S22 in a specific frequency band. Based on these predicted S-parameters, and ignoring nonlinearity and anisotropic materials, its performance indicators can be calculated using microwave network theory formulas. These indicators include all key performance parameters such as passband insertion loss, stopband rejection, and rectangularity coefficient. Therefore, this model set constitutes the electro-holographic model set for the RF filter circuit.

[0045] For Scheme 1 (Online Iterative Optimization, as shown in Figure 1): Responding to the user's deep optimization needs for analog circuit layout and synthesis, the samples generated in Stage 3 are used as the initial sample set and input into the MLAO optimization engine. This engine constructs and iteratively updates a lightweight surrogate regression model online. The optimization process uses the difference between the prediction results of this lightweight model and the optimization objective as the loss function, and uses component optimization attributes as optimization variables for iterative search. For each candidate sample feature data generated in the iteration, the core logic of the layout control sampler is first used to determine whether there is component overlap in the corresponding layout; for samples that pass the layout check, the numerical solver is used to obtain their high-fidelity sample labels, and the new sample is added to the training set to update the model. This process is iterated until a globally optimal solution that simultaneously satisfies the optimization performance indicators and has no component overlap is generated.

[0046] As a preferred embodiment of this scheme, the present invention employs a dual-model driven approach: using a sufficient number (e.g., more than 100 times the feature dimension) of samples generated in stage 3, the electro-holographic model set of the designed circuit is pre-trained and saved to a model library. During the iteration process of the aforementioned MLAO optimization engine, a reliability evaluation mechanism based on this holographic model is introduced. For each iteration candidate point, a pre-trained knowledge boundary discrimination model is first used to evaluate its reliability: for samples judged as "reliable" (within the model's knowledge boundary), the electro-holographic model is directly used for rapid prediction to generate labels; for samples judged as "unreliable" (outside the model's knowledge boundary), labels are still obtained through expensive numerical simulations. The construction method of the knowledge boundary discrimination model is as follows: Step 1: Receive the user's optimization goal; Step 2: Input the validation set sample features of the electro-holographic model into the model, and calculate the performance solution predicted by the model according to the optimization goal; Step 3: Calculate the true performance solution according to the true simulation label of the validation set sample; Step 4: Calculate the error between the solutions obtained in Step 2 and Step 3, compare the error with a preset threshold value (e.g., 5%), and generate Boolean labels (e.g., if the error is less than the threshold, it is marked as "1" to indicate reliability, otherwise it is marked as "0"); Step 5: Use the validation set sample features as input and the above Boolean labels as output to train a binary classification model (preferably a random forest model) as the knowledge boundary discrimination model of the electro-holographic model.

[0047] For Option 2 (rapid optimization, as shown in Figure 2): In response to the user's requirements for rapid optimization of analog circuit layout and synthesis: Step 1: Receive the input design circuit, the specified optimization variables and their upper and lower bounds, and the optimization target.

[0048] Step 2: Using the sufficient samples generated in Stage 3, pre-construct the electro-holographic model and store it in the model library.

[0049] Step 3: Using the distance between the prediction result of the electro-holographic model matched and loaded from the model library and the optimization target as the loss function, the component optimization attributes as the optimization parameters, and the layout legality judgment of the layout control sampler as the constraint, a one-time optimization solution is performed to quickly obtain the (approximate) optimal solution of circuit performance that satisfies the layout constraints.

[0050] Defensive steps in phase 4: When more than a set number of candidate solutions that fail the layout check are generated consecutively in a single optimization iteration, an alert is issued to the user that the design constraints may be contradictory or too tight.

[0051] Specifically, for Scheme 3, its application method also includes optimizing layout components to conform to the current layout environment; Step 1: Receive user input of the design circuit, performance indicators, optimization loss function, and component optimization attributes and their upper and lower bounds; Step 2: Find the sub-layout where the component to be optimized is located, and establish an undirected graph port for layout analysis of each component in the sub-layout; Step 3: Use the component optimization attributes as optimization variables and the optimization loss function as the objective to perform optimization solution, and obtain a set of candidate solutions; Step 4: Substitute the optimal solution into the circuit, and use the layout analysis method described in claim 10 to determine whether there is component overlap in the sub-layout; Step 5: Iteratively execute the optimization solution and layout verification steps until the optimal solution that meets the performance indicators and whose sub-layout has no component overlap is obtained.

[0052] Overall Technical Effects: 1. The core technical effect of this invention lies in the first-ever deep collaboration and synchronous completion of layout control and performance optimization, fundamentally overcoming the fundamental defect of existing EDA design platforms that cannot combine layout with circuit and component parameter optimization. Traditional EDA systems only support isolated parameter tuning driven by schematics, and their layout generation is completely detached from the optimization loop: layout splicing relies on mechanical automatic placement, which cannot perceive geometric constraints (such as DRC violations) in real time during the optimization stage, nor can it feed the layout environment back to the parameter adjustment process, causing designers to have to repeatedly iterate manually (increasing the design cycle by an average of 30%-50%).

[0053] This invention achieves the following breakthroughs by innovatively constructing a layout-performance co-optimization system based on hierarchical analysis: Complete decoupling and co-optimization of layout and performance analysis: 2. This invention establishes a comprehensive hierarchical analysis system for performance and layout through the definition of multiple component ports (first-layer performance analysis port, second-layer layout control port, and third-layer coupling analysis port). This system completely decouples the circuit analysis object from user-specific design identifiers, enabling layout compliance judgment and performance optimization to be executed in parallel and independently, yet with deep collaboration: performance analysis relies only on the first-layer connection relationship, focusing on electrical response calculation; layout control relies only on the second-layer connection relationship, focusing on geometric constraint verification (such as component overlap checking); the third-layer connection relationship serves the coupling behavior modeling of local circuit modules, supporting refined performance evaluation.

[0054] The three components are seamlessly connected through a standardized port naming framework, the analysis process does not interfere with each other, and the results are independent of specific design identifiers, thus possessing high reusability.

[0055] This mechanism completely eliminates the disconnect between "parameter optimization" and "layout generation" in existing platforms. Traditional methods require additional manual layout adjustments after optimization, while this invention deeply couples layout compliance determination during the optimization process, enabling performance optimization and conflict-free layout generation to be achieved simultaneously, without the need for post-verification.

[0056] Beyond traditional tools, this invention achieves intelligent component synthesis at the component level based on the current layout environment, significantly surpassing the limitations of general component synthesis tools. For component layout synthesis, the system can dynamically sense the real-time layout environment of the sub-layout where the component is located (such as the positions of adjacent components and interconnect topology), and directly output the optimal solution that is compatible with the surrounding layout through the constraints of the second-level layout control port (for example, when optimizing the parameters of a component, it automatically avoids local overlap and adapts to spatial constraints). For circuit layout synthesis, through the closed-loop verification of the hierarchical analysis system, the dual verification of automatic circuit performance synthesis and automatic layout is achieved simultaneously—each optimized output simultaneously meets performance indicators and layout compliance (such as zero violations in DRC), ensuring that the results are "ready to use and synthesize".

[0057] This capability upgrades the invention from a passive verification tool to an active design engine, solving the fundamental problem that existing tools cannot dynamically adapt to the layout environment at the component level.

[0058] 4. Intelligent Acceleration Mechanism to Overcome the Bottleneck of MLAO Practicality: The core bottleneck of traditional Machine Learning Assisted Optimization (MLAO) technology lies in its excessively long iteration time—it relies on expensive numerical simulations to generate sample labels, resulting in a single optimization cycle lasting several hours or even days. This invention achieves a fundamental breakthrough through an electro-holographic model and a knowledge boundary determination mechanism: the pre-constructed electro-holographic model set can directly map parameter combinations to high-fidelity electrical responses (such as S-parameter matrices), and its output can be used to derive all key performance indicators through standard circuit theory; it innovatively introduces a knowledge boundary discrimination model (such as a random forest classifier) ​​to determine in real time whether each candidate solution is within the reliable domain of the model: for candidate points within the knowledge boundary, the electro-holographic model is directly called for millisecond-level prediction, completely replacing time-consuming numerical simulations; simulation verification is triggered only for a very small number of points outside the boundary, forming an efficient closed loop of "prediction as the main method and simulation as the auxiliary method".

[0059] This mechanism significantly reduces the number of times the numerical solver must be called during optimization iterations, fundamentally solving the industry pain point that MLAO technology is difficult to put into practical use due to its high computational cost.

[0060] 5. Improved Design Efficiency and Reliability: By deeply embedding layout control into the optimization closed loop, this invention transforms layout from a time-consuming manual adjustment step into a core optimization dimension: eliminating repeated backtracking caused by layout conflicts in the traditional process (accounting for more than 40% of design time), and reducing the number of design iterations by more than 60%; through the dynamic closed loop of "optimization-layout verification-model update", it ensures that each candidate solution passes real-time layout checks, and the output results meet 100% of manufacturability requirements; the hierarchical analysis system supports the efficient reuse of samples and models, shortening the start-up time of new design tasks by 80%, which is especially suitable for complex hybrid design scenarios (such as schematic and layout mixed circuits).

[0061] In summary, this invention, for the first time in the EDA field, constructs a complete technical system for hierarchical analysis of performance and layout. Through layered decoupling and deep collaboration, it achieves simultaneous optimization of circuit parameters and generation of layout. Its core breakthrough lies in: not only supporting dual verification of circuit-level performance and layout, but also realizing component-level intelligent synthesis based on the current layout environment—dynamically adapting to local layout constraints during optimization and outputting an optimal solution seamlessly integrated with the environment. Combined with an intelligent acceleration mechanism driven by an electro-holographic model, this invention completely overcomes the efficiency bottleneck of traditional MLAO technology, enabling collaborative layout design to move from theoretical concept to engineering practice, and providing a full-stack intelligent solution from component to system for high-precision integrated circuit design. Attached Figure Description

[0062] Figure 1 is a schematic diagram of a sample-driven automatic placement and synthesis method for analog circuit layout proposed in this invention and its system.

[0063] Figure 2 is a schematic diagram of a sample-driven rapid automatic placement and synthesis method for analog circuit layout proposed in this invention and its system.

[0064] Figure 3 is a schematic diagram of the performance and layout collaborative analysis and application method of design identifier stripping based on physical field coupling perception for hybrid design circuits proposed in this invention.

[0065] Figure 4 is an example diagram of the electro-holographic model group described in this invention.

[0066] Figure 5 is an architecture diagram of a preferred embodiment of the present invention: a dual-mode driven automatic layout synthesis algorithm. Detailed Implementation

[0067] To make the objectives, technical solutions, and advantages of this invention clearer, the technical solutions in the embodiments of this invention will be clearly and completely described below in conjunction with the embodiments of this invention. Obviously, the described embodiments are only a part of the embodiments of this invention, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this invention without creative effort are within the scope of protection of this invention.

[0068] The following description is divided into two parts: the first part is the deployment of system components, and the second part is a specific implementation case.

[0069] Part 1, Component Deployment: Component 1, Undirected Graph Analyzer: This component is responsible for implementing the core functions of Phase 1 (Circuit Standardization Analysis Phase). Specifically, it includes: performing undirected graph analysis and standardizing port generation based on the components and connections of the designed circuit, providing a connection basis for subsequent layout sampling and coordinate point generation, and assisting in sub-layout partitioning.

[0070] Component 1 Function 1, Component Standardized Port Generation (as shown in Figure 3): Function 1 Step 1: Input the circuit to be analyzed, including the names of each component and other component instances connected to each port.

[0071] Function 1 Step 2: Based on the above port connection relationship, construct an undirected graph containing the original design instance symbols with the components as vertices and the connections between components as edges, and generate its adjacency list.

[0072] Function 1, Step 3: Simplify the constructed undirected graph (e.g., merge vertices with a degree greater than 2) to obtain a simplified topology. Assign a unique identifier to each node (representing a cluster of connections) in the simplified graph. Based on the application level of the connection, add a specific feature field prefix to generate standardized undirected graph port names. The connection hierarchy is divided into: Level 1: Circuit analysis undirected graph ports, with prefixes used for identification, serving circuit performance analysis, sample generation, and model feature storage.

[0073] The second layer is the undirected graph port for layout analysis. The prefix is ​​used for identification and it serves layout analysis, coordinate splicing, and sampling.

[0074] The third layer: the undirected graph port for coupling analysis, with a prefix for identification, serving the analysis of physical field coupling effects and the generation of coupled block samples.

[0075] Component 1 Function 2, Sub-layout Search: Function 2 Step 1: If there is a user-defined coupling block in the circuit, first disassemble it, replace the coupling block element with the layout element contained inside it, and at the same time keep the overall electrical connection relationship of the circuit unchanged before and after disassembly.

[0076] Function 2, Step 2: Extract all layout components from the disassembled circuit and construct an adjacency list based on their electrical connections. Perform a depth-first search (DFS) or connected component analysis algorithm on this adjacency list to find all interconnected layout component subgraphs.

[0077] Function 2 Step 3: Define each connected subgraph (i.e., a set of interconnected layout elements) as a sub-layout, which serves as the basic unit for subsequent layout analysis and control.

[0078] Component 2, Layout Control Sampler: This component is responsible for implementing the core functions of Phase 2 (Sampling and Layout Control Phase), and its goal is to generate a sufficient number of samples that ensure no geometric overlap of layout elements.

[0079] Step 1: Within the design space defined by the upper and lower bounds of the user-specified optimization variables, randomly generate a set of parameter combinations as candidate sample features.

[0080] Step 2: Input the circuit sub-layout to be processed (from component 1 function 2) and its corresponding layout analysis undirected graph port adjacency list.

[0081] Step 3: Analyze the adjacency list and extract all binary connection pairs that represent direct connections between elements and their corresponding connection ports. For example, if the adjacency list indicates that e1 is connected to e2 at port p1 and e2 is connected to e3 at port p2, then generate binary connection pairs [e1, e2] and [e2, e3] and record the corresponding ports.

[0082] Step 4: Assign the sample feature data generated in Step 1 to the optimized attributes of the corresponding components in the sub-layout to obtain a sub-layout circuit instance with complete attributes.

[0083] Step 5: Calculate and generate the layout coordinates and outline polygon data structure of each element based on the layout geometry attributes of each element.

[0084] Step 6 (Coordinate splicing): Based on the binary connection pairs and port information obtained in Step 3, perform iterative coordinate splicing: a. Calculate the movement vector: For the connection pair [e1, e2], calculate the coordinate difference between the connection port P_A of e1 and its connected port P_B of e2, and use it as the movement vector for translating e2.

[0085] b. Coordinate stitching: Translate all coordinate points of e2 according to the above-described translation vector, and then merge the translated e2 coordinates with the e1 coordinates to form a common stitched coordinate dataset of e1 and e2, denoted as agg. At this time, agg represents the overall shape after stitching e1 and e2.

[0086] c. Iteration: Treat agg as a new "element" and repeat steps a and b with the next connecting element (e.g., e3). Iterate in this way until all elements in the sub-layout are processed, and finally obtain the data structure of the overall coordinates of the entire sub-layout and the outline coordinates of all its elements.

[0087] Step 7 (Overlap Determination): Perform pairwise intersection detection on the outline polygons of all elements within the sub-layout obtained in Step 6. If the overlapping area of ​​any two outlines exceeds a preset threshold, the current sample feature is deemed invalid, the sampling fails, and the process must return to Step 1 for resampling.

[0088] Step 8: Repeat steps 1 to 7 until a specified number of qualified samples that pass the layout legality check are successfully collected.

[0089] Component 3, Numerical Solver: This component is responsible for performing high-fidelity circuit simulations, providing accurate performance labels for sample generation and iterative verification (corresponding to stage 3).

[0090] The object is a layout element (including patch antenna elements): using sample characteristic parameters as input and combining other static properties of the element, the geometric coordinate data of the element (such as GDSII file) is obtained through an automated layout generation algorithm. Combined with process documents (such as technology library, material properties), the electromagnetic simulator is driven to perform simulation under preset conditions to obtain electromagnetic response data (such as S-parameters, radiation pattern).

[0091] The target is a schematic circuit: using sample characteristic parameters as input and combining them with the static properties of components, a circuit netlist is generated. A driving circuit simulator, combined with a process device model, performs simulation to obtain circuit performance data.

[0092] For circuits composed of layout elements (such as layout circuits or antenna arrays): First, perform the simulation process described above for each layout element that makes up the circuit to obtain an electromagnetic simulation result file (such as a .snpTouchstone file) for each element. Then, use these result files as equivalent models of the corresponding elements, substitute them into a schematic netlist describing their connection relationships, and perform circuit simulation again to obtain the performance results of the entire circuit.

[0093] For circuits designed using a hybrid schematic and layout approach: First, perform an independent electromagnetic simulation for each layout element in the design to obtain its simulation result file. Then, in the circuit simulation environment, assign these .snp files to the corresponding schematic symbols and perform field-circuit co-simulation to obtain the complete circuit performance that simultaneously considers distributed effects and lumped element behavior.

[0094] Component 4, Attribute Management Module: This module is used to uniformly manage all attribute information related to the design object, and is the key to achieving accurate matching and reuse of models and samples.

[0095] Component 4 Function 1, Attribute Matching: When a user defines a design object (component or circuit), this module generates two structured messages: one describing the object's general attributes (including static and dynamic attribute names), and the other describing the simulation conditions.

[0096] Matching Process: This module works collaboratively when a candidate model or sample needs to be loaded from the library for the current design object. It compares the current object's regular attributes and simulation conditions with the attributes stored in the candidate library field by field. Matching means that the candidate entry and the current object have exactly the same static attributes and simulation conditions, and the current object's dynamic attribute set matches the attribute set marked as model input in the candidate entry.

[0097] Preferred implementation: Use a DataFrame (such as pandas.DataFrame) data structure to store attribute data, where each column represents an attribute and each row represents a sample or model record. During matching, the attributes of the current object are converted into query conditions, and filtering operations are performed on the DataFrames in the candidate database to efficiently obtain matching results.

[0098] Component 4 Function 2, Attribute Package Creation: This function works in conjunction with the undirected graph analyzer to build a unified attribute description structure for the circuit—an attribute package—for storage and loading.

[0099] The content of an attribute package is a collection of multiple sub-attribute packages with the port of the undirected graph of the component's circuit analysis as the key. Each sub-attribute package corresponds to a component and contains all the attribute names and values ​​of that component.

[0100] Example: Suppose a circuit has two components. Component 1 (inductor) has attributes {"turns": 3, "radius": 50}, and its undirected graph port is "gol1gol2"; Component 2 (capacitor) has attributes {"fingers": 40, "length": 20}, and its port is "gol2gol3". Then the attribute package of this circuit is: {"gol1gol2_turns": 3, "gol1gol2_radius": 50, "gol2gol3_fingers": 40,"gol2gol3_length": 20}.

[0101] Specifically, for attribute packages created for model storage, the values ​​corresponding to dynamic attributes that serve as input variables in the model need to be replaced with a special marker (e.g., "modelX"). This allows for quick identification of which attributes are model inputs during subsequent model loading and matching, thus enabling them to be matched with the optimization variables of the current design task.

[0102] Component 5: Holographic Model Library: This component is responsible for the construction, storage, matching, evaluation, and selection of electro-holographic model sets.

[0103] Component 5 Function 1, holographic model establishment and storage: Function 1 Step 0, Initialization: Input design circuit, specify the dynamic attribute set O as model input, simulation conditions T, and circuit sample set S for training.

[0104] Function 1 Step 1: Call the undirected graph analyzer to obtain the undirected graph ports of each component in the circuit.

[0105] Function 1 Step 2: Call the attribute management module (Component 4 Function 2), construct the standardized attribute package of the circuit based on the port information in Step 1, and save the corresponding undirected graph adjacency list file.

[0106] Function 1 Step 3, Dataset Splitting: Randomly divide the sample set S into a training set and a test set according to a predetermined ratio (e.g., 9:1).

[0107] Function 1, Step 4: Regression Model Training: Using the training set, independently train a regression model for each output variable (such as the real / imaginary part of the S-parameters) defined in the electro-holographic model group. The preferred model structure is a fully connected neural network, trained using backpropagation and the Adam optimizer. This set of models collectively constitutes an electro-holographic model group.

[0108] Function 1, Step 5: Serialization and Storage: Serialize and save the trained electro-holographic model group, the attribute package generated in Step 2 (where dynamic attribute values ​​have been replaced with "modelX" tags), the simulation conditions T, and the circuit's adjacency list file together to the model library.

[0109] Component 5 Function 2, Loading and Evaluation of Holographic Model: Function 2 Step 0: Call the undirected graph analyzer to obtain the circuit analysis undirected graph ports of each component of the current design circuit.

[0110] Function 2 Step 1: Call the attribute management module to generate the reference attribute package and reference adjacency list (UGA_ref) for the current circuit.

[0111] Function 2 Step 2: Using the matching function of the attribute management module (Component 4 Function 1), select candidate electro-holographic models that match the attributes of the current circuit from the model library.

[0112] Function 2 Step 3: Generate a set of test samples S_test using Latin hypercube sampling within the design space (within the dynamic attribute range).

[0113] Function 2 Step 4: For each candidate model, train a knowledge boundary discrimination model using its built-in validation set data (see Function 3).

[0114] Function 2, Step 5: Use the knowledge boundary discrimination model of each candidate model to predict the test set S_test and count the number of samples judged as "reliable" (within the knowledge boundary).

[0115] Function 2 Step 6: Select the candidate electro-holographic model with the largest number of reliable samples as the optimal model suitable for the current design task.

[0116] Component 5 Function 3, Knowledge Boundary Establishment: Function 3 Step 1: Receive user optimization goals.

[0117] Function 3, Step 2: Input the features of the validation set samples of the electro-holographic model into the model to obtain the model's predicted value for the optimization objective.

[0118] Function 3, Step 3: Calculate the true value of the optimization target based on the true simulation labels of the validation set samples.

[0119] Function 3, Step 4: Calculate the error between the predicted value and the true value. Compare the error with a preset threshold (e.g., 5%) and generate a Boolean label for each validation sample (e.g., error ≤ threshold = True / 1, indicating reliability).

[0120] Function 3, Step 5: Using the features of the validation set samples as input and the above Boolean labels as output, train a binary classification model (such as a random forest classifier). This model is the knowledge boundary discrimination model of the electro-holographic model.

[0121] Component 6: Sample Library Function 1, Circuit Sample Generation and Storage: Input: Dynamic variable names and upper and lower bounds of each component, static attributes, simulation conditions, and component port connection relationships of the circuit (e.g., {e1_1:e2_1,e1_2:e3_3}); Function 1 Step 1: Use the undirected graph analyzer to obtain the circuit analysis undirected graph ports of each component (Component 1 Function 1); Use the undirected graph analyzer to obtain the circuit sub-layout (Component 1 Function 2); For the circuit sub-layout, use the undirected graph analyzer to obtain the layout analysis undirected graph ports of each component (Component 1 Function 1), and for coupled block components, use the undirected graph analyzer to obtain the coupling analysis undirected graph ports of its internal components; Use the attribute management component to obtain the current circuit attribute package; Function 1 Step 2: Execute the layout analysis component Function 2 to obtain non-overlapping circuit samples; Function 1 Step 3: Circuit Sample Tag Generation: First, substitute the sampling results one by one into the current circuit to obtain N circuit samples with complete attributes; Then, for coupled blocks... The components are simulated using a numerical solver to obtain their physical field simulation results. Then, the simulation results of each layout component in the circuit are obtained one by one using the numerical solver. Furthermore, the circuit simulation results are obtained using the numerical solver with the simulation results of the coupling block and the layout components as input, and the sample labels are obtained by combining the optimization objective. Function 1 Step 4: Substitute the sampling results one by one into the current circuit to obtain circuit samples with complete attributes, and establish an attribute package (Component 4 Function 2) to obtain the circuit attribute package. Function 1 Step 5: Record the sample generation conditions. Function 1 Step 6: Refer to the component sample generation process to record the complete conditions used in the circuit simulation and associate them with the metadata of each sample. Function 1 Step 7: Serialize and store the circuit sample set: Serialize and store all sample descriptors generated in this sampling, their associated simulation data file paths, sample labels, simulation conditions, and the undirected graph adjacency list UGA of the circuit together into a complete circuit sample set circuit_SG.

[0122] Component 6 Function 2, Circuit Sample Loading Steps: Function 2 Step 0: Obtain the undirected graph ports for circuit analysis of each component in the current circuit using the undirected graph analyzer; Function 2 Step 1: Establish a circuit reference attribute package (Component 4 Function 2); Function 2 Step 2: Component attribute filtering (Component 4 Function 1): Dynamic attribute range filtering: In the sample set output in the previous step, filter out samples whose dynamic attribute values ​​completely fall within the upper and lower bounds of the user-specified dynamic variables, forming a range-compliant sample set D. This step limits the candidate samples to the design space of interest in the current design.

[0123] Function 2 Step 3: Sample generation condition filtering: Among the filtered samples above, select samples whose simulation conditions are consistent with the current design task.

[0124] Component 6 Function 3, Layout Component Sample Loading: Function 3 Step 0: Locate the sub-layout where the layout component is located, establish the second-level connection relationship through the undirected graph analyzer, and obtain the layout analysis undirected graph port; Function 3 Step 1: Establish the reference attribute of the current component through the attribute manager (Component 4 Function 2), and load the sample matching the component attribute in the sample library (Component 4 Function 1); Function 3 Step 2: Substitute the sample features output from Step 1 into the component one by one, and take its sub-layout as the input (the attribute parameters of other components in the sub-layout are fixed, only the attribute of this component is substituted), use the layout sampler to determine whether each sample overlaps (Component 2 Function 2), remove the component samples with overlap, and obtain the sample of the component suitable for the current design circuit.

[0125] Component 7: MLAO Iteration Engine: Component 7 Function 1, Optimization Iteration (as shown in Figure 5): Preparation stage: Load the holographic model of each layout element or coupling block in the circuit (if any), and receive a specified number of circuit samples as the initial sample set I.

[0126] Function 1 Step 1: Preparation stage: Input a surrogate regression model as a distillation sample to generate a model, and use its validation set to establish a temporary knowledge boundary discrimination model for the current optimization objective.

[0127] Function 1 Step 2: Quick Trial of Electro-Holographic Model: If the electro-holographic model has been loaded, it will first directly optimize the target parameters to obtain a candidate optimal solution, holo0. The layout and performance of holo0 will be verified. If it meets the target and the layout has no overlap, the optimization will end directly.

[0128] Function 1 Step 3: Lightweight and Agile Model Building: Train a Gaussian regression model (still referred to as Model A) from the initial sample set I.

[0129] Function 1 Step 4: Dual-model collaborative optimization: Using the distance between the prediction results of the electro-holographic model and Model A and the optimization target as the loss function, and the model input as the optimization variable, optimization is performed to obtain the optimal solution set {o} feature parameters of each.

[0130] Optionally, the distance is a first-order Minkowski distance (i.e., Manhattan distance).

[0131] Optionally, the optimization algorithm uses a genetic algorithm, and the multi-objective strategy uses Pareto front exploration.

[0132] Function 1 Step 5: Model Update Sampling: Sampling is performed in four cumulative ways: a. Cluster the sample features of the best solution in the iteration history, determine the cluster center and radius of the class to which the top 50% of the best samples belong, and construct a Latin hypercube sampling space based on the center and radius to generate a1 new sample features; b. Perform Latin hypercube sampling in the space formed by the upper and lower bounds of the optimization variables to generate b1 sample features; c. In the sample library, find samples with similar label shapes to the current best sample to obtain c1 sample features; d. Randomly extract d1 sample features from the Pareto front obtained by optimization; merge a1, b1, c1, and d1 to form the sample set {a} for model update sampling.

[0133] Function 1, Step 6: Perform layout verification on the samples in set {o,a}: When the optimization object is a circuit, directly call Function 2 of the layout control sampler and execute steps 2 to 8 to determine whether there is component outline overlap in its layout; when the optimization object is a component, substitute its sample features into the corresponding component, construct its sub-layout, and then call the above process to perform overlap detection. Remove all samples that cause overlap; if the remaining samples are empty, return and re-execute steps 4 and 5 until at least one valid sample is obtained, finally forming the iterative sample set {ioa}.

[0134] Function 1 Step 7: Perform knowledge boundary determination, and divide the samples into a sample set oa1 inside the knowledge boundary and a sample set oa2 outside the knowledge boundary.

[0135] For samples in oa2, the labels are obtained through numerical solver simulation; for samples in oa1, the labels are directly predicted by the electro-holographic model.

[0136] Check if there exists a solution in {o,a} that satisfies the objective. If so, output the solution and end the iteration.

[0137] Model update and optimizer dynamic modulation: merge sample sets I,o,a for retraining or incremental learning of model A.

[0138] Function 1, Step 8: Re-execute steps 4-6 using the sample set {I,o,a} and the new optimization configuration until a solution that achieves the optimization objective is found.

[0139] Component 7 Function 2, Parameter Optimization: Input: Current design circuit, surrogate regression model, optimization objective, optimization variables and their upper and lower bounds.

[0140] Function 2 Step 1: Use an undirected graph analyzer to divide the current circuit design into blocks to obtain several sub-layouts (Component 1 Function 2); use the undirected graph analyzer to obtain the layout analysis of the circuit sub-layouts and the undirected graph ports.

[0141] Function 2 Step 2: Use the difference between the prediction results of the surrogate regression model and the optimization objective as the loss function to perform optimization and obtain the optimal solution.

[0142] Function 2 Step 3: Use the layout sampler to determine whether there is layout element overlap in the optimal solution (Component 2 Function 2).

[0143] Function 2 Step 4: Repeat steps 2-3 until the optimal solution with no overlapping layout elements is obtained.

[0144] Part Two, Implementation Case: Assume the input circuit has a layout element e16, as shown in Figure 2, where e3 is a schematic element and the rest are layout elements, and e4, e5, and e6 constitute the coupling block (referred to as e456). The circuit optimization variables are v1-7, which are certain attributes acting on e1-7 respectively, and the upper and lower bound sets are ULB.

[0145] Case 1, responding to user circuit optimization iteration task, as a specific implementation of the content scheme 1 of this invention: Step 1: Receive each input item of this implementation case.

[0146] Step 2: Call the undirected graph analyzer to generate sub-layout (Component 1 Function 2): Divide (e1,e2) and (e4,e5,e6) into a sub-layout block and generate the corresponding layout control undirected graph port; call the undirected graph analyzer to obtain the circuit analysis undirected graph port of each component of the circuit (Component 1 Function 1).

[0147] Step 3: Call the undirected graph analyzer, start the component normalization port generation function, and generate the corresponding coupling analysis undirected graph ports (component 1 function 1) for the coupled blocks (e4, e5, e6).

[0148] Step 4: Call the sample library component to perform sample loading (component 6 function 2), obtain samples that match the component attributes, and denote the sample set L.

[0149] Step 5: Call the model library component to perform sample loading (component 5 function 2) and obtain an electro-holographic model with matching component attributes.

[0150] Step 6: Call the sample library component to perform sample loading (component 6 function 1) to obtain circuit samples without overlapping component diagrams, and denote the sample set G.

[0151] Step 7: Merge sample sets L and G as the initial sample set, and use the loaded electro-holographic model as the distillation sample generation model. With the input optimization objective as the goal, call the MLAO optimization engine to obtain the optimal solution for circuit layout and synthesis (Component 7 Function 1).

[0152] Case 2, responding to user circuit rapid optimization tasks, as a specific implementation of the content scheme 2 of this invention: Step 1: Receive each input item of this implementation case, call the model library, and obtain an electro-holographic model that matches the current circuit attributes.

[0153] Step 2: Initiate parameter optimization based on the model to obtain the optimal solution (Component 7 Function 2).

[0154] Case 3, responding to a user's optimization task as an application of the method of Scheme 3 of the present invention: Assume that the layout element to be optimized is e1.

[0155] Step 1: Call the sample library to load the sample for component e1 (Component 6 Function 3).

[0156] Step 2: Call the MLAO optimization engine to obtain the optimal solution for e1 applicable to the circuit (component 7 function 2).

[0157] Although embodiments of the invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the appended claims and their equivalents.

Claims

1. A sample-driven automatic placement and synthesis method and system for analog circuit layout, comprising a placement control sampler, a circuit numerical solver, and an MLAO optimization engine, characterized in that: Layout control sampler: used to acquire a specified number of circuit layout sample features without component overlap, and to verify whether the layout output by the optimizer has component overlap; Circuit numerical solver: used to simulate the circuit based on the input circuit layout sample feature data, and obtain sample labels through the simulation results; MLAO optimization engine: used to perform online iterative optimization based on a lightweight proxy model on the user-specified optimization object; wherein, the above components work together to realize the following automatic layout and synthesis process with closed-loop verification of circuit layout: S1. Receive the input design circuit, specified optimization variables and their upper and lower bounds, optimization target, and use the optimization variables to act on the layout attributes of circuit elements as optimization attributes; S2. Using the layout control sampler, obtain a specified number of samples based on the component attributes and their electrical connection relationships. This feature data ensures that there is no component overlap between each circuit layout sample; S3. Using the circuit numerical solver, based on the optimization objective, generate sample labels corresponding to each sample feature; S4. Input the generated samples as the initial sample set into the MLAO optimization engine, which constructs a lightweight surrogate regression model online, and uses the difference between the model prediction result and the optimization objective as the loss function, and uses the component optimization attributes as the optimization variables for iterative optimization; In each iteration, for the generated candidate sample feature data, the layout control sampler first determines whether there is component overlap in the corresponding circuit layout; For samples without overlap, the circuit numerical solver is called to obtain their high-fidelity sample labels, which are used to update the model and continue iterating until a global optimal solution that simultaneously meets the performance optimization index and has no component overlap is obtained.

2. The method and system according to claim 1, further comprising a model library, wherein the model library stores, manages, and constructs at least one surrogate regression model capable of predicting or deriving performance parameters of the optimized object based on the prediction results; during the optimization process, the MLAO optimization engine, in conjunction with the knowledge boundary discrimination mechanism in the model library, performs reliability determination on each candidate sample generated in each iteration: if the sample is within the reliable domain of the model, the corresponding surrogate model is directly used to predict and generate sample labels; if it is determined to be unreliable, the circuit numerical solver is called to perform simulation to obtain accurate labels.

3. The method and system according to claim 1, further comprising a sample library, wherein the sample library stores qualified samples generated in S2 of claim 1 and iterative samples generated in S3; and supports loading relevant samples according to user requests or system scheduling, with application scenarios including but not limited to: loading qualified samples from the sample library as an initial sample set before the optimization iteration begins, to replace the sample generation process described in S2 and S3 of claim 1; during the optimization process, loading historical samples within a specific interval as supplementary iterative samples according to the exploration strategy of the MLAO optimization engine, wherein the strategy includes: Perform additional Latin hypercube sampling, or sample within the neighborhood of the cluster center after performing cluster analysis based on the current optimal solution set.

4. The specific process of obtaining the feature data of the sample in the layout control sampler according to claim 1 is as follows: S41. Randomly generate a set of parameter combinations within the upper and lower bounds of the optimization variables, and substitute them into the corresponding component attributes in the design circuit to form a candidate sample feature; S42. Construct an undirected graph with components in the circuit as vertices and electrical connections as edges, and generate the corresponding adjacency list; S43. Generate the layout drawing coordinate points and contour polygon data structure of each component based on its layout geometric attributes; then, according to the connection relationships in the adjacency list obtained in S42, perform coordinate splicing in sequence to finally form the layout coordinate set of the entire circuit and the contour coordinate data structure of each component after splicing; S44. Perform pairwise overlap detection on all spliced ​​component contours. If the overlap area of ​​any two contours exceeds a preset threshold, the sample is determined to be invalid, and return to S41 for resampling; S45. Repeat steps S41 to S44 until a preset number of qualified samples without overlapping components are successfully collected.

5. The method according to claim 1, characterized in that, In step S2, when the input design circuit is a hybrid design circuit composed of schematic elements and layout elements, the layout control sampler first divides the circuit into multiple sub-layout units, each sub-layout consisting of interconnected layout elements; then, layout splicing and overlap detection are performed on each sub-layout unit. Only when there is no overlap of element outlines within all sub-layouts is the sample determined to be valid, thus completing the sample acquisition process described in S2.

6. The method according to claim 1, characterized in that, In S1, it is also supported to receive a user input of a coupling block definition instruction, which specifies a group of interconnected layout element instances in the circuit; the response is as follows: S61. While performing the element overlap determination in S2, for a group of layout elements marked as coupling blocks, a local undirected graph is constructed with these elements as vertices and their electrical connection relationships as edges, and an adjacency list is generated. S62. Based on the adjacency list, the coordinates of each element inside the coupling block are spliced ​​together to generate a complete coupling block layout coordinate structure, and the corresponding layout file is output for subsequent electromagnetic simulation to analyze the physical field coupling effect between its internal elements.

7. A sample-driven, fast automatic placement and synthesis method and system for analog circuit layout, comprising a placement control sampler, a circuit numerical solver, a model library, and an optimizer, characterized in that: Layout control sampler: used to acquire a specified number of circuit layout sample features without component overlap, and to verify whether there is component overlap in the layout output by the optimizer; Circuit numerical solver: used to simulate the circuit based on the input circuit layout sample feature data, and to obtain sample labels through the simulation results; Model library: Used to store, manage, and build at least one surrogate regression model that can predict or derive the performance parameters of an optimized object based on the prediction; Optimizer: Used to perform optimization based on the surrogate regression model and to coordinate with the layout control sampler to obtain the optimal solution for the circuit layout without component overlap; wherein, the above components work together to realize the following fast automatic layout and synthesis process for the circuit layout: S71. Receive the input design circuit, specified optimization variables and their upper and lower bounds, optimization target, and use the optimization variables to act on the layout attributes of the circuit elements as optimization attributes; S72. Utilize the layout control sampler to obtain a specified number of sample feature data based on the component attributes and their electrical connection relationships, so that each circuit layout sample is consistent with the specified design circuit. No component overlap; S73. Using the circuit numerical solver, generate sample labels corresponding to each sample feature based on the optimization objective; S74. Using the samples generated above, establish a surrogate regression model and store it in the model library; S75. Using the optimizer, take the difference between the prediction result of the surrogate regression model and the optimization objective as the loss function, take the component optimization attribute as the optimization variable, and take the judgment result of the layout control sampler on whether the candidate solution causes component overlap as a hard constraint, perform a one-time optimization solution, and finally obtain an approximate optimal solution that satisfies both the performance objective and the layout constraints.

8. The specific process of acquiring the feature data of the sample in the layout control sampler according to claim 7 is as follows: S81. Randomly generate a set of data for the component attributes affected by the optimization variables within their optimization upper and lower bounds, and input it into the design circuit; S82. For the input design circuit, form an undirected graph with its internal components as edges and connection points as points, and simplify the undirected graph to obtain an undirected graph adjacency list; S83. For the obtained circuit layout, firstly, generate the layout coordinate points and their contour polygon data structures of each component according to the layout attributes of its internal components, and then perform coordinate splicing according to the corresponding undirected graph adjacency list to form the overall layout coordinate structure and the contour coordinate data structure of each component after splicing; S84. Perform overlap determination on the spliced ​​contour coordinates. When there is component contour overlap, repeat steps S81-S83 until there is no component overlap; S85. Repeat S81 to S84 until enough non-overlapping layout circuit samples are collected.

9. According to the method of claim 7, when the input design circuit is a hybrid design circuit composed of schematic elements and layout elements, in step S72, the layout control sampler first divides the circuit into several sub-layout units, each sub-layout being composed of interconnected layout elements; and performs layout splicing and overlap detection on a unit basis for each sub-layout, and only accepts the sample as a valid sample when there are no overlapping elements inside all sub-layouts.

10. A method for performance and layout co-analysis and application of design identifier stripping based on physical field coupling awareness for hybrid design circuits, characterized in that, The method described is used for hybrid circuits that simultaneously support schematic and layout elements. It establishes and utilizes two different connection layers to determine element ports: The first layer constructs an undirected graph using elements as vertices and electrical connections as edges, generating a corresponding adjacency list. The second layer divides the circuit into sub-layouts using interconnected layout elements as basic units. Within each sub-layout, a local undirected graph is constructed using elements as vertices and electrical connections as edges, generating its own adjacency list. During circuit performance analysis, a first standardized port identifier is generated based on the first layer connection layer, serving as the basis for element port naming. Electrical connections are then established accordingly, and the circuit ports are used as excitation sources for overall circuit simulation. During layout analysis, for each sub-layout, a second standardized port identifier is generated based on the second layer connection layer, serving as the basis for coordinate splicing. This identifier is used to calculate the layout position and contour coordinates of each element, thereby generating the spliced ​​sub-circuit layout coordinates, which serve as the analysis object for element overlap detection.

11. A method for performance and layout co-analysis and application of design identifier stripping based on physical field coupling awareness for hybrid design circuits, as described in claim 10, is characterized in that... The hybrid circuit, in addition to carrying schematic and layout elements, also carries coupling block elements. Its characteristic is that it is a local circuit composed of interconnected layout elements. The ports used by the coupling block elements are analyzed using the following connection relationships: Third-level connection relationship: An undirected graph is formed with each element within the coupling block as a point and electrical connection lines as edges, resulting in an undirected graph adjacency list. The coupling block, as a whole element, has its ports determined in the first-level connection relationship in the same way as other circuit elements. Circuit performance analysis includes two levels: First-level analysis: For the analysis of each coupling block element, it is first identified by the third-level connection relationship and a fixed third feature field, forming the ports of its internal elements. The name of the coupling block is used as the basis for electrical connection. The overall layout coordinates are calculated. Then, the coupling block port is used as the excitation port. The performance simulation considering the physical field coupling effect between internal components is performed using a numerical solver to obtain the analysis or simulation results of the coupling block considering the physical field coupling effect. Second-level analysis: For the analysis of the entire circuit, based on the analysis results of the coupling block, the analysis results of the entire circuit are obtained according to the circuit analysis method described in claim 10. The circuit layout analysis has only one level: First, each coupling block is split to obtain the internally interconnected components, and the internal and external connection relationships are maintained before and after the split. Then, according to the method described in claim 10, the second-level connection relationship is found and the layout analysis is performed.

12. A method for performance and layout co-analysis and application of design identifier stripping based on physical field coupling awareness for hybrid design circuits according to claim 10, wherein the application method includes generating reusable circuit samples without component overlap: performing the following steps: S121. Receiving user input, including at least the component connection relationships and design attributes of the target design object; wherein, The design attributes are divided into dynamic attributes that can be adjusted during the design space exploration process and static attributes that remain fixed, based on design needs. The design space exploration process refers to the process in which the user is optimizing parameters, collecting design instance samples, or constructing a proxy model based on the design object. S122. Within the design space, sample the parameters corresponding to the dynamic attributes to obtain sample feature data; S123. Assign the sample feature data sequentially to the dynamic attributes of the design object, and combine it with its static attributes to construct an attribute package, and encapsulate the attribute package by component; S124. Based on the third-layer connection relationship described in claim 11, generate a layout analysis object according to the method described in claim 10, and determine whether there is component overlap, and filter out circuit sample features without component overlap; S125. Based on the first-layer connection relationship, obtain the circuit analysis result according to the method described in claim 10, and use the result to obtain the sample label corresponding to the design target; finally, obtain the circuit sample that is separated from the design identifier and has no component overlap.

13. A performance and layout collaborative analysis and application method for design identifier stripping based on physical field coupling perception for hybrid design circuits according to claim 10, the application method comprising verifying whether the circuit optimization parameters meet the target and using the layout determination result as a reusable sample: S131. Receiving user input, including at least the optimal solution parameters; S132. Substituting the optimal parameters into the circuit, generating a layout analysis object according to the method of claim 10 based on the third-layer connection relationship of the circuit as described in claim 11, and determining whether there is component overlap. If so, the layout verification fails and the process is terminated; S133. Obtaining the circuit analysis result according to the method of claim 10 based on the first-layer connection relationship of the circuit, and using the result to obtain the analysis result corresponding to the optimization target as a sample label, and then generating a sample corresponding to the optimal solution using the optimal parameters as sample features.

14. A performance and layout collaborative analysis and application method for design identifier stripping based on physical field coupling awareness for hybrid design circuits according to claim 10, wherein the application method includes sampling or loading layout component samples in combination with the current circuit layout environment: S141. Receiving the design circuit of claim 11 or claim 10 input by the user; S142. Finding the sub-layout where the component to be loaded is located, and receiving the sample feature data to be loaded or sampled; S143. Assigning the sample feature data one by one to the component to be loaded, and judging and filtering out the sample feature data that will not cause component overlap in its sub-layout based on the second layer connection relationship and layout analysis method.

15. A performance and layout collaborative analysis and application method for design identifier stripping based on physical field coupling awareness for hybrid design circuits according to claim 10, the application method comprising: optimizing layout components that conform to the current layout environment; S151. Receiving user input of the design circuit, performance indicators, optimization loss function, and component optimization attributes and their upper and lower bounds as described in claim 11 or claim 10; S152. Finding the sub-layout where the component to be optimized is located, and establishing the second-layer connection relationship as described in claim 10; S153. Using the component optimization attributes as optimization variables, the optimization loss function as the objective, and the component optimization attributes as variables, performing optimization solution to obtain a set of candidate solutions; S154. Substituting the optimal solution into the circuit, using the layout analysis method as described in claim 10, determining whether there is component overlap in the sub-layout; S155. Iteratively executing the optimization solution and layout verification steps until obtaining the optimal solution that satisfies the performance indicators and whose sub-layout has no component overlap.

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