Wafer defect analysis method and electronic equipment

Abstract

The invention relates to the technical field of industrial quality inspection, provides a wafer defect analysis method and electronic equipment, and is used for improving the wafer defect detection efficiency and precision. For a wafer whose appearance defect detection yield is lower than a preset yield threshold, mapping graphs corresponding to detection results of each core particle on the wafer are used as input of a defect segmentation model, independent defect areas of different defect types are identified, blob analysis is carried out on each defect area by using a computer vision technology, defect geometric information is obtained, and the defect geometric information is used as a defect segmentation model. According to the method, the defect geometric information of the wafer is obtained, whether the wafer has process abnormity or not is judged according to the comparison result of the defect geometric information and the defect card control parameters corresponding to the defect types, AI reasoning based on deep learning and traditional CV card control are combined, generalization of AI and accuracy of CV are fully utilized, and the defect detection precision and efficiency are improved.

Description

A wafer defect analysis method and electronic device Technical Field

[0001] This application relates to the field of industrial quality inspection technology, and provides a wafer defect analysis method and electronic device. Background Technology

[0002] Currently, in the semiconductor industry, automated optical inspection of wafers is still at the stage of "chip inspection" to "yield statistics." It primarily involves simply inspecting the appearance defects of the chips on the wafer, calculating the wafer yield, and generating a yield report for each wafer. Wafers with acceptable yield proceed to the next sorting machine for chip sorting. Wafers with unacceptable yield rely on manual analysis on the production line (the process by which engineers or technicians on the production line use a series of tools and methods to manually investigate, analyze, and locate the root cause of unacceptable yield). Wafers with process issues require further review by process engineers. These engineers determine whether a process problem exists, which process is causing the problem, and then develop, review, and implement a process optimization plan, as shown in Figure 1.

[0003] Unlike inspection scenarios where the inspection target is a single object, wafer inspection targets a 4-inch to 8-inch wafer containing a large number of chips. Each chip is an inspection object. Taking LED wafer inspection as an example, a single wafer can contain up to nearly 800,000 chips, which are arranged in rows and columns according to a set pattern. If a method of manual analysis on the production line followed by review by process engineers is used, it is difficult for the human eye to observe directly and requires the use of a high-powered microscope. Furthermore, due to the large number of objects to be inspected, this process is lengthy, requiring long hours and high concentration from manual workers, which can easily lead to visual fatigue, affecting the judgment of process issues, and resulting in very low efficiency and a reduction in the output of high-quality wafers.

[0004] Therefore, improving the accuracy and efficiency of analyzing low-yield wafer process problems has become a key technology in the wafer manufacturing process. Summary of the Invention

[0005] This application provides a wafer defect analysis method and electronic device to improve the efficiency and accuracy of wafer process problem analysis.

[0006] In a first aspect, embodiments of this application provide a wafer defect analysis method, comprising: when the wafer production yield is lower than a preset yield threshold, generating a chip defect distribution map of the wafer based on the defect detection results of each chip on the wafer, wherein different types of chips in the chip defect distribution map are distinguished by different colors; inputting the chip defect distribution map into a trained defect segmentation model to obtain at least one defect region and a defect type corresponding to each defect region; for each defect region, performing geometric analysis on the defect region using a computer vision algorithm to obtain geometric defect information of the defect region, comparing the geometric defect information with defect control parameters associated with the defect type corresponding to the defect region, and determining whether the wafer has a process abnormality based on the comparison result.

[0007] The beneficial effects of the above technical solution are as follows: For wafers with low production yield, the defect distribution map, composed of defect detection results of each chip on the wafer, first uses a defect segmentation model to identify the defect region and defect type, and then uses computer vision algorithms to perform geometric analysis on the defect region. The defect size is quantified through defect control parameters, realizing a wafer process judgment method that combines AI deep learning with traditional CV control. This leverages the advantages of AI deep learning's easy iteration and strong generalization, combined with the high accuracy and quantifiability of traditional CV control, to improve the accuracy of wafer process anomaly judgment. It achieves automated analysis from defect identification to process root cause analysis, thereby improving the efficiency of wafer process quality inspection. Furthermore, based on the analysis of the chip defect distribution map, which distinguishes different types of chips with different colors, compared to the original wafer image, it is rich in spatial distribution information of defect locations, has quantifiable and anti-interference capabilities, and the spatial distribution characteristics have high value for defect root cause analysis, thus enabling rapid traceability of defect processes.

[0008] Optionally, the defect detection result includes at least the row number, column number, and type of each chip. Based on the defect detection results of each chip on the wafer, a chip defect distribution map of the wafer is generated, including: constructing a two-dimensional image matrix with the maximum row number as the width and the maximum column number as the height, where each pixel in the two-dimensional image matrix represents a chip; setting the color value of the corresponding pixel according to the type of each chip according to a preset mapping relationship between chip type and color; and calling an image creation interface to generate the chip defect distribution map based on the color value of each pixel in the two-dimensional image matrix.

[0009] The beneficial effects of the above technical solution are as follows: by using pixels to represent core particles and using the type of core particle to set the color value of the pixels, a core particle defect distribution map that represents the spatial distribution of defect locations can be reconstructed. It has strong versatility and can be applied to process anomaly analysis scenarios for various types of wafers.

[0010] Optionally, the defect segmentation model is obtained in the following manner: wafer images from various viewpoints on the production line are acquired, and defect detection is performed on each chip image contained in each wafer image to obtain detection results. Chip defect distribution samples are generated based on the detection results, where different types of chips are distinguished by different colors. A training dataset is generated based on the chip defect distribution samples covering at least one real defect type. Each chip defect distribution sample in the training dataset is labeled with a real defect region composed of chips of the same real defect type. Multiple rounds of model training are performed based on the training dataset to obtain the defect segmentation model. Each round of training includes: extracting pixel features from multiple selected chip defect distribution samples; determining at least one predicted defect region and the predicted defect type corresponding to each predicted defect region based on the pixel features; and tuning the model parameters based on the regional differences between the predicted defect regions and the corresponding real defect regions, and the type differences between the predicted defect types and the corresponding real defect types.

[0011] The beneficial effects of the above technical solution are as follows: by obtaining the defect detection results of wafer images on the production line, core defect distribution samples covering multiple defect types are obtained, thereby constructing a training dataset for the defect segmentation model, enabling the model to learn the feature extraction capability required for defect identification from the core defect distribution samples, so as to realize defect analysis based on the core defect distribution map.

[0012] Optionally, each pixel in the core defect distribution sample corresponds to one core, and the color value of the pixel is set according to the type of the core.

[0013] The beneficial effects of the above technical solution are as follows: by using pixels to represent core particles and using the type of core particle to set the color value of the pixels, a core particle defect distribution sample that represents the spatial distribution of defect locations can be reconstructed. It has strong versatility and can be applied to process anomaly analysis scenarios of various types of wafers.

[0014] Optionally, a training dataset is generated based on the core defect distribution samples covering at least one real defect type, including: processing each core defect distribution sample with at least one image enhancement algorithm to obtain a new core defect distribution sample; and generating a training dataset based on the annotation results of the core defect distribution samples before and after image enhancement.

[0015] The beneficial effect of the above technical solution is that it improves the robustness of model training through data augmentation.

[0016] Optionally, when it is determined that there is a process abnormality in the wafer, the method further includes: displaying a pop-up reminder about the process abnormality on the system page and issuing an audible and visual alarm.

[0017] The beneficial effects of the above technical solution are: by alerting to process anomalies, the root causes of defects can be addressed in a timely manner, thereby obtaining high-quality wafers.

[0018] Secondly, embodiments of this application provide an electronic device, including a processor, a memory, and a communication interface. The communication interface, the memory, and the processor are connected via a bus. The communication interface is configured to transmit and receive data. The memory stores a computer program. The processor performs the following operations according to the computer program: when the wafer production yield is lower than a preset yield threshold, a chip defect distribution map of the wafer is generated based on the defect detection results of each chip on the wafer. Different types of chips in the chip defect distribution map are distinguished by different colors. The chip defect distribution map is input into a trained defect segmentation model to obtain at least one defect region and the defect type corresponding to each defect region. For each defect region, a computer vision algorithm is used to perform geometric analysis on the defect region to obtain geometric defect information of the defect region. The geometric defect information is compared with the defect control parameters associated with the defect type corresponding to the defect region, and the wafer is determined to have a process abnormality based on the comparison result.

[0019] Optionally, the defect detection result includes at least the row number, column number, and type of each chip. The processor generates a chip defect distribution map of the wafer based on the defect detection results of each chip on the wafer. Specifically, the process involves: constructing a two-dimensional image matrix using the maximum row number as the width and the maximum column number as the height, where each pixel in the two-dimensional image matrix represents a chip; setting the color value of the corresponding pixel according to the type of each chip based on a preset mapping relationship between chip type and color; and calling an image creation interface to generate the chip defect distribution map based on the color value of each pixel in the two-dimensional image matrix.

[0020] Optionally, the processor trains the defect segmentation model using the following operations: acquiring wafer images from various perspectives on the production line, performing defect detection on each chip image contained in each wafer image, obtaining detection results, and generating chip defect distribution samples based on the detection results, wherein different types of chips in the chip defect distribution samples are distinguished by different colors; generating a training dataset based on the chip defect distribution samples covering at least one real defect type, wherein each chip defect distribution sample in the training dataset is labeled with a real defect region composed of chips of the same real defect type; performing multiple rounds of model training based on the training dataset to obtain the defect segmentation model, wherein each round of training includes: extracting pixel features from multiple selected chip defect distribution samples, determining at least one predicted defect region and a predicted defect type corresponding to each predicted defect region based on the pixel features; and tuning the model parameters based on the regional differences between the predicted defect regions and the corresponding real defect regions, and the type differences between the predicted defect types and the corresponding real defect types.

[0021] Optionally, each pixel in the core defect distribution sample corresponds to one core, and the color value of the pixel is set according to the type of the core.

[0022] Optionally, the processor generates a training dataset based on the core defect distribution samples covering at least one real defect type. Specifically, for each core defect distribution sample, at least one image enhancement algorithm is used to process it to obtain a new core defect distribution sample; and a training dataset is generated based on the annotation results of the core defect distribution samples before and after image enhancement.

[0023] Optionally, the electronic device also includes a display screen and an alarm. When it is determined that there is a process abnormality in the wafer, the processor further executes: displaying a pop-up reminder of the process abnormality on the system page through the display screen, and using the alarm to issue an audible and visual alarm.

[0024] Thirdly, embodiments of this application provide a computer-readable storage medium storing computer-executable instructions that, when executed, can implement the steps of the above-described wafer defect analysis method.

[0025] The technical effects of any of the implementation methods in the second to third aspects can be found in the technical effects of the corresponding implementation methods in the first aspect, and will not be repeated here. Attached Figure Description

[0026] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0027] Figure 1 is a flowchart of wafer defect analysis using related technologies provided in this application embodiment; Figure 2 is an automatic wafer defect analysis system provided in this application embodiment; Figure 3 is an automatic analysis flow of the mapping inference system provided in this application embodiment; Figure 4 is a training flow of the defect segmentation model provided in this application embodiment; Figure 5 is a document example of the detection results provided in this application embodiment; Figures 6 and 7 are AOI appearance inspection systems provided in this application embodiment; Figure 8 is the mapping map reconstruction effect provided in this application embodiment; Figure 9 is a schematic diagram of the model training process provided in this application embodiment; Figure 10 is a wafer defect analysis system architecture provided in this application embodiment; Figure 11 is a flowchart of the wafer defect analysis method provided in this application embodiment; Figure 12 is a complete flow of wafer defect analysis based on mapping maps provided in this application embodiment; Figure 13 is a wafer defect analysis system architecture based on mapping map AI inference and CV combined provided in this application embodiment; Figure 14 is a structural diagram of an electronic device provided in this application embodiment. Detailed Implementation

[0028] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of this application will be clearly and completely described below with reference to the accompanying drawings of the embodiments of this application. Obviously, the described embodiments are only some embodiments of the technical solutions of this application, and not all embodiments. Based on the embodiments recorded in this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the technical solutions of this application.

[0029] Based on the exemplary embodiments shown in this application, all other embodiments obtained by those skilled in the art without inventive effort are within the scope of protection of this application. Furthermore, although the disclosures in this application are presented by way of one or more exemplary examples, it should be understood that each aspect of these disclosures can constitute a complete technical solution on its own.

[0030] It should be noted that the brief descriptions of terms in this application are only for the convenience of understanding the embodiments described below, and are not intended to limit the embodiments of this application. Unless otherwise stated, these terms should be understood in their ordinary and common meaning.

[0031] The terms "first," "second," etc., used in the specification, claims, and accompanying drawings of this application are used to distinguish similar or related products or entities and do not necessarily imply a specific order or sequence, unless otherwise indicated. It should be understood that such terms can be used interchangeably where appropriate, for example, in situations where implementation can proceed in a sequence other than those given in the embodiments illustrated or described in this application.

[0032] Furthermore, the terms “comprising” and “having”, and any variations thereof, are intended to cover but not exclusively include, for example, a product or device that includes a series of components is not necessarily limited to those that are explicitly listed, but may include other components that are not explicitly listed or that are inherent to such product or device.

[0033] Currently, AOI wafer inspection technology on the market is still at the stage of "chip inspection" -> "yield statistics". In particular, the localization of process problems still relies on manual methods to determine whether there is a problem in the process and which process is problematic, based on defect statistical analysis and physical visual inspection. This requires process personnel to perform long hours of visual labor with high concentration, which can easily lead to visual fatigue, affect the judgment of process anomalies, and has very low efficiency, affecting the production quality and efficiency of wafers.

[0034] The following is an explanation of the terms used in the embodiments of this application.

[0035] Core defect distribution map: also known as a mapping map, it uses different colors to represent different types of cores and is an image that can characterize the spatial distribution characteristics of defect locations.

[0036] Core defect distribution sample: an image using the core defect distribution map as a sample.

[0037] In view of this, this application provides a wafer defect analysis method. Using a chip defect distribution map as input, it automatically identifies defect regions of different defect types through a deep learning-based defect segmentation model. Then, it employs traditional computer vision (CV) technology to perform blob analysis on the defect regions, extracting geometric information such as area, shape, and connectivity. This information is then combined with control parameters set for the defect type to determine process problems. Because this method combines AI inference with traditional CV control, it leverages the advantages of AI deep learning's ease of iteration and strong generalization with the high accuracy and quantifiability of traditional CV control. This improves the intelligence and reliability of wafer quality analysis, enabling high-precision and interpretable rapid process problem localization.

[0038] Figure 2 illustrates an automated wafer defect analysis system provided in this embodiment of the application. It mainly comprises five parts: an AI algorithm server, a data server, an AOI (Analog and Inspection Institute) system, a Mapping inference system, and a Manufacturing Execution System (MSE). The AI ​​algorithm server serves as the computing power foundation of the entire system, used for training and publishing models (including models in the AOI system and the Mapping inference system). The data server manages model storage, stores production data, and provides training data to the AI ​​algorithm server. The AOI system performs appearance defect detection on images of wafers on the production line, generating production data (such as reports and work files) to provide input data for the Mapping inference system. The Mapping inference system infers from the mapping map (which can be directly output by the AOI system or reconstructed based on the production data from the AOI system) to identify process anomalies. The MSE system, as a production information management system for wafer production lines, enables early detection, precise location, and quantitative monitoring of defects during the production process.

[0039] In the above system architecture, the Mapping inference system, as the main content of this application embodiment, is a key part for realizing automatic wafer defect analysis. As shown in Figure 3, this part, for wafers with unqualified yield, inputs the chip defect distribution map obtained by AOI wafer appearance defect detection into a deep learning-based defect segmentation model, outputs defect regions of different defect types, and then uses computer vision technology to extract geometric information such as area, shape, and connectivity of the defect regions. After comparing with the control parameters of the defect type, it automatically determines whether the wafer has an anomaly. For anomalies caused by process problems, the wafer enters the next sorting machine process for chip sorting, and completes the process optimization plan formulation, process optimization plan review, and implementation based on the process problems. For anomalies caused by imaging problems, the wafer is re-inspected.

[0040] Experimental tests have shown that this system can help production lines quickly locate process problems and issue alarms, improving detection efficiency by more than three times compared to manual methods and saving production lines 50% of manpower.

[0041] In the mapping inference system, the defect distribution map of the core particles, which is represented by different colors for different types of core particles, is rich in spatial distribution information of defect locations compared with the original wafer image. It is quantifiable, anti-interference, and the spatial distribution features are of high value for root cause analysis of defects. Therefore, using it as input to the defect segmentation model helps to achieve rapid traceability of defect processes.

[0042] The training process of the defect segmentation model in the Mapping inference system is described in detail below.

[0043] As shown in Figure 4, the training process of the defect segmentation model provided in this application embodiment mainly includes the following steps: S401: Obtain wafer images from various perspectives on the production line, and perform defect detection on each chip image contained in each wafer image to obtain the detection results.

[0044] Typically, multiple cameras are used on the production line to capture wafer images of the same wafer from different perspectives. Each wafer image contains multiple chips, which are the objects to be inspected. Therefore, it is necessary to perform target inspection on the wafer images, crop out the chip images of each chip based on the target inspection results, perform defect inspection on each chip image, and then stitch the inspected chip images together to obtain the inspection results of all chips.

[0045] In some embodiments, the wafer inspection results can be presented through an initial mapping diagram, in which the dies at different locations are represented by rectangles. To distinguish different types of dies, each type of rectangle can be represented by a unique color.

[0046] In some embodiments, the wafer inspection results can also be output in report or job file format (including but not limited to csv, txt, excel, etc.). The report or job file stores key information in the inspection results, including the location (row number and column number on the wafer) and type of the chip. Different types of chips can be represented by different numbers.

[0047] In some embodiments, the core particle type can be divided into two types: OK and NG, or into multiple types such as OK, Defect 1, Defect 2, etc. Multi-classification allows for more detailed identification of process anomalies, and compared to binary classification, AI has stronger generalization and recognition capabilities after learning.

[0048] Taking multi-class classification as an example, as shown in Figure 5, this is the work file of the detection results. Each row in the work file corresponds to a core. The PosX and PosY columns in the work file represent the row number and column number of the core in the global coordinates of the wafer, respectively. The Bin column represents the type of core. Different values ​​represent different types, such as 148 for qualified and 150 for dirty.

[0049] In some embodiments, the wafer inspection results can be implemented using an AOI appearance inspection system based on traditional computer vision technology, as shown in Figure 6. Alternatively, they can be implemented using an AOI appearance inspection system based on computer vision technology and AI deep learning, as shown in Figure 7. This part of the inspection is not the focus of this application embodiment and will not be described in detail here.

[0050] S402: Generate a core defect distribution sample based on the test results. Different types of core particles in the core defect distribution sample are distinguished by different colors.

[0051] For wafers with a yield rate lower than a preset yield threshold, a chip defect distribution sample can be generated based on the detection results. The yield threshold can be set according to actual needs, such as 80% or 90%. This application does not impose limiting requirements. In some embodiments, when the initial mapping image data volume in the detection results is small and the image is uncompressed, the initial mapping image can be directly used as the chip defect distribution sample for training the defect segmentation model.

[0052] In some embodiments, a new mapping image can be reconstructed based on a preset unified rule using reports or job files from the detection results, and this new mapping image can be used as a core defect distribution sample for training the defect segmentation model. The reconstruction process does not require the transmission of images (such as in BMB format), and since the core defect distribution sample is reconstructed using a unified rule, the quality of the reconstructed mapping image is controllable and applicable to wafers with different model rules.

[0053] In some embodiments, the mapping map reconstruction process is as follows:

[0054] 1. Parse the work file of the test results to obtain the maximum row number and maximum column number of each chip on the wafer.

[0055] 2. Construct a two-dimensional image matrix using the maximum row number as the width and the maximum column number as the height.

[0056] In this two-dimensional image matrix, each pixel represents a core particle.

[0057] 3. Based on the preset mapping relationship between pixel type and color, set the color value of the corresponding pixel according to the type of each pixel.

[0058] The mapping relationship between core type and color can be preset according to actual needs, and the color corresponding to each type is unique.

[0059] For example, 150 represents a defect type of dirt, indicated by red “#ff0000”, while 151 represents a defect type of scratch, indicated by purple “#ff00ff”.

[0060] By querying the mapping relationship between core type and color, the color value of the corresponding pixel can be set according to the type of each core in the job file. For example, the pixel corresponding to core type 151 is set to #ff00ff.

[0061] 4. Call the image creation interface to generate core defect distribution samples based on the color value of each pixel in the two-dimensional image matrix.

[0062] After constructing the two-dimensional image matrix, the OpenCV image creation interface cv:mat is called to reconstruct the two-dimensional image matrix and output a mapping image representing the spatial distribution characteristics of the defect location. This mapping image is then used as a sample of the core defect distribution.

[0063] Figure 8 shows the effect of the reconstructed mapping image. In the job file, each row represents a core particle, which is represented by a pixel. The color of the pixel depends on the type detected in the core particle image.

[0064] It should be noted that, whether it is the initial mapping map or the reconstructed mapping map used as core defect distribution samples for model training, since different types of core particles are represented by different colors, both of these mapping maps can represent the spatial distribution characteristics of defect locations and can be used to determine process anomalies.

[0065] S403: Generate a training dataset based on the core defect distribution samples covering at least one real defect type.

[0066] In real-world scenarios, a batch of chip defect distribution samples with low yield and process anomalies can be collected from the wafer production line. These process anomalies need to cover some common defect types (referred to as real defect types to distinguish them from subsequent model outputs), including but not limited to focal length anomalies, ITO over-etching, offset cutting, and stage contamination.

[0067] In some embodiments, the defect types of the collected core defect distribution samples cover more than 80% of the production line, and the data volume of each defect type is 100+, in order to ensure balanced data distribution, prevent overfitting, and ensure the generalization ability of the model.

[0068] In some embodiments, after collecting all core defect distribution samples, the real defect regions composed of cores of the same real defect type in each core defect distribution sample are labeled to obtain the training dataset of the defect segmentation model.

[0069] In some embodiments, during the construction of the training dataset, image enhancement processing can be performed on the core defect distribution samples to improve the robustness of model training. Specifically, for each core defect distribution sample, at least one image enhancement algorithm is used to process it to obtain a new core defect distribution sample. Based on the annotation results of the core defect distribution samples before and after image enhancement, a training dataset is generated.

[0070] In some embodiments, during the process of accurately training the dataset, a validation dataset may also be prepared to test the performance of the trained model.

[0071] The ratio of the training dataset to the validation dataset can be determined based on the actual data collection situation. This application embodiment does not impose any limiting requirements. For example, the ratio of the validation dataset to the training dataset can be set to 2:8.

[0072] S404: Perform multiple rounds of model training based on the training dataset to obtain a defect segmentation model.

[0073] Each training round includes: S4041: Extracting pixel features from multiple selected core defect distribution samples, and determining at least one predicted defect region and the predicted defect type corresponding to each predicted defect region based on the pixel features.

[0074] In the core defect distribution sample, the color of each pixel can reflect the type of core. Therefore, by using pixel features (including color features, position features, etc.), at least one predicted defect region and the predicted defect type corresponding to each predicted defect region can be determined.

[0075] When the core defect distribution sample is a reconstructed mapping image, the predicted defect region is an independent region that only represents the pixel category.

[0076] S4042: Model parameter tuning is performed based on the regional differences between the predicted defect region and the corresponding real defect region, and the type differences between the predicted defect type and the corresponding real defect type.

[0077] In each training round, the core defect distribution samples are labeled with real defect regions and real defect types. After model processing, predicted defect regions and predicted defect types are also output. Therefore, the loss calculated by the model should include the regional differences between the predicted defect regions and the corresponding real defect regions, as well as the type differences between the predicted defect types and the corresponding real defect types. In this way, the model parameters can be optimized after backpropagation through the gradient of the loss.

[0078] In some embodiments, during model training, a graphics processing unit (GPU) cluster can be invoked on the AI ​​algorithm server for processing, thereby making full use of the GPU's image processing performance to improve the training speed of the model.

[0079] During the training of the defect segmentation model, the defect detection results of wafer images on the production line are used to obtain core defect distribution samples covering multiple defect types, thereby constructing the training dataset of the defect segmentation model. This enables the model to learn the feature extraction capability required for defect identification from the core defect distribution samples, so as to realize inference based on mapping graphs.

[0080] In some embodiments, after the model is trained, it is tested using a validation dataset, and the model is released and deployed after passing the test.

[0081] In practical applications, when new process problems arise or the model's recognition accuracy needs to be improved, the model's generalization ability and accuracy can be continuously enhanced by supplementing the training data corresponding to the new process problems.

[0082] Taking the reconstructed mapping map as training data as an example, see Figure 9 for the overall process of model training. Alternatively, the initial mapping map directly output from the detection results can be used to construct the training dataset.

[0083] In some embodiments, the present application does not impose restrictive requirements on the deep learning algorithm used in the defect segmentation model. For example, the YOLO-Seg instance segmentation network structure can be used to construct the defect segmentation model, the Mask R-CNN network can be used to construct the defect segmentation model, or a self-developed lightweight CNN network can be used to construct the defect segmentation model.

[0084] Based on a trained defect segmentation model, this application provides a wafer defect analysis system architecture, as shown in Figure 10. It mainly includes two parts: an AOI detection system and a mapping inference system. The AOI detection system is used to perform appearance inspection based on wafer images and output the wafer defect detection results. The defect detection results can be an initial mapping image or a document recording the position and type of the chips on the wafer. The mapping inference system takes the output of the AOI inspection system as input. When the output is an initial mapping map, it is used as the wafer's core defect distribution map. When the output is a document of the inspection results, the document is parsed, and a new mapping map is reconstructed based on the parsing results. This new mapping map is then used as the wafer's core defect distribution map. Furthermore, for the core defect distribution map, a defect segmentation model is used for mapping inference to identify different types of defect regions and defect types. An independent defect instance mask is output for each defect region. Then, traditional computer vision technology is used to perform blob analysis on each defect region, calculating geometric defect information such as area, shape, aspect ratio, connectivity, and spatial distribution. Based on the control parameters corresponding to each defect type, the geometric defect information is judged for anomaly type. The final judgment result is presented on the page, and warnings are issued when process problems are found.

[0085] Referring to Figure 11, the flowchart of the wafer defect analysis method provided in the embodiment of this application mainly includes the following steps: S1101: When the wafer production yield is lower than the preset yield threshold, a wafer core defect distribution map is generated based on the defect detection results of each core on the wafer.

[0086] In the core defect distribution map, different types of core particles are distinguished by different colors. The core defect distribution map can be the initial mapping map directly output by wafer inspection, or it can be the mapping map reconstructed based on the inspection document.

[0087] In some embodiments, the defect detection results of the wafer include at least the row number, column number and type of each core. The reconstruction process of the core defect distribution map is as follows: 1. Establish the mapping relationship between core type and color.

[0088] Different core types are uniquely identified by different numbers, and different numbers correspond to different colors.

[0089] 2. Construct a two-dimensional image matrix using the maximum row number as the width and the maximum column number as the height.

[0090] In this two-dimensional image matrix, each pixel represents a core particle.

[0091] 3. Based on the preset mapping relationship between pixel type and color, set the color value of the corresponding pixel according to the type of each pixel.

[0092] 4. Call the image creation interface to generate a core defect distribution map based on the color value of each pixel in the two-dimensional image matrix.

[0093] During the mapping reconstruction process, a unified rule is used to reconstruct a core defect distribution map that represents the spatial distribution of defect locations by using pixels to represent core particles and setting color values ​​for pixels based on the type of core particle. Compared to the initial mapping map, this method is more versatile and applicable to process anomaly analysis scenarios for various types of wafers.

[0094] S1102: Input the core defect distribution map into the trained defect segmentation model to obtain at least one defect region in the core defect distribution map and the defect type corresponding to each defect region.

[0095] The defect segmentation model is used to extract features from the input core defect distribution map. Based on the extracted pixel features (including color and position, etc.), the predicted defect regions of different predicted defect types are identified.

[0096] S1103: For each defect area, a computer vision algorithm is used to perform geometric analysis on the defect area to obtain the geometric defect information of the defect area. The geometric defect information is compared with the defect control parameters associated with the defect type corresponding to the defect area, and the wafer is determined to have process abnormalities based on the comparison results.

[0097] Computer vision technology is used to perform blob analysis on each defect region to calculate geometric defect information such as area, shape, aspect ratio, connectivity, and spatial distribution of each defect region. Different defect types have different criteria for judging process problems. Therefore, different defect types are set with defect control parameters that meet the defect criteria. By comparing the extracted defect geometric information with the corresponding defect control parameters, potential process anomalies, such as process problems and imaging problems, can be identified.

[0098] In some embodiments, defect control parameters include, but are not limited to: area control operator, length control operator, shape control operator, aspect ratio control operator, etc.

[0099] Taking the red area (bin=151-scratches) as an example, when the defect area meets all of the following conditions, it is determined that there is a process problem of the type of "large area-long strip scratch", which is a process abnormality: a. The area of ​​the defect area accounts for more than 1 / 10 of the wafer area; b. The shape of the defect area tends to be long strip; c. The aspect ratio of the defect area is greater than 10.

[0100] In some embodiments, when a process abnormality is detected, a pop-up notification about the abnormality is displayed on the system interface, along with an audible and visual alarm. This allows production line personnel to directly view the core defect distribution map and the assessment results after seeing or hearing the warning, enabling them to quickly and accurately locate the process abnormality without manual analysis.

[0101] In some embodiments, production line personnel may adopt different handling methods depending on the cause of the process abnormality.

[0102] For example, process problems that can be handled on-site (such as abnormal camera focal length) can be resolved immediately on-site. For some complex process problems (such as dirt caused by byproducts in photolithography and etching), it is necessary to conduct quality analysis and formulate corresponding process optimization solutions.

[0103] For wafers with low production yields, a chip defect distribution map, composed of defect detection results for each chip on the wafer, is constructed. First, a defect segmentation model is used to identify defect regions and types. Then, computer vision algorithms are employed to perform geometric analysis on the defect regions. Defect size is quantified using defect control parameters. This approach combines AI deep learning with traditional CV control for wafer process judgment. It leverages the advantages of AI deep learning's ease of iteration and strong generalization with the high accuracy and quantifiability of traditional CV control to improve the accuracy of wafer process anomaly detection. This automates the analysis from defect identification to root cause analysis, thereby increasing the efficiency of wafer process quality inspection. Furthermore, analysis of the chip defect distribution map, which uses different colors to distinguish different types of chips, provides richer spatial distribution information on defect locations compared to the original wafer image. This information is quantifiable, anti-interference, and the spatial distribution characteristics are highly valuable for root cause analysis of defects, enabling rapid traceability of defective processes.

[0104] Referring to Figure 12, the complete process of wafer defect analysis mainly includes the following steps: S1: Acquire wafer images of the same wafer from different perspectives.

[0105] S2: Perform target detection on the wafer image, identify individual core images, and perform defect detection on the core images.

[0106] S3: Use the initial mapping map of defect detection as the core defect distribution map.

[0107] S4: Parse the document, assign each core particle to a pixel, and set color values ​​for the corresponding pixels according to the type of core particle to generate a core particle defect distribution map.

[0108] S5: Input the core defect distribution map into the defect segmentation model to segment out independent defect regions of different defect types.

[0109] S6: Use computer vision technology to perform blob analysis on each defect area to obtain the defect geometric information of the defect area.

[0110] S7: Compare the defect geometry information with the defect control parameters associated with the defect type.

[0111] S8: Determine whether there are any process abnormalities in the wafer based on the comparison results.

[0112] The wafer defect analysis method of this application combines deep learning-based AI inference with traditional computer vision technology, effectively improving the efficiency and accuracy of wafer defect analysis. Figure 13 shows the system architecture for a judgment system combining mapping-based AI inference and computer vision. This system can adopt a one-to-many distributed architecture, where one mapping inference system can be associated with multiple AOI appearance inspection systems. In the entire system architecture, both the mapping inference system and the AOI appearance inspection system can provide training and optimization data to the AI ​​algorithm server. The mapping inference system provides the mapping image, and the AOI appearance inspection system provides the image of the missed chip. The AI ​​algorithm server uses the collected data to train and optimize the model, and then publishes the model to the data server. The data server manages the model version and distributes it to the AOI appearance inspection system and the mapping inference system. During the AOI appearance inspection process, the AI ​​model is called to inspect the core image to be inspected, and the inspection result document is sent to the data server for data storage and management. At the same time, the document with a yield of less than 80% is sent to the mapping inference system. The mapping inference system completes the reconstruction and inference of the mapping map, outputs the process anomaly judgment result, and issues anomaly warning when a process anomaly exists.

[0113] Those skilled in the art will understand that various aspects of this application can be implemented as a system, method, or program product. Therefore, various aspects of this application can be specifically implemented in the following forms: a completely hardware implementation, a completely software implementation (including firmware, microcode, etc.), or a combination of hardware and software implementations, collectively referred to herein as a "circuit," "module," or "system."

[0114] Based on the same technical concept, this application provides an electronic device, which can be a terminal device (such as a computer or testing device) or a server, capable of implementing the steps of the above-described wafer defect analysis method and achieving the same technical effect.

[0115] Referring to Figure 14, the electronic device includes a processor 1401, a memory 1402, and a communication interface 1403. The communication interface 1403, the memory 1402, and the processor 1401 are connected via a bus 1404. The communication interface 1403 is used to send and receive data. The memory 1402 stores a computer program, and the processor 1401 executes the steps of the above-mentioned wafer defect analysis method according to the computer program.

[0116] It should be noted that Figure 14 is only an example, and the electronic device may also include conventional components such as memory, power supply, buttons, display screen, and alarm.

[0117] In this embodiment, the memory may primarily include a program storage area and a data storage area. The program storage area may store the operating system and programs required for running instant messaging functions; the data storage area may store various instant messaging information and operation instruction sets. The memory may be volatile memory, such as random-access memory (RAM); it may also be non-volatile memory, such as read-only memory, flash memory, hard disk drive (HDD), or solid-state drive (SSD); or it may be any other medium capable of carrying or storing a desired computer program having an instruction or data structure form and accessible by a computer, but is not limited thereto. The memory may be a combination of the above-mentioned memories. The processor may include one or more central processing units (CPUs), GPUs, or digital processing units, etc.

[0118] This application does not limit the specific connection medium between the communication interface, memory, and processor. In this application, the bus between the communication, memory, and processor is depicted with a thick line in the figure. The connection methods between other components are only for illustrative purposes and are not intended to be limiting. The bus can be divided into address bus, data bus, control bus, etc. For ease of description, only one thick line is used to describe it in the figure, but it does not mean that there is only one bus or one type of bus.

[0119] This application also provides a computer-readable storage medium for storing instructions that, when executed, can perform the steps of any of the wafer defect analysis methods described in the foregoing embodiments.

[0120] This application also provides a computer program product for storing a computer program that performs the steps of any of the wafer defect analysis methods described in the foregoing embodiments.

[0121] Those skilled in the art will understand that embodiments of this application can be provided as methods, systems, or computer program products. Therefore, this application can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, this application can take the form of a computer program product embodied on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0122] This application is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to this application. It should be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in one or more blocks of the flowchart illustrations and / or one or more blocks of the block diagrams.

[0123] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means that implement the functions specified in one or more flowcharts and / or one or more block diagrams.

[0124] These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer-implemented process, such that the instructions, which execute on the computer or other programmable apparatus, provide steps for implementing the functions specified in one or more flowcharts and / or one or more block diagrams.

[0125] Obviously, those skilled in the art can make various modifications and variations to this application without departing from the spirit and scope of this application. Therefore, if such modifications and variations fall within the scope of the claims of this application and their equivalents, this application also intends to include such modifications and variations.

Claims

1. A method for analyzing wafer defects, characterized in that, include: When the wafer production yield is lower than a preset yield threshold, a chip defect distribution map of the wafer is generated based on the defect detection results of each chip on the wafer. Different types of chips in the chip defect distribution map are distinguished by different colors. The chip defect distribution map is input into a trained defect segmentation model to obtain at least one defect region and the defect type corresponding to each defect region. For each defect region, a computer vision algorithm is used to perform geometric analysis on the defect region to obtain the geometric defect information of the defect region. The geometric defect information is compared with the defect control parameters associated with the defect type corresponding to the defect region, and the wafer is determined to have a process abnormality based on the comparison result.

2. The method as described in claim 1, characterized in that, The defect detection results include at least the row number, column number, and type of each chip. Based on the defect detection results of each chip on the wafer, a chip defect distribution map of the wafer is generated, including: constructing a two-dimensional image matrix with the maximum row number as the width and the maximum column number as the height, where each pixel in the two-dimensional image matrix represents a chip; setting the color value of the corresponding pixel according to the type of each chip according to a preset mapping relationship between chip type and color; and calling an image creation interface to generate the chip defect distribution map based on the color value of each pixel in the two-dimensional image matrix.

3. The method as described in claim 1, characterized in that, The defect segmentation model is obtained in the following way: wafer images from various perspectives on the production line are acquired, and defect detection is performed on each chip image contained in each wafer image to obtain detection results. Based on the detection results, chip defect distribution samples are generated, in which different types of chips are distinguished by different colors. Based on the chip defect distribution samples covering at least one real defect type, a training dataset is generated, in which each chip defect distribution sample in the training dataset is labeled with a real defect region composed of chips of the same real defect type. Multiple rounds of model training are performed based on the training dataset to obtain a defect segmentation model. Each round of training includes: extracting pixel features from multiple selected core defect distribution samples; determining at least one predicted defect region and the predicted defect type corresponding to each predicted defect region based on the pixel features; and tuning the model parameters based on the regional differences between the predicted defect regions and the corresponding real defect regions, as well as the type differences between the predicted defect types and the corresponding real defect types.

4. The method as described in claim 3, characterized in that, In the core defect distribution sample, each pixel corresponds to one core, and the color value of the pixel is set according to the type of the core.

5. The method as described in claim 3, characterized in that, A training dataset is generated based on core defect distribution samples covering at least one real defect type. This includes: processing each core defect distribution sample using at least one image enhancement algorithm to obtain new core defect distribution samples; and generating the training dataset based on the annotation results of the core defect distribution samples before and after image enhancement.

6. The method according to any one of claims 1-5, characterized in that, When it is determined that there is a process abnormality in the wafer, the method further includes: displaying a pop-up reminder of the process abnormality on the system page and issuing an audible and visual alarm.

7. An electronic device, characterized in that, The system includes a processor, a memory, and a communication interface, which are connected via a bus. The communication interface is configured to transmit and receive data. The memory stores a computer program, and the processor performs the following operations according to the computer program: when the wafer production yield is lower than a preset yield threshold, a chip defect distribution map of the wafer is generated based on the defect detection results of each chip on the wafer, wherein different types of chips in the chip defect distribution map are distinguished by different colors; the chip defect distribution map is input into a trained defect segmentation model to obtain at least one defect region and the defect type corresponding to each defect region; for each defect region, a computer vision algorithm is used to perform geometric analysis on the defect region to obtain geometric defect information of the defect region; the geometric defect information is compared with the defect control parameters associated with the defect type corresponding to the defect region, and the wafer is determined to have a process abnormality based on the comparison result.

8. The electronic device as claimed in claim 7, characterized in that, The defect detection results include at least the row number, column number, and type of each chip. The processor generates a chip defect distribution map of the wafer based on the defect detection results of each chip on the wafer. Specifically, the process involves: constructing a two-dimensional image matrix using the maximum row number as the width and the maximum column number as the height, where each pixel in the two-dimensional image matrix represents a chip; setting the color value of the corresponding pixel according to the type of each chip based on a preset mapping relationship between chip type and color; and calling the image creation interface to generate the chip defect distribution map based on the color value of each pixel in the two-dimensional image matrix.

9. The electronic device as claimed in claim 7, characterized in that, The processor trains the defect segmentation model using the following operations: acquiring wafer images from various perspectives on the production line, performing defect detection on each chip image contained in each wafer image, obtaining detection results, and generating chip defect distribution samples based on the detection results, wherein different types of chips in the chip defect distribution samples are distinguished by different colors; generating a training dataset based on the chip defect distribution samples covering at least one real defect type, wherein each chip defect distribution sample in the training dataset is labeled with a real defect region composed of chips of the same real defect type; Multiple rounds of model training are performed based on the training dataset to obtain a defect segmentation model. Each round of training includes: extracting pixel features from multiple selected core defect distribution samples; determining at least one predicted defect region and the predicted defect type corresponding to each predicted defect region based on the pixel features; and tuning the model parameters based on the regional differences between the predicted defect regions and the corresponding real defect regions, as well as the type differences between the predicted defect types and the corresponding real defect types.

10. The electronic device as claimed in claim 9, characterized in that, In the core defect distribution sample, each pixel corresponds to one core, and the color value of the pixel is set according to the type of the core.

Images