Chip image registration method, device and equipment
By obtaining the preset and actual overlap rates of the chip image, the overlapping area of the chip image is accurately determined, which solves the problems of computational redundancy and information loss caused by improper overlap rate settings in the prior art, and improves the accuracy and reliability of chip image registration.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- SHENZHEN LIXIN SEMICON CO LTD
- Filing Date
- 2025-12-31
- Publication Date
- 2026-05-01
AI Technical Summary
In the existing technology, the overlap rate setting in the chip image registration process relies on manual experience or a fixed value, which can lead to an overlap rate that is too large or too small, affecting the accuracy, efficiency and reliability of image registration.
By obtaining a preset overlap rate, the preset overlap region of adjacent chip images is calculated, and the actual overlap rate is obtained based on the matching similarity within the preset overlap region. The actual overlap rate is then used to register the adjacent chip images.
It accurately determines the size of the overlapping area during the registration process, avoiding increased computation and information loss caused by improper overlapping area settings, thus improving the efficiency and reliability of registration.
Smart Images
Figure CN121962653A_ABST
Abstract
Description
Chip image registration methods, apparatus and equipment Technical Field
[0001] This application relates to the field of image processing technology, and in particular to chip image registration methods, apparatus and devices. Background Technology
[0002] In the field of electronic design automation (EDA) for chip analysis, chip image registration is a crucial step. It involves precisely aligning and matching chip images from different sources, perspectives, or time points to ensure the accuracy and consistency of subsequent design, analysis, and manufacturing processes. In practical applications, chip image registration faces numerous challenges and pain points. Microscopic chip images are typically captured in fixed steps, so we generally assume that the overlap of the obtained chip images is almost uniform. However, due to external factors, the overlap rate between adjacent rows or columns of chip images may be inconsistent. Therefore, it is necessary to specifically determine the overlap rate of two chip images in adjacent rows or columns to ensure that overlapping areas can be found quickly and accurately.
[0003] Currently, in practice, the overlapping areas of adjacent chip images are often estimated manually to set the corresponding overlap rate, or a specific value is provided directly by the system. However, these methods rely on the experience of the person assembling the image or the machine, lacking accuracy and failing to ensure that the overlap rate is optimal each time. When the overlap rate is set too high, it significantly increases the redundant computation during image registration, leading to longer processing time and reduced overall efficiency. Conversely, when the overlap rate is set too low, it may fail to completely cover the effective information areas between adjacent images, resulting in missing image information and affecting the accuracy and reliability of the registration results. This fails to meet the high-precision and high-efficiency image registration requirements of modern chip manufacturing.
[0004] The above content is only used to help understand the technical solution of this application and does not represent an admission that the above content is prior art. Summary of the Invention
[0005] The main objective of this application is to provide a chip image registration method, apparatus, and device, which aims to solve the technical problem that in the process of chip image registration, the overlap rate of chip images is usually estimated by human experience or a fixed value set by the machine, resulting in an overlap rate that is too large or too small, affecting the accuracy, efficiency, and reliability of image registration.
[0006] To achieve the above objectives, this application proposes a chip image registration method, which includes: obtaining a preset overlap rate; calculating a preset overlap region of adjacent chip images based on the preset overlap rate; obtaining the actual overlap rate of the chip images based on the matching similarity within the preset overlap region; and registering the adjacent chip images based on the actual overlap rate to obtain a target chip image.
[0007] In one embodiment, the chip image registration method further includes: acquiring an initial chip image; performing baseline correction on the initial chip image to acquire a chip image; and arranging the chip images in a matrix according to their positional relationships.
[0008] In one embodiment, the preset overlap rate includes: a first preset sub-overlap rate and a second preset sub-overlap rate; the preset overlap region includes: a first sub-preset overlap region and a second sub-preset overlap region; calculating and obtaining the preset overlap region of adjacent chip images based on the preset overlap rate includes: obtaining the first preset sub-overlap region based on the first preset sub-overlap rate; obtaining the second preset sub-overlap region based on the second preset sub-overlap rate; using the following formula:
[0009] Where IoU represents the overlap rate, This indicates the size of the overlapping region, and S indicates the size of the chip image region.
[0010] In one embodiment, obtaining the actual overlap rate of a chip image based on the matching similarity within a preset overlapping region includes: determining the actual overlapping region within the preset overlapping region based on the matching similarity within the preset overlapping region; and calculating the actual overlap rate based on the actual overlapping region.
[0011] In one embodiment, the actual overlapping region includes a first actual sub-overlapping region and a second actual sub-overlapping region. Determining the actual overlapping region within the preset overlapping region based on the matching similarity within the preset overlapping region includes: calculating the similarity of the sliding window regions of the chip images in the first row and first column and the first row and second column within the first preset sub-overlapping region according to a first preset overlap rate to obtain a first similarity value; in response to the first similarity value being greater than a first similarity threshold, indicating that the sliding window region corresponding to the current step size is the first actual sub-overlapping region; calculating the similarity of the sliding windows of the chip images in the first row and first column and the second row and first column within the second preset sub-overlapping region according to a second preset sub-overlap rate to obtain a second similarity value; in response to the second similarity value being greater than a second similarity threshold, indicating that the sliding window region corresponding to the current step size is the second actual sub-overlapping region.
[0012] In one embodiment, similarity calculation includes: calculating the structural similarity within the current sliding window to obtain a first value; calculating the normalized cross-correlation value within the current sliding window to obtain a second value; calculating the feature matching degree within the current sliding window to obtain a third value; and weightedly fusing the first value, the second value, and the third value to obtain a similarity.
[0013] In one embodiment, the actual overlap rate includes a first actual overlap rate and a second actual overlap rate; calculating the actual overlap rate based on the actual overlap region includes: calculating and obtaining the first actual overlap rate between adjacent columns of the chip image based on the first actual sub-overlap region; calculating and obtaining the second actual overlap rate between adjacent rows of the chip image based on the second actual sub-overlap region; wherein, the following formula is included:
[0014] For the first actual overlap rate, For the first preset sub-overlap rate, or For the second actual overlap rate, The second preset sub-overlap ratio, where H is the chip height and W is the chip width. Let n be the step size and n be the sliding window.
[0015] In one embodiment, registering adjacent chip images according to the actual overlap rate includes: calculating a third actual sub-overlapping region between adjacent columns of the chip images based on a first actual overlap rate; calculating a fourth actual sub-overlapping region between adjacent rows of the chip images based on a second actual overlap rate; obtaining image transformation parameters based on the third and fourth actual sub-overlapping regions; wherein the image transformation parameters include translation parameters and rotation parameters; and sequentially registering adjacent chip images according to the image transformation parameters.
[0016] In addition, to achieve the above objectives, this application also proposes a chip image registration device, which includes: a processing module, used to obtain a preset overlapping region of adjacent chip images according to a preset overlap rate; and to obtain the actual overlap rate of the chip images according to the matching similarity within the preset overlapping region; and a registration module, used to register adjacent chip images according to the actual overlap rate to obtain a target chip image.
[0017] In addition, to achieve the above objectives, this application also proposes a chip image registration device, the device comprising: a memory, a processor, and a computer program stored in the memory and executable on the processor, the computer program being configured to implement the steps of the chip image registration method described above.
[0018] In addition, to achieve the above objectives, this application also proposes a storage medium, which is a computer-readable storage medium, on which a computer program is stored, and when the computer program is executed by a processor, it implements the steps of the chip image registration method described above.
[0019] In addition, to achieve the above objectives, this application also provides a computer program product, which includes a computer program that, when executed by a processor, implements the steps of the chip image registration method described above.
[0020] The present application proposes one or more technical solutions, which have at least the following technical effects: Based on a preset overlap rate, the actual overlap rate is obtained within a preset overlap area according to the similarity, so that registration can be completed in the subsequent matching process based on the actual overlap rate. This accurately determines the size of the overlap area in the registration process, avoiding the increase in computational load in the subsequent registration process due to regional redundancy when the overlap area is set too large, and the inability to cover all effective areas when the overlap area is set too small, resulting in information loss and affecting the accuracy and reliability of registration. The present application obtains a more accurate actual overlap area to avoid the above problems and thus improve the efficiency of registration, meeting the requirements for accuracy and reliability of registration. Attached Figure Description
[0021] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.
[0022] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, for those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0023] Figure 1 is a flowchart illustrating a first embodiment of the chip image registration method provided in this application; Figure 2 is a flowchart illustrating a first embodiment of step S10 in the chip image registration method provided in this application; Figure 3 is a flowchart illustrating a second embodiment of step S10 in the chip image registration method provided in this application; Figure 4 is a flowchart illustrating a first embodiment of step S20 in the chip image registration method provided in this application; Figure 5 is a flowchart illustrating a first embodiment of step A21 in the chip image registration method provided in this application; Figure 6 is a flowchart illustrating a first embodiment of similarity calculation in the chip image registration method provided in this application; Figure 7 is a flowchart illustrating a first embodiment of step A22 in the chip image registration method provided in this application; Figure 8 is a flowchart illustrating a first embodiment of step S30 in the chip image registration method provided in this application; Figure 9 is a structural schematic diagram of an embodiment of the chip image registration device provided in this application; Figure 10 is a structural schematic diagram of an embodiment of the chip image registration equipment provided in this application.
[0024] The purpose, features, and advantages of this application will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation
[0025] It should be understood that the specific embodiments described herein are merely illustrative of the technical solutions of this application and are not intended to limit this application.
[0026] To better understand the technical solution of this application, a detailed description will be provided below in conjunction with the accompanying drawings and specific implementation methods.
[0027] The main solution of this application embodiment is to provide a chip image registration method, apparatus and device, which relates to the field of image processing technology. The chip image registration method includes: obtaining a preset overlap rate; calculating a preset overlap region of adjacent chip images based on the preset overlap rate; obtaining the actual overlap rate of the chip images based on the matching similarity within the preset overlap region; and registering adjacent chip images based on the actual overlap rate to obtain a target chip image.
[0028] In existing technologies, the overlapping area in chip image registration is usually estimated manually or determined by a specific value provided by the computer system. However, these methods rely too heavily on empirical methods, which can easily lead to significant deviations and fail to guarantee that the overlap rate is set within an optimal range. Setting the overlap rate too high results in computational redundancy and increased computational load, while setting it too low leads to the loss of effective signals, affecting the accuracy and reliability of registration and failing to meet registration requirements.
[0029] To address the aforementioned issues, this application provides a chip image registration method, apparatus, and device to set the overlap rate within a suitable range, thereby meeting the accuracy, efficiency, and reliability requirements of chip image registration.
[0030] It should be noted that the executing entity in this embodiment can be a computing service device with data processing, network communication, and program execution functions, such as a tablet computer, personal computer, or mobile phone, or an electronic device or apparatus capable of performing the above functions. The following description uses an electronic device as an example to illustrate this embodiment and the subsequent embodiments.
[0031] Based on this, this application provides a chip image registration method. Referring to FIG1, FIG1 is a flowchart of the first embodiment of the chip image registration method provided in this application.
[0032] It is understood that the present application mainly involves chip image registration methods, apparatus and devices. Therefore, before processing step S10 in the present application, the chip image registration method of the present application may also include the process of acquiring and processing chip images.
[0033] In one feasible implementation, as shown in FIG2, FIG2 is a schematic flowchart of the first embodiment of step S10 in the chip image registration method provided in this application; specifically, before processing step S10 in the solution of this application, the chip image registration method may also include steps S11 to S13, the specific steps are as follows: Step S11: Obtain the initial image of the chip.
[0034] Understandably, acquiring initial images of the chip can involve using image acquisition devices, including but not limited to microscopes, to capture images from multiple angles and positions. Understandably, during the imaging process, it's necessary to ensure that the image acquisition device has sufficiently high resolution and accuracy to capture subtle features on the chip surface. Simultaneously, by precisely controlling the shooting angle and position, image information from different areas of the chip can be obtained, providing rich data support for subsequent image registration.
[0035] In some feasible embodiments, an automated shooting system can also be used during shooting to achieve rapid and accurate acquisition of chip images through preset shooting parameters and paths, thereby further improving acquisition efficiency and accuracy.
[0036] Step S12: Perform baseline correction on the initial chip image to obtain the chip image.
[0037] It should be noted that image baseline correction is a correction operation for image geometric distortion or shooting angle deviation. Its core purpose is to restore the image baseline (or reference standard) to a horizontal, vertical or preset standard state, eliminating image tilting and distortion caused by shooting device posture deviation, carrier movement or sensor error.
[0038] Since chip images are mostly captured using wide-angle lenses, radial distortion is prone to occur. This means that a photographed straight line will not be a straight line when projected onto the image plane, causing the chip image to appear curved and distorted, affecting the accuracy of subsequent image registration. To solve this problem, distortion correction can be performed on the acquired chip image using image processing software after image acquisition. By establishing a distortion model, the coordinates of each pixel in the image are transformed and corrected to an ideal, distortion-free position, thereby eliminating the influence of radial distortion on the chip image and ensuring the accuracy of subsequent image registration.
[0039] By using the above method, the baselines of the overlapping areas of multiple images to be stitched are aligned, avoiding the accumulation of registration errors caused by baseline offset, and solving the problems of distortion and misalignment of the stitched images.
[0040] Step S13: Arrange the chip images in a matrix according to their positional relationships.
[0041] Understandably, in the subsequent image registration process, it is necessary to register the overlapping areas between the images based on their positional relationships. Therefore, the chip images are arranged in rows and columns in a matrix to better locate the images.
[0042] In this embodiment, the chip image registration method includes steps S10 to S30, as follows: Step S10: Obtain a preset overlap rate, and calculate the preset overlap region of adjacent chip images based on the preset overlap rate.
[0043] In one feasible implementation, as shown in FIG3, FIG3 is a schematic flowchart of the second embodiment of step S10 in the chip image registration method provided in this application; step S10 may include steps A11 to A13, and the specific steps are as follows: the preset overlap rate includes: a first preset sub-overlap rate and a second preset sub-overlap rate; the preset overlap region includes: a first sub-preset overlap region and a second sub-preset overlap region; the preset overlap region of adjacent chip images is calculated according to the preset overlap rate, including: step A11: the first preset sub-overlap region is obtained according to the first preset sub-overlap rate.
[0044] Step A12: Obtain the second preset sub-overlapping region based on the second preset sub-overlapping rate.
[0045] It should be noted that the first preset sub-overlap rate and the second preset sub-overlap rate represent the overlap rates corresponding to the overlapping areas between the columns and rows of chip images, respectively. The first preset sub-overlap area refers to the overlapping area between chip images in the same row; the second preset sub-overlap area refers to the overlapping area between chip images in the same column.
[0046] The above steps are performed using the following formula:
[0047] Where IoU represents the overlap rate, This indicates the size of the overlapping region, and S indicates the size of the chip image region.
[0048] In one embodiment, both the first preset overlap rate and the second preset overlap rate can be set to 20% to ensure that the actual overlap range is covered, while avoiding affecting the accurate overlap rate calculation due to setting too high.
[0049] Understandably, the size of the preset overlapping area can be directly calculated based on the preset overlap rate. This preset overlapping area can be set based on the jigsaw puzzle operator's experience or previous findings; typically, the preset overlap rate is slightly larger than the actual overlap rate to facilitate finding the actual overlapping area based on the preset overlap rate.
[0050] Step S20: Obtain the actual overlap rate of the chip image based on the matching similarity within the preset overlapping area.
[0051] In one feasible implementation, as shown in FIG4, FIG4 is a schematic flowchart of step S20 of the chip image registration method provided in this application; step S20 may include steps A21 to A22, and the specific steps are as follows: step A21: determine the actual overlapping area within the preset overlapping area based on the matching similarity within the preset overlapping area.
[0052] Grayscale processing is performed on chip images R(1,1) and R(1,2) respectively, and a first preset overlap rate is defined. The corresponding chip width is the maximum width of the sliding window. The chip height is H, and the step size is... The width of the current sliding window n is .
[0053] For each sliding window, multi-scale similarity can be used to calculate the similarity within the corresponding sliding window, including structural similarity (SSIM), normalized cross-correlation (NCC), and feature point matching degree.
[0054] In one feasible implementation, as shown in FIG5, FIG5 is a schematic flowchart of step A21 of the chip image registration method provided in this application; step A21 may include steps B211 to B214, and the specific steps are as follows: the actual overlapping area includes a first actual sub-overlapping area and a second actual sub-overlapping area; the actual overlapping area within the preset overlapping area is determined according to the matching similarity within the preset overlapping area, including: step B211: according to the first preset overlap rate, the similarity of the chip images in the first row and first column and the first row and second column within the first preset sub-overlapping area is calculated sequentially to obtain the first similarity value.
[0055] Step B212: In response to the first similarity value being greater than the first similarity threshold, the sliding window region corresponding to the current step size is characterized as the first actual sub-overlapping region.
[0056] Step B213: Based on the second preset sub-overlap rate, perform similarity calculations on the sliding windows of the chip images in the first row and first column and the second row and first column within the second preset sub-overlap area to obtain the second similarity value.
[0057] Step B214: In response to the second similarity value being greater than the second similarity threshold, the sliding window region corresponding to the current step size is characterized as the second actual sub-overlapping region.
[0058] In the above embodiments, as shown in Figure 6, Figure 6 is a flowchart of an embodiment of similarity calculation in the chip image registration method provided in this application; in steps B211 and B213, the similarity calculation described includes the following steps in a feasible embodiment: Step B211a: Calculate the structural similarity within the current sliding window and obtain a first value.
[0059] The formula for calculating structural similarity is as follows:
[0060] Brightness comparison:
[0061] Contrast comparison:
[0062] Structural comparison:
[0063] Where μ1 and μ2 are the values of R(1,1) on the right side. Corresponding area The mean within, R(1,2) is on the left. Corresponding area The mean value of the pixel region, C1 is a stability constant; σ1, σ2 are the corresponding values of the aforementioned region. and The standard deviation within the range, C2 is the stability constant; σ1 and σ2 are the standard deviations of the corresponding regions mentioned above. and Covariance within.
[0064] Step B211b: Calculate the normalized cross correlation value within the current sliding window and obtain the second value.
[0065] The formula for calculating normalized cross-correlation (NCC) is as follows:
[0066] in, Indicates the region median coordinate The pixel grayscale value at that location; It is a region The average gray value; Indicates the region median coordinate The pixel grayscale value at that location; It is a region The average gray value.
[0067] Step B211c: Calculate the feature matching degree within the current sliding window and obtain the third value.
[0068] The formula for calculating feature matching degree is expressed as: Feature matching quality:
[0069]
[0070] Match rate:
[0071] Average matching distance:
[0072] Distance quality factor:
[0073] Feature matching degree:
[0074] Step B211d: Weighted fusion of the first, second, and third values to obtain the similarity score.
[0075] Based on the above formulas and the weighted fusion of multiple indicators, the corresponding matching region is determined. and Region similarity;
[0076] Among them , and For the corresponding weighted values.
[0077] Understandable, when When the similarity exceeds the threshold, it indicates that the sliding window region corresponding to the nth step size is an overlapping region. Since the first and second actual sub-overlapping regions have been determined, a first preset overlap rate is assumed. 20%, step size If the overlap rate is 1% and the window size is n=4, then the fourth sliding window region is an overlapping region. Based on the adjacency relationship between the two, subsequent sliding window regions do not need to be traversed again, which improves the accuracy of the overlap rate and reduces unnecessary computation.
[0078] By combining similarity calculation with the above-described embodiments, the preset overlapping area range can be effectively narrowed to obtain the actual overlapping area. The deviation of the actual overlapping area is small, thereby avoiding the increase in computational load caused by inaccurate overlapping area settings or the loss of information caused by incomplete coverage of the effective area, thus improving the efficiency, accuracy and reliability of chip image registration.
[0079] Step A22: Calculate the actual overlap rate based on the actual overlapping area.
[0080] In a feasible embodiment, as shown in FIG7, FIG7 is a schematic flowchart of step A22 of the chip image registration method provided in this application; step A22 may include steps B221 to B222, and the specific steps are as follows: step B221: calculate and obtain the first actual overlap rate between adjacent columns of the chip image based on the first actual sub-overlapping region.
[0081] Step B222: Calculate the second actual overlap rate between adjacent rows of the chip image based on the second actual sub-overlap region.
[0082] The above calculation process includes the following formulas.
[0083] For the first actual overlap rate, For the first preset sub-overlap rate, or For the second actual overlap rate, The second preset sub-overlap ratio, where H is the chip height and W is the chip width. Let n be the step size and n be the sliding window.
[0084] It should be noted that, as can be seen from the calculations in the above embodiments, for for In one embodiment, the first actual overlap rate is:
[0085] That is, the actual overlap rate between chip image R(1,1) and chip image R(1,2) is 17%.
[0086] Step S30: Based on the actual overlap rate, register adjacent chip images to obtain the target chip image.
[0087] In one feasible implementation, as shown in FIG8, FIG8 is a schematic flowchart of step S30 of the chip image registration method provided in this application; step S30 may include steps A31 to A34, and the specific steps are as follows: registering adjacent chip images according to the actual overlap rate, including: step A31: calculating and obtaining the third actual sub-overlap region between adjacent columns of the chip image according to the first actual overlap rate.
[0088] Step A32: Calculate and obtain the fourth actual sub-overlapping region between adjacent rows of the chip image based on the second actual overlap rate.
[0089] Step A33: Obtain image transformation parameters based on the third and fourth actual sub-overlapping regions; wherein, the image transformation parameters include translation parameters and rotation parameters.
[0090] It is understood that in this application, the overlap rate of other chip images can be determined by referring to the actual overlap rate and the corresponding overlap area determined in the above embodiments.
[0091] Based on the actual overlapping regions calculated in the above embodiments, namely the first, second, third, and fourth actual sub-overlapping regions, corresponding transformation parameters can be obtained. These image transformation parameters include, but are not limited to, translation and rotation parameters. These parameters can accurately describe the relative position and pose changes between images. For example, in one embodiment, based on the first and second actual sub-overlapping regions, a transformation operation is performed on the chip image in the first row and first column to achieve a better match in position and pose with adjacent chip images.
[0092] Step A34: Register adjacent chip images sequentially according to the image transformation parameters.
[0093] In one embodiment, transformation parameters of the first row and first column chip images are determined based on the first actual overlap region and the second actual overlap region. These transformation parameters include translation parameters and rotation parameters, which can accurately describe the relative position and orientation changes between the images. Based on the transformation parameters of the first row and first column chip images, transformation operations are performed on the first row and first column chip images to achieve a better matching effect with adjacent chip images in terms of position and orientation.
[0094] Furthermore, following similar steps, for example, based on the third overlapping region of the first row, second column and the first row, third column, the corresponding transformation parameters are determined. Based on the overlapping regions corresponding to other chip images confirmed by the first / second actual overlap rate, the corresponding transformation parameters are confirmed. The chip images in other rows and columns are processed sequentially, and the registration of all images is gradually completed, finally obtaining a complete chip image sequence.
[0095] By using the above method, the actual overlap rate is obtained within the preset overlap area based on the similarity, and the registration is completed according to the actual overlap rate in the subsequent matching process. This accurately determines the size of the overlap area in the registration process, avoiding the problems that arise in subsequent registration processes. For example, if the overlap area is set too large, there will be regional redundancy, leading to increased computation in the registration process. Conversely, if the overlap area is set too small, it will not be able to cover all effective areas, resulting in information loss and affecting the accuracy and reliability of the registration. This application obtains a more accurate actual overlap area to avoid the above problems and improve the efficiency of registration, thus meeting the requirements for accuracy and reliability of registration.
[0096] It should be noted that the above examples are only for understanding this application and do not constitute a limitation on the chip image registration method of this application. Any simple transformations based on this technical concept are all within the protection scope of this application.
[0097] This application also provides a chip image registration device 100. Please refer to FIG9, which is a schematic diagram of an embodiment of the chip image registration device provided in this application. The chip image registration device 100 includes: a processing module 10, used to obtain a preset overlapping region of adjacent chip images according to a preset overlap rate; and to obtain the actual overlap rate of the chip images according to the matching similarity within the preset overlapping region; and a registration module 20, used to register adjacent chip images according to the actual overlap rate to obtain a target chip image.
[0098] The chip image registration apparatus 100 provided in this application, employing the chip image registration method in the above embodiments, can solve the technical problem of chip image registration overlap rate setting deviation. Compared with the prior art, the beneficial effects of the chip image registration apparatus 100 provided in this application are the same as those of the chip image registration method provided in the above embodiments, and other technical features in the chip image registration apparatus 100 are the same as those disclosed in the methods of the above embodiments, and will not be repeated here.
[0099] This application provides a chip image registration device 200, as shown in FIG10. FIG10 is a schematic diagram of the structure of an embodiment of the chip image registration device provided in this application. The chip image registration device 200 includes: at least one processor; and a memory communicatively connected to the at least one processor. The memory stores instructions that can be executed by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to perform the chip image registration method in the above embodiment 1.
[0100] Referring now to FIG9, a schematic diagram of a chip image registration device 200 suitable for implementing embodiments of this application is shown. The chip image registration device 200 in embodiments of this application may include, but is not limited to, mobile terminals such as mobile phones, laptops, digital broadcast receivers, PDAs (Personal Digital Assistants), PADs (Portable Application Description), PMPs (Portable Media Players), in-vehicle terminals (e.g., in-vehicle navigation terminals), and fixed terminals such as digital TVs and desktop computers. The chip image registration device 200 shown in FIG9 is merely an example and should not impose any limitations on the functionality and scope of use of embodiments of this application.
[0101] As shown in Figure 9, the chip image registration device 200 may include a processing unit 1001 (e.g., a central processing unit, a graphics processing unit, etc.), which can perform various appropriate actions and processes according to a program stored in a read-only memory (ROM) 1002 or a program loaded from a storage device 1003 into a random access memory (RAM) 1004. The RAM 1004 also stores various programs and data required for the operation of the chip image registration device 200. The processing unit 1001, ROM 1002, and RAM 1004 are interconnected via a bus 1005. An input / output (I / O) interface 1006 is also connected to the bus. Typically, the following systems can be connected to I / O interface 1006: input devices 1007 including, for example, touchscreens, touchpads, keyboards, mice, image sensors, microphones, accelerometers, gyroscopes, etc.; output devices 1008 including, for example, liquid crystal displays (LCDs), speakers, vibrators, etc.; storage devices 1003 including, for example, magnetic tapes, hard disks, etc.; and communication devices 1009. Communication device 1009 allows chip image registration device 200 to communicate wirelessly or wiredly with other devices to exchange data. Although a chip image registration device 200 with various systems is shown in the figure, it should be understood that it is not required to implement or possess all the systems shown. More or fewer systems may be implemented alternatively.
[0102] Specifically, according to the embodiments disclosed in this application, the processes described above with reference to the flowcharts can be implemented as computer software programs. For example, embodiments disclosed in this application include a computer program product comprising a computer program carried on a computer-readable medium, the computer program containing program code for performing the methods shown in the flowcharts. In such embodiments, the computer program can be downloaded and installed from a network via a communication device, or installed from storage device 1003, or installed from ROM 1002. When the computer program is executed by processing device 1001, it performs the functions defined in the methods of the embodiments disclosed in this application.
[0103] The chip image registration device 200 provided in this application, employing the chip image registration method in the above embodiments, can solve the technical problem of chip image registration overlap rate setting deviation. Compared with the prior art, the beneficial effects of the chip image registration device 200 provided in this application are the same as those of the chip image registration method provided in the above embodiments, and other technical features of the chip image registration device 200 are the same as those disclosed in the method of the previous embodiment, and will not be repeated here.
[0104] It should be understood that the various parts disclosed in this application can be implemented using hardware, software, firmware, or a combination thereof. In the description of the above embodiments, specific features, structures, materials, or characteristics can be combined in any suitable manner in one or more embodiments or examples.
[0105] The above are merely specific embodiments of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.
[0106] This application provides a computer-readable storage medium having computer-readable program instructions (i.e., a computer program) stored thereon, the computer-readable program instructions being used to execute the chip image registration method in the above embodiments.
[0107] The computer-readable storage medium provided in this application may be, for example, a USB flash drive, but is not limited to, electrical, magnetic, optical, electromagnetic, infrared, or semiconductor systems or devices, or any combination thereof. More specific examples of computer-readable storage media may include, but are not limited to: electrical connections having one or more wires, portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination thereof. In this embodiment, the computer-readable storage medium may be any tangible medium containing or storing a program that can be used by or in conjunction with an instruction execution system or device. The program code contained on the computer-readable storage medium may be transmitted using any suitable medium, including but not limited to: wires, optical cables, RF (Radio Frequency), etc., or any suitable combination thereof.
[0108] The aforementioned computer-readable storage medium may be included in the chip image registration device 200; or it may exist independently and not be assembled into the chip image registration device 200.
[0109] The aforementioned computer-readable storage medium carries one or more programs, which, when executed by the chip image registration device 200, enable the chip image registration device 200 to implement the steps of the aforementioned chip image registration method.
[0110] Computer program code for performing the operations of this application can be written in one or more programming languages or a combination thereof, including object-oriented programming languages such as Java, Smalltalk, and C++, and conventional procedural programming languages such as the "C" language or similar programming languages. The program code can be executed entirely on the user's computer, partially on the user's computer, as a standalone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In cases involving remote computers, the remote computer can be connected to the user's computer via any type of network—including a Local Area Network (LAN) or a Wide Area Network (WAN)—or can be connected to an external computer (e.g., via the Internet using an Internet service provider).
[0111] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of this application. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions indicated in the blocks may occur in a different order than those indicated in the drawings. For example, two consecutively indicated blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, can be implemented using a dedicated hardware-based system that performs the specified function or operation, or using a combination of dedicated hardware and computer instructions.
[0112] The modules described in the embodiments of this application can be implemented in software or hardware. The names of the modules do not necessarily limit the functionality of the unit itself.
[0113] The readable storage medium provided in this application is a computer-readable storage medium that stores computer-readable program instructions (i.e., a computer program) for executing the above-described chip image registration method, which can solve the technical problem of chip image registration overlap rate setting deviation. Compared with the prior art, the beneficial effects of the computer-readable storage medium provided in this application are the same as the beneficial effects of the chip image registration method provided in the above embodiments, and will not be repeated here.
[0114] This application also provides a computer program product, including a computer program that, when executed by a processor, implements the steps of the chip image registration method described above.
[0115] The computer program product provided in this application can solve the technical problem of misalignment in chip image registration overlap rate settings. Compared with the prior art, the beneficial effects of the computer program product provided in this application are the same as those of the chip image registration method provided in the above embodiments, and will not be repeated here.
[0116] The above are only some embodiments of this application and do not limit the patent scope of this application. All equivalent structural transformations made under the technical concept of this application and using the contents of the specification and drawings of this application, or direct / indirect applications in other related technical fields, are included in the patent protection scope of this application.
Claims
1. A chip image registration method, characterized in that, The chip image registration method includes: obtaining a preset overlap rate; calculating a preset overlap region of adjacent chip images based on the preset overlap rate; obtaining the actual overlap rate of the chip images based on the matching similarity within the preset overlap region; and registering adjacent chip images based on the actual overlap rate to obtain a target chip image.
2. The chip image registration method as described in claim 1, characterized in that, The chip image registration method further includes: acquiring an initial chip image; performing baseline correction on the initial chip image to acquire a chip image; and arranging the chip images in a matrix according to their positional relationships.
3. The chip image registration method as described in claim 1, characterized in that, The preset overlap rate includes: a first preset sub-overlap rate and a second preset sub-overlap rate; the preset overlap region includes: a first sub-preset overlap region and a second sub-preset overlap region; the step of calculating and obtaining the preset overlap region of adjacent chip images based on the preset overlap rate includes: obtaining the first preset sub-overlap region based on the first preset sub-overlap rate; obtaining the second preset sub-overlap region based on the second preset sub-overlap rate; using the following formula: Where IoU represents the overlap rate, This indicates the size of the overlapping region, and S indicates the size of the chip image region.
4. The chip image registration method as described in claim 3, characterized in that, The step of obtaining the actual overlap rate of the chip image based on the matching similarity within the preset overlapping region includes: determining the actual overlapping region within the preset overlapping region based on the matching similarity within the preset overlapping region; and calculating the actual overlap rate based on the actual overlapping region.
5. The chip image registration method as described in claim 4, characterized in that, The actual overlapping region includes a first actual sub-overlapping region and a second actual sub-overlapping region; The step of determining the actual overlapping region within the preset overlapping region based on the matching similarity within the preset overlapping region includes: calculating the similarity of the sliding window regions of the chip images in the first row and first column and the first row and second column within the first preset sub-overlapping region according to the first preset overlap rate to obtain a first similarity value; indicating that the sliding window region corresponding to the current step size is the first actual sub-overlapping region when the first similarity value is greater than a first similarity threshold; calculating the similarity of the sliding windows of the chip images in the first row and first column and the second row and first column within the second preset sub-overlapping region according to the second preset sub-overlap rate to obtain a second similarity value; indicating that the sliding window region corresponding to the current step size is the second actual sub-overlapping region when the second similarity value is greater than a second similarity threshold.
6. The chip image registration method as described in claim 5, characterized in that, The similarity calculation includes: calculating the structural similarity within the current sliding window to obtain a first value; calculating the normalized cross-correlation value within the current sliding window to obtain a second value; calculating the feature matching degree within the current sliding window to obtain a third value; and weightedly fusing the first value, the second value, and the third value to obtain the similarity.
7. The chip image registration method as described in claim 5, characterized in that, The actual overlap rate includes a first actual overlap rate and a second actual overlap rate; calculating the actual overlap rate based on the actual overlap region includes: calculating the first actual overlap rate between adjacent columns of the chip image based on the first actual sub-overlap region; and calculating the second actual overlap rate between adjacent rows of the chip image based on the second actual sub-overlap region; wherein, the following formula is included: For the first actual overlap rate, For the first preset sub-overlap rate, or For the second actual overlap rate, The second preset sub-overlap ratio, where H is the chip height and W is the chip width. Let n be the step size and n be the sliding window.
8. The chip image registration method as described in claim 7, characterized in that, The step of registering adjacent chip images according to the actual overlap rate includes: calculating and obtaining the third actual sub-overlap region between adjacent columns of the chip images according to the first actual overlap rate; calculating and obtaining the fourth actual sub-overlap region between adjacent rows of the chip images according to the second actual overlap rate; obtaining image transformation parameters according to the third actual sub-overlap region and the fourth actual sub-overlap region; wherein the image transformation parameters include translation parameters and rotation parameters; and sequentially registering the adjacent chip images according to the image transformation parameters.
9. A chip image registration device, characterized in that, The chip image registration device includes: a processing module, used to obtain a preset overlapping region of adjacent chip images according to a preset overlap rate; and to obtain the actual overlap rate of the chip images according to the matching similarity within the preset overlapping region; and a registration module, used to register adjacent chip images according to the actual overlap rate to obtain a target chip image.
10. A chip image registration device, characterized in that, The device includes: a memory, a processor, and a computer program stored in the memory and executable on the processor, the computer program being configured to implement the steps of the chip image registration method as described in any one of claims 1 to 8.