Pixel of display device, display device and electronic device

Abstract

The invention relates to a pixel of a display device, the display device and an electronic device. A pixel of a display device includes: a first transistor having a first gate connected to a first node, a first terminal receiving a first power supply voltage, and a second terminal connected to a second node; a first capacitor connected between the first node and the second node; a second capacitor connected between the first power supply voltage and a second node; a second transistor transmitting a data voltage to the first node; and a third transistor selectively connecting the second node to the anode electrode of the light emitting element based on the first emission signal. In a first mode, during data writing, the third transistor is turned off, and the first transistor generates an emission current independent of a capacitance of the light emitting element. In the second mode, the third transistor is turned on, and the emission current depends on the capacitance of the light emitting element.

Description

Pixels of a display device, display device, and electronic device Technical Field

[0001] Embodiments of the present invention relate to display devices, and more specifically, to pixels of display devices, display devices, and electronic devices. Background Technology

[0002] Modern display devices include electronic screens used to visually present information, images, or videos. These devices include display devices such as liquid crystal displays (LCDs), light-emitting diode (LED) displays, organic LED (OLED) displays, and micro LED (MicroLED) displays. Modern display devices focus on high resolution, fast refresh rates, high touch sensitivity, and slim, flexible dimensions. A pixel (short for image element) is the smallest unit for displaying a digital image. In modern display devices such as LCDs, OLEDs, or LEDs, a pixel is a tiny dot that can emit or control light to display a specific color.

[0003] A pixel may include a storage capacitor, a scanning transistor that transmits a data voltage to the storage capacitor in response to a scanning signal, a driving transistor that generates an emission current based on the data voltage stored in the storage capacitor, and a light-emitting element that emits light based on the emission current.

[0004] Driving transistors are typically implemented using low-temperature polycrystalline silicon (“LTPS”) transistors. However, to improve image quality, pixels using oxide transistors as driving transistors have recently been developed. While oxide transistors can improve image quality, they exhibit larger current fluctuations in response to voltage fluctuations compared to LTPS transistors. As a result, pixels using oxide transistors as driving transistors may have higher luminance sensitivity than pixels using LTPS transistors. Summary of the Invention

[0005] Some embodiments provide pixels of a display device capable of improving or reducing brightness sensitivity in response to voltage fluctuations, a display device including pixels, and an electronic device including a display device.

[0006] According to an embodiment, a pixel of a display device is provided. The pixel includes: a first transistor including a first gate connected to a first node, a first terminal configured to receive a first power supply voltage, and a second terminal connected to a second node; a first capacitor including a first electrode connected to the first node and a second electrode connected to the second node; a second capacitor including a first electrode configured to receive the first power supply voltage and a second electrode connected to the second node; a second transistor including a gate configured to receive a first gate signal, a first terminal connected to a data line, and a second terminal connected to the first node; a light-emitting element including an anode electrode and a cathode electrode configured to receive a second power supply voltage; and a third transistor including a gate configured to receive a first emission signal, a first terminal connected to the second node, and a second terminal connected to the anode electrode, wherein the third transistor is configured to be turned off while the second transistor is turned on in a first mode, and to be turned on while the second transistor is turned on in a second mode.

[0007] In one embodiment, during the data write cycle of the first mode, the second electrode of the first capacitor can be connected to the second capacitor, and the second electrode of the first capacitor can be disconnected from the anode electrode. During the data write cycle of the second mode, the second electrode of the first capacitor can be connected to both the second capacitor and the anode electrode.

[0008] In an embodiment, during the emission cycle of the first mode, the first transistor can generate an emission current based on the voltage of the capacitor independent of the light-emitting element. During the emission cycle of the second mode, the first transistor can generate an emission current based on the voltage stored in the first capacitor and dependent on the voltage of that capacitor.

[0009] In an embodiment, the emitter current generated by the first transistor in the first mode may be less than the emitter current generated by the first transistor in the second mode, relative to the same data voltage.

[0010] In an embodiment, the emitter current generated by the first transistor in the first mode can be expressed as... It is determined that, in the second mode, the emitter current generated by the first transistor can be expressed by the formula... It is determined that, where IEL is the emission current generated by the first transistor in the first mode or the emission current generated by the first transistor in the second mode, K is the current coefficient, Cst is the capacitance of the first capacitor, Chold is the capacitance of the second capacitor, VDAT is the data voltage, VREF is the reference voltage, and Cel is the capacitance of the light-emitting element.

[0011] In this embodiment, the first mode can be a normal mode, and the second mode can be a high-brightness mode.

[0012] In an embodiment, the first transistor may be an N-type metal-oxide-semiconductor transistor.

[0013] In one embodiment, the first transistor may further include a second gate connected to a second node.

[0014] In an embodiment, the pixel may further include: a fourth transistor, including a gate configured to receive a second gate signal, a first terminal configured to receive a reference voltage, and a second terminal connected to the first node.

[0015] In an embodiment, the pixel may further include: a fifth transistor, including a gate configured to receive a third gate signal, a first terminal configured to receive an initialization voltage, and a second terminal connected to the anode electrode.

[0016] In an embodiment, the pixel may further include: a sixth transistor, including a gate configured to receive a second transmit signal, a first terminal configured to receive a first power supply voltage, and a second terminal connected to the first terminal of the first transistor.

[0017] In the embodiments, the first transistor, the second transistor, the third transistor, the fourth transistor, and the fifth transistor may be N-type metal-oxide-semiconductor transistors, and the sixth transistor may be a P-type metal-oxide-semiconductor transistor.

[0018] In the embodiments, the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, and the sixth transistor may be N-type metal-oxide-semiconductor transistors.

[0019] In the embodiments, the first transistor, the second transistor, the fourth transistor, and the fifth transistor may be N-type metal-oxide-semiconductor transistors, and the third transistor and the sixth transistor may be P-type metal-oxide-semiconductor transistors.

[0020] In an embodiment, the frame period for a pixel of a display device may include: an initialization period in which a first node and a second node are initialized; a compensation period in which a threshold voltage of a first transistor is stored in a first capacitor; a data writing period in which a data voltage is transmitted to the first node; and an emission period in which a light-emitting element emits light.

[0021] In the embodiments, in the first mode, the third transistor can be turned off during the compensation period and the data write period, and can be turned on during the initialization period and the transmit period. In the second mode, the third transistor can be turned off during the compensation period, and can be turned on during the initialization period, the data write period, and the transmit period.

[0022] In an embodiment, in a first mode, the third transistor can be turned off during the compensation period and the data write period, and can be turned on during the initialization period and the transmit period. In a second mode, the third transistor can be turned on throughout the entire frame period.

[0023] In an embodiment, in each of the first and second modes, the fifth transistor can be turned off during the compensation cycle, the data write cycle, and the transmit cycle, and can be turned on during the initialization cycle.

[0024] In the embodiments, in the first mode, the fifth transistor can be turned off during the emit cycle and turned on during the initialization cycle, the compensation cycle, and the data write cycle. In the second mode, the fifth transistor can be turned off during the compensation cycle, the data write cycle, and the emit cycle, and can be turned on during the initialization cycle.

[0025] In an embodiment, the frame period may further include an anode initialization period, in which the anode electrode is initialized.

[0026] In an embodiment, under each of the first and second modes, the anode initialization cycle can be between the data write cycle and the transmit cycle.

[0027] In an embodiment, in a first mode, the anode initialization cycle may overlap with the compensation cycle and the data write cycle. In a second mode, the anode initialization cycle may occur between the data write cycle and the transmit cycle.

[0028] According to an embodiment, a display device is provided, comprising: a display panel including a plurality of pixels; a data driver configured to provide a data voltage to each of the plurality of pixels; a scan driver configured to provide a first gate signal to each of the plurality of pixels; an emission driver configured to provide a first emission signal to each of the plurality of pixels; and a controller configured to receive a mode signal and control the data driver, the scan driver, and the emission driver. Each of the plurality of pixels includes: a first transistor including a first gate connected to a first node, a first terminal configured to receive a first power supply voltage, and a second terminal connected to a second node; a first capacitor including a first electrode connected to a first node and a second electrode connected to a second node; a second capacitor including a first electrode configured to receive a first power supply voltage and a second electrode connected to a second node; a second transistor including a gate configured to receive the first gate signal, a first terminal connected to a data line, and a second terminal connected to a first node; a light-emitting element including an anode electrode and a cathode electrode configured to receive a second power supply voltage; and a third transistor including a gate configured to receive the first emission signal, a first terminal connected to a second node, and a second terminal connected to the anode electrode. When the mode signal indicates the first mode, the third transistor is turned off simultaneously with the data voltage applied to the first node through the data line and the second transistor. When the mode signal indicates the second mode, the third transistor is turned on simultaneously with the data voltage applied to the first node through the data line and the second transistor.

[0029] According to an embodiment, an electronic device is provided, comprising: a processor configured to provide input image data and a mode signal; and a display device including a plurality of pixels, the display device being configured to receive the input image data and the mode signal and to drive the plurality of pixels based on the input image data and the mode signal. Each of the plurality of pixels includes: a first transistor including a first gate connected to a first node, a first terminal configured to receive a first power supply voltage, and a second terminal connected to a second node; a first capacitor including a first electrode connected to the first node and a second electrode connected to the second node; a second capacitor including a first electrode configured to receive the first power supply voltage and a second electrode connected to the second node; a second transistor including a gate configured to receive a first gate signal, a first terminal connected to a data line, and a second terminal connected to the first node; a light-emitting element including an anode electrode and a cathode electrode configured to receive a second power supply voltage; and a third transistor including a gate configured to receive a first emission signal, a first terminal connected to the second node, and a second terminal connected to the anode electrode. When the mode signal indicates a first mode, the third transistor is turned off while a data voltage is applied to the first node through the data line and the second transistor. When the mode signal indicates the second mode, the third transistor turns on while the data voltage is applied to the first node through the data line and the second transistor.

[0030] As described above, in the pixels, display device, and electronic device of the display device according to the embodiment, when a data voltage is provided to the pixel in a first mode (e.g., a normal mode), a third transistor (e.g., an emitter path switch) connected between a second capacitor (e.g., a holding capacitor) and an anode electrode can be turned off, and when a data voltage is provided to the pixel in a second mode (e.g., a high brightness mode (“HBM”)), the third transistor can be turned on. Therefore, in the second mode, not only can the second capacitor be used, but the capacitance of the light-emitting element can also be used, and the capacitance of the second capacitor can be reduced compared to a conventional pixel. Therefore, brightness sensitivity to voltage changes (or voltage fluctuations) can be improved or reduced. Attached Figure Description

[0031] The illustrative, non-limiting embodiments will become clearer from the following detailed description taken in conjunction with the accompanying drawings.

[0032] Figure 1 is a circuit diagram showing the pixels of a display device according to an embodiment.

[0033] Figure 2 is a timing diagram illustrating an example of the operation of the pixel in Figure 1 in the first mode.

[0034] Figure 3 is a circuit diagram illustrating an example of pixel operation during the initialization cycle.

[0035] Figure 4 is a circuit diagram illustrating an example of pixel operation during the compensation period.

[0036] Figure 5 is a circuit diagram illustrating an example of pixel operation during a data write cycle in the first mode.

[0037] Figure 6 is a circuit diagram illustrating an example of pixel operation during the emission cycle in the first mode.

[0038] Figure 7 is a timing diagram illustrating an example of the operation of pixels of a display device in a second mode.

[0039] Figure 8 is a circuit diagram illustrating an example of pixel operation during a data write cycle in the second mode.

[0040] Figure 9 is a circuit diagram illustrating an example of pixel operation during the emission cycle in the second mode.

[0041] Figure 10 is a diagram showing examples of the current in a low-temperature polysilicon (“LTPS”) transistor and the current in an oxide transistor based on the absolute value of the gate-source voltage.

[0042] Figure 11 is a diagram illustrating an example of the brightness of a pixel according to a data voltage in a first mode and a second mode according to an embodiment.

[0043] Figure 12 is a timing diagram for describing another example of the operation of a pixel in a first mode and a second mode according to an embodiment.

[0044] Figure 13 is a timing diagram illustrating yet another example of the operation of a pixel in a first mode and a second mode according to an embodiment.

[0045] Figure 14 is a timing diagram illustrating yet another example of the operation of a pixel in a first mode and a second mode according to an embodiment.

[0046] Figure 15 is a circuit diagram illustrating an example of pixel operation during the anode initialization cycle in the first mode and the anode initialization cycle in the second mode.

[0047] Figure 16 is a timing diagram illustrating yet another example of the operation of a pixel in a first mode and a second mode according to an embodiment.

[0048] Figure 17 is a circuit diagram showing the pixels of a display device according to an embodiment.

[0049] Figure 18 is a timing diagram illustrating an example of the operation of the pixels of Figure 17 according to an embodiment in a first mode and a second mode.

[0050] Figure 19 is a circuit diagram showing the pixels of a display device according to an embodiment.

[0051] Figure 20 is a timing diagram illustrating an example of the operation of the pixels of Figure 19 according to an embodiment in a first mode and a second mode.

[0052] Figure 21 is a block diagram illustrating a display device according to an embodiment.

[0053] Figure 22 is a block diagram illustrating an electronic device including a display device according to an embodiment.

[0054] Figure 23 is a block diagram illustrating an example of an electronic device according to an embodiment. Detailed Implementation

[0055] Embodiments are described more fully below with reference to the accompanying drawings. The same or similar reference numerals always refer to the same or similar elements.

[0056] At least one embodiment involves adaptively changing how a pixel handles voltage storage depending on the display mode, with the aim of improving brightness performance and reducing visual artifacts. Specifically, the pixel introduces an emission path switch positioned between a holding capacitor and the anode of the light-emitting element. The operation of this emission path switch varies depending on whether the display is in normal mode or high brightness mode (HBM).

[0057] In normal mode, the emitter path switch is off during data writing, so the pixel operates using only the holding capacitor to store the voltage for emission. This configuration isolates the inherent capacitance of the light-emitting element from the storage path, resulting in more stable operation and reduced sensitivity to fluctuations in power supply or data voltage. This is particularly advantageous when using oxide transistors, which are more susceptible to current variations based on voltage fluctuations compared to LTPS transistors.

[0058] However, in high-brightness mode, the emitter path switch is turned on during data writing, allowing the inherent capacitance to be used in combination with the holding capacitor. This increases the effective capacitance during voltage storage, contributing to a higher emitter current and thus higher brightness. Because the inherent capacitance now contributes to voltage storage, the holding capacitor can be designed to have a smaller capacitance, which helps minimize the impact of power supply voltage fluctuations and reduces the likelihood of brightness artifacts such as copy unevenness (or mura) and horizontal crosstalk.

[0059] Because of its ability to switch emission paths between modes, this pixel architecture can be dynamically optimized for image stability or brightness depending on the environment. This flexibility improves display quality and power efficiency, making the design particularly useful in mobile and high-performance display applications where both low-power operation and high brightness are important.

[0060] Figure 1 is a circuit diagram showing the pixels of a display device according to an embodiment.

[0061] Referring to FIG1, a pixel 100 of a display device according to an embodiment includes a first transistor T1, a first capacitor CST, a second capacitor CHOLD (e.g., a holding capacitor), a second transistor T2, a third transistor T3 (e.g., an emitter path switch or an emitter path transistor), and a light-emitting element EL. In some embodiments, the pixel 100 may further include a fourth transistor T4, a fifth transistor T5, and a sixth transistor T6. For example, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 may be omitted.

[0062] The first transistor T1 can generate an emission current supplied to the light-emitting element EL based on the voltage between the first node N1 and the second node N2, or the voltage stored across the first electrode and the second electrode of the first capacitor CST. In some embodiments, the first node N1 can be a gate node connected to the gate of the first transistor T1, and the second node N2 can be a source node connected to the source of the first transistor T1. The first transistor T1 can be referred to as a driving transistor for driving the light-emitting element EL. In some embodiments, the first transistor T1 may include a first gate connected to the first node N1, a first terminal receiving a first power supply voltage ELVDD (e.g., a high power supply voltage) through a sixth transistor T6, and a second terminal connected to the second node N2. Furthermore, in some embodiments, as shown in FIG1, the first transistor T1 may also include a second gate connected to the second node N2. For example, the first gate may be a top gate located above the active layer of the first transistor T1, the second gate may be a bottom gate located below the active layer of the first transistor T1, and the first transistor T1 may have a dual-gate structure.

[0063] A first capacitor CST may be connected between a first node N1 and a second node N2. The first capacitor CST may be referred to as a storage capacitor for storing the data voltage transmitted via the data line DL and the second transistor T2. In some embodiments, the first capacitor CST may include a first electrode connected to the first node N1 and a second electrode connected to the second node N2.

[0064] A second capacitor, CHOLD, may be connected between the line transmitting the first power supply voltage ELVDD and the second node N2. The second capacitor, CHOLD, may be referred to as a holding capacitor for maintaining the voltage at the second node N2. In some embodiments, the second capacitor, CHOLD, may include a first electrode receiving the first power supply voltage ELVDD and a second electrode connected to the second node N2.

[0065] The second transistor T2 can transmit a data voltage from the data line DL to the first node N1 in response to the first gate signal GW. The first gate signal GW can be referred to as a write signal, and the second transistor T2 can be referred to as a scan transistor for transmitting the data voltage from the data line DL. In some embodiments, the second transistor T2 may include a gate for receiving the first gate signal GW, a first terminal connected to the data line DL, and a second terminal connected to the first node N1.

[0066] The third transistor T3 can selectively connect the anode of the light-emitting element EL to the second node N2 or to the second electrode of the first capacitor CST and the second capacitor CHOLD in response to the first emission signal EM1. The third transistor T3 can be referred to as a first emission transistor (e.g., an emission path switch) for forming a path of emission current from the line transmitting the first power supply voltage ELVDD to the line transmitting the second power supply voltage ELVSS (e.g., a low power supply voltage). In some embodiments, the third transistor T3 may include a gate receiving the first emission signal EM1, a first terminal connected to the second node N2, and a second terminal connected to the anode of the light-emitting element EL.

[0067] The fourth transistor T4 can transmit the reference voltage VREF to the first node N1 in response to the second gate signal GR. The second gate signal GR can be referred to as a reference signal or a reset signal, and the fourth transistor T4 can be referred to as a reference transistor or a reset transistor for applying the reference voltage VREF to the first node N1. In some embodiments, the fourth transistor T4 may include a gate for receiving the second gate signal GR, a first terminal for receiving the reference voltage VREF, and a second terminal connected to the first node N1.

[0068] The fifth transistor T5 can transmit an initialization voltage VINT to the second terminal of the third transistor T3 and the anode of the light-emitting element EL in response to the third gate signal GI. The third gate signal GI can be referred to as the initialization signal, and the fifth transistor T5 can be referred to as the initialization transistor for initializing the second node N2 and / or the anode. In some embodiments, the fifth transistor T5 may include a gate for receiving the third gate signal GI, a first terminal for receiving the initialization voltage VINT, and a second terminal connected to the second terminal of the third transistor T3 and the anode of the light-emitting element EL.

[0069] The sixth transistor T6 can transmit the first power supply voltage ELVDD to the first terminal of the first transistor T1 in response to the second transmit signal EM2. The sixth transistor T6 can be referred to as the second emitter transistor for forming a path of emitter current from the line transmitting the first power supply voltage ELVDD to the line transmitting the second power supply voltage ELVSS. In some embodiments, the sixth transistor T6 may include a gate that receives the second transmit signal EM2, a first terminal that receives the first power supply voltage ELVDD, and a second terminal connected to the first terminal of the first transistor T1.

[0070] The light-emitting element EL can emit light based on the emission current generated by the first transistor T1. In some embodiments, the light-emitting element EL can be, but is not limited to, an organic light-emitting diode (“OLED”). In other embodiments, the light-emitting element EL can be any suitable light-emitting element. For example, the light-emitting element EL can be a nano-light-emitting diode (“NED”), a quantum dot (“QD”) light-emitting diode, a micro-light-emitting diode, an inorganic light-emitting diode, or any other suitable light-emitting element. In some embodiments, the light-emitting element EL can include an anode electrode connected to the third transistor T3 and the fifth transistor T5, and a cathode electrode receiving a second power supply voltage ELVSS. Furthermore, the light-emitting element EL can exhibit parasitic capacitance or intrinsic capacitance between the anode and cathode electrodes.

[0071] In some embodiments, the first transistor T1 may be an N-type metal-oxide-semiconductor (“NMOS”) transistor. Alternatively, the first transistor T1 may be an oxide transistor. In some embodiments, as shown in FIG1, the second transistor T2, the third transistor T3, the fourth transistor T4, and the fifth transistor T5 may be, but are not limited to, NMOS transistors, and the sixth transistor T6 may be, but is not limited to, a P-type metal-oxide-semiconductor (“PMOS”) transistor.

[0072] In pixel 100 according to an embodiment, as described below with reference to FIGS. 1 to 11, the third transistor T3 can be turned off in a first mode while the second transistor T2 is turned on, and turned on in a second mode while the second transistor T2 is turned on. That is, the second electrode of the first capacitor CST can be separated from the anode electrode of the light-emitting element EL during the data write cycle of the first mode, but can be connected to the anode electrode of the light-emitting element EL during the data write cycle of the second mode. In some embodiments, the first mode can be a normal mode, and the second mode can be a high-brightness mode (“HBM”). Therefore, during the emission cycle of the first mode (e.g., normal mode), the first transistor T1 can generate an emission current based on the voltage of the capacitor CEL independent of the light-emitting element EL, but during the emission cycle of the second mode (e.g., high-brightness mode), the first transistor T1 can generate an emission current based on the voltage of the capacitor CEL reflecting the light-emitting element EL. For example, in the second mode, this voltage can be stored in the first capacitor CST and depends on the capacitor CEL. Therefore, in the second mode (e.g., high brightness mode), not only can the second capacitor CHOLD be used, but also the capacitor CEL of the light-emitting element EL can be used, and the capacitance of the second capacitor CHOLD can be reduced compared to conventional pixels where the capacitor CEL of the light-emitting element EL is not used. Furthermore, the brightness sensitivity of pixel 100 to voltage changes (or voltage fluctuations) can be improved or reduced, and replication unevenness and / or horizontal crosstalk that occur when the voltage of the second node N2 fluctuates due to fluctuations in the first power supply voltage ELVDD and the second capacitor CHOLD can be prevented or reduced.

[0073] In the following text, referring to Figures 1 to 6, an example of the operation of pixel 100 in a first mode according to an embodiment is described below.

[0074] Figure 2 is a timing diagram illustrating an example of the operation of the pixel of Figure 1 in a first mode; Figure 3 is a circuit diagram illustrating an example of the operation of the pixel in an initialization cycle; Figure 4 is a circuit diagram illustrating an example of the operation of the pixel in a compensation cycle; Figure 5 is a circuit diagram illustrating an example of the operation of the pixel in a data writing cycle in the first mode; and Figure 6 is a circuit diagram illustrating an example of the operation of the pixel in an emission cycle in the first mode.

[0075] Referring to Figures 1 and 2, in the first mode M1 (e.g., the normal mode), the frame period FP for the pixel 100 of the display device includes an initialization period PINI in which the first node N1 and the second node N2 are initialized, a compensation period PCMP in which the threshold voltage of the first transistor T1 is stored in the first capacitor CST, a data write period PDW@M1 in which the data voltage is transmitted to the first node N1, and an emission period PEM@M1 in which the light-emitting element EL emits light.

[0076] During the initialization cycle PNI, the first transmit signal EM1, the second transmit signal EM2, the second gate signal GR, and the third gate signal GI can have a first logic level (e.g., high level), and the first gate signal GW can have a second logic level (e.g., low level). As shown in FIG3, the fourth transistor T4 can be turned on in response to the second gate signal GR having a high level, and can apply the reference voltage VREF to the first node N1. Furthermore, the third transistor T3 can be turned on in response to the first transmit signal EM1 having a high level, and the fifth transistor T5 can be turned on in response to the third gate signal GI having a high level, and the third transistor T3 and the fifth transistor T5 can apply the initialization voltage VINT to the second node N2. Therefore, the first node N1 can be initialized based on the reference voltage VREF, and the second node N2 can be initialized based on the initialization voltage VINT. In addition, the fifth transistor T5 can apply the initialization voltage VINT to the anode electrode of the light-emitting element EL, and the anode electrode of the light-emitting element EL can be initialized based on the initialization voltage VINT. Furthermore, the second transistor T2 can be turned off in response to the first gate signal GW having a low level, and the sixth transistor T6 can be turned off in response to the second transmit signal EM2 having a high level.

[0077] During the compensation period PCMP, the second gate signal GR can be high, and the first transmit signal EM1, the second transmit signal EM2, the first gate signal GW, and the third gate signal GI can be low. As shown in FIG4, the fourth transistor T4 can be turned on in response to the second gate signal GR having a high level, and can apply the reference voltage VREF to the first node N1. Furthermore, the sixth transistor T6 can be turned on in response to the second transmit signal EM2 having a low level, and can apply the first power supply voltage ELVDD to the first terminal of the first transistor T1. Therefore, the first terminal (e.g., the drain) of the first transistor T1 can receive the first power supply voltage ELVDD, the gate of the first transistor T1 can receive the reference voltage VREF, and the first transistor T1 can be turned on until the voltage of the second node N2 becomes the voltage "VREF-VTH" obtained by subtracting the threshold voltage VTH of the first transistor T1 from the reference voltage VREF. Therefore, the first capacitor CST can store the threshold voltage VTH of the first transistor T1 between the first electrode and the second electrode of the first capacitor CST. Furthermore, the second transistor T2 can be turned off in response to the first gate signal GW having a low level, the third transistor T3 can be turned off in response to the first transmit signal EM1 having a low level, and the fifth transistor T5 can be turned off in response to the third gate signal GI having a low level.

[0078] As shown in Figure 2, during the data write cycle PDW@M1 in the first mode M1, the second transmit signal EM2 and the first gate signal GW can be at a high level, while the first transmit signal EM1, the second gate signal GR, and the third gate signal GI can be at a low level. As shown in Figure 5, the second transistor T2 can be turned on in response to the high-level first gate signal GW, and can apply the data voltage VDAT to the first node N1. Therefore, the voltage at the first node N1, or the voltage at the first electrode of the first capacitor CST, can be changed from the reference voltage VREF to the data voltage VDAT, or "VDAT-VREF" can be changed. For example, the voltage at the first node N1 can be increased by an amount equal to the difference between the data voltage VDAT and the reference voltage VREF.

[0079] Furthermore, the third transistor T3 can be turned off in response to a first transmit signal EM1 with a low level. Therefore, during the data write cycle PDW@M1 of the first mode M1, the second electrode of the first capacitor CST can be connected to the second capacitor CHOLD and can be separated from the anode electrode of the light-emitting element EL. Therefore, if the voltage at the first electrode of the first capacitor CST changes by “VDAT-VREF”, the voltage at the second electrode of the first capacitor CST can change by “Cst / (Cst+Chold)×(VDAT-VREF)”. For example, when the voltage at the first electrode of the first capacitor CST changes by “VDAT-VREF”, the voltage at the second electrode of the first capacitor CST changes by the amount determined by the ratio “Cst / (Cst+Chold)”. Here, Cst can represent the capacitance of the first capacitor CST, and Chold can represent the capacitance of the second capacitor CHOLD. Therefore, the voltage stored between the first and second electrodes of the first capacitor CST, or the gate-source voltage of the first transistor T1, can be… In other words, during the data write cycle PDW@M1 of the first mode M1, the voltage between the first and second electrodes of the first capacitor CST should not be affected by the capacitance CEL of the light-emitting element EL. Furthermore, the fourth transistor T4 can be turned off in response to the second gate signal GR with a low level, the fifth transistor T5 can be turned off in response to the third gate signal GI with a low level, and the sixth transistor T6 can be turned off in response to the second transmit signal EM2 with a high level.

[0080] As shown in Figure 2, during the transmit cycle PEM@M1 of the first mode M1, the first transmit signal EM1 can be high, and the first gate signal GW, the second gate signal GR, the third gate signal GI, and the second transmit signal EM2 can be low. As shown in Figure 6, the second transistor T2 can be turned off in response to the low level of the first gate signal GW, the fourth transistor T4 can be turned off in response to the low level of the second gate signal GR, the fifth transistor T5 can be turned off in response to the low level of the third gate signal GI, the third transistor T3 can be turned on in response to the high level of the first transmit signal EM1, and the sixth transistor T6 can be turned on in response to the low level of the second transmit signal EM2. Furthermore, the first transistor T1 can be based on the voltage stored between the first and second electrodes of the first capacitor CST, or... This generates the emission current IEL. Therefore, during the emission period PEM@M1 of the first mode M1, the emission current IEL generated by the first transistor T1 can be expressed by the formula... Determined. Here, K is a current coefficient that can be determined by at least one of the mobility, capacitance, width, or length of the first transistor T1. The light-emitting element EL can emit light based on the emission current IEL.

[0081] In the following description, referring to FIG1 and FIGS. 7 to 9, an example of the operation of pixel 100 in a second mode according to an embodiment is described below.

[0082] Figure 7 is a timing diagram illustrating an example of pixel operation in a second mode; Figure 8 is a circuit diagram illustrating an example of pixel operation in a data write cycle in a second mode; Figure 9 is a circuit diagram illustrating an example of pixel operation in an emit cycle in a second mode; Figure 10 is a diagram illustrating examples of current in a low-temperature polysilicon (“LTPS”) transistor and current in an oxide transistor based on the absolute value of the gate-source voltage; and Figure 11 is a diagram illustrating examples of brightness of a pixel based on data voltage in a first mode and a second mode according to an embodiment.

[0083] Referring to Figures 1 and 7, in the second mode M2 ​​(e.g., high brightness mode), the frame period FP of the pixel 100 for the display device includes an initialization period PIN1, a compensation period PCMP, a data write period PDW@M2, and a transmit period PEM@M2. In some embodiments, the operation of the pixel 100 in the initialization period PIN1 and compensation period PCMP in the second mode M2 ​​is the same as or substantially the same as the operation of the pixel 100 in the initialization period PIN1 and compensation period PCMP in the first mode M1 (see Figure 2).

[0084] During the data write cycle PDW@M2 of the second mode M2, the first transmit signal EM1, the second transmit signal EM2, and the first gate signal GW can be at a high level, while the second gate signal GR and the third gate signal GI can be at a low level. As shown in Figure 8, the second transistor T2 can be turned on in response to the high level of the first gate signal GW, and can apply the data voltage VDAT to the first node N1. Therefore, the voltage of the first node N1 or the voltage of the first electrode of the first capacitor CST can be changed from the reference voltage VREF to the data voltage VDAT, or "VDAT-VREF" can be changed. In addition, the third transistor T3 can be turned on in response to the high level of the first transmit signal EM1. Therefore, during the data write cycle PDW@M2 of the second mode M2, the second electrode of the first capacitor CST can be connected not only to the second capacitor CHOLD, but also to the anode electrode of the light-emitting element EL, thereby affecting the voltage stored at the first capacitor CST by the capacitance CEL of the light-emitting element EL. Therefore, if the voltage at the first electrode of the first capacitor CST changes by "VDAT-VREF", then the voltage at the second electrode of the first capacitor CST can change by "Cst / (Cst+Chold+Cel)×(VDAT-VREF)". Here, Cel can represent the value of the capacitance CEL of the light-emitting element EL. Therefore, the voltage stored across the first and second electrodes of the first capacitor CST, or the gate-source voltage of the first transistor T1, can be... In other words, during the data write cycle PDW@M2 of the second mode M2, the voltage stored across the first and second electrodes of the first capacitor CST can be the voltage of the capacitor CEL, which reflects the light-emitting element EL. Furthermore, the fourth transistor T4 can be turned off in response to the second gate signal GR having a low level, the fifth transistor T5 can be turned off in response to the third gate signal GI having a low level, and the sixth transistor T6 can be turned off in response to the second transmit signal EM2 having a high level.

[0085] In the transmit cycle PEM@M2 of the second mode M2, the first transmit signal EM1 can be high, and the first gate signal GW, the second gate signal GR, the third gate signal GI, and the second transmit signal EM2 can be low. As shown in Figure 9, the second transistor T2 can be turned off in response to the low level of the first gate signal GW, the fourth transistor T4 can be turned off in response to the low level of the second gate signal GR, the fifth transistor T5 can be turned off in response to the low level of the third gate signal GI, the third transistor T3 can be turned on in response to the high level of the first transmit signal EM1, and the sixth transistor T6 can be turned on in response to the low level of the second transmit signal EM2. Furthermore, the first transistor T1 can be based on the voltage stored across the first and second electrodes of the first capacitor CST, or... This generates the emission current IEL. Therefore, during the emission cycle PEM@M2 of the second mode M2, the emission current IEL generated by the first transistor T1 can be expressed by the formula... Confirmed. The light-emitting element (EL) can emit light based on the emission current (IEL).

[0086] Figure 10 illustrates the current 210 of a P-channel metal-oxide-semiconductor (PMOS) transistor (or LTPS transistor) and the current 230 (or drain-source current Ids) of an N-channel metal-oxide-semiconductor (NMOS) transistor (or oxide transistor) based on the absolute value of the gate-source voltage |Vgs|. As shown in Figure 10, the voltage change ΔV2 of an NMOS transistor can be smaller than the voltage change ΔV1 of a PMOS transistor relative to the same current change ΔI. In other words, the current change of an NMOS transistor can be greater than the current change of a PMOS transistor relative to the same voltage change. Therefore, a pixel where the driving transistor is implemented as an NMOS transistor can have a higher brightness sensitivity to voltage changes (or voltage fluctuations) compared to a pixel where the driving transistor is implemented as a PMOS transistor. That is, the brightness of a pixel where the driving transistor is implemented as an NMOS transistor may be undesirably distorted due to undesirable voltage fluctuations (e.g., undesirable fluctuations in the data voltage VDAT (see Figures 8 and 9) or the first supply voltage ELVDD (see Figures 8 and 9)). Therefore, when a pixel with a driving transistor implemented as an NMOS transistor emits light at a brightness corresponding to a low gray level, especially when a pixel with a driving transistor implemented as an NMOS transistor emits light at a brightness corresponding to a low gray level in normal mode, brightness distortion caused by high brightness sensitivity may be noticed.

[0087] Furthermore, pixels with a driving transistor implemented as an NMOS transistor can use the same gamma curve (or a brightness curve based on the data voltage VDAT) in both normal and high-brightness modes. For example, pixels with a driving transistor implemented as an NMOS transistor can emit light with the brightness curve 270 shown in FIG. 11 in both normal and high-brightness modes. Moreover, for example, in the case of pixels with a driving transistor implemented as an NMOS transistor, the portion of brightness curve 270 corresponding to a relatively small data voltage range can be used in normal mode, and the entire brightness curve 270 corresponding to a relatively large data voltage range can be used in high-brightness mode. Therefore, in the case of pixels with a driving transistor implemented as an NMOS transistor, in normal mode, a relatively large brightness fluctuation ΔL2 may occur and may be noticeable due to the undesirable data voltage fluctuation ΔVDAT.

[0088] However, in pixel 100 according to an embodiment of this disclosure, as described above with reference to FIG6 and FIG9, in the first mode M1 (e.g., normal mode), the emission current IEL generated by the first transistor T1 can be expressed by formula It is confirmed, but in the second mode M2 ​​(e.g., high brightness mode), the emission current IEL generated by the first transistor T1 can be expressed by the formula... Confirmed. That is to say, relative to the same data voltage VDAT, the emitter current IEL generated by the first transistor T1 in the first mode M1 can be less than the emitter current IEL generated by the first transistor T1 in the second mode M2.

[0089] For example, as shown in FIG11, when the data voltage VDAT is the maximum data voltage VDAT_MAX (e.g., the data voltage VDAT_255G corresponding to 255 gray levels), the emission current IEL in the first mode M1 (see FIG6) can be less than the emission current IEL in the second mode M2, and therefore the brightness L1@M1 of pixel 100 (see FIGS. 8 and 9) in the first mode M1 can be lower than the brightness L2@M2 of pixel 100 in the second mode M2. That is, as shown in FIG11, pixel 100 according to the embodiment can use a relatively low gamma curve or a relatively low brightness curve 250 in the first mode M1 (e.g., normal mode), and can use a relatively high gamma curve or a relatively high brightness curve 270 in the second mode M2 ​​(e.g., high brightness mode). For example, when the maximum data voltage VDAT is 5V, the emission current in the first mode (normal mode) can be approximately 14.2μA, while the emission current in the second mode (high brightness mode) can be approximately 18.0μA. Therefore, even under the same data voltage, pixel 100 emits lower brightness light in conventional mode compared to the high-brightness mode, demonstrating the difference in emission current and brightness between the two modes described. Therefore, relative to the same data voltage fluctuation ΔVDAT, the brightness fluctuation ΔL1 in the first mode M1 can be smaller than the brightness fluctuation ΔL2 in the second mode M2 ​​(or the brightness fluctuation of a conventional pixel). Therefore, even if the first transistor T1 is implemented as an NMOS transistor (or oxide transistor), the brightness sensitivity of pixel 100 according to the embodiment can be improved or reduced based on voltage changes (or voltage fluctuations) in the first mode M1.

[0090] Furthermore, in pixels with a driving transistor implemented as an NMOS transistor, when the first power supply voltage ELVDD fluctuates, the voltage of the second node N2 (e.g., the source node) fluctuates due to the second capacitor CHOLD, and due to the undesirable fluctuations in the voltage of the second node N2, replication unevenness and / or horizontal crosstalk may occur. However, in pixels using NMOS driving transistors, the capacitor CEL of the light-emitting element EL is not used. In contrast, according to embodiments of this disclosure, in the second mode M2, pixel 100 uses both the second capacitor CHOLD and the capacitor CEL of the light-emitting element EL. Therefore, the second capacitor CHOLD of pixel 100 according to the embodiment can be designed such that the capacitance of the second capacitor CHOLD is smaller than that of the second capacitor CHOLD of the pixel using the NMOS driving transistor. For example, the capacitance of the second capacitor CHOLD of pixel 100 according to the embodiment can be smaller than or equal to the capacitance CEL of the light-emitting element EL compared to the capacitance of the pixel using the NMOS driving transistor. Therefore, in pixel 100 according to the embodiment, since the capacitance of the second capacitor CHOLD is reduced, the voltage fluctuation of the second node N2 caused by the fluctuation of the first power supply voltage ELVDD can be reduced, and the phenomenon of uneven replication and / or horizontal crosstalk can be prevented or reduced.

[0091] As described above, in pixel 100 according to the embodiment, when the data voltage VDAT is provided to pixel 100 in the first mode M1 (e.g., normal mode), the third transistor T3 connected between the second capacitor CHOLD and the anode electrode can be turned off, and when the data voltage VDAT is provided to pixel 100 in the second mode M2 ​​(e.g., high brightness mode), the third transistor T3 can be turned on. Therefore, in the second mode M2, not only can the second capacitor CHOLD be used, but the capacitance CEL of the light-emitting element EL can also be used, and the capacitance of the second capacitor CHOLD can be reduced compared to pixels using NMOS driving transistors. Therefore, in pixel 100 according to the embodiment, brightness sensitivity to voltage changes (or voltage fluctuations) can be reduced, replication unevenness can be reduced, and / or horizontal crosstalk can be reduced.

[0092] Figure 12 is a timing diagram for describing another example of the operation of a pixel in a first mode and a second mode according to an embodiment.

[0093] Referring to Figures 1 and 12, the frame period FP for the pixel 100 of the display device includes an initialization period PINI, a compensation period PCMP, a data write period PDW, and a transmit period PEM. Similar to the first transmit signal EM1 shown in Figure 2, the first transmit signal EM1@M1 shown in Figure 12 under the first mode M1 (see Figure 2) can have a high level during the initialization period PINI and the transmit period PEM, and a low level during the compensation period PCMP and the data write period PDW. Therefore, in the first mode M1, as described above with reference to Figures 2 to 6, the third transistor T3 can be turned off during the compensation period PCMP and the data write period PDW, and can be turned on during the initialization period PINI and the transmit period PEM.

[0094] However, unlike the first transmit signal EM1 shown in FIG. 7, which has a low level during the compensation period PCMP, the first transmit signal EM1@M2 shown in FIG. 12 in the second mode M2 ​​(see FIG. 7) can have a high level H throughout the entire frame period FP. Therefore, unlike the embodiment described above with reference to FIG. 7, where the third transistor T3 is turned on during the initialization period PINI, the data write period PDW@M2, and the transmit period PEM@M2 in the second mode M2 ​​and turned off during the compensation period PCMP, in the embodiment where pixel 100 receives the first transmit signal EM1@M2 shown in FIG. 12 in the second mode M2, the third transistor T3 can be turned on throughout the entire frame period FP. For example, unlike the embodiment previously described with reference to FIG. 7, where the third transistor T3 is turned on during the initialization period PINI, the data write period PDW@M2, and the transmit period PEM@M2 in the second mode M2 ​​but turned off during the compensation period PCMP, the embodiment shown in FIG. 12 provides the first transmit signal EM1@M2 such that the third transistor T3 remains on throughout the entire frame period FP.

[0095] Figure 13 is a timing diagram illustrating yet another example of the operation of a pixel in a first mode and a second mode according to an embodiment.

[0096] Referring to Figures 1 and 13, the frame period FP for the pixel 100 of the display device includes an initialization period PINI, a compensation period PCMP, a data write period PDW, and a transmit period PEM. The first transmit signals EM1@M1 and EM1@M2, the second transmit signal EM2, the first gate signal GW, and the second gate signal GR shown in Figure 13 may be the same as or substantially the same as the first transmit signals EM1@M1 and EM1@M2, the second transmit signal EM2, the first gate signal GW, and the second gate signal GR shown in Figure 12.

[0097] Similar to the third gate signal GI shown in Figures 2, 7, and 12, the third gate signal GI@M2 shown in Figure 13 under the second mode M2 ​​(see Figure 7) can be high during the initialization period PNI and low during the compensation period PCMP, data write period PDW, and transmit period PEM. Similar to the embodiment shown in Figures 2, 7, and 12 where pixel 100 receives the third gate signal GI, in the second mode M2, the fifth transistor T5 can be off during the compensation period PCMP, data write period PDW, and transmit period PEM, and can be on during the initialization period PNI.

[0098] However, unlike the third gate signal GI shown in Figures 2, 7 and 12, the third gate signal GI@M1 shown in Figure 13 under the first mode M1 (see Figure 2) has a high level during the initialization period PINI, the compensation period PCMP and the data write period PDW, and a low level during the transmit period PEM.

[0099] Therefore, unlike the embodiment described above with reference to Figures 2 and 3, where the fifth transistor T5 is turned off during the compensation period PCMP, the data write period PDW@M1, and the transmit period PEM@M1 in the first mode M1 and turned on during the initialization period PINI, in the embodiment where pixel 100 receives the third gate signal GI@M1 in the first mode M1 as shown in Figure 13, the fifth transistor T5 can be turned off during the transmit period PEM and can be turned on during the initialization period PINI, the compensation period PCMP, and the data write period PDW. For example, in the embodiment of Figure 13, the fifth transistor T5 remains turned on throughout the initialization period PINI, the compensation period PCMP, and the data write period PDW in the first mode M1; whereas in the previously described embodiments (Figures 2 and 3), the fifth transistor T5 is turned on only during the initialization period PINI. Therefore, in the first mode M1, the fifth transistor T5 can apply the initialization voltage VINT to the anode of the light-emitting element EL during the initialization cycle PINI, the compensation cycle PCMP, and the data write cycle PDW, and the anode of the light-emitting element EL can be initialized based on the initialization voltage VINT during the initialization cycle PINI, the compensation cycle PCMP, and the data write cycle PDW.

[0100] Figure 14 is a timing diagram illustrating yet another example of the operation of a pixel in a first mode and a second mode according to an embodiment, and Figure 15 is a circuit diagram illustrating an example of the operation of a pixel in an anode initialization cycle in a first mode and an anode initialization cycle in a second mode.

[0101] Referring to Figures 1 and 14, the frame period FP for the pixel 100 of the display device includes an initialization period PINI, a compensation period PCMP, a data write period PDW, an anode initialization period PAINI in which the anode electrode of the light-emitting element EL is initialized, and an emission period PEM. Compared with the frame periods FP shown in Figures 2, 7, 12, and 13, the frame period FP shown in Figure 14 also includes the anode initialization period PAINI between the data write period PDW and the emission period PEM. Furthermore, the first emission signals EM1@M1 and EM1@M2, the second emission signal EM2, the first gate signal GW, and the second gate signal GR shown in Figure 14 may be the same as or substantially the same as the first emission signals EM1@M1 and EM1@M2, the second emission signal EM2, the first gate signal GW, and the second gate signal GR shown in Figure 12.

[0102] The third gate signal GI shown in Figure 14 can be high not only during the initialization period PINI, but also during the anode initialization period PAINI, which is located between the data write period PDW and the transmit period PEM. Therefore, in each of the first mode M1 (see Figure 2) and the second mode M2 ​​(see Figure 7), as shown in Figure 15, the fifth transistor T5 can be turned on not only during the initialization period PINI, but also during the anode initialization period PAINI, and the anode electrode of the light-emitting element EL can be initialized based on the initialization voltage VINT not only during the initialization period PINI, but also during the anode initialization period PAINI. Furthermore, in each of the anode initialization periods PAINI of the first mode M1 and the second mode M2, the second transistor T2, the fourth transistor T4, and the sixth transistor T6 can be turned off. The third transistor T3 can be turned off during the anode initialization period PAINI of the first mode M1, but can be turned on during the anode initialization period PAINI of the second mode M2.

[0103] Figure 16 is a timing diagram illustrating yet another example of the operation of a pixel in a first mode and a second mode according to an embodiment.

[0104] Referring to Figures 1 and 16, the frame period FP for the pixel 100 of the display device may include an initialization period PINI, a compensation period PCMP, a data write period PDW, an anode initialization periods PAINI@M1 and PAINI@M2, and a transmission period PEM. The first transmission signals EM1@M1 and EM1@M2, the second transmission signal EM2, the first gate signal GW, and the second gate signal GR shown in Figure 16 may be the same as or substantially the same as the first transmission signals EM1@M1 and EM1@M2, the second transmission signal EM2, the first gate signal GW, and the second gate signal GR shown in Figure 14.

[0105] Similar to the third gate signal GI shown in Figure 14, the third gate signal GI@M2 shown in Figure 16 under the second mode M2 ​​can be high during the initialization period PINI, and also high during the anode initialization period PAINI@M2 located between the data write period PDW and the emitter period PEM. Therefore, under the second mode M2, the fifth transistor T5 can be turned on not only during the initialization period PINI, but also during the anode initialization period PAINI@M2 located between the data write period PDW and the emitter period PEM, and the anode electrode of the light-emitting element EL can be initialized based on the initialization voltage VINT not only during the initialization period PINI, but also during the anode initialization period PAINI@M2 located between the data write period PDW and the emitter period PEM.

[0106] However, unlike the third gate signal GI shown in FIG14, the third gate signal GI@M1 shown in FIG16 under the first mode M1 can be maintained at a high level from the start time of the initialization period PINI to the time point between the data write period PDW and the transmit period PEM. For example, unlike the segmented timing shown in FIG14, the embodiment of FIG16 continuously maintains the third gate signal GI at a high level without interruption across multiple periods (initialization period PINI, compensation period PCMP, and data write period PDW). Therefore, the anode initialization period PAINI@M1 under the first mode M1 can overlap with the initialization period PINI, compensation period PCMP, and data write period PDW. Therefore, under the first mode M1, the fifth transistor T5 can be turned on in the anode initialization period PAINI@M1 that overlaps with the initialization period PINI, compensation period PCMP, and data write period PDW, and the anode electrode of the light-emitting element EL can be initialized based on the initialization voltage VINT in the anode initialization period PAINI@M1 that overlaps with the initialization period PINI, compensation period PCMP, and data write period PDW.

[0107] FIG17 is a circuit diagram showing the pixels of a display device according to an embodiment, and FIG18 is a timing diagram for describing examples of the operation of the pixels of FIG17 according to an embodiment in a first mode and a second mode.

[0108] Referring to FIG17, the pixel 300 of the display device according to the embodiment may include a first capacitor CST, a second capacitor CHOLD, a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6', and a light-emitting element EL. Except that the sixth transistor T6' is an NMOS transistor, the pixel 300 of FIG17 may have substantially the same structure and substantially the same operation as the pixel 100 of FIG1. ​​Furthermore, as shown in FIGS. 17 and 18, the second transmit signal EM2' applied to the sixth transistor T6' may be low during the initialization period PINI and the data write period PDW, and may be high during the compensation period PCMP and the transmit period PEM. For example, during the initialization period PINI, the second transmit signal EM2' may be low, and the sixth transistor T6' may be turned off in response to the low level of the second transmit signal EM2'. During the compensation period PCMP, the second transmit signal EM2' may be high, turning on the sixth transistor T6' to apply the first power supply voltage ELVDD to the first terminal of the first transistor T1. During the data write cycle PDW, the second transmit signal EM2' can again be low, and thus the sixth transistor T6' can be turned off. During the transmit cycle PEM, the second transmit signal EM2' can be high, thereby turning on the sixth transistor T6'.

[0109] In some embodiments, the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6' are NMOS transistors and may be oxide transistors. Therefore, pixel 300 of FIG17 can be referred to as an all-oxide pixel comprising only oxide transistors.

[0110] FIG19 is a circuit diagram showing the pixels of a display device according to an embodiment, and FIG20 is a timing diagram for describing examples of the operation of the pixels of FIG19 according to an embodiment in a first mode and a second mode.

[0111] Referring to FIG19, the pixel 400 of the display device according to the embodiment may include a first capacitor CST, a second capacitor CHOLD, a first transistor T1, a second transistor T2, a third transistor T3', a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, and a light-emitting element EL. Except that the third transistor T3' is a PMOS transistor, the pixel 400 of FIG19 may have substantially the same structure and substantially the same operation as the pixel 100 of FIG1. ​​Furthermore, as shown in FIGS19 and 20, the first transmit signal EM1'@M1 applied to the third transistor T3' in the first mode M1 (see FIG2) may have a low level in the initialization period PIN1 and the transmit period PEM, and may have a high level in the compensation period PCMP and the data write period PDW. Furthermore, the first transmit signal EM1'@M2 applied to the third transistor T3' in the second mode M2 ​​(see FIG7) may have a low level L throughout the entire period of the frame period FP.

[0112] In some embodiments, the first transistor T1, the second transistor T2, the fourth transistor T4, and the fifth transistor T5 are NMOS transistors, and the third transistor T3' and the sixth transistor T6 are PMOS transistors. Although FIG1 shows an example of pixel 100 in which the sixth transistor T6 is a PMOS transistor, FIG17 shows an example of pixel 300 without PMOS transistors, and FIG19 shows an example of pixel 400 in which the third transistor T3' and the sixth transistor T6 are PMOS transistors, the pixels supported by this disclosure are not limited to the examples of FIG1, FIG17, and FIG19. For example, the first transistor T1 may be an NMOS transistor, and each of the second transistor T2, the third transistor T3', the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 may be either a PMOS transistor or an NMOS transistor.

[0113] Figure 21 is a block diagram illustrating a display device according to an embodiment.

[0114] Referring to FIG21, the display device 700 according to the embodiment may include a display panel 710, a data driver 720 (e.g., a first driver circuit), a scan driver 730 (e.g., a second driver circuit), a transmit driver 740 (e.g., a third driver circuit), and a controller 750 (e.g., a controller circuit).

[0115] The display panel 710 may include a plurality of pixels PX. According to an embodiment, each pixel PX of the display panel 710 may be pixel 100 of FIG. 1, pixel 300 of FIG. 17, pixel 400 of FIG. 19, or a pixel having a similar structure.

[0116] The data driver 720 can provide a data voltage VDAT to multiple pixels PX based on the data control signal DCTRL received from the controller 750 and the output image data ODAT. The data control signal DCTRL may include, but is not limited to, an output data enable signal, a level start signal, and a load signal. In some embodiments, the data driver 720 and the controller 750 may be implemented as a single integrated circuit, and the single integrated circuit may be referred to as a timing controller embedded data driver (“TED”) integrated circuit. In other embodiments, the data driver 720 and the controller 750 may be implemented as separate integrated circuits.

[0117] The scan driver 730 can provide a first gate signal GW, a second gate signal GR, and a third gate signal GI to a plurality of pixels PX based on a scan control signal SCTRL received from the controller 750. The scan control signal SCTRL may include, but is not limited to, a scan start signal and a scan clock signal. In some embodiments, the scan driver 730 may be integrated or formed in the display panel 710. In other embodiments, the scan driver 730 may be implemented as one or more integrated circuits.

[0118] The transmit driver 740 can provide a first transmit signal EM1 and a second transmit signal EM2 to a plurality of pixels PX based on a transmit control signal EMCTRL received from the controller 750. The transmit control signal EMCTRL may include, but is not limited to, a transmit start signal and a transmit clock signal. In some embodiments, the transmit driver 740 may be integrated or formed in the display panel 710. In other embodiments, the transmit driver 740 may be implemented as one or more integrated circuits.

[0119] Controller 750 (e.g., a timing controller) can receive input image data IDAT and control signal CTRL from an external processor (e.g., a graphics processing unit (“GPU”), application processor (“AP”), or graphics card). The control signal CTRL may include a mode signal SMODE indicating a first mode or a second mode. In some embodiments, the first mode may be a normal mode, and the second mode may be a high-brightness mode. Furthermore, in some embodiments, the control signal CTRL may also include, but is not limited to, a vertical sync signal, a horizontal sync signal, an input data enable signal, a master clock signal, etc. Controller 750 can generate output image data ODAT, a data control signal DCTRL, a scan control signal SCTRL, and a transmit control signal EMCTRL based on the input image data IDAT and the control signal CTRL. Controller 750 can control data driver 720 by providing the output image data ODAT and the data control signal DCTRL to data driver 720, control scan driver 730 by providing the scan control signal SCTRL to scan driver 730, and control transmit driver 740 by providing the transmit control signal EMCTRL to transmit driver 740.

[0120] In the display device 700 according to an embodiment, when the mode signal SMODE indicates a first mode, the third transistor of each pixel PX can be turned off, while the data voltage VDAT is applied to the first node through the data line and the second transistor. However, when the mode signal SMODE indicates a second mode, the third transistor of each pixel PX can be turned on, while the data voltage VDAT is applied to the first node through the data line and the second transistor. Therefore, in the second mode, not only the second capacitor can be used, but also the capacitance of the light-emitting element can be used, and the capacitance of the second capacitor can be reduced compared to a conventional pixel. Therefore, the brightness sensitivity of the pixel PX according to voltage changes (or voltage fluctuations) can be improved or reduced.

[0121] Figure 22 is a block diagram illustrating an electronic device including a display device according to an embodiment.

[0122] Referring to FIG22, electronic device 1100 may include processor 1110, memory device 1120, storage device 1130, input / output (I / O) device 1140, power supply 1150, and display device 1160. Electronic device 1100 may also include multiple ports for communicating with video cards, sound cards, memory cards, universal serial bus (“USB”) devices, other electronic devices, etc.

[0123] Processor 1110 can perform various computing functions or tasks. Processor 1110 can be an application processor (“AP”), a microprocessor, a central processing unit (“CPU”), etc. Processor 1110 can be coupled to other components via address buses, control buses, data buses, etc. In addition, in some embodiments, processor 1110 can also be coupled to an expansion bus such as a peripheral component interconnect (“PCI”) bus.

[0124] The memory device 1120 may store data for the operation of the electronic device 1100. For example, the memory device 1120 may include at least one non-volatile memory device such as an erasable programmable read-only memory (“EPROM”) device, an electrically erasable programmable read-only memory (“EEPROM”) device, a flash memory device, a phase-change random access memory (“PRAM”) device, a resistive random access memory (“RRAM”) device, a nano-floating gate memory (“NFGM”) device, a polymer random access memory (“PoRAM”) device, a magnetic random access memory (“MRAM”) device, a ferroelectric random access memory (“FRAM”) device, and / or at least one volatile memory device such as a dynamic random access memory (“DRAM”) device, a static random access memory (“SRAM”) device, a mobile dynamic random access memory (“mobile DRAM”) device, and the like.

[0125] Storage device 1130 may be a solid-state drive (“SSD”) device, a hard disk drive (“HDD”) device, an optical disc read-only memory (“CD-ROM”) device, etc. I / O device 1140 may be an input device such as a keyboard, keypad, mouse, touchscreen, etc., and an output device such as a printer, speaker, etc. Power supply 1150 provides power for the operation of electronic device 1100. Display device 1160 may be coupled to other components via a bus or other communication link.

[0126] In each pixel of the display device 1160, when a data voltage is supplied to the pixel in a first mode (e.g., normal mode), a third transistor (e.g., emitter path switch) connected between a second capacitor (e.g., holding capacitor) and the anode electrode can be turned off, and when a data voltage is supplied to the pixel in a second mode (e.g., high brightness mode), the third transistor can be turned on. Therefore, in the second mode, not only can the second capacitor be used, but the capacitance of the light-emitting element can also be used, and the capacitance of the second capacitor can be reduced compared to a conventional pixel. Therefore, brightness sensitivity based on voltage changes (or voltage fluctuations) can be improved or reduced.

[0127] The inventive concept can be applied to any electronic device 1100 including display device 1160. For example, the inventive concept can be applied to virtual reality (“VR”) devices, augmented reality (“AR”) devices, mixed reality (“MR”) devices, extended reality (“XR”) devices, mobile phones, smartphones, televisions (“TV”) (e.g., digital TV, 3D TV, etc.), wearable electronic devices, personal computers (“PC”) (e.g., laptop computers, tablet computers, etc.), home appliances, personal digital assistants (“PDAs”), portable multimedia players (“PMPs”), digital cameras, music players, portable game consoles, navigation devices, etc.

[0128] At least one embodiment of this disclosure provides a pixel for a display device, the pixel comprising: a first transistor having a first gate connected to a first node, a first terminal receiving a first power supply voltage, and a second terminal connected to a second node; a first capacitor connected between the first node and a second node; a second capacitor connected between the first power supply voltage and the second node; a second transistor transmitting a data voltage to the first node; and a third transistor selectively connecting the second node to the anode electrode of a light-emitting element based on a first emission signal. In a first mode, during data writing, the third transistor is off, and the first transistor generates an emission current independent of the capacitance of the light-emitting element. In a second mode, the third transistor is on, and the emission current depends on the capacitance of the light-emitting element, thereby improving brightness sensitivity.

[0129] Figure 23 is a block diagram illustrating an example of an electronic device according to an embodiment.

[0130] The electronic device 2101 can output various information via the display module 2140 in the operating system. When the processor 2110 executes the application stored in the memory 2120, the display module 2140 can provide application information to the user via the display panel 2141.

[0131] Processor 2110 can obtain external input via input module 2130 or sensor module 2161, and can execute applications corresponding to the external input. For example, when a user selects the camera icon displayed on display panel 2141, processor 2110 can obtain user input via input sensor 2161-2 and activate camera module 2171. Processor 2110 can transmit image data corresponding to the image captured by camera module 2171 to display module 2140. Display module 2140 can display the image corresponding to the captured image via display panel 2141.

[0132] As another example, when personal information authentication is performed in display module 2140, fingerprint sensor 2161-1 can obtain the input fingerprint information as input data. Processor 2110 can compare the input data obtained by fingerprint sensor 2161-1 with the authentication data stored in memory 2120, and can execute the application based on the comparison result. Display module 2140 can display the information executed according to the application logic via display panel 2141.

[0133] As another example, when the music stream icon displayed in display module 2140 is selected, processor 2110 obtains user input via input sensor 2161-2 and can activate the music stream application stored in memory 2120. When a music execution command is entered in the music stream application, processor 2110 can activate sound output module 2163 to provide the user with sound information corresponding to the music execution command.

[0134] The operation of electronic device 2101 has been briefly described above. The configuration of electronic device 2101 will be described in detail below. Some components of electronic device 2101 described below can be integrated and provided as a single component, or a single component can be provided separately as two or more components.

[0135] Referring to FIG23, electronic device 2101 can communicate with external electronic device 2102 via a network (e.g., a short-range wireless communication network or a long-range wireless communication network). In some embodiments, electronic device 2101 may include processor 2110, memory 2120, input module 2130, display module 2140, power management module 2150, internal module 2160, and external module 2170. In some embodiments, at least one of the components may be omitted from electronic device 2101, or one or more other components may be added to electronic device 2101. In some embodiments, some of the components (e.g., sensor module 2161, antenna module 2162, or sound output module 2163) may be implemented as a single component (e.g., display module 2140).

[0136] Processor 2110 can execute software to control at least one other component (e.g., hardware or software component) of electronic device 2101 coupled to processor 2110, and can perform various data processing or calculations. According to some embodiments, as at least part of data processing or calculation, processor 2110 can store commands or data received from another component (e.g., input module 2130, sensor module 2161, or communication module 2173) in volatile memory 2121, can process commands or data stored in volatile memory 2121, and can store result data in non-volatile memory 2122.

[0137] Processor 2110 may include a main processor 2111 and an auxiliary processor 2112. Main processor 2111 may include one or more of a central processing unit (“CPU”) 2111-1 and an application processor (“AP”). Main processor 2111 may also include one or more of a graphics processing unit (“GPU”) 2111-2, a communication processor (“CP”), and an image signal processor (“ISP”). Main processor 2111 may also include a neural processing unit (“NPU”) 2111-3. NPU 2111-3 may be a processor specifically designed to process artificial intelligence models, and these models may be generated through machine learning. The artificial intelligence model may include multiple layers of artificial neural networks (artificial neural networks). The artificial neural network may be a deep neural network (“DNN”), a convolutional neural network (“CNN”), a recurrent neural network (“RNN”), a restricted Boltzmann machine (“RBM”), a deep belief network (“DBN”), a bidirectional recurrent deep neural network (“BRDNN”), a deep Q-network, or a combination of two or more of these, but is not limited thereto. In addition to hardware architecture, artificial intelligence models may additionally or optionally include software architecture. At least two of the processing units and processors described above can be implemented as integrated components (e.g., a single chip), or the corresponding processing units and processors can be implemented as independent components (e.g., multiple chips).

[0138] The auxiliary processor 2112 may include a controller. The controller included in the auxiliary processor 2112 may correspond to the controller 750 shown in FIG. 21. The controller may include interface conversion circuitry and timing control circuitry. The controller can receive image signals from the main processor 2111, convert the data format of the image signals to meet the interface specifications with the display module 2140, and output image data. The controller can output various control signals required to drive the display module 2140.

[0139] The auxiliary processor 2112 may also include a data conversion circuit 2112-2, a gamma correction circuit 2112-3, or a rendering circuit 2112-4, etc. The data conversion circuit 2112-2 can receive image data from the controller. The data conversion circuit 2112-2 can compensate the image data to display an image with the desired brightness according to the characteristics of the electronic device 2101 or user settings, or it can convert the image data to reduce power consumption or eliminate afterimages. The gamma correction circuit 2112-3 can convert the image data or gamma reference voltage so that the image displayed in the electronic device 2101 has the desired gamma characteristics. The rendering circuit 2112-4 can receive image data from the controller and can render the image data taking into account the pixel arrangement of the display panel 2141 in the electronic device 2101. At least one of the data conversion circuit 2112-2, the gamma correction circuit 2112-3, and the rendering circuit 2112-4 can be integrated into another component (e.g., the main processor 2111 or the controller). At least one of the data conversion circuit 2112-2, the gamma correction circuit 2112-3, and the rendering circuit 2112-4 can be integrated into the data driver 2143 described below.

[0140] Memory 2120 may store various data used by at least one component of electronic device 2101 (e.g., processor 2110 or sensor module 2161). For example, the various data may include input data or output data for commands associated therewith. Memory 2120 may include at least one of volatile memory 2121 and non-volatile memory 2122.

[0141] The input module 2130 can receive commands or data from outside the electronic device 2101 (e.g., a user or external electronic device 2102) that will be used by components of the electronic device 2101 (e.g., processor 2110, sensor module 2161, or sound output module 2163).

[0142] Input module 2130 may include a first input module 2131 for receiving commands or data from a user and a second input module 2132 for receiving commands or data from an external electronic device 2102. The first input module 2131 may include a microphone, mouse, keyboard, keys (e.g., buttons), or a pen (e.g., a passive or active pen). The second input module 2132 may support a specified protocol that enables wired or wireless connection of electronic device 2101 to external electronic device 2102. In some embodiments, the second input module 2132 may include a High Definition Multimedia Interface (“HDMI”), a Universal Serial Bus (“USB”) interface, a Secure Digital (“SD”) card interface, or an audio interface. The second input module 2132 may include a connector that allows physical connection of electronic device 2101 to external electronic device 2102. For example, the second input module 2132 may include an HDMI connector, a USB connector, an SD card connector, or an audio connector (e.g., a headphone connector).

[0143] Display module 2140 can visually provide information to the user. Display module 2140 may include display panel 2141, scan driver 2142, and data driver 2143. Display module 2140 may also include a window, base, and bracket for protecting display panel 2141.

[0144] Display panel 2141 may include multiple pixels. In each pixel, when a data voltage is supplied to the pixel in a first mode (e.g., normal mode), a third transistor (e.g., emission path switch) connected between a second capacitor (e.g., holding capacitor) and the anode electrode can be turned off, and when a data voltage is supplied to the pixel in a second mode (e.g., high brightness mode), the third transistor can be turned on. Therefore, in the second mode, not only the second capacitor can be used, but also the capacitance of the light-emitting element can be used, and the capacitance of the second capacitor can be reduced compared to a conventional pixel. Therefore, brightness sensitivity based on voltage changes (or voltage fluctuations) can be improved or reduced.

[0145] Display panel 2141 may include a liquid crystal display panel, an organic light-emitting display panel, or an inorganic light-emitting display panel, but the type of display panel 2141 is not limited to these. Display panel 2141 may be a rigid type display panel or a flexible type display panel that can be rolled or folded. Display module 2140 may also include a support member, bracket, or heat dissipation component that supports display panel 2141.

[0146] The scan driver 2142 can be mounted as a driver chip in the display panel 2141. Alternatively, the scan driver 2142 can be integrated into the display panel 2141. For example, the scan driver 2142 may include an amorphous silicon thin-film transistor (“TFT”) gate driver circuit (“ASG”), a low-temperature polycrystalline silicon (“LTPS”) TFT gate driver circuit, or an oxide semiconductor TFT gate driver circuit (“OSG”) embedded in the display panel 2141. The scan driver 2142 can receive control signals from a controller and can output scan signals to the display panel 2141 in response to the control signals.

[0147] The display panel 2141 may also include a transmitter driver. The transmitter driver can output a transmitter control signal to the display panel 2141 in response to a control signal received from the controller. The transmitter driver may be formed separately from the scan driver 2142, or it may be integrated into the scan driver 2142.

[0148] The data driver 2143 can receive control signals from the controller, can convert image data into analog voltages (e.g., data voltages) in response to the control signals, and can then output the data voltages to the display panel 2141.

[0149] The data driver 2143 can be integrated into other components (e.g., a controller). Furthermore, the functions of the interface conversion circuitry and timing control circuitry of the controller described above can be integrated into the data driver 2143.

[0150] The display module 2140 may also include a voltage generator circuit, etc. The voltage generator circuit can output various voltages for driving the display panel 2141.

[0151] Power management module 2150 can supply power to components of electronic device 2101. Power management module 2150 may include a battery charged with a power supply voltage. The battery may include a non-rechargeable primary battery, a rechargeable secondary battery, or a fuel cell. Power management module 2150 may include a power management integrated circuit (“PMIC”). The PMIC can supply optimized power to each of the modules described above and below. Power management module 2150 may include a wireless power transmitting / receiving component electrically connected to the battery. The wireless power transmitting / receiving component may include multiple antenna radiators in the form of coils.

[0152] The electronic device 2101 may also include an internal module 2160 and an external module 2170. The internal module 2160 may include a sensor module 2161, an antenna module 2162, and a sound output module 2163. The external module 2170 may include a camera module 2171, an optical module 2172, and a communication module 2173.

[0153] Sensor module 2161 can detect input through the user's body or through the pen of the first input module 2131, and can generate an electrical signal or data value corresponding to the input. Sensor module 2161 may include at least one of fingerprint sensor 2161-1, input sensor 2161-2, and digitizer 2161-3.

[0154] The fingerprint sensor 2161-1 can generate data values ​​corresponding to a user's fingerprint. The fingerprint sensor 2161-1 can include either an optical fingerprint sensor or a capacitive fingerprint sensor.

[0155] Input sensor 2161-2 can generate data values ​​corresponding to the coordinate information of a user's body input or pen input. Input sensor 2161-2 can convert capacitance changes caused by input into data values. Input sensor 2161-2 can detect input through a passive pen, or can transmit data to or receive data from an active pen.

[0156] Input sensor 2161-2 can measure biosignals such as blood pressure, water content, or body fat. For example, when a part of a user's body touches the sensor layer or sensing panel and remains stationary for a specific period of time, input sensor 2161-2 can detect biosignals based on changes in the electric field caused by said part of the body and output the information desired by the user to display module 2140.

[0157] The digitizer 2161-3 can generate data values ​​corresponding to coordinate information input through a pen. The digitizer 2161-3 can convert the quantity of electromagnetic changes caused by the input into data values. The digitizer 2161-3 can detect input through a passive pen, or can transmit data to or receive data from an active pen.

[0158] At least one of the fingerprint sensor 2161-1, the input sensor 2161-2, and the digitizer 2161-3 can be implemented as a sensor layer formed on the display panel 2141 by a continuous process. The fingerprint sensor 2161-1, the input sensor 2161-2, and the digitizer 2161-3 can be disposed above the display panel 2141, or at least one of the fingerprint sensor 2161-1, the input sensor 2161-2, and the digitizer 2161-3 can be disposed below the display panel 2141.

[0159] Two or more of the fingerprint sensor 2161-1, input sensor 2161-2, and digitizer 2161-3 can be integrated into a single sensing panel using the same process. When integrated into a single sensing panel, the sensing panel can be positioned between the display panel 2141 and a window positioned above the display panel 2141. In some embodiments, the sensing panel can be positioned on the window, but the location of the sensing panel is not limited thereto.

[0160] At least one of the fingerprint sensor 2161-1, the input sensor 2161-2, and the digitizer 2161-3 can be embedded in the display panel 2141. In other words, at least one of the fingerprint sensor 2161-1, the input sensor 2161-2, and the digitizer 2161-3 can be formed simultaneously by a process for forming elements (e.g., light-emitting elements, transistors, etc.) included in the display panel 2141.

[0161] Furthermore, sensor module 2161 can generate electrical signals or data values ​​corresponding to the internal or external states of electronic device 2101. For example, sensor module 2161 may also include a gesture sensor, gyroscope sensor, atmospheric pressure sensor, magnetic sensor, accelerometer, grip sensor, proximity sensor, color sensor, infrared (“IR”) sensor, biometric sensor, temperature sensor, humidity sensor, or illuminance sensor.

[0162] Antenna module 2162 may include one or more antennas for transmitting or receiving signals or power to or from an external source. In some embodiments, communication module 2173 may transmit or receive signals to or from external electronic device 2102 via an antenna suitable for a communication method. The antenna pattern of antenna module 2162 may be integrated into a component of display module 2140 (e.g., display panel 2141) or input sensor 2161-2.

[0163] The sound output module 2163 can output sound signals to the outside of the electronic device 2101. For example, the sound output module 2163 may include a speaker or a receiver. The speaker can be used for general purposes such as playing multimedia or playing recordings. The receiver can be used to receive incoming calls. In some embodiments, the receiver can be implemented separately from the speaker or as part of the speaker. The sound output pattern of the sound output module 2163 can be integrated into the display module 2140.

[0164] Camera module 2171 can capture still images and moving images. In some embodiments, camera module 2171 may include one or more lenses, an image sensor, or an image signal processor. Camera module 2171 may also include an infrared camera capable of measuring the presence or absence of a user, the user's position, and the user's line of sight.

[0165] The optical module 2172 can provide light. The optical module 2172 may include a light-emitting diode or a xenon lamp. The optical module 2172 can operate in conjunction with the camera module 2171, or it can operate independently of the camera module 2171.

[0166] Communication module 2173 can support the establishment of a wired or wireless communication channel between electronic device 2101 and external electronic device 2102, and perform communication via the established communication channel. Communication module 2173 may include a wireless communication module (e.g., a cellular communication module, a short-range wireless communication module, or a Global Navigation Satellite System (“GNSS”) communication module) or a wired communication module (e.g., a local area network (“LAN”) communication module or a power line communication (“PLC”) module). Communication module 2173 can communicate via a short-range communication network (e.g., Bluetooth). The external electronic device 2102 communicates with a wireless fidelity (“Wi-Fi”) direct connection or infrared data association (“IrDA”) or a remote communication network (e.g., a cellular network, the Internet, or a computer network (e.g., a LAN or a wide area network (“WAN”)). These various types of communication modules 2173 can be implemented as a single chip or as multiple chips that are separate from each other.

[0167] Input module 2130, sensor module 2161, and camera module 2171 can be used in conjunction with processor 2110 to control the operation of display module 2140.

[0168] The processor 2110 can output commands or data to the display module 2140, the sound output module 2163, the camera module 2171, or the optical module 2172 based on the input data received from the input module 2130. For example, the processor 2110 can generate image data corresponding to the input data applied by a mouse or active pen, and can output the image data to the display module 2140. Optionally, the processor 2110 can generate command data corresponding to the input data, and can output the command data to the camera module 2171 or the optical module 2172. When no input data is received from the input module 2130 within a certain time period, the processor 2110 can switch the operating mode of the electronic device 2101 to a low-power mode or a sleep mode, thereby reducing the power consumption of the electronic device 2101.

[0169] Processor 2110 can output commands or data to display module 2140, sound output module 2163, camera module 2171, or optical module 2172 based on sensing data received from sensor module 2161. For example, processor 2110 can compare authentication data applied by fingerprint sensor 2161-1 with authentication data stored in memory 2120, and then execute an application based on the comparison result. Processor 2110 can execute commands or output corresponding image data to display module 2140 based on sensing data sensed by input sensor 2161-2 or digitizer 2161-3. If sensor module 2161 includes a temperature sensor, processor 2110 can receive temperature data from sensor module 2161 and can also perform brightness correction on image data based on the temperature data.

[0170] Processor 2110 can receive measurement data from camera module 2171 regarding the presence or absence of a user, the user's position, and the user's gaze. Processor 2110 can also perform brightness correction on image data based on the measurement data. For example, after processor 2110 determines the presence or absence of a user based on input from camera module 2171, data conversion circuit 2112-2 or gamma correction circuit 2112-3 can perform brightness correction on the image data, and processor 2110 can provide the brightness-corrected image data to display module 2140.

[0171] At least some of the components described above can be coupled to each other and transmit signals (e.g., commands or data) between them via inter-peripheral communication schemes (e.g., bus, general purpose input and output (“GPIO”), serial peripheral interface (“SPI”), mobile industrial processor interface (“MIPI”), or hyperpath interconnect (“UPI”)). Processor 2110 can communicate with display module 2140 via a pre-defined interface. Furthermore, any of the communication methods described above can be used between processor 2110 and display module 2140, but the communication methods between processor 2110 and display module 2140 are not limited to those described above.

[0172] The electronic device 2101 according to the various embodiments described above can be one of a variety of types of devices. For example, the electronic device 2101 may include at least one of portable communication devices (e.g., smartphones), computer devices, portable multimedia devices, portable medical devices, cameras, wearable devices, and home appliances. However, the electronic device 2101 according to the embodiments is not limited to the devices described above.

[0173] The foregoing is illustrative of the embodiments and should not be construed as limiting the embodiments. Although some embodiments have been described, those skilled in the art will readily appreciate that many modifications can be made to the embodiments without substantially departing from the novel teachings of the inventive concept. Therefore, all such modifications are intended to be included within the scope of the inventive concept as defined in the claims. It will therefore be understood that the foregoing is illustrative of various embodiments and should not be construed as limiting to the specific embodiments disclosed, and modifications to the disclosed embodiments and other embodiments are intended to be included within the scope of the appended claims.

Claims

1. A pixel of a display device, wherein, The pixel includes: a first transistor including a first gate connected to a first node, a first terminal configured to receive a first power supply voltage, and a second terminal connected to a second node; a first capacitor including a first electrode connected to the first node and a second electrode connected to the second node; a second capacitor including a first electrode configured to receive the first power supply voltage and a second electrode connected to the second node; a second transistor including a gate configured to receive a first gate signal, a first terminal connected to a data line, and a second terminal connected to the first node; a light-emitting element including an anode electrode and a cathode electrode configured to receive a second power supply voltage; and a third transistor including a gate configured to receive a first emission signal, a first terminal connected to the second node, and a second terminal connected to the anode electrode, wherein the third transistor is configured to be off while the second transistor is on in a first mode, and to be on while the second transistor is on in a second mode.

2. The pixel according to claim 1, wherein, During the data write cycle of the first mode, the second electrode of the first capacitor is connected to the second capacitor, and the second electrode of the first capacitor is separated from the anode electrode, wherein, during the data write cycle of the second mode, the second electrode of the first capacitor is connected to the second capacitor and the anode electrode.

3. The pixel according to claim 1, wherein, During the emission cycle of the first mode, the first transistor generates an emission current based on the voltage of the capacitor independent of the light-emitting element, and wherein, during the emission cycle of the second mode, the first transistor generates an emission current based on the voltage stored in the first capacitor and dependent on the voltage of the capacitor.

4. The pixel according to claim 1, wherein, For the same data voltage, the emitter current generated by the first transistor in the first mode is less than the emitter current generated by the first transistor in the second mode.

5. The pixel according to claim 1, wherein, In the first mode, the emission current generated by the first transistor is given by the formula Determined, and wherein, in the second mode, the emitter current generated by the first transistor is determined by the formula It is determined that, where IEL is the emission current generated by the first transistor in the first mode or the emission current generated by the first transistor in the second mode, K is the current coefficient, Cst is the capacitance of the first capacitor, Chold is the capacitance of the second capacitor, VDAT is the data voltage, VREF is the reference voltage, and Cel is the capacitance of the light-emitting element.

6. The pixel according to claim 1, wherein, The first mode is the normal mode, and the second mode is the high brightness mode.

7. The pixel according to claim 1, wherein, The first transistor is an N-type metal-oxide-semiconductor transistor.

8. The pixel according to claim 1, wherein, The first transistor further includes a second gate connected to the second node.

9. The pixel according to claim 1, wherein, The pixel further includes: a fourth transistor, including a gate configured to receive a second gate signal, a first terminal configured to receive a reference voltage, and a second terminal connected to the first node; a fifth transistor, including a gate configured to receive a third gate signal, a first terminal configured to receive an initialization voltage, and a second terminal connected to the anode electrode; and a sixth transistor, including a gate configured to receive a second transmission signal, a first terminal configured to receive the first power supply voltage, and a second terminal connected to the first terminal of the first transistor.

10. The pixel according to claim 9, wherein, The first transistor, the second transistor, the third transistor, the fourth transistor, and the fifth transistor are N-type metal-oxide-semiconductor transistors, and the sixth transistor is a P-type metal-oxide-semiconductor transistor.

11. The pixel according to claim 9, wherein, The frame cycle for the pixel of the display device includes: an initialization cycle in which the first node and the second node are initialized; a compensation cycle in which the threshold voltage of the first transistor is stored in the first capacitor; a data write cycle in which a data voltage is transmitted to the first node; and an emission cycle in which the light-emitting element emits light.

12. The pixel according to claim 11, wherein, In the first mode, the third transistor is turned off during the compensation cycle and the data write cycle and turned on during the initialization cycle and the transmit cycle, and wherein, in the second mode, the third transistor is turned off during the compensation cycle and turned on during the initialization cycle, the data write cycle and the transmit cycle.

13. The pixel according to claim 11, wherein, In the first mode, the third transistor is turned off during the compensation period and the data write period and turned on during the initialization period and the transmit period, and wherein, in the second mode, the third transistor is turned on throughout the entire frame period.

14. The pixel according to claim 11, wherein, In each of the first and second modes, the fifth transistor is turned off during the compensation cycle, the data write cycle, and the transmit cycle, and turned on during the initialization cycle.

15. The pixel according to claim 11, wherein, In the first mode, the fifth transistor is turned off during the transmit cycle and turned on during the initialization cycle, the compensation cycle, and the data write cycle, and wherein, in the second mode, the fifth transistor is turned off during the compensation cycle, the data write cycle, and the transmit cycle and turned on during the initialization cycle.

16. The pixel according to claim 11, wherein, The frame period also includes an anode initialization period, in which the anode electrode is initialized.

17. The pixel according to claim 16, wherein, In each of the first and second modes, the anode initialization cycle occurs between the data write cycle and the transmit cycle.

18. The pixel according to claim 16, wherein, In the first mode, the anode initialization cycle overlaps with the compensation cycle and the data write cycle, and in the second mode, the anode initialization cycle is between the data write cycle and the transmission cycle.

19. A display device, wherein, The display device includes: a display panel including a plurality of pixels; a data driver configured to provide a data voltage to each of the plurality of pixels; a scan driver configured to provide a first gate signal to each of the plurality of pixels; a transmit driver configured to provide a first transmit signal to each of the plurality of pixels; and a controller configured to receive a mode signal and control the data driver, the scan driver, and the transmit driver, wherein each of the plurality of pixels includes: a first transistor including a first gate connected to a first node, a first terminal configured to receive a first power supply voltage, and a second terminal connected to a second node; a first capacitor including a first electrode connected to the first node and a second electrode connected to the second node; and a second capacitor including a first electrode configured to receive the first power supply voltage. The device includes an electrode and a second electrode connected to the second node; a second transistor including a gate configured to receive the first gate signal, a first terminal connected to a data line, and a second terminal connected to the first node; a light-emitting element including an anode electrode and a cathode electrode configured to receive a second power supply voltage; and a third transistor including a gate configured to receive the first emission signal, a first terminal connected to the second node, and a second terminal connected to the anode electrode, wherein, when the mode signal indicates a first mode, the third transistor is turned off while the data voltage is applied to the first node through the data line and the second transistor, and wherein, when the mode signal indicates a second mode, the third transistor is turned on while the data voltage is applied to the first node through the data line and the second transistor.

20. An electronic device, wherein, The electronic device includes: a processor configured to provide input image data and a mode signal; and a display device including a plurality of pixels, the display device being configured to receive the input image data and the mode signal and to drive the plurality of pixels based on the input image data and the mode signal, wherein each of the plurality of pixels includes: a first transistor including a first gate connected to a first node, a first terminal configured to receive a first power supply voltage, and a second terminal connected to a second node; a first capacitor including a first electrode connected to the first node and a second electrode connected to the second node; a second capacitor including a first electrode configured to receive the first power supply voltage and a second electrode connected to the second node; and a second transistor including... The device comprises: a gate configured to receive a first gate signal; a first terminal connected to a data line; and a second terminal connected to the first node; a light-emitting element including an anode electrode and a cathode electrode configured to receive a second power supply voltage; and a third transistor including a gate configured to receive a first emission signal, a first terminal connected to the second node, and a second terminal connected to the anode electrode, wherein, when the mode signal indicates a first mode, the third transistor is turned off while a data voltage is applied to the first node through the data line and the second transistor, and wherein, when the mode signal indicates a second mode, the third transistor is turned on while a data voltage is applied to the first node through the data line and the second transistor.

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