Sub-pixel and display device

Abstract

Embodiments of the present disclosure may provide a sub-pixel and a display device. The sub-pixel comprises a light-emitting element, and the light-emitting element comprises a pixel electrode, a light-emitting layer and a common electrode; a first driving transistor connected between a first driving voltage line and the pixel electrode and configured to switch based on a first gate voltage; and a second driving transistor connected between a second driving voltage line and the pixel electrode and configured to be switched based on a second gate voltage different from the first gate voltage, thereby providing a sub-pixel including two driving transistors alternately drivable in one sub-pixel.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2024-0152890, filed on October 31, 2024, which is incorporated herein by reference for all purposes, as if fully set forth herein. Technical Field

[0003] Embodiments of this disclosure relate to subpixels and display devices.

[0004] Description of related technologies

[0005] Recently, organic light-emitting display devices, which have attracted much attention as display devices, have advantages such as fast response speed, high luminous efficiency, high brightness, and wide viewing angle by using self-emissive organic light-emitting diodes (OLEDs).

[0006] As driving time increases, the driving transistors in each subpixel of an organic light-emitting display device degrade, and characteristics such as threshold voltage and mobility may change.

[0007] Furthermore, as the driving time increases, the organic light-emitting diodes (OLEDs) may also degrade, leading to changes in characteristics such as threshold voltage, as well as changes in characteristics between OLEDs in sub-pixels, because the degree of degradation may differ between OLEDs. Summary of the Invention

[0008] Therefore, methods are needed to compensate for the characteristic values ​​between driving transistors and to compensate for the characteristic values ​​caused by the degradation of organic light-emitting diodes.

[0009] Conventional devices using organic light-emitting diodes (OLEDs) require separate time to compensate for characteristic values ​​due to degradation of the OLEDs or driving transistors. Embodiments of this disclosure can provide sub-pixels and display devices capable of compensating for the characteristic values ​​of the OLEDs or driving transistors during OLED driving.

[0010] Embodiments of this disclosure may provide a subpixel and a display device comprising two driving transistors capable of being driven alternately within a subpixel.

[0011] Embodiments of this disclosure may provide sub-pixels and display devices including multiple emission control transistors, wherein the multiple emission control transistors control the connection of nodes according to a single emission control signal.

[0012] Embodiments of this disclosure may provide a sub-pixel and a display device comprising two driving transistors connected between a pixel electrode and two driving voltage lines.

[0013] Embodiments of this disclosure may provide a display panel including a plurality of sub-pixels, a plurality of data lines, and a plurality of reference voltage lines, wherein each of the plurality of sub-pixels includes a light-emitting element, the light-emitting element including a pixel electrode, an intermediate layer, and a common electrode; a first driving transistor connected between a second node and a third node and configured to switch based on a voltage applied to a first node to drive the light-emitting element; a first scanning transistor connected between a first data line of the plurality of data lines and a first node and configured to switch based on a first scanning signal; a first sensing transistor connected between a first reference voltage line of the plurality of reference voltage lines and a second node and configured to switch based on a first sensing signal; a first emission control transistor connected between a first node and a fourth node and configured to switch based on a first emission control signal; a second emission control transistor connected between a second node and a fifth node and configured to switch based on the first emission control signal; and a storage capacitor electrically connected between the fourth node and the fifth node, wherein a first gate node of the first emission control transistor and a second gate node of the second emission control transistor are connected.

[0014] Embodiments of this disclosure may provide a display device including a first sub-pixel, a first data line connected to the first sub-pixel, a second data line connected to the first sub-pixel, a first reference voltage line connected to the first sub-pixel, a second reference voltage line connected to the first sub-pixel, a data link line connected to receive a data voltage, a sensing drive link line connected to receive a sensing drive voltage, and a first selection circuit electrically connecting one of the data link line or the sensing drive link line to one of the first data line or the second data line.

[0015] Embodiments of this disclosure may provide a sub-pixel including a light-emitting element comprising a pixel electrode, a light-emitting layer, and a common electrode; a first driving transistor connected between a first driving voltage line and the pixel electrode and configured to switch based on a first gate voltage; and a second driving transistor connected between a second driving voltage line and the pixel electrode and configured to switch based on a second gate voltage different from the first gate voltage.

[0016] According to embodiments of this disclosure, a sub-pixel and display device may be provided, which provides a first emission control transistor and a second emission control transistor connected to a node according to a first emission control signal.

[0017] According to embodiments of this disclosure, a sub-pixel and display device may be provided, which provides a third and a fourth emission control transistor connected to a node according to a second emission control signal.

[0018] According to embodiments of the present disclosure, a sub-pixel and display device can be provided that simultaneously senses the light emission of a light-emitting element and the characteristic values ​​of the driving transistor when a first driving transistor and a second driving transistor can be driven alternately.

[0019] According to embodiments of this disclosure, a display device may be provided, which includes a selection circuit for saving data lines required for light emission of light-emitting elements and sensing characteristic values ​​of driving transistors.

[0020] According to embodiments of this disclosure, the efficiency, mobility, and lifetime of the driving transistor can be improved by compensating the characteristic values ​​of the driving transistor during the driving of the sub-pixel, and the sub-pixel can be driven at low power. Attached Figure Description

[0021] The above and other objects, features and advantages of this disclosure will become clearer from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0022] Figure 1 This is a view showing the system configuration of a display device according to an embodiment of the present disclosure;

[0023] Figure 2 A first selection circuit and a second selection circuit of a display device according to an embodiment of the present disclosure are shown;

[0024] Figure 3 Sub-pixels of a display device according to an embodiment of the present disclosure are shown;

[0025] Figure 4 This is a timing diagram showing the sub-pixels SP of a display device according to an embodiment of the present disclosure;

[0026] Figure 5 The third driving period of a first driving period in a method for driving sub-pixels of a display device according to an embodiment of the present disclosure is shown;

[0027] Figure 6 The fourth driving period of a first driving period in a method for driving sub-pixels of a display device according to an embodiment of the present disclosure is shown;

[0028] Figure 7 The fifth driving period of the second driving period in a method for driving sub-pixels of a display device according to an embodiment of the present disclosure is shown; and

[0029] Figure 8 The sixth driving period of the second driving period in a method for driving sub-pixels of a display device according to an embodiment of the present disclosure is shown. Detailed Implementation

[0030] In the following description of examples or embodiments of this disclosure, reference will be made to the accompanying drawings, which illustrate specific examples or embodiments that may be implemented by way of illustration. The same reference numerals and symbols may be used in the drawings to denote the same or similar components, even when these components are shown in different drawings. Furthermore, in the following description of examples or embodiments of this disclosure, detailed descriptions of well-known functions and components incorporated herein are omitted where it is determined that the description may make the subject matter of some embodiments of this disclosure considerably unclear. Terms such as “comprising,” “having,” “including,” “constituting,” “made of,” and “formed from” as used herein are generally intended to allow for the addition of additional components, unless said terms are used in conjunction with the term “only.” As used herein, the singular forms are intended to include the plural forms unless the context clearly indicates otherwise.

[0031] Terms such as “first,” “second,” “A,” “B,” “(A),” or “(B)” may be used herein to describe elements of this disclosure. Each of these terms is not intended to define the nature, order, sequence, or number of elements, but is only used to distinguish the corresponding element from other elements.

[0032] When referring to a first element being "connected or coupled to" a second element, or "in contact with or overlapping" a second element, it should be interpreted that not only can the first element be "directly connected or coupled to" the second element or "directly in contact with or overlapping" a second element, but a third element can also be "placed" between the first and second elements, or the first and second elements can be "connected or coupled," "in contact with," or "overlapped" with each other via a fourth element. Here, the second element can be included in at least one of two or more elements that are "connected or coupled" to each other, or that are "in contact with" or "overlapped" with each other.

[0033] When time-related terms, such as “after,” “later,” “next,” “before,” etc., are used to describe the process or operation of an element or configuration, or the flow or steps in an operation, processing, or manufacturing method, these terms may be used to describe a discontinuous or non-sequential process or operation, unless used with the terms “directly” or “immediately.”

[0034] Furthermore, when referring to any size, relative dimensions, etc., the numerical or corresponding information of the component or feature (e.g., level, range, etc.) should be considered, including tolerances or error ranges that may be caused by various factors (e.g., processing factors, internal or external influences, noise, etc.), even if no relevant description is specified. In addition, the term "may" fully encompasses all the meanings of the term "able to".

[0035] In the following, various embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0036] Figure 1 This is a view showing the system configuration of a display device 100 according to an embodiment of the present disclosure.

[0037] Reference Figure 1 The display device 100 according to embodiments of the present disclosure may include a display panel 110 as a component for displaying images and a display driving circuit. The display driving circuit may be a circuit for driving the display panel 110. The display driving circuit may include a data driving circuit 120, a gate driving circuit 130, and a controller 140, but embodiments of the present disclosure are not limited thereto.

[0038] The display panel 110 may include a substrate SUB and a plurality of sub-pixels SP disposed on the substrate SUB.

[0039] The substrate SUB may include a display area DA and a non-display area NDA.

[0040] The display area (DA) is the area where an image can be displayed, and it can also be called the active area. Multiple sub-pixels (SPs) can be set within the display area (DA) for displaying the image.

[0041] The non-display area NDA is the area where no image is displayed, and it can be the area outside the display area DA. The non-display area NDA can also be called the border (or border area). The non-display area NDA can include the pad area PA.

[0042] For example, the non-display area NDA may include a first non-display area, a second non-display area, a third non-display area, and a fourth non-display area. The first non-display area may be located outside the display area DA in the row direction. The second non-display area may be located outside the display area DA in the row direction and may be positioned opposite the first non-display area. The third non-display area may also be located outside the display area DA in the column direction. The fourth non-display area may be located outside the display area DA in the column direction and may be positioned opposite the third non-display area.

[0043] In the first to fourth non-display areas, the fourth non-display area may include a pad area for connecting, bonding (or attaching) a driving circuit, and the first to third non-display areas may have a very small size, but embodiments of the present disclosure are not limited thereto.

[0044] As another example, the boundary region between the display area DA and the non-display area NDA can be curved, so that the non-display area NDA can be located below the display area.

[0045] When a user views the display area DA from the front, the non-display area NDA shown to the user may not be changed or may be changed very little, but the implementation of this disclosure is not limited thereto.

[0046] The display device 100 according to the embodiments of the present disclosure may be a self-emissive display device in which the display panel 110 emits its own light, but the embodiments of the present disclosure are not limited thereto. When the display device 100 according to the embodiments of the present disclosure is a self-emissive display device, each of the plurality of sub-pixels SP may include a light-emitting element.

[0047] For example, the display device 100 according to embodiments of the present disclosure may be an organic light-emitting diode (OLED) display, wherein the light-emitting element is implemented as an organic light-emitting diode (OLED). As another example, the display device 100 according to embodiments of the present disclosure may be an inorganic light-emitting display device, wherein the light-emitting element is implemented as a light-emitting diode based on inorganic materials. As another example, the display device 100 according to embodiments of the present disclosure may be a quantum dot display device, wherein the light-emitting element is implemented as a quantum dot, which is a self-emitting semiconductor crystal. As another example, the display device 100 according to embodiments of the present disclosure may be a micro-LED display device or a mini-LED display device.

[0048] The structure of each of the plurality of sub-pixels SP can vary depending on the type of display device 100. For example, when the display device 100 is a self-emissive display device in which the sub-pixels SP emit their own light, each sub-pixel SP may include a self-emissive light-emitting element, one or more transistors, and one or more capacitors, but the embodiments of this disclosure are not limited thereto.

[0049] Various types of signal lines for driving multiple sub-pixels SP can be provided on the substrate SUB of the display panel 110. For example, the various types of signal lines may include multiple data lines DL for transmitting data signals (also known as data voltages or image signals) and multiple gate lines GL for transmitting gate signals (also known as scan signals).

[0050] Multiple data lines DL and multiple gate lines GL can intersect each other. Each of the multiple data lines DL can be configured to extend along a column direction. Each of the multiple gate lines GL can be configured to extend along a row direction. According to embodiments of this disclosure, the column direction and the row direction can be relative directions. For example, depending on the viewing angle, the column direction can be the row direction, and depending on the viewing angle, the row direction can be the column direction. For ease of description, the following describes an example where each of the multiple data lines DL is configured in the column direction and each of the multiple gate lines GL is configured in the row direction, but embodiments of this disclosure are not limited thereto. In embodiments of this disclosure, the angle between the row direction and the column direction can be 90 degrees, or it can be an angle other than 90 degrees. Furthermore, in embodiments of this disclosure, the row direction can be referred to as the first direction, and the column direction can be referred to as the second direction.

[0051] The data driving circuit 120 can be a circuit for driving multiple data lines DL and can output data signals to multiple data lines DL.

[0052] The data drive circuit 120 can receive digital image data DATA from the controller 140, and can convert the received image data DATA into an analog data signal (or data voltage) and output it to multiple data lines DL.

[0053] For example, the data driving circuit 120 can be connected to the display panel 110 via a tape auto-bonding (TAB) method, or connected to the bonding pads of the display panel 110 via a chip-on-glass (COG) or chip-on-panel (COP) method, or implemented and connected to the display panel 110 via a chip-on-film (COF) method, but the embodiments of this disclosure are not limited thereto.

[0054] The data driving circuit 120 can be connected to one side of the display panel 110 (e.g., the top or bottom side). As another example, depending on the driving scheme or panel design, the data driving circuit 120 can be connected to both sides of the display panel 110 (e.g., both the top and bottom sides) or two or more of the four sides of the display panel 110.

[0055] The data driving circuit 120 can be located outside the display area DA of the display panel 110, but as another example, the data driving circuit 120 can be located within the display area DA of the display panel 110.

[0056] The gate drive circuit 130 is a circuit used to drive multiple gate lines GL and can output gate signals to multiple gate lines GL.

[0057] The gate drive circuit 130 can receive a first gate voltage corresponding to an on-state voltage (or also called an on-level voltage) and a second gate voltage corresponding to an off-state voltage (or also called an off-level voltage), as well as various gate drive control signals GCS, generate a gate signal including portions having the first gate voltage and portions having the second gate voltage for a predetermined time (e.g., one frame time), and supply the generated gate signal to multiple gate lines GL. For example, the on-state voltage can be a high-level voltage, and the off-state voltage can be a low-level voltage. As another example, the on-state voltage can be a low-level voltage, and the off-state voltage can be a high-level voltage.

[0058] In the display device 100 according to an embodiment of the present disclosure, the gate driving circuit 130 may be embedded in the display panel 110 as a gate in panel (GIP) type, but the embodiments of the present disclosure are not limited thereto. When the gate driving circuit 130 is of the gate in panel type, the gate driving circuit 130 may be formed on the substrate SUB of the display panel 110 during the manufacturing process of the display panel 110.

[0059] For example, the gate drive circuit 130 can be disposed in the non-active region NDA of the display panel 110.

[0060] As another example, the gate driving circuit 130 can be disposed in the display area DA of the display panel 110. For example, the gate driving circuit 130 can be disposed in a first portion of the display area DA (e.g., the left or right portion of the display area DA). As another example, the gate driving circuit 130 can be disposed in both a first portion of the display area DA (e.g., the left or right portion of the display area DA) and a second portion of the display area DA (e.g., the right or left portion of the display area DA). As yet another example, the gate driving circuit 130 can be disposed over the entire display area DA.

[0061] When the gate driving circuit 130 is disposed in the display area DA of the display panel 110, the gate driving circuit 130 may vertically overlap with the sub-pixels SP disposed in the display area DA. For example, the gate driving circuit 130 may vertically overlap with the light-emitting elements and transistors included in the sub-pixels SP disposed in the display area DA. The gate driving circuit 130 may vertically overlap with multiple light-emitting elements and multiple transistors, which are included in multiple sub-pixels SP disposed in the display area DA. The gate driving circuit 130 may include multiple transistors. Each of the multiple transistors included in the gate driving circuit 130 may include an active layer comprising a first semiconductor material, and each of the multiple transistors included in the sub-pixels SP may include an active layer comprising a second semiconductor material. For example, the first semiconductor material and the second semiconductor material may be substantially the same. As another example, the first semiconductor material and the second semiconductor material may be different from each other. For example, the first semiconductor material may be a silicon-based semiconductor material (such as low-temperature polycrystalline silicon), and the second semiconductor material may be an oxide semiconductor material. For example, the active layer may be, but is not limited to, a semiconductor layer.

[0062] The controller 140 is a device for controlling the data drive circuit 120 and the gate drive circuit 130, and can control the driving timing of multiple data lines DL and multiple gate lines GL.

[0063] The controller 140 can supply a data drive control signal DCS to the data drive circuit 120 to control the data drive circuit 120, and can supply a gate drive control signal GCS to the gate drive circuit 130 to control the gate drive circuit 130.

[0064] The controller 140 can receive input image data from the host system 150 and supply image data DATA to the data drive circuit 120 based on the input image data.

[0065] The controller 140 can be implemented as a component independent of the data drive circuit 120, or the controller 140 and the data drive circuit 120 can be integrated into an integrated circuit (IC).

[0066] The controller 140 may be a timing controller used in display technology, a control device capable of performing other control functions and the functions of a timing controller, or a control device other than a timing controller, or it may be a circuit in a control device. The controller 140 may be implemented as various circuits or electronic components, such as integrated circuits (ICs), field-programmable gate arrays (FPGAs), application-specific integrated circuits (ASICs), or processors, but is not limited thereto.

[0067] The controller 140 can be mounted on a printed circuit board or flexible printed circuit and can be electrically connected to the data drive circuit 120 and the gate drive circuit 130 via the printed circuit board or flexible printed circuit.

[0068] The controller 140 can send / receive signals to / from the data drive circuit 120 according to one or more predetermined interfaces. The interfaces may include, for example, a low-voltage differential signaling (LVDS) interface, an embedded clock point interface (EPI), and a serial peripheral interface (SPI), but embodiments of this disclosure are not limited thereto.

[0069] To provide touch sensing and image display functions, the display device 100 according to embodiments of the present disclosure may include a touch sensor and a touch sensing circuit that senses the touch sensor to detect whether a touch occurs by a touch object such as a finger or a pen, or the location of the touch.

[0070] The touch sensing circuit may include: a touch driving circuit that drives and senses the touch sensor, and generates and outputs touch sensing data; and a touch controller that can use the touch sensing data to detect the occurrence of a touch or the location of a touch.

[0071] A touch sensor may include multiple touch electrodes. A touch sensor may also include multiple touch lines for electrically connecting the multiple touch electrodes and touch driving circuitry.

[0072] The touch sensor can exist outside the display panel 110 in the form of a touch panel, or it can exist inside the display panel 110. When the touch panel exists outside the display panel 110 in the form of a touch panel, the touch panel is referred to as an external type. When the touch sensor is of the external type, the touch panel and the display panel 110 can be manufactured separately, or they can be combined during the assembly process. The external type touch panel may include a touch panel substrate and multiple touch electrodes on the touch panel substrate.

[0073] When the touch sensor is present inside the display panel 110, the touch sensor can be formed on the substrate SUB together with the signal lines and electrodes related to the display drive during the manufacturing process of the display panel 110.

[0074] The touch driving circuit can supply a touch driving signal to at least one of a plurality of touch electrodes and can sense at least one of the plurality of touch electrodes to generate touch sensing data.

[0075] Touch sensing circuits can perform touch sensing using either self-capacitance sensing or mutual-capacitance sensing.

[0076] When a touch sensing circuit performs touch sensing using a self-capacitance sensing scheme, it can perform touch sensing based on the capacitance between each touch electrode and the touch object (e.g., a finger or pen). According to the self-capacitance sensing scheme, each of the multiple touch electrodes can be used as both a driving touch electrode and a sensing touch electrode. The touch driving circuit can drive all or some of the multiple touch electrodes and sense all or some of the multiple touch electrodes.

[0077] When a touch sensing circuit performs touch sensing using a mutual capacitance sensing scheme, it can perform touch sensing based on the capacitance between the touch electrodes. According to the mutual capacitance sensing scheme, multiple touch electrodes are divided into driving touch electrodes and sensing touch electrodes. The touch driving circuit can drive the driving touch electrodes and sense the sensing touch electrodes.

[0078] The touch driver circuit and touch controller included in the touch sensing circuit can be implemented as separate devices or a single device. The touch driver circuit and data driver circuit can be implemented as separate devices or a single device.

[0079] The display device 100 may further include a power supply circuit for supplying various types of power to the display driving circuit and / or touch sensing circuit. The power supply circuit may supply various voltages and electrical voltages related to display driving to the display driving circuit or the display panel 110.

[0080] The display device 100 according to the embodiments of this disclosure may be a mobile terminal, such as a smartphone or tablet computer, or a monitor or television (TV) of various sizes, but is not limited thereto, and may be a display of various types and sizes capable of displaying information or images.

[0081] The display device 100 according to embodiments of this disclosure may further include electronic devices, such as a camera (image sensor), a detection sensor, etc. For example, the detection sensor may be a sensor that detects an object or human body by receiving light such as infrared, ultrasonic, or ultraviolet light, but embodiments of this disclosure are not limited thereto.

[0082] The following describes Figure 1 The display device 100 includes a first selection circuit MUX1 and a second selection circuit MUX2.

[0083] Figure 2 A first selection circuit MUX1 and a second selection circuit MUX2 of a display device 100 according to an embodiment of the present disclosure are shown.

[0084] Reference Figure 2Sub-pixels SP can be disposed in the display area DA. Multiple sub-pixels SP can be included in the display area DA. The first selection circuit MUX1 and the second selection circuit MUX2 can be disposed in the non-display area NDA. Alternatively, the first selection circuit MUX1 and the second selection circuit MUX2 can be disposed in the data driving circuit 120. The first selection circuit MUX1 and the second selection circuit MUX2 can be composed of multiplexers or demultiplexers. However, this disclosure is not limited thereto. The analog-to-digital converter ADC can be disposed in the data driving circuit 120. The analog-to-digital converter ADC can be electrically connected to the controller 140.

[0085] The first selection circuit MUX1 and the data drive circuit 120 can be electrically connected via a data link line DLL with an applied data voltage VDATA and a sensing drive link line SLL with an applied sensing drive voltage VSEN.

[0086] The first selection circuit MUX and the sub-pixel SP can be electrically connected via the first data line DL1 and the second data line DL2.

[0087] The second selection circuit MUX2 and the data drive circuit 120 can be electrically connected via a reference voltage link line RLL with a reference voltage VREF applied and a readout line ROL connected to the analog-to-digital converter ADC.

[0088] The second selection circuit MUX and the sub-pixel SP can be electrically connected via the first reference voltage line VREFL1 and the second reference voltage line VREFL2.

[0089] The first selection circuit MUX1 can electrically connect one of the data link line DLL or the sensor drive link line SLL to one of the first data line DL1 or the second data line DL2. Therefore, the number of lines connected between the sub-pixel SP and the data drive circuit 120 can be reduced.

[0090] The second selection circuit MUX2 can electrically connect one of the reference voltage link line RLL and the readout line ROL to one of the first reference voltage line VREFL1 and the second reference voltage line VREFL2. Therefore, the number of lines connected between the sub-pixel SP and the data drive circuit 120 can be reduced.

[0091] When the first reference voltage line VREFL1 and the second reference voltage line VREFL2 are connected to the readout line ROL, the voltage used to sense the characteristic value of the driving transistor can be output from either the first reference voltage line VREFL1 or the second reference voltage line VREFL2 to the readout line ROL. The voltage output to the readout line ROL can be input to the analog-to-digital converter (ADC). For example, the voltage or current charged into the capacitor connected to the readout line ROL can be input to the ADC.

[0092] An analog-to-digital converter (ADC) can convert input voltage or current into digital sensed data. The ADC can then provide the sensed data to the controller 140.

[0093] The controller 140 can calculate a compensation value based on the provided sensing data. The compensation value can be stored in a memory. The data voltage VDATA applied to the sub-pixel SP can be changed based on the compensation value. The changed data voltage VDATA can be output to data lines (e.g., first data line DL1 and second data line DL2).

[0094] When the output data voltage VDATA is provided to the sub-pixel SP, the driving efficiency of the degraded driving transistor can be improved, and the brightness unevenness of the sub-pixel SP can be prevented or reduced.

[0095] The following describes the sub-pixel SP to which the changed data voltage VDATA is supplied.

[0096] Figure 3 A sub-pixel SP of a display device 100 according to an embodiment of the present disclosure is shown.

[0097] Reference Figure 3 The sub-pixel SP may include a light-emitting element ED, which includes a pixel electrode PE, an intermediate layer EL, and a common electrode CE. The sub-pixel SP may include a first driving transistor DT1, used to control the connection between a second node N2 and a third node N3 based on a voltage applied to a first node N1, and to drive the light-emitting element ED. That is, the first driving transistor DT1 is connected between the second node N2 and the third node N3 and is configured to switch based on the voltage applied to the first node N1 to drive the light-emitting element ED.

[0098] The sub-pixel SP may include a first scan transistor SCT1, which controls the connection between a first data line DL1 and a first node N1 among a plurality of data lines according to a first scan signal SC1. That is, the first scan transistor SCT1 is connected between the first data line DL1 and the first node N1 and is configured to switch based on the first scan signal SC1. The sub-pixel SP may also include a first sensing transistor SENT1, which controls the connection between a first reference voltage line VREFL1 and a second node N2 among a plurality of reference voltage lines according to a first sensing signal SEN1. That is, the first sensing transistor SENT1 is connected between the first reference voltage line VREFL1 and the second node N2 and is configured to switch based on the first sensing signal SEN1.

[0099] The sub-pixel SP may include a first emitter control transistor EMT1, which controls the connection between a first node N1 and a fourth node N4 according to a first emitter control signal EM1. That is, the first emitter control transistor EMT1 is connected between the first node N1 and the fourth node N4 and is configured to switch based on the first emitter control signal EM1. The sub-pixel SP may include a second emitter control transistor EMT2, which controls the connection between a second node N2 and a fifth node N5 according to the first emitter control signal EM1. That is, the second emitter control transistor EMT2 is connected between the second node N2 and the fifth node N5 and is configured to switch based on the first emitter control signal EM1. The first gate node of the first emitter control transistor EMT1 and the second gate node of the second emitter control transistor EMT2 may be connected to each other.

[0100] Subpixel SP may include a storage capacitor CST electrically connected between the fourth node N4 and the fifth node N5. The storage capacitor CST may not be a parasitic capacitor (such as Cgs and Cgd) that is an internal capacitor, but may be an external capacitor that is intentionally designed to be outside the driving transistor.

[0101] The sub-pixel SP may include a second driving transistor DT2 for controlling the connection between the seventh node N7 and the eighth node N8 and driving the light-emitting element ED based on the voltage applied to the sixth node N6. That is, the second driving transistor DT2 is connected between the seventh node N7 and the eighth node N8 and is configured to switch based on the voltage applied to the sixth node N6 to drive the light-emitting element ED.

[0102] The sub-pixel SP may include a second scan transistor SCT2 for controlling the connection between a second data line DL2 and a sixth node N6 among a plurality of data lines according to a second scan signal SC2. That is, the second scan transistor SCT2 is connected between the second data line DL2 and the sixth node N6 among the plurality of data lines and is configured to switch based on the second scan signal SC2. The sub-pixel SP may also include a second sensing transistor SENT2, which controls the connection between a second reference voltage line VREFL2 and a seventh node N7 among a plurality of reference voltage lines according to a second sensing signal SEN2. That is, the second sensing transistor SENT2 is connected between the second reference voltage line VREFL2 and the seventh node N7 among the plurality of reference voltage lines and is configured to switch based on the second sensing signal SEN2.

[0103] The sub-pixel SP may include a third emitter control transistor EMT3, which controls the connection between the sixth node N6 and the fourth node N4 according to a second emitter control signal EM2. That is, the third emitter control transistor EMT3 is connected between the sixth node N6 and the fourth node N4 and is configured to switch based on the second emitter control signal EM2. The sub-pixel SP may include a fourth emitter control transistor EMT4, which controls the connection between the seventh node N7 and the fifth node N5 according to the second emitter control signal EM2. That is, the fourth emitter control transistor EMT4 is connected between the seventh node N7 and the fifth node N5 and is configured to switch based on the second emitter control signal EM2. The third gate node of the third emitter control transistor EMT3 and the fourth gate node of the fourth emitter control transistor EMT4 may be connected to each other.

[0104] The first driving transistor DT1, the second driving transistor DT2, the first scanning transistor SCT1, the second scanning transistor SCT2, the first sensing transistor SENT1, the second sensing transistor SENT2, the first emitter control transistor EMT1, the second emitter control transistor EMT2, the third emitter control transistor EMT3, and the fourth emitter control transistor EMT4 can be either N-type transistors or P-type transistors. In the following description, for ease of description, the first driving transistor DT1, the second driving transistor DT2, the first scanning transistor SCT1, the second scanning transistor SCT2, the first sensing transistor SENT1, the second sensing transistor SENT2, the first emitter control transistor EMT1, the second emitter control transistor EMT2, the third emitter control transistor EMT3, and the fourth emitter control transistor EMT4 can be described as N-type transistors.

[0105] The following describes the connections between the components included in the subpixel SP of this disclosure.

[0106] Reference Figure 3 The light-emitting element ED can be connected between the low-potential drive voltage line VSSL, to which a low-potential drive voltage VSS is applied, and the fifth node N5. The drain node or source node of the first driving transistor DT1 corresponds to the third node N3 and can be electrically connected to the first high-potential drive voltage line VDDL1, to which a first high-potential drive voltage VDD1 is applied. The source node or drain node of the first driving transistor DT1 can be a node corresponding to the second node N2.

[0107] The drain or source node of the first scanning transistor SCT1 can be electrically connected to the first data line DL1 to which the first data voltage VDATA1 or the first sensing drive voltage VSEN1 is applied. The gate node of the first scanning transistor SCT1 can be electrically connected to the first scan signal line SCL1 to which the first scan signal SC1 is applied. The source or gate node of the first scanning transistor SCT1 can be a node corresponding to the first node N1. The first node N1 can be a node corresponding to the gate node of the first driving transistor DT1 and the drain or source node of the first emitter control transistor EMT1. The source or drain node of the first emitter control transistor EMT1 can be a node corresponding to the fourth node N4.

[0108] The drain or source node of the first sensing transistor SENT1 can be electrically connected to the first reference voltage line VREFL1 to which the first reference voltage VREF1 is applied. The gate node of the first sensing transistor SENT1 can be electrically connected to the first sensing signal line SENL1 ​​to which the first sensing signal SEN1 is applied. The source or drain node of the first sensing transistor SENT1 can be a node corresponding to the second node N2.

[0109] The second node N2 can be a node corresponding to either the source or drain node of the first driving transistor DT1. The second node N2 can also be a node corresponding to either the drain or source node of the second emitter control transistor EMT2. The source or drain node of the second emitter control transistor EMT2 can be a node corresponding to the fifth node N5.

[0110] The gate nodes of the first emitter control transistor EMT1 and the second emitter control transistor EMT2 can be connected to each other and electrically connected to the first emitter control signal line EML1 to which the first emitter control signal EM1 is applied. The on or off states of the first emitter control transistor EMT1 and the second emitter control transistor EMT2 can be changed according to the first emitter control signal EM1.

[0111] The storage capacitor Cst can be electrically connected between the fourth node N4 and the fifth node N5.

[0112] Reference Figure 3 The drain or source node of the second driving transistor DT2 can correspond to the eighth node N8, and can be electrically connected to the high-potential driving voltage line VDDL2 to which the second high-potential driving voltage VDD2 can be applied. The source or drain node of the second driving transistor DT2 can be the node corresponding to the seventh node N7.

[0113] The drain or source node of the second scanning transistor SCT2 can be electrically connected to the second data line DL2 to which the second data voltage VDATA2 or the second sensing drive voltage VSEN2 is applied. The gate node of the second scanning transistor SCT2 can be electrically connected to the second scan signal line SCL2 to which the second scan signal SC2 is applied. The source or gate node of the second scanning transistor SCT2 can be a node corresponding to the sixth node N6. The sixth node N6 can be a node corresponding to the gate node of the second driving transistor DT2 and the drain or source node of the third emitter control transistor EMT3. The source or drain node of the third emitter control transistor EMT3 can be a node corresponding to the fourth node N4.

[0114] The drain or source node of the second sensing transistor SENT2 can be electrically connected to the second reference voltage line VREFL2 to which the second reference voltage VREF2 is applied. The gate node of the second sensing transistor SENT2 can be electrically connected to the second sensing signal line SENL2 to which the second sensing signal SEN2 is applied. The source or drain node of the second sensing transistor SENT2 can be a node corresponding to the seventh node N7.

[0115] The seventh node N7 can be a node corresponding to either the source or drain node of the second driving transistor DT2. The seventh node N7 can also be a node corresponding to either the drain or source node of the fourth emitter control transistor EMT4. The source or drain node of the fourth emitter control transistor EMT4 can be a node corresponding to the fifth node N5.

[0116] The gate nodes of the third emitter control transistor EMT3 and the fourth emitter control transistor EMT4 can be connected to each other and electrically connected to the second emitter control signal line EML2 to which the second emitter control signal EM2 is applied. The on or off states of the third emitter control transistor EMT3 and the fourth emitter control transistor EMT4 can be changed according to the second emitter control signal EM2.

[0117] The timing diagram for driving the subpixel SP is described below.

[0118] Figure 4 A timing diagram is shown for driving sub-pixels SP of a display device 100 according to an embodiment of the present disclosure.

[0119] According to the driving method of the display device 100 according to the embodiments of the present disclosure, each driving period of the sub-pixel SP may include a first driving period S10, a second driving period S30, a third driving period S11, a fourth driving period S13, a fifth driving period S31, a sixth driving period S33, and a seventh driving period S20.

[0120] The first driving period S10 can be referred to as the period for sensing the characteristic value of the second driving transistor DT2. The second driving period S30 can be referred to as the period for sensing the characteristic value of the first driving transistor DT1. The third driving period S11 can be referred to as the addressing period for driving the first driving transistor DT1. The fourth driving period S13 can be referred to as the emitt period using the first driving transistor DT1. The fifth driving period S31 can be referred to as the addressing period for driving the second driving transistor DT2. The sixth driving period S33 can be referred to as the emitt period using the second driving transistor DT2. The seventh driving period S20 can be referred to as the blank period.

[0121] In the display device 100 according to an embodiment of the present disclosure, during the first driving period S10, the first transmission control signal EM1 may have an on-level voltage, and the second transmission control signal EM2 may have an off-level voltage.

[0122] During the first driving period S10, the first data voltage VDATA1 may have a data voltage VDATA corresponding to the image signal, and the second sensing driving voltage VSEN2 may have a voltage corresponding to the sensing driving voltage VSEN.

[0123] During the first driving period S10, the second scan signal SC2 and the second sensing signal SEN2 may have on-level voltages. The first reference voltage VREF1 may have a voltage corresponding to the reference voltage VREF.

[0124] During the second driving period S30, the second transmit control signal EM2 may have a turn-on level voltage, and the first transmit control signal EM1 may have a turn-off level voltage.

[0125] During the second driving period S30, the second data voltage VDATA2 may have a data voltage VDATA corresponding to the image signal, and the first sensing driving voltage VSEN1 may have a voltage corresponding to the sensing driving voltage VSEN.

[0126] During the second driving period S30, the first scan signal SC1 and the first sensing signal SEN1 may have on-level voltages. The second reference voltage VREF2 may have a voltage corresponding to the reference voltage VREF.

[0127] During the third driving period S11, the first scan signal SC1 and the first sensing signal SEN1 may have a conduction level voltage. During the fourth driving period S13, the first scan signal SC1 and the first sensing signal SEN1 may have a deactivation level voltage.

[0128] During the fifth driving period S31, the second scan signal SC2 and the second sensing signal SEN2 may have on-level voltages. During the sixth driving period S33, the second scan signal SC2 and the second sensing signal SEN2 may have off-level voltages.

[0129] During the seventh driving period S20, the first scan signal SC1, the first sensing signal SEN1, and the second transmit control signal EM2 may have on-level voltages. During the seventh driving period S20, the first transmit control signal EM1, the second scan signal SC2, and the second sensing signal SEN2 may have off-level voltages.

[0130] During the seventh driving period S20, the voltage applied to the first data line DL1 can be changed from the first data voltage VDATA1 corresponding to the data voltage VDATA to the first sensing voltage VSEN1 corresponding to the sensing drive voltage VSEN. During the seventh driving period S20, the voltage applied to the second data line DL2 can be changed from the second sensing voltage VSEN2 corresponding to the sensing drive voltage VSEN to the second data voltage VDATA2 corresponding to the data voltage VDATA.

[0131] During the seventh driving period S20, the voltage applied to the first reference voltage line VREFL1 can be changed from the first reference voltage VREF1 corresponding to the reference voltage VREF to the voltage used to sense the characteristic value of the first driving transistor DT1. During the seventh driving period S20, the voltage applied to the second reference voltage line VREFL2 can be changed from the voltage used to sense the characteristic value of the second driving transistor DT2 to the second reference voltage VREF2 corresponding to the reference voltage VREF.

[0132] The following describes a driving method for each driving period of a display device 100 according to an embodiment of the present disclosure. During a first driving period S10, the display device 100 can use a first driving transistor DT1 to control the light emission of the light-emitting element ED and sense a voltage for sensing the characteristic value of a second driving transistor DT2. During a second driving period S30, the display device 100 can use the second driving transistor DT2 to control the light emission of the light-emitting element ED and sense a voltage for sensing the characteristic value of the first driving transistor DT1. Therefore, the first driving transistor DT1 and the second driving transistor DT2 can alternately control the light emission of the light-emitting element ED, and a sensing period for compensating for changes in the characteristic values ​​of the first driving transistor DT1 and the second driving transistor DT2 is not required.

[0133] During the first driving period S10, the first selection circuit MUX1 can electrically connect the data link line DLL and the first data line DL1. When the data link line DLL and the first data line DL1 are connected, the data voltage VDATA can be applied to the first data line DL1. The first selection circuit MUX1 can also electrically connect the sensing drive link line SLL and the second data line DL2. When the sensing drive link line SLL and the second data line DL2 are electrically connected to each other, the sensing drive voltage VSEN can be applied to the second data line DL2.

[0134] During the first drive period S10, the second selection circuit MUX2 can electrically connect the reference voltage link line RLL and the first reference voltage line VREFL1. When the reference voltage link line RLL and the first reference voltage line VREFL1 are electrically connected to each other, the reference voltage VREF can be applied to the first reference voltage line VREFL1. The second selection circuit MUX2 can also electrically connect the readout line ROL to the second reference voltage line VREFL2. When the readout line ROL and the second reference voltage line VREFL2 are electrically connected to each other, the voltage input to the second reference voltage line VREFL2 can be applied to the readout line ROL. The voltage applied to the readout line ROL can be applied to the analog-to-digital converter (ADC).

[0135] During the second driving period S30, the first selection circuit MUX1 can electrically connect the data link line DLL and the second data line DL2. When the data link line DLL and the second data line DL2 are electrically connected to each other, the data voltage VDATA can be applied to the second data line DL2. The first selection circuit MUX1 can also electrically connect the sensing drive link line SLL and the first data line DL1. When the sensing drive link line SLL and the first data line DL1 are electrically connected to each other, the sensing drive voltage VSEN can be applied to the first data line DL1.

[0136] During the second drive period S30, the second selection circuit MUX2 can electrically connect the reference voltage link line RLL to the second reference voltage. When the reference voltage link line RLL and the second reference voltage line VREFL2 are electrically connected to each other, the reference voltage VREF can be applied to the second reference voltage line VREFL2. The second selection circuit MUX2 can also electrically connect the readout line ROL to the first reference voltage line VREFL1. When the readout line ROL and the first reference voltage line VREFL1 are electrically connected to each other, the voltage input to the first reference voltage line VREFL1 can be applied to the readout line ROL. The voltage applied to the readout line ROL can be applied to the analog-to-digital converter (ADC).

[0137] The data voltage VDATA applied from the data link line DLL can be either a first data voltage VDATA1 or a second data voltage VDATA2. The first data voltage VDATA1 and the second data voltage VDATA2 can have the same voltage level. During the first driving period S10, the first data voltage VDATA1 can be the data voltage VDATA corresponding to the image signal modified using a compensation value used to compensate for degradation based on changes in the characteristic value of the first driving transistor DT1. During the second driving period S30, the second data voltage VDATA2 can be the data voltage VDATA corresponding to the image signal modified using a compensation value used to compensate for degradation based on changes in the characteristic value of the second driving transistor DT2.

[0138] The sensing drive voltage VSEN applied from the sensing drive link SLL can be either a first sensing drive voltage VSEN1 or a second sensing drive voltage VSEN2. The first sensing drive voltage VSEN1 and the second sensing drive voltage VSEN2 can have the same voltage level. The reference voltage VREF applied from the reference voltage link RLL can be either a first reference voltage VREF1 or a second reference voltage VREF2. The first reference voltage VREF1 and the second reference voltage VREF2 can have the same voltage level.

[0139] Figure 5 The third driving period S11 of the first driving period S10 in the driving method of the sub-pixel SP of the display device 100 according to an embodiment of the present disclosure is shown.

[0140] Reference Figure 5 During the third driving period S11, when the first transmit control signal EM1 with a conduction level is applied to the first transmit control signal line EML1, the first transmit control transistor EMT1 and the second transmit control transistor EMT2 can be turned on. When the second transmit control signal EM2 with a turn-off level is applied to the second transmit control signal line EML2, the third transmit control transistor EMT3 and the fourth transmit control transistor EMT4 can be turned off.

[0141] During the third driving period S11, when a first scan signal SC1 with an on level is applied to the first scan signal line SCL1, the first scan transistor SCT1 can be turned on. When the first scan transistor SCT1 is turned on, a first data voltage VDATA1 corresponding to the image signal applied from the first data line DL1 can be applied to the first node N1. When the first emitter control transistor EMT1 is turned on, the first data voltage VDATA1 applied to the first node N1 can be applied to the fourth node N4.

[0142] During the third driving period S11, when a first sensing signal SEN1 with a conduction level voltage is applied to the first sensing signal line SENL1, the first sensing transistor SENT1 can be turned on. When the first sensing transistor SENT1 is turned on, the first reference voltage VREF1 applied from the first reference voltage line VREFL1 can be applied to the second node N2. When the second emitter control transistor EMT2 is turned on, the voltage applied to the second node N2 can be applied to the fifth node N5. Therefore, the storage capacitor CST connected between the fourth node N4 and the fifth node N5 can be charged.

[0143] When the second scan signal SC2, which has an on-level voltage, is applied to the second scan signal line SCL2 during the third drive period S11, the second scan transistor SCT2 can be turned on. When the second scan transistor SCT2 is turned on, the second sensing drive voltage VSEN2 applied from the second data line DL2 can be applied to the sixth node N6.

[0144] When the second sensing drive voltage VSEN2 is applied to the sixth node N6, current can flow from the eighth node N8 of the second drive transistor DT2 to the seventh node N7 of the second drive transistor DT2.

[0145] During the third driving period S11, when the second sensing signal SEN2, which has a conduction level voltage, is applied to the second sensing signal line SENL2, the second sensing transistor SENT2 can be turned on. When the second sensing transistor SENT2 is turned on, current can flow from the seventh node N7 to the second reference voltage line VREFL2.

[0146] The characteristic value of the second drive transistor DT2 can be sensed using the current flowing to the second reference voltage line VREFL2.

[0147] In the following text, for ease of description, the resistances of the first emitter control transistor EMT1, the second emitter control transistor EMT2, the third emitter control transistor EMT3, and the fourth emitter control transistor EMT4 can be ignored. However, it is not intended to exclude the presence of resistances in the first emitter control transistor EMT1, the second emitter control transistor EMT2, the third emitter control transistor EMT3, and the fourth emitter control transistor EMT4, and even in the on-state, the first emitter control transistor EMT1, the second emitter control transistor EMT2, the third emitter control transistor EMT3, and the fourth emitter control transistor EMT4 may have a certain resistive component.

[0148] Figure 6 The fourth driving period S13 of the first driving period S10 in the driving method of the sub-pixel SP of the display device 100 according to an embodiment of the present disclosure is shown.

[0149] Reference Figure 6 During the fourth driving period S13, when the first transmit control signal EM1 with a conduction level is applied to the first transmit control signal line EML1, the first transmit control transistor EMT1 and the second transmit control transistor EMT2 can be turned on. When the second transmit control signal EM2 with a turn-off level is applied to the second transmit control signal line EML2, the third transmit control transistor EMT3 and the fourth transmit control transistor EMT4 can be turned off.

[0150] During the fourth driving period S13, when a first scan signal SC1 with a turn-off level is applied to the first scan signal line SCL1, the first scan transistor SCT1 can be turned off. During the fourth driving period S13, when a first sensing signal SEN1 with a turn-off level voltage is applied to the first sensing signal line SENL1, the first sensing transistor SENT1 can be turned off.

[0151] When the first scanning transistor SCT1 and the first sensing transistor SENT1 are turned off, the first node N1, the second node N2, the fourth node N4, and the fifth node N5 may be electrically floating, and voltage fluctuations may occur. Therefore, current can flow from the third node N3 of the first driving transistor DT1 to the light-emitting element ED. When current flows to the light-emitting element ED, the light-emitting element ED can emit light.

[0152] When the second scan signal SC2, which has an on-level voltage, is applied to the second scan signal line SCL2 during the fourth drive period S13, the second scan transistor SCT2 can be turned on. When the second scan transistor SCT2 is turned on, the second sensing drive voltage VSEN2 applied from the second data line DL2 can be applied to the sixth node N6.

[0153] When the second sensing drive voltage VSEN2 is applied to the sixth node N6, current can flow from the eighth node N8 of the second drive transistor DT2 to the seventh node N7 of the second drive transistor DT2.

[0154] During the fourth driving period S13, when the second sensing signal SEN2, which has a conduction level voltage, is applied to the second sensing signal line SENL2, the second sensing transistor SENT2 can be turned on. When the second sensing transistor SENT2 is turned on, current can flow from the seventh node N7 to the second reference voltage line VREFL2.

[0155] The characteristic value of the second driving transistor DT2 can be sensed using the current flowing to the second reference voltage line VREFL2. Therefore, when the characteristic value of the second driving transistor DT2 is sensed, the light-emitting element ED can emit light through the current flowing from the first driving transistor DT1.

[0156] Figure 7 The fifth driving period S31 of the second driving period S30 in the driving method of the sub-pixel SP of the display device 100 according to an embodiment of the present disclosure is shown.

[0157] Reference Figure 7 During the fifth driving period S31, when the second transmit control signal EM2, which has a conduction level, is applied to the second transmit control signal line EML2, the third transmit control transistor EMT3 and the fourth transmit control transistor EMT4 can be turned on. When the first transmit control signal EM1, which has a turn-off level, is applied to the first transmit control signal line EML1, the first transmit control transistor EMT1 and the second transmit control transistor EMT2 can be turned off.

[0158] During the fifth driving period S31, when the second scan signal SC2, which has an on level, is applied to the second scan signal line SCL2, the second scan transistor SCT2 can be turned on. When the second scan transistor SCT2 is turned on, the second data voltage VDATA2, corresponding to the image signal applied from the second data line DL2, can be applied to the sixth node N6. When the third emitter control transistor EMT3 is turned on, the second data voltage VDATA2 applied to the sixth node N6 can be applied to the fourth node N4.

[0159] During the fifth driving period S31, when the second sensing signal SEN2, which has a conduction level voltage, is applied to the second sensing signal line SENL2, the second sensing transistor SENT2 can be turned on. When the second sensing transistor SENT2 is turned on, the second reference voltage VREF2 applied from the second reference voltage line VREFL2 can be applied to the seventh node N7. When the fourth emitter control transistor EMT4 is turned on, the voltage applied to the seventh node N7 can be applied to the fifth node N5. Therefore, the storage capacitor CST connected between the fourth node N4 and the fifth node N5 can be charged.

[0160] When a first scan signal SC1 with a conduction level voltage is applied to the first scan signal line SCL1 during the fifth drive period S31, the first scan transistor SCT2 can be turned on. When the first scan transistor SCT1 is turned on, the first sensing drive voltage VSEN1 applied from the first data line DL1 can be applied to the first node N1.

[0161] When the first sensing drive voltage VSEN1 is applied to the first node N1, current can flow from the third node N3 of the first drive transistor DT1 to the second node N2 of the first drive transistor DT1.

[0162] During the fifth driving period S31, when a first sensing signal SEN1 with a conduction level voltage is applied to the first sensing signal line SENL1, the first sensing transistor SENT1 can be turned on. When the first sensing transistor SENT1 is turned on, current can flow from the second node N2 to the first reference voltage line VREFL1.

[0163] The characteristic value of the second driving transistor DT2 can be sensed using the current flowing to the second reference voltage line VREFL2. Therefore, when the characteristic value of the second driving transistor DT2 is sensed, the light-emitting element ED can emit light through the current flowing from the first driving transistor DT1.

[0164] Figure 8 The sixth driving period S33 of the second driving period S30 in the driving method of the sub-pixel SP of the display device 100 according to an embodiment of the present disclosure is shown.

[0165] Reference Figure 8 During the sixth driving period S33, when the second transmit control signal EM2, which has an on level, is applied to the second transmit control signal line EML2, the third transmit control transistor EMT3 and the fourth transmit control transistor EMT4 can be turned on. When the first transmit control signal EM1, which has an off level, is applied to the first transmit control signal line EML1, the first transmit control transistor EMT1 and the second transmit control transistor EMT2 can be turned off.

[0166] During the sixth driving period S33, when the second scan signal SC2 with a turn-off level is applied to the second scan signal line SCL2, the second scan transistor SCT2 can be turned off. During the sixth driving period S33, when the second sensing signal SEN2 with a turn-off level voltage is applied to the second sensing signal line SENL2, the second sensing transistor SENT2 can be turned off.

[0167] When the second scanning transistor SCT2 and the second sensing transistor SENT2 are turned off, the sixth node N6, the seventh node N7, the fourth node N4, and the fifth node N5 can be electrically floated and voltage fluctuations can occur. Therefore, current can flow from the eighth node N8 of the second driving transistor DT2 to the light-emitting element ED. When current flows to the light-emitting element ED, the light-emitting element ED can emit light.

[0168] During the sixth driving period S33, when a first scan signal SC1 with a conduction level voltage is applied to the first scan signal line SCL1, the first scan transistor SCT1 can be turned on. When the first scan transistor SCT1 is turned on, the first sensing drive voltage VSEN1 applied from the first data line DL1 can be applied to the first node N1.

[0169] When the first sensing drive voltage VSEN1 is applied to the first node N1, current can flow from the third node N3 of the first drive transistor DT1 to the second node N2 of the first drive transistor DT1.

[0170] During the sixth driving period S33, when a first sensing signal SEN1 with a conduction level voltage is applied to the first sensing signal line SENL1, the first sensing transistor SENT1 can be turned on. When the first sensing transistor SENT1 is turned on, current can flow from the second node N2 to the first reference voltage line VREFL1.

[0171] The characteristic value of the first driving transistor DT1 can be sensed using the current flowing to the first reference voltage line VREFL1. Therefore, when the characteristic value of the first driving transistor DT1 is sensed, the light-emitting element ED can emit light through the current flowing from the second driving transistor DT2.

[0172] The following is a brief description of implementation methods of the disclosure described above.

[0173] A display device may include a plurality of sub-pixels, a plurality of data lines, and a plurality of reference voltage lines.

[0174] Each of the plurality of sub-pixels may include: a light-emitting element, the light-emitting element including a pixel electrode, an intermediate layer, and a common electrode; a first driving transistor connected between a second node and a third node and configured to switch based on a voltage applied to a first node to drive the light-emitting element; a first scanning transistor connected between a first data line of the plurality of data lines and the first node and configured to switch based on a first scanning signal; a first sensing transistor connected between a first reference voltage line of the plurality of reference voltage lines and the second node and configured to switch based on a first sensing signal; a first emission control transistor connected between the first node and a fourth node and configured to switch based on a first emission control signal; a second emission control transistor connected between the second node and a fifth node and configured to switch based on the first emission control signal; and a storage capacitor electrically connected between the fourth node and the fifth node.

[0175] The first gate node of the first emitter control transistor and the second gate node of the second emitter control transistor can be connected.

[0176] The display device may further include: a second driving transistor connected between a seventh node and an eighth node and configured to switch based on a voltage applied to a sixth node to drive the light-emitting element; a second scanning transistor connected between a second data line of the plurality of data lines and the sixth node and configured to switch based on a second scanning signal; a second sensing transistor connected between a second reference voltage line of the plurality of reference voltage lines and the seventh node and configured to switch based on a second sensing signal; a third emission control transistor connected between the sixth node and the fourth node and configured to switch based on a second emission control signal; and a fourth emission control transistor connected between the seventh node and the fifth node and configured to switch based on the second emission control signal.

[0177] The third gate node of the third emitter control transistor and the fourth gate node of the fourth emitter control transistor can be connected.

[0178] The display device may include: a data link line connected to receive a data voltage; a sensing drive link line connected to receive a sensing drive voltage; a reference voltage link line connected to receive a reference voltage; an analog-to-digital converter; a readout line connected to the analog-to-digital converter; a first selection circuit electrically connecting one of the data link line or the sensing drive link line to one of the first data line or the second data line; and a second selection circuit electrically connecting one of the reference voltage link line or the readout line to one of the first reference voltage line or the second reference voltage line.

[0179] During the first driving period, the first selection circuit can electrically connect the data link line and the first data line, and can also electrically connect the second data line from the sensing drive link line.

[0180] The second selection circuit can electrically connect the reference voltage link line and the first reference voltage line, and can also electrically connect the readout line and the second reference voltage line.

[0181] During the second driving period, the first selection circuit can electrically connect the data link line and the second data line, and can also electrically connect the first data line from the sensing drive link line.

[0182] The second selection circuit can electrically connect the reference voltage link line and the second reference voltage line, and can also electrically connect the readout line and the first reference voltage line.

[0183] During the first driving period, the first emitter control transistor and the second emitter control transistor can be turned on as a first emitter control signal with an on-level voltage is supplied to the first gate node and the second gate node.

[0184] During the first driving period, the first node and the fourth node may be electrically connected when the first emitter control transistor is turned on, and the second node and the fifth node may be electrically connected when the second emitter control transistor is turned on.

[0185] During the first driving period, the third emitter control transistor and the fourth emitter control transistor can be turned off as a second emitter control signal with a turn-off level is supplied to the third gate node and the fourth gate node.

[0186] During the first driving period, the sixth node and the fourth node can be electrically disconnected when the third emitter control transistor is turned off, and the seventh node and the fifth node can be electrically disconnected when the fourth emitter control transistor is turned off.

[0187] During the second driving period, the third emitter control transistor and the fourth emitter control transistor can be turned on by supplying the second emitter control signal with an on level to the third gate node and the fourth gate node.

[0188] During the second driving period, the sixth node and the fourth node can be electrically connected when the third emitter control transistor is turned on, and the seventh node and the fifth node can be electrically connected when the fourth emitter control transistor is turned on.

[0189] During the second driving period, the first emitter control transistor and the second emitter control transistor can be turned off as a first emitter control signal with a turn-off level is supplied to the first gate node and the second gate node.

[0190] During the second driving period, the first node and the fourth node can be electrically disconnected when the first emitter control transistor is turned off, and the second node and the fifth node can be electrically disconnected when the second emitter control transistor is turned off.

[0191] During the first driving period, the second scan transistor can be turned on as a second scan signal with an on level is supplied to the gate node of the second scan transistor.

[0192] During the first driving period, the second sensing driving voltage can be supplied from the second data line to the sixth node as the second scanning transistor is turned on.

[0193] During the second driving period, the first scan transistor can be turned on as a first scan signal with an on level is supplied to the gate node of the first scan transistor.

[0194] During the second driving period, the first sensing driving voltage can be supplied from the first data line to the first node as the first scanning transistor is turned on.

[0195] During the first driving period, the second sensing transistor can be turned on as a second sensing signal with a conduction level is supplied to the gate node of the second sensing transistor.

[0196] During the first driving period, voltage can be applied from the seventh node to the second reference voltage line as the second sensing transistor is turned on.

[0197] During the second driving period, the first sensing transistor can be turned on as a first sensing signal with an on level is supplied to the gate node of the first sensing transistor.

[0198] During the second driving period, voltage can be applied from the second node to the first reference voltage line as the first sensing transistor is turned on.

[0199] The first driving period may include a third driving period and a fourth driving period.

[0200] During the third driving period, the first scan transistor may be turned on as a first scan signal with a turn-on level voltage is supplied to the gate node of the first scan transistor.

[0201] During the third driving period, the first data voltage can be supplied from the first data line to the first node as the first scan transistor is turned on.

[0202] During the third driving period, the first sensing transistor can be turned on as a first sensing signal having a turn-on voltage is supplied to the gate node of the first sensing transistor.

[0203] During the third driving period, a second reference voltage can be supplied from the first reference voltage line to the second node as the first sensing transistor is turned on.

[0204] During the fourth driving period, the first scan transistor can be turned off as a first scan signal with a turn-off level voltage is supplied to the gate node of the first scan transistor.

[0205] During the fourth driving period, the first sensing transistor can be turned off as a first sensing signal with a turn-off level voltage is supplied to the gate node of the first sensing transistor.

[0206] During the fourth driving period, the first node and the second node may be electrically floated as the first scanning transistor and the first sensing transistor are turned off.

[0207] During the fourth driving period, the second driving period may include a fifth driving period and a sixth driving period.

[0208] During the fifth driving period, the second scan transistor may be turned on as a second scan signal with an on-level voltage is supplied to the gate node of the second scan transistor.

[0209] During the fifth driving period, the second data voltage can be supplied from the second data line to the sixth node as the second scan transistor is turned on.

[0210] During the fifth driving period, the second sensing transistor may be turned on as a second sensing signal with a turn-on level voltage is supplied to the gate node of the second sensing transistor.

[0211] During the fifth driving period, the second reference voltage can be supplied from the second reference voltage line to the seventh node as the second sensing transistor is turned on.

[0212] During the sixth driving period, the second scan transistor can be turned off as a second scan signal with a turn-off level voltage is supplied to the gate node of the second scan transistor.

[0213] During the sixth driving period, the second sensing transistor can be turned off as a second sensing signal with a turn-off level voltage is supplied to the gate node of the second sensing transistor.

[0214] During the sixth driving period, the sixth node and the seventh node may be electrically floated as the second scanning transistor and the second sensing transistor are turned off.

[0215] A display device may include: a first sub-pixel; a first data line connected to the first sub-pixel; a second data line connected to the first sub-pixel; a first reference voltage line connected to the first sub-pixel; a second reference voltage line connected to the first sub-pixel; a data link line connected to receive a data voltage; a sensing drive link line connected to receive a sensing drive voltage; and a first selection circuit that electrically connects one of the data link line or the sensing drive link line to one of the first data line or the second data line.

[0216] The display device may include: a reference voltage link line connected to receive a reference voltage; an analog-to-digital converter; a readout line connected to the analog-to-digital converter; and a second selection circuit that electrically connects one of the reference voltage link line or the readout line to one of the first reference voltage line or the second reference voltage line.

[0217] The first sub-pixel may include: a light-emitting element comprising a pixel electrode, an intermediate layer, and a common electrode; a first driving transistor connected between a second node and a third node and configured to switch based on a voltage applied to the first node to drive the light-emitting element; a first scanning transistor connected between a first data line of the plurality of data lines and the first node and configured to switch based on a first scanning signal; a first sensing transistor connected between a first reference voltage line of the plurality of reference voltage lines and the second node and configured to switch based on a first sensing signal; a first emission control transistor connected between the first node and a fourth node and configured to switch based on a first emission control signal; a second emission control transistor connected between the second node and a fifth node and configured to switch based on the first emission control signal; and a storage capacitor electrically connected between the fourth node and the fifth node.

[0218] The first gate node of the first emitter control transistor and the second gate node of the second emitter control transistor can be connected.

[0219] The first sub-pixel may include: a light-emitting element, the light-emitting element including a pixel electrode, a light-emitting layer and a common electrode; a first driving transistor, the first driving transistor being connected between the first driving voltage line and the pixel electrode and configured to switch based on a first gate voltage; and a second driving transistor, the second driving transistor being connected between the second driving voltage line and the pixel electrode and configured to switch based on a second gate voltage different from the first gate voltage.

[0220] A sub-pixel may include: a light-emitting element comprising a pixel electrode, a light-emitting layer, and a common electrode; a first driving transistor connected between a first driving voltage line and the pixel electrode and configured to switch based on a first gate voltage; and a second driving transistor connected between a second driving voltage line and the pixel electrode and configured to switch based on a second gate voltage different from the first gate voltage.

[0221] The sub-pixel may further include: a first emission control transistor connected between the first driving transistor and the pixel electrode, and configured to switch based on a first emission control signal; a second emission control transistor having a second gate node connected to a first gate node of the first emission control transistor and configured to turn on or off based on the first emission control signal; a third emission control transistor connected between the second driving transistor and the pixel electrode, and configured to turn on or off based on a second emission control signal; and a fourth emission control transistor having a fourth gate node connected to the third gate node of the third emission control transistor and configured to turn on or off based on the second emission control signal.

[0222] During the first driving period, a first data voltage can be applied to the fifth gate node from a first data line electrically connected to the fifth gate node of the first driving transistor, and a second sensing driving voltage can be applied to the sixth gate node from a second data line electrically connected to the sixth gate node of the second driving transistor.

[0223] During the second driving period, a first sensing drive voltage can be applied from the first data line to the fifth gate node, and a second data voltage can be applied from the second data line to the sixth gate node.

[0224] The above description is presented to enable any person skilled in the art to make and use the technical concepts of this disclosure, and is provided in the context of a particular application and its requirements. Various modifications, additions, and substitutions to the described embodiments will be readily apparent to those skilled in the art, and the general principles defined herein can be applied to other embodiments and applications without departing from the spirit and scope of this disclosure. The above description and accompanying drawings are provided as examples of the technical concepts of this disclosure for illustrative purposes only. That is, the disclosed embodiments are intended to illustrate the scope of the technical concepts of this disclosure.

[0225] The embodiments described above can be combined to provide other embodiments. Modifications to various aspects of these embodiments may be made as necessary to provide other embodiments using the concepts of each embodiment.

[0226] Based on the detailed description above, these and other modifications can be made to these embodiments. Generally, the terminology used in the appended claims should not be construed as limiting the claims to the specific embodiments disclosed in the specification and claims, but should be interpreted to include all possible embodiments and the full scope of equivalents entitled to be obtained by these claims. Therefore, the claims are not limited by this disclosure.

Claims

1. A display device, comprising: Multiple sub-pixels; Multiple data cables; as well as Multiple reference voltage lines, wherein each of the multiple sub-pixels includes: A light-emitting element, the light-emitting element comprising a pixel electrode, an intermediate layer, and a common electrode; A first driving transistor is connected between a second node and a third node and is configured to switch based on a voltage applied to the first node to drive the light-emitting element; A first scanning transistor is connected between a first data line of the plurality of data lines and the first node and is configured to switch based on a first scanning signal; A first sensing transistor is connected between a first reference voltage line and the second node in the plurality of reference voltage lines and is configured to switch based on a first sensing signal; A first emitter control transistor is connected between the first node and the fourth node and is configured to switch based on a first emitter control signal; A second emitter control transistor, connected between the second node and the fifth node and configured to switch based on the first emitter control signal; and A storage capacitor, which is electrically connected between the fourth node and the fifth node, and The first gate node of the first emitter control transistor and the second gate node of the second emitter control transistor are connected.

2. The display device according to claim 1, further comprising: A second driving transistor, connected between the seventh and eighth nodes and configured to switch based on the voltage applied to the sixth node, drives the light-emitting element. The second scanning transistor is connected between the second data line of the plurality of data lines and the sixth node and is configured to switch based on the second scanning signal; The second sensing transistor is connected between the second reference voltage line of the plurality of reference voltage lines and the seventh node and is configured to switch based on the second sensing signal; A third emitter control transistor is connected between the sixth node and the fourth node and is configured to switch based on a second emitter control signal; as well as A fourth emitter control transistor, connected between the seventh node and the fifth node and configured to switch based on the second emitter control signal, and The third gate node of the third emitter control transistor and the fourth gate node of the fourth emitter control transistor are connected.

3. The display device according to claim 2, further comprising: A data link line, which is connected to receive data voltage; A sensing drive link line is connected to receive a sensing drive voltage; A reference voltage link line is connected to receive a reference voltage; Analog-to-digital converter; A readout line, which is connected to the analog-to-digital converter; A first selection circuit electrically connects one of the data link line or the sensing drive link line to one of the first data line or the second data line. as well as A second selection circuit electrically connects one of the reference voltage link line or the readout line to one of the first reference voltage line or the second reference voltage line.

4. The display device according to claim 3, wherein, During the first driving period, the first selection circuit electrically connects the data link line and the first data line, and electrically connects the second data line and the sensing drive link line; the second selection circuit electrically connects the reference voltage link line and the first reference voltage line, and electrically connects the readout line and the second reference voltage line.

5. The display device according to claim 4, wherein, During the second driving period, the first selection circuit electrically connects the data link line and the second data line, and electrically connects the first data line and the sensing drive link line; the second selection circuit electrically connects the reference voltage link line and the second reference voltage line, and electrically connects the readout line and the first reference voltage line.

6. The display device according to claim 2, wherein, During the first driving period, the first emitter control transistor and the second emitter control transistor are turned on when the first emitter control signal with an on-level voltage is supplied to the first gate node and the second gate node, respectively. The first node and the fourth node are electrically connected when the first emitter control transistor is turned on, the second node and the fifth node are electrically connected when the second emitter control transistor is turned on, the third emitter control transistor and the fourth emitter control transistor are turned off when the second emitter control signal with an off-level voltage is supplied to the third gate node and the fourth gate node, the sixth node and the fourth node are electrically disconnected when the third emitter control transistor is turned off, and the seventh node and the fifth node are electrically disconnected when the fourth emitter control transistor is turned off.

7. The display device according to claim 6, wherein, During the second driving period, the third and fourth emitter control transistors are turned on when a second emitter control signal with an on level is supplied to the third and fourth gate nodes, respectively. The sixth node is electrically connected to the fourth node when the third emitter control transistor is turned on, and the seventh and fifth nodes are electrically connected when the fourth emitter control transistor is turned on. The first and second emitter control transistors are turned off when a first emitter control signal with an off level is supplied to the first and second gate nodes, respectively. The first node is electrically disconnected from the fourth node when the first emitter control transistor is turned off, and the second node is electrically disconnected from the fifth node when the second emitter control transistor is turned off.

8. The display device according to claim 7, wherein, During the first driving period, the second scan transistor is turned on when a second scan signal with an on level is supplied to the gate node of the second scan transistor, and a second sensing drive voltage is supplied from the second data line to the sixth node when the second scan transistor is turned on; and during the second driving period, the first scan transistor is turned on when a first scan signal with an on level is supplied to the gate node of the first scan transistor, and a first sensing drive voltage is supplied from the first data line to the first node when the first scan transistor is turned on.

9. The display device according to claim 7, wherein, During the first driving period, the second sensing transistor is turned on when a second sensing signal with an on level is supplied to the gate node of the second sensing transistor, and a voltage is applied from the seventh node to the second reference voltage line as the second sensing transistor is turned on. During the second driving period, the first sensing transistor is turned on when a first sensing signal with an on level is supplied to the gate node of the first sensing transistor, and a voltage is applied from the second node to the first reference voltage line when the first sensing transistor is turned on.

10. The display device according to claim 7, wherein, The first driving period includes a third driving period and a fourth driving period, and During the third driving period, the first scan transistor is turned on by a first scan signal having an on-level voltage supplied to its gate node; a first data voltage is supplied from the first data line to the first node as the first scan transistor is turned on; the first sensing transistor is turned on by a first sensing signal having an on-level voltage supplied to its gate node; and a second reference voltage is supplied from the first reference voltage line to the second node as the first sensing transistor is turned on. During the fourth driving period, the first scanning transistor is turned off as a first scanning signal with a turn-off level voltage is supplied to the gate node of the first scanning transistor, the first sensing transistor is turned off as a first sensing signal with a turn-off level voltage is supplied to the gate node of the first sensing transistor, and the first node and the second node are electrically floated as the first scanning transistor and the first sensing transistor are turned off.

11. The display device according to claim 7, wherein, The second driving period includes the fifth driving period and the sixth driving period, and During the fifth driving period, the second scan transistor is turned on by a second scan signal having an on-level voltage supplied to its gate node; a second data voltage is supplied from the second data line to the sixth node as the second scan transistor is turned on; the second sensing transistor is turned on by a second sensing signal having an on-level voltage supplied to its gate node; and a second reference voltage is supplied from the second reference voltage line to the seventh node as the second sensing transistor is turned on. During the sixth driving period, the second scan transistor is turned off as a second scan signal with a turn-off level voltage is supplied to the gate node of the second scan transistor, the second sensing transistor is turned off as a second sensing signal with a turn-off level voltage is supplied to the gate node of the second sensing transistor, and the sixth node and the seventh node are electrically floated as the second scan transistor and the second sensing transistor are turned off.

12. A display device, comprising: First sub-pixel; A first data line is connected to the first sub-pixel; The second data line is connected to the first sub-pixel; A first reference voltage line is connected to the first sub-pixel; A second reference voltage line is connected to the first sub-pixel; A data link line, which is connected to receive data voltage; A sensing drive link line is connected to receive a sensing drive voltage; as well as A first selection circuit electrically connects one of the data link line or the sensing drive link line to one of the first data line or the second data line.

13. The display device according to claim 12, comprising A reference voltage link line is connected to receive a reference voltage; Analog-to-digital converter; A readout line, which is connected to the analog-to-digital converter; as well as A second selection circuit electrically connects one of the reference voltage link line or the readout line to one of the first reference voltage line or the second reference voltage line.

14. The display device according to claim 12, wherein, The first sub-pixel includes: A light-emitting element, the light-emitting element comprising a pixel electrode, an intermediate layer, and a common electrode; A first driving transistor is connected between a second node and a third node and is configured to switch based on a voltage applied to the first node to drive the light-emitting element; A first scanning transistor is connected between a first data line of the plurality of data lines and the first node and is configured to switch based on a first scanning signal; A first sensing transistor is connected between a first reference voltage line and the second node in the plurality of reference voltage lines and is configured to switch based on a first sensing signal; A first emitter control transistor is connected between the first node and the fourth node and is configured to switch based on a first emitter control signal; A second emitter control transistor, connected between the second node and the fifth node and configured to switch based on the first emitter control signal; and A storage capacitor, which is electrically connected between the fourth node and the fifth node, and The first gate node of the first emitter control transistor and the second gate node of the second emitter control transistor are connected.

15. The display device according to claim 12, wherein, The first sub-pixel includes: A light-emitting element, comprising a pixel electrode, a light-emitting layer, and a common electrode; A first driving transistor, connected between the first driving voltage line and the pixel electrode and configured to switch based on a first gate voltage; and The second driving transistor is connected between the second driving voltage line and the pixel electrode and is configured to switch based on a second gate voltage different from the first gate voltage.

16. A sub-pixel, comprising: A light-emitting element, comprising a pixel electrode, a light-emitting layer, and a common electrode; A first driving transistor is connected between the first driving voltage line and the pixel electrode and is configured to switch based on a first gate voltage; as well as The second driving transistor is connected between the second driving voltage line and the pixel electrode and is configured to switch based on a second gate voltage different from the first gate voltage.

17. The sub-pixel of claim 16, further comprising: A first emission control transistor is connected between the first driving transistor and the pixel electrode and is configured to switch based on a first emission control signal; A second emitter control transistor having a second gate node and configured to switch based on the first emitter control signal, the second gate node being connected to the first gate node of the first emitter control transistor; A third emission control transistor is connected between the second driving transistor and the pixel electrode and is configured to be turned on or off based on a second emission control signal. as well as A fourth emitter control transistor having a fourth gate node and configured to be turned on or off based on the second emitter control signal, the fourth gate node being connected to the third gate node of the third emitter control transistor.

18. The sub-pixel according to claim 17, in, During the first driving period, a first data voltage is applied to the fifth gate node from a first data line electrically connected to the fifth gate node of the first driving transistor, and a second sensing driving voltage is applied to the sixth gate node from a second data line electrically connected to the sixth gate node of the second driving transistor. During the second driving period, a first sensing drive voltage is applied from the first data line to the fifth gate node, and a second data voltage is applied from the second data line to the sixth gate node.

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