Electrical device and method for manufacturing same

Abstract

The invention relates to an electrical device and a manufacturing method thereof. The proposed device (100) comprises a capacitor comprising a porous structure (300), the porous structure (300) comprising: a first electrode region (310) comprising first pores (311), where the first pores (311) comprise a first electrically conductive wire (312); a second electrode region (320) including second holes (321), where the second holes (321) include second electrically conductive wires (322); and a dielectric region (330) including a third hole (331) and interposed between the first electrode region (310) and the second electrode region (320), in which the capacitor is formed by facing the first hole (311) of the first electrode region (310) and the second hole (321) of the second electrode region (320) to each other and being separated by the third hole (331) of the dielectric region (330).

Description

Electrical apparatus and methods of manufacture thereof Technical Field

[0001] This invention relates to the field of electrical apparatus. More specifically, this invention relates to electrical apparatus including capacitors and methods of manufacturing the same. Background Technology

[0002] This invention is particularly relevant in the context of electrical devices that include capacitors with high capacitance density and suitable for high-voltage applications.

[0003] In this context, a capacitor application EP 3 992 999 A1 (hereinafter referred to as EP999, and which is incorporated herein by reference) has been filed. As shown in FIG1, the capacitor CAP is formed using a porous structure 105. The latter is filled with a dielectric material 109 to form the capacitor dielectric 112. The capacitor electrodes 111A-111B are formed using trenches 107A-107B etched in the porous structure 105 and filled with a conductive material 111.

[0004] The capacitor proposed in EP999 is particularly advantageous because it enables the deposition of dielectric material 109 in the pores of the porous structure 105 using thin-layer deposition techniques such as atomic layer deposition (ALD) to obtain a thick capacitor dielectric 112 capable of withstanding high voltages.

[0005] However, emerging applications such as electric vehicles require even higher capacitance densities and the ability to reliably withstand even higher voltages (e.g., over 900 V or 1200 V).

[0006] Therefore, the present invention aims to improve the capacitor of application EP999 to achieve higher capacitance density and withstand higher voltage. Summary of the Invention

[0007] According to one side The present invention provides an electrical device including a capacitor, the capacitor including a porous structure, the porous structure comprising:

[0008] - A first capacitor electrode region including a first hole, wherein the first hole in the region includes a first conductive wire (partially or completely filled by the first conductive wire).

[0009] - A second capacitor electrode region including a second hole, wherein the second hole in this region includes a second conductive wire (partially or completely filled by the second conductive wire) (the first capacitor electrode region and the second capacitor electrode region are non-intersecting regions, the first hole and the second hole are different holes, and the first conductive wire and the second conductive wire are different wires), and

[0010] - A capacitor dielectric region, including a third hole and inserted between the first capacitor electrode region and the second capacitor electrode region.

[0011] The capacitor is formed by having a first hole in the first capacitor electrode region and a second hole in the second capacitor electrode region facing each other and separated by a third hole in the capacitor dielectric region.

[0012] This invention proposes forming capacitor electrodes by growing conductive nanowires in the pores of a porous structure (e.g., anodized aluminum oxide structure). This provides several advantages (in addition to the advantages of the capacitors described in EP999).

[0013] First, the proposed electrical device enables higher capacitance density to be achieved.

[0014] In the capacitor for which EP999 is applied, electrodes are formed by depositing conductive material in trenches using electrodeposition (ELD). As detailed below, this deposition technique limits the maximum thickness that can be used in porous structures (unless the trenches are widened, but this would reduce the capacitance density).

[0015] In contrast, the capacitor electrodes of the proposed electrical device are formed by growing nanowires (e.g., using ALD) in the pores of a porous structure. This can be achieved even for particularly thick porous structures. The porous structures in the proposed device can be 10 μm, 50 μm, 100 μm, or even 200 μm thick.

[0016] Therefore, the proposed device enables the formation of a capacitor using a porous structure that is thicker than that of the capacitor in application EP999. Consequently, the capacitor of the proposed device has electrodes with a larger surface area facing each other in the vertical direction (i.e., along the z-axis), and thus has a higher capacitance density.

[0017] Secondly, the proposed device enables the reduction of mechanical stress.

[0018] In the capacitor for which EP999 is applied, the electrodes are formed by completely filling the trenches in a porous structure with conductive material. Such monolithic electrodes may cause mechanical stress to build up within the capacitor.

[0019] In contrast, the use of nanowires arranged within the pores alleviates mechanical stress within the capacitor structure. This helps prevent cracking, thus enabling reliable withstand of high voltages.

[0020] For these reasons, the present invention provides an electrical device comprising a capacitor having high capacitance density and capable of reliably withstanding high voltage.

[0021] In a specific implementationThe first conductive wire and the second conductive wire (completely) fill the first hole and the second hole of the first capacitor electrode region and the second capacitor electrode region.

[0022] In this embodiment, the pores in the electrode region of the porous structure are completely filled with conductive wires. That is, there is no empty volume at the center of the pores in the electrode region. This helps to reduce the resistance of the capacitor along the vertical direction (i.e., along the z-axis).

[0023] In a specific implementation The first conductive wire and the second conductive wire (only) partially fill the first hole and the second hole of the first capacitor electrode region and the second capacitor electrode region, and the volume in the center of these holes remains empty (void).

[0024] In this embodiment, the conductive wire does not completely fill the hole in the electrode region. That is, the center of the hole remains unfilled. This embodiment offers several advantages. It allows for a reduction in the time required to manufacture the electrical device (eliminating the need to grow wires until the hole is completely filled). It also helps to further reduce mechanical stress within the capacitor.

[0025] In a specific implementation The capacitor also includes:

[0026] - A first connection region comprising (filled with) a conductive material (e.g., tungsten, aluminum, or copper) electrically connecting first conductive wires that electrically connect (different) first holes of the first capacitor electrode region, and

[0027] - A second connection region comprising (filled with) a conductive material (e.g., tungsten, aluminum, or copper) that electrically connects the second conductive wires of the (different) second holes of the second capacitor electrode region.

[0028] In this embodiment, a connection area filled with conductive material is used to connect conductive wires from different holes. This makes it possible to electrically connect the wires forming capacitor electrodes.

[0029] In a specific implementation The first capacitor electrode region and the second capacitor electrode region of the porous structure include a first recess and a second recess, respectively, such that the top surface (highest surface) of the first hole and the second hole is located below the top surface (highest surface) of the porous structure.

[0030] Furthermore, the first connection region and the second connection region extend (partially or completely fill) the recesses of the first capacitor electrode region and the second capacitor electrode region, respectively, such that the top surfaces (highest surfaces) of the first connection region and the second connection region are located below or (substantially) horizontally to the top surface of the porous structure.

[0031] Here, the connection region (which electrically connects the conductive wires forming the capacitor electrodes) is confined within the porous structure. Specifically, the connection region extends within the recesses of the capacitor electrode region but does not protrude above the porous structure.

[0032] Thus, most of the electrostatic field is confined within the porous structure (including the desired dielectric), which allows most of the electrostatic field to be kept outside structural weaknesses (i.e., geometric singularities, weaker layers). This implementation prevents localized increases in the electrostatic field, thereby reducing leakage current in the capacitor. This contributes to reliable withstand of high voltages.

[0033] Alternative implementations are conceivable. As detailed below, the connection regions can be located at other locations within the capacitor. For example, they can extend above and / or below the porous structure (instead of within the recesses of the porous structure).

[0034] In a specific implementation The thicknesses of the first and second connection regions are between 100 nm and 3 μm.

[0035] The thickness of the connection region along the vertical direction (i.e., along the z-axis) represents a trade-off between (i) the manufacturing time required to form recesses in the porous structure and deposit conductive material to fill these recesses, and (ii) the resistance of the capacitor in the horizontal plane (i.e., in the xy plane). Therefore, the thickness of the connection region should be determined based on the intended application of the capacitor.

[0036] If the capacitor resistance is not critical for the intended application, the connection region can be relatively thin (e.g., between 100 nm and 1 μm) to ensure rapid fabrication. Conversely, if the intended application requires minimal capacitor resistance, the connection region can be thicker (e.g., between 1 μm and 3 μm).

[0037] In a specific implementation The porous structure includes holes extending to the lateral edge (die edge) of the electrical device (using a monolithic porous structure).

[0038] This implementation proposes the use of a monolithic porous structure. This has several advantages.

[0039] First, it simplifies the manufacturing process of the proposed electrical device. Various manufacturing steps can be performed on the entire sheet, and therefore less patterning is required. Patterning leads to the formation of surface irregularities (or requires appropriate treatments such as chemical-mechanical polishing to eliminate these irregularities). For this reason, this implementation (which requires less patterning) allows the different layers forming the capacitor to maintain a flatter surface.

[0040] Secondly, let us consider using anodized aluminum oxide (AAO) structures to form the proposed electrical device.

[0041] If the structure does not have pores across its entire surface (it is not a monolithic porous structure), then structural expansion occurs at the transition between the aluminum region and the AAO region. More specifically, during the anodizing process used to form the porous AAO structure, the aluminum absorbs oxygen atoms and expands. Referring to Figure 1, at the interface between the porous AAO region 105 and the remaining aluminum region 102, this volume difference causes layer 103 to deform. This can lead to cracks in the structure and many surface irregularities that are often difficult to remove. The degree of this expansion is related to the thickness of the structure. For this reason, the maximum thickness of the structure that can be used will be limited to prevent cracking.

[0042] In contrast, the use of an AAO structure with pores across its entire surface (which is a monolithic porous structure) overcomes this limitation. Surface irregularities can be significantly reduced through monolithic anodizing because the flatness issue shifts from the capacitance region to the wafer edge (where no product is being manufactured, and therefore cracks are unlikely to be a problem). A significantly thicker porous structure can then be used, which increases capacitance density.

[0043] Third, this implementation enables the use of porous structures manufactured in situ and then placed on a substrate.

[0044] In a specific implementation The third hole of the capacitor dielectric region, in whole or in part, contains (completely or partially filled) dielectric material (e.g., silicon oxide and / or hafnium oxide and / or aluminum oxide).

[0045] This implementation enables stronger dielectric strength and helps to reliably withstand high voltages.

[0046] Alternatively, it is conceivable to keep the holes in the dielectric region of the capacitor empty. Dielectric regions with holes (in the case of achieving a vacuum during manufacturing) can have sufficient dielectric strength for certain applications. This simplifies the fabrication of the proposed device. For some applications, the holes can also be used to create regions where parasitic capacitance is kept as low as possible (e.g., regions with other electrical components / parts).

[0047] In a specific implementation The first capacitor electrode region and the second capacitor electrode region are arranged in an interlocking comb structure or an interlocking spiral structure (the capacitor dielectric region is between the two structures).

[0048] This arrangement of capacitor electrodes maximizes the surface area for forming the capacitor. As a result, the capacitance density increases.

[0049] In a specific implementationThe electrical device is configured to be used when the operating voltage measured between the first conductive wire in the first capacitor electrode region and the second conductive wire in the second capacitor electrode region exceeds 900 V or 1200 V.

[0050] According to another aspect The present invention provides a method for manufacturing an electrical device including a capacitor, the method comprising:

[0051] - Provides a porous structure,

[0052] - A first conductive wire is formed in the first hole of the first capacitor electrode region of the porous structure (e.g., using an ALD).

[0053] - A second conductive wire is formed in the second hole of the second capacitor electrode region of the porous structure (e.g., using an ALD), and

[0054] in:

[0055] - The porous structure includes a capacitor dielectric region, which includes a third hole and is inserted between the first capacitor electrode region and the second capacitor electrode region.

[0056] - A capacitor is formed by having a first hole in a first capacitor electrode region and a second hole in a second capacitor electrode region facing each other and separated by a third hole in a capacitor dielectric region.

[0057] The proposed manufacturing method can be adapted to obtain any of the electrical devices defined in this disclosure.

[0058] The proposed method for manufacturing electrical devices presents the advantages described with respect to the proposed electrical device implementation.

[0059] In a particular implementation, the method includes:

[0060] - Depositing a mask on a porous structure, the mask comprising:

[0061] Define at least one solid portion of the first capacitor electrode region and the second capacitor electrode region.

[0062] Defines at least one opening in the dielectric region of the capacitor.

[0063] - Deposit dielectric material in the third hole of the capacitor dielectric region (through at least one opening in the mask), and

[0064] - Remove the mask before forming the first conductive wire and the second conductive wire in the first hole and the second hole of the first capacitor electrode region and the second capacitor electrode region.

[0065] Here, a single hard mask is used to define both the capacitor dielectric region and the capacitor electrode region of the porous structure. Alignment of the capacitor dielectric and capacitor electrodes is achieved in a single operation. This helps to reliably withstand high voltages.

[0066] Because of this implementation, it is not necessary to use multiple masks to define the electrode and dielectric regions of the porous structure. Using multiple masks would lead to alignment problems between the capacitor electrodes and the capacitor dielectric, which would adversely affect the capacitor's breakdown voltage and thus its ability to withstand high voltages.

[0067] In a particular implementation, the method includes:

[0068] - Etch a first recess and a second recess in the first capacitor electrode region and the second capacitor electrode region respectively, such that the top surfaces of the first hole and the second hole in these regions are located below the top surface of the porous structure, and

[0069] - Deposit a conductive material layer on a porous structure to form:

[0070] A first connection region extends within a recess in the first capacitor electrode region and electrically connects the first conductive wire in that region.

[0071] The second connection region extends within the recess of the second capacitor electrode region and electrically connects the second conductive wire of that region.

[0072] - The conductive material layer is planarized such that the top surfaces of the first and second connection regions are located below or substantially horizontally to the top surface of the porous structure.

[0073] In a specific implementation Providing a porous structure involves anodizing an aluminum layer to form pores on substantially the entire surface of the layer (bulk anodizing, maskless anodizing).

[0074] In another embodiment Providing a porous structure includes placing (non-in-situ manufactured) anodized aluminum structure on (e.g., attaching it to) a substrate.

[0075] In a specific implementation The method involves using atomic layer deposition to deposit dielectric material in a third hole in the dielectric region. Attached Figure Description

[0076] Further features and advantages of the invention will become apparent from the following description of specific embodiments of the invention, given by way of illustration only and not limitation, in the accompanying drawings:

[0077] Figure 1 shows a capacitor (prior art) proposed in application EP999.

[0078] Figure 2 shows a cross-sectional view of an electrical device according to an embodiment of the present invention.

[0079] Figures 3A to 3H illustrate the steps of a method for manufacturing an electrical device according to an embodiment of the present invention.

[0080] Figures 4A and 4B show cross-sectional views of an electrical device according to an embodiment of the present invention.

[0081] Figures 5A and 5B show simulation results related to the electrostatic field in an electrical device according to an embodiment of the present invention, and

[0082] Figure 6 shows a top view of an electrical device according to an embodiment of the present invention. Detailed Implementation

[0083] This invention provides an electrical device with high capacitance density and suitable for high-voltage applications. More specifically, embodiments of the invention seek to improve upon the capacitor proposed in application EP999 in terms of capacitance density and ability to withstand high voltages.

[0084] Figure 2 shows a cross-sectional view of an electrical device according to an embodiment of the present invention. Specifically, the figure shows a cross-section of the proposed electrical device 100 along axis X1 shown in Figure 6.

[0085] Here, Electrical installations 100 It includes a substrate structure 200, a porous structure 300, and an insulating structure 400. These structures will be described in detail below.

[0086] Substrate structure 200 This includes a substrate 210 (e.g., a conductor substrate, a semiconductor substrate, or even an insulator substrate). For example, substrate 210 may be a silicon substrate.

[0087] One or more dielectric layers 220 to 230 may be formed on the substrate 210. For example, a silicon oxide (SiO2) layer 220 may be formed by thermal oxidation of the silicon substrate 210, and another silicon oxide layer 230 may be formed on the silicon oxide layer 220 by TEOS (i.e., chemical vapor deposition by tetraethyl orthosilicate).

[0088] Porous structure 300 It includes a first capacitor electrode region 310, a second capacitor electrode region 320, and a capacitor dielectric region 330 (these are non-intersecting regions of a porous structure).

[0089] Before detailing these different regions 310 to 330, it should be noted that the porous structure 300 includes holes 301 extending to the lateral edges (i.e., the die edges) of the electrical device 100. The holes 301 extend downward from the top surface of the porous structure 300 and may extend to the bottom surface of the porous structure 300. These holes 301 are (substantially) vertical and (substantially) perpendicular to the top surface of the porous structure 300. As shown here, the porous structure 300 is continuous and includes holes 301 (uniformly) distributed across its entire surface.

[0090] For example, the porous structure 300 may be an anodized aluminum oxide (AAO) structure. However, other embodiments in which other porous structures are used are also conceivable within the scope of this invention.

[0091] First capacitor electrode region 310 (For example, the VDD electrode in Figure 6) includes a first aperture 311. All or part of the first aperture 311 in this region 310 includes a first conductive wire 312 (e.g., a nanowire). In other words, the first conductive wire 312 is disposed in all or part of the first aperture 311 in this region 310.

[0092] Second capacitor electrode region 320 (For example, the GND electrode in Figure 6) includes a second hole 321. All or part of the second hole 321 in this region 320 includes a second conductive wire 322 (e.g., a nanowire). In other words, the second conductive wire 322 is arranged in all or part of the second hole 321 in this region 320. The first hole 311 and the second hole 321 are different holes in the porous structure 300.

[0093] Conductive wires 312 and 322 are each formed in an array that acts as an isopotential equivalent to a single electrode under electrostatic interaction. More specifically, conductive wires 312 and 322 form isopotential equivalents to a single electrode when the distance between them is small relative to the dielectric thickness (e.g., <1 / 10). In other words, the closer the conductive wires are, the more effective their isopotential properties become. For example, the manufacturing process may include anodizing an aluminum layer, allowing conductive wires 312 to 322 to be formed at distances of tens of nm (approximately 10 nm to 100 nm) from each other, while the thickness of the dielectric region 330 can vary from 1 µm to several µm (for high-voltage applications). The formation of conductive wires 312 and 322 will be detailed below with reference to Figures 3A to 3H.

[0094] In this disclosure, the term "conductive wire" is used to refer to a layer of conductive material extending into the pores of a porous structure. The conductive wire partially or completely fills the pores of the porous structure.

[0095] Capacitor dielectric region 330 It includes a third hole 331 and is inserted between the first capacitor electrode region 310 and the second capacitor electrode region 320 to form a capacitor of the electrical device 100.

[0096] The first capacitor electrode region 310 and the second capacitor electrode region 320 face each other and are separated by the capacitor dielectric region 330, thereby forming the capacitor of the electrical device 100. In other words, the capacitor is formed by making the first hole 311 of the first capacitor electrode region 310 and the second hole 321 of the second capacitor electrode region 320 face each other and are separated by the third hole 331 of the capacitor dielectric region 330.

[0097] All or part of the third hole 331 of the capacitor dielectric region 330 may contain dielectric material 332. For example, these holes 331 may be filled with silicon oxide (SiO2) and / or hafnium oxide (HfO2) and / or aluminum oxide (Al2O3) using an ALD. Other embodiments are also conceivable in which the holes 331 of the region 330 remain empty (as previously discussed).

[0098] In addition, the electrical device 100 includes a first connection area 313 and a second connection area 323.

[0099] First connection area 313 The first conductive wires 312 electrically connect the different first holes 311 of the first capacitor electrode region 310. The conductive material (e.g., tungsten, aluminum, copper, or copper with a barrier layer) is included.

[0100] Second connection area 323 Similarly, it includes a conductive material (e.g., tungsten, aluminum, copper, or copper with a barrier layer) that electrically connects the different second holes 321 of the second capacitor electrode region 320 to the second conductive wires 322.

[0101] The connection regions 313 and 323 will be formed in detail below with reference to Figures 3A to 3H.

[0102] Insulation structure 400 This includes one or more insulating layers 410 to 420 extending on the porous structure 300. For example, the insulating structure 400 may include a stack of silicon oxide (SiO2) layer 410 and silicon nitride (Si3N4) layer 420.

[0103] The proposed electrical device 100 has several advantages.

[0104] Similar to the capacitor in application EP999, the proposed electrical device 100 enables the deposition of dielectric material 332 in the pores 331 of the porous structure 300 using ALD technology, resulting in a thick capacitor dielectric 112 capable of withstanding high voltages. In other words, forming a capacitor using the porous structure 300 enables the use of thin-film technology for high-voltage applications (the porous structure 300 serves as a 3D support for material deposition using ALD).

[0105] In addition to the advantages of the capacitor described in EP999, the proposed electrical device 100 also offers the following advantages. These additional advantages arise from the use of conductive wires to form capacitor electrodes within the pores of the porous structure.

[0106] In the capacitor of application EP999, electrodes 111A to 111B are formed using trenches 107A to 107B etched in a porous structure 105 and filled with conductive material 111 using an ELD. Using an ELD requires a seed layer 110 deposited by pressure vapor deposition (PVD) or chemical vapor deposition (CVD). This limits the aspect ratio (width-to-depth ratio) that can be used for the trenches 107A to 107B (e.g., less than 1 / 5 or 1 / 10). For thick porous structures 105 (e.g., thickness greater than 10 µm or 100 µm), this deposition technique requires wider trenches 107A to 107B (e.g., greater than 1 µm or 10 µm) to form the capacitor electrodes 111A to 111B. This adversely affects the capacitance density of the capacitor.

[0107] In contrast, using conductive wires 312 to 322 grown in holes 311 to 321 (using ALD) to form capacitor electrodes 310 to 320 overcomes the aforementioned limitations regarding the aspect ratio of the electrodes. The width of the capacitor electrodes 310 to 320 can be reduced to several holes (even for particularly thick porous structures 300). For example, electrodes 310 to 320 with a width of 0.25 µm can be used in porous structures 300 with thicknesses of 10 µm, 50 µm, or 100 µm. This increases the surface area of ​​the capacitor electrodes facing each other and thus improves the capacitance density.

[0108] Furthermore, the proposed electrical device 100 enables the reduction of mechanical stress in the capacitor structure.

[0109] In the capacitor of application EP999, electrodes 111A to 111B are formed using trenches 107A to 107B etched in a porous structure 105 and filled with conductive material 111. These individual electrodes 111A to 11B may cause mechanical stress to build up within the capacitor.

[0110] In contrast, using nanowires makes it possible to reduce mechanical stress within the capacitor structure. This helps prevent cracking and thus allows it to reliably withstand high voltages.

[0111] Therefore, the present invention provides an electrical device 100 comprising a capacitor having high capacitance density and capable of reliably withstanding high voltage.

[0112] For example, the electrical device 100 can be configured for use when the operating voltage measured between the first capacitor electrode region 310 and the second capacitor electrode region 320 exceeds 900 V or 1200 V.

[0113] The overall structure of the proposed electrical device 100 has been described above. The proposed method for manufacturing the device 100 will be described below, and some features of the device 100 will be further detailed.

[0114] Figures 3A to 3H illustrate the steps of a method for manufacturing an electrical device according to an embodiment of the present invention.

[0115] The proposed method for manufacturing electrical device 100 includes the following steps (in whole or in part).

[0116] Figure 3A The steps for providing substrate structure 200 are illustrated. As shown, an aluminum layer AL extends on substrate structure 200. This layer AL is used to form a porous structure 300, as detailed below.

[0117] Figure 3B The steps for forming a porous structure 300 by anodizing an aluminum layer AL are shown (alternatively, the porous structure 300 can be fabricated in situ and then placed on a substrate structure 200). The thickness of the porous structure 300 can be, for example, between 10 µm and 200 µm.

[0118] The pores 301 of the porous structure 300 are (substantially) vertical and (substantially) perpendicular to the top surface of the porous structure 300. Utilizing an anodized aluminum structure, the pores 301 typically have a diameter on the order of tens of nanometers (e.g., approximately 80 nm in diameter).

[0119] In this embodiment, the hole 301 extends to the lateral edge of the electrical device 100. This means that the anodizing of the aluminum layer AL is performed (substantially) over its entire surface area (i.e., bulk anodizing, maskless anodizing). Using a bulk AAO structure 300 has several advantages.

[0120] The figure also illustrates the steps of forming mask HM1 on porous structure 300.

[0121] On one hand, the solid portion of the mask HM1 defines electrode regions 310 to 320 (with holes 311 to 321 in the electrode regions 310 to 320 located below the solid portion of the mask HM1). On the other hand, the opening of the mask HM1 defines a dielectric region 330 (with holes 331 in the dielectric region 330 located below the opening of the mask HM1).

[0122] It is important to note that a single hard mask HM1 is used to simultaneously define the dielectric region 330 and the electrode regions 310 to 320. This ensures perfect alignment of the capacitor dielectric region and the capacitor electrode region (in a single operation). This is particularly important for tolerating high voltages (as previously discussed).

[0123] Given the required ESR / ESL and capacitance / breakdown voltage, the width and spacing of the electrode regions 310 to 320 are set according to the intended application of the electrical device 100 (using hard mask HM1).

[0124] Figure 3C The steps of filling the third hole 331 (fully or partially) of the dielectric region 330 with dielectric material 332 are shown. For example, these holes 331 can be filled with silicon oxide (SiO2) and / or hafnium oxide (HfO2) and / or aluminum oxide (Al2O3) using ALD. This enables the achievement of stronger dielectric strength and helps to reliably withstand high voltages.

[0125] Figure 3D The step of etching the solid portion of mask HM1 is shown. As shown in the figure, mask HM1 is partially etched. The portion of mask HM1 etched in this step corresponds to the portion defining electrode regions 310 to 320.

[0126] Figure 3E The steps of etching a first recess and a second recess in the first capacitor electrode region 310 and the second capacitor electrode region 320 are shown. The top surfaces of the first hole 311 in the first capacitor electrode region 310 and the second hole 321 in the second capacitor electrode region 320 are located below the top surface of the porous structure 300.

[0127] The figure also illustrates the steps of forming (growing) a first conductive wire 312 and a second conductive wire 322 in the holes 311 of electrode region 310 and the holes 322 of electrode region 320.

[0128] In this embodiment, conductive wires 312 to 322 completely fill (all or part of) the holes 311 of electrode region 310 and 321 of electrode region 320. There are no empty volumes at the centers of the holes 312 of electrode region 310 and 322 of electrode region 320. This embodiment helps to reduce the resistance of the capacitor in the vertical direction (i.e., along the z-axis).

[0129] In another embodiment, conductive wires 312 to 322 (only) partially fill the holes 311 of electrode region 310 and the holes 321 of electrode region 320. The volume at the center of these holes 311 to 321 remains empty. This embodiment enables a reduction in manufacturing time and helps reduce mechanical stress within the capacitor.

[0130] The conductive wires 312 of electrode region 310 and 322 of electrode region 320 can be made of different materials. They can be titanium nitride (TiN) wires (directly) grown on the holes 311 of electrode region 310 and 321 of electrode region 320, or ruthenium (Ru) wires (directly) grown on the holes 311 of electrode region 310 and 321 of electrode region 320. The conductive wires 312 to 322 can also be ruthenium (Ru) wires grown on a titanium nitride (TiN) layer (i.e., a seed layer) that compliantly extends over the holes of electrode regions 310 to 320. Using titanium nitride as a seed layer enables the catalytic growth of ruthenium wires.

[0131] Conductive wires 312 to 322 are formed using an ALD. As previously discussed, growing conductive wires 312 to 322 in holes 311 to 321 using an ALD enables the formation of capacitors using particularly thick porous structures 300 (with holes having a high aspect ratio). This provides capacitors with high capacitance density.

[0132] However, the present invention is not limited to using ALD to form conductive wires, and other deposition techniques can be considered. For example, ELD can be used, but this would limit the aspect ratio of the holes and therefore the thickness of the porous structure. Conductive wires that completely fill the holes can be grown from bottom to top using ELD, or hollow conductive wires that partially fill the holes can be grown from the vertical side of the holes using ELD in combination with a seed layer.

[0133] Figure 3E also shows the steps for removing the remaining portion of mask HM1.

[0134] Figure 3F The steps for depositing a conductive layer CL on a porous structure 300 are illustrated. The conductive layer CL may be a layer containing tungsten (e.g., deposited using CVD combined with deep recesses), or aluminum, or copper. The conductive layer CL may also be a composite layer of an aluminum or copper layer and a barrier layer (such as titanium or tungsten).

[0135] As shown in the figure, the conductive layer CL (partially or completely) fills the recesses in electrode regions 310 to 320.

[0136] Figure 3GThe steps of planarizing the conductive layer CL such that the top surface of the conductive layer CL is located below or substantially at the level of the top surface of the porous structure 300 are illustrated. For example, this step can be performed using chemical mechanical polishing (CMP).

[0137] This step forms connection regions 313 to 323. The first connection region 313 electrically connects the first conductive wire 312 of the first hole 311 of the first capacitor electrode region 310, and the second connection region 323 electrically connects the second conductive wire 322 of the second hole 321 of the second capacitor electrode region 320.

[0138] Here, the connection regions 313 to 323 are confined within the porous structure 300. The top surfaces of the connection regions 313 to 323 are (essentially) located at the same level as the top surface of the porous structure 300. Therefore, a significant portion of the electrostatic field is confined within the porous structure 300 (containing the desired dielectric material 332), which allows a large portion of the electrostatic field to be kept outside the structural weak points (i.e., geometric singularities, weaker layers). This prevents localized increases in the electrostatic field.

[0139] Within the scope of this invention, alternative embodiments are conceivable. The connection region may be located at other locations within the capacitor. Such alternative embodiments are given below with reference to Figures 4A and 4B.

[0140] The thickness of the first connection region 313 and the second connection region 323 is between 100 nm and 3 μm. Given the aforementioned trade-off between manufacturing time and capacitor resistance, the thickness of the connection regions 313 to 323 should be set according to the intended application of the capacitor.

[0141] Figure 3H The steps for forming the insulating structure 400 are shown.

[0142] As mentioned above, connection areas 313 to 323 can be implemented in various ways. Alternative embodiments of the implementation shown in FIG2 will now be described with reference to FIGS. 4A and 4B.

[0143] Figures 4A and 4B show cross-sectional views of an electrical device according to an embodiment of the present invention.

[0144] Figure 4A An embodiment is shown in which the connecting regions 313 to 323 each extend above and below the porous structure 300 (instead of extending in the recesses of the porous structure).

[0145] Compared to the embodiment shown in Figure 2, this embodiment does not require etching recesses in the porous structure 300 to form the connection regions 313 to 323 (but requires other additional manufacturing steps).

[0146] With the connection regions 313 to 323 extending above and below the porous structure 300, this embodiment is advantageous in that it helps to reduce the capacitor resistance (at least in the xy plane).

[0147] However, here, the connection regions 313 to 323 extend into the insulating layer 410 (which may have a lower dielectric strength than the dielectric region 330 containing the dielectric material 332). Therefore, (compared to the embodiment of FIG2) this embodiment may result in a potential local increase in the electrostatic field. This aspect will be described in detail below with reference to FIGS. 5A and 5B.

[0148] Figure 4B An embodiment is shown in which the first connection region 313 extends above the porous structure 300 and the second connection region 323 extends below the porous structure 200.

[0149] Compared to the embodiment shown in Figure 2, this embodiment also does not require etching recesses in the porous structure 300 (but requires other additional manufacturing steps).

[0150] With the connection regions 313 and 323 extending above and below the porous structure 300, respectively, this embodiment has the advantage (compared to the embodiment of FIG4A) in helping to reduce the local increase of the electrostatic field in the capacitor.

[0151] Furthermore, regarding the implementation of connection areas 313 to 323, it is conceivable to combine the above (technically compatible) implementation methods.

[0152] For example, the embodiments of Figures 2 and 4B can be combined. That is, the connection regions 313 to 323 can extend in the recesses of the porous structure as well as above and below the porous structure. This implementation allows for a reduction in capacitor resistance while preventing localized increases in the electrostatic field.

[0153] After presenting different implementations of the connection regions 313 to 323, these implementations are compared in terms of electrostatic field with reference to the following figures.

[0154] Figures 5A and 5B show simulation results related to electrostatic fields in an electrical device according to an embodiment of the present invention.

[0155] Specifically, these figures illustrate the intensity of the electrostatic field in the electrical device 100 in different embodiments. In these embodiments, the capacitor dielectric region 330 is formed by depositing aluminum oxide (Al2O3) in the third hole 331, and the insulating structure 400 is formed using silicon oxide (SiO2).

[0156] Figure 5AAn embodiment in which the connecting regions 313 to 323 extend above the porous structure 300 is shown (similar to the embodiment in FIG4A).

[0157] The top surface of the porous structure 300 is depicted with solid lines.

[0158] As shown by the dashed line, the electrostatic field strength is relatively high: a field strength of over 8.5 MV / cm was measured in the insulating layer 410.

[0159] This can adversely affect the capacitor's breakdown voltage.

[0160] Figure 5B An embodiment in which the connecting regions 313 to 323 are confined within the porous structure 300 is shown (similar to the embodiment in Figure 2).

[0161] The top surface of the porous structure 300 is depicted with solid lines.

[0162] As shown by the dashed line, the strength of the electrostatic field is relatively low: a field strength of less than 6 MV / cm was measured in the insulating layer 410.

[0163] This allows the capacitor to reliably withstand high voltages.

[0164] Figure 6 shows a top view of an electrical device according to an embodiment of the present invention.

[0165] The figure illustrates the layout of the first capacitor electrode region 310 and the second capacitor electrode region 320. Here, the first capacitor electrode region 310 and the second capacitor electrode region 320 are arranged in an interlocking comb-like structure. The capacitor dielectric region 330 is inserted therebetween.

[0166] This arrangement of capacitor electrodes maximizes the surface area of ​​the porous structure 300 forming the capacitor. As a result, the capacitance density increases.

[0167] Other embodiments are conceivable within the scope of this invention. For example, the first capacitor electrode region 310 and the second capacitor electrode region 320 may be arranged in an interlocking helical structure.

[0168] Additional variations: Although the present invention has been described above with reference to specific embodiments, it will be understood that the invention is not limited to the specific circumstances of these embodiments. Various variations, modifications, and improvements can be made to the above embodiments within the scope of the claims.

[0169] It should be understood that the directions and locations mentioned herein, such as “top” and “bottom”, or “front” and “rear”, refer only to the directions applicable when orienting structures and components as shown in the accompanying drawings.

Claims

1. An electrical device (100) including a capacitor, said capacitor including a porous structure (300), said porous structure (300) comprising: - A first capacitor electrode region (310) including a first hole (311), wherein the first hole (311) includes a first conductive wire (312); - A second capacitor electrode region (320) including a second hole (321), wherein the second hole (321) includes a second conductive wire (322); and - A capacitor dielectric region (330) including a third hole (331) and inserted between the first capacitor electrode region (310) and the second capacitor electrode region (320), wherein the capacitor is formed by making the first hole (311) of the first capacitor electrode region (310) and the second hole (321) of the second capacitor electrode region (320) face each other and are separated by the third hole (331) of the capacitor dielectric region (330).

2. The electrical device (100) according to claim 1, wherein, The first conductive wire (312) and the second conductive wire (322) fill the first hole (311) of the first capacitor electrode region (310) and the second hole (321) of the second capacitor electrode region (320).

3. The electrical device (100) according to claim 1, wherein, The first conductive wire (312) and the second conductive wire (322) partially fill the first hole (311) of the first capacitor electrode region (310) and the second hole (321) of the second capacitor electrode region (320), with the central volume of these holes (311, 321) remaining empty.

4. The electrical device (100) according to any one of claims 1 to 3, wherein, The capacitor includes: - a first connection region (313) containing a conductive material electrically connecting a first conductive wire (312) of a first hole (311) of the first capacitor electrode region (310), and - a second connection region (323) containing a conductive material electrically connecting a second conductive wire (322) of a second hole (321) of the second capacitor electrode region (320).

5. The electrical device (100) according to claim 4, wherein: - The first capacitor electrode region (310) and the second capacitor electrode region (320) each include a first recess and a second recess, such that the top surfaces of the first hole (311) and the second hole (321) are located below the top surface of the porous structure (300), and - the first connection region (313) and the second connection region (323) extend in the first recess of the first capacitor electrode region (310) and the second recess of the second capacitor electrode region (320), such that the top surfaces of the first connection region (313) and the second connection region (323) are located below the top surface of the porous structure (300) or at the level of the top surface of the porous structure (300).

6. The electrical device (100) according to claim 4 or 5, wherein, The thicknesses of the first connection region (313) and the second connection region (323) are between 100 nm and 3 μm.

7. The electrical device (100) according to any one of claims 1 to 6, wherein, The porous structure (300) includes holes (301) extending to the lateral edges of the electrical device (100).

8. The electrical device (100) according to any one of claims 1 to 7, wherein, The third hole (331) of all or part of the dielectric region (330) of the capacitor contains dielectric material (332).

9. The electrical device (100) according to any one of claims 1 to 8, wherein, The first capacitor electrode region (310) and the second capacitor electrode region (320) are arranged in an interlocking comb structure or an interlocking spiral structure.

10. The electrical device (100) according to any one of claims 1 to 9, wherein, The electrical device (100) is configured to be used when the operating voltage measured between the first conductive wire (312) of the first capacitor electrode region (310) and the second conductive wire (322) of the second capacitor electrode region (320) exceeds 900 V or 1200 V.

11. A method for manufacturing an electrical device (100) including a capacitor, the method comprising: - Provides a porous structure (300), - Forms a first conductive wire (312) in a first hole (311) of a first capacitor electrode region (310) of the porous structure (300), - Forms a second conductive wire (322) in a second hole (321) of a second capacitor electrode region (320) of the porous structure (300), and wherein: - The porous structure (300) includes a capacitor dielectric region (330), the capacitor dielectric region (330) includes a third hole (331) and is inserted between the first capacitor electrode region (310) and the second capacitor electrode region (320), - The capacitor is formed by making the first hole (311) of the first capacitor electrode region (310) and the second hole (321) of the second capacitor electrode region (320) face each other and are separated by the third hole (331) of the capacitor dielectric region (330).

12. The method of claim 11, comprising: - Deposit a mask (HM1) on the porous structure (300), the mask comprising: defining at least one solid portion defining the first capacitor electrode region (310) and the second capacitor electrode region (320), defining at least one opening defining the capacitor dielectric region (330), - depositing dielectric material (332) in a third hole (331) of the capacitor dielectric region (330), and - removing the mask (HM1) before forming the first conductive wire (312) and the second conductive wire (322) in the first hole (311) of the first capacitor electrode region (310) and the second hole (321) of the second capacitor electrode region (320).

13. The method according to claim 11 or 12, comprising: - Etch a first recess and a second recess in the first capacitor electrode region (310) and the second capacitor electrode region (320), respectively, such that the top surfaces of the first hole (311) and the second hole (321) of these regions (310, 320) are located below the top surface of the porous structure (300), and - Deposit a conductive material layer (CL) on the porous structure (300) to form: a first connection region (313) extending in the first recess of the first capacitor electrode region (310) and electrically connecting the first conductive wire (312) of the region (310), and a second connection region (323) extending in the second recess of the second capacitor electrode region (320) and electrically connecting the second conductive wire (322) of the region (320), - The conductive material layer (CL) is planarized such that the top surfaces of the first connection region (313) and the second connection region (323) are located below the top surface of the porous structure (300) or at the level of the top surface of the porous structure (300).

14. The method according to any one of claims 11 to 13, wherein, Providing the porous structure (300) includes: anodizing an aluminum layer (AL) to form pores (301) on substantially the entire surface of the layer (AL).

15. The method according to any one of claims 11 to 14, comprising: Atomic layer deposition is used to deposit dielectric material (332) in the third hole (331) of the dielectric region (330) of the capacitor.

Images