Digital down-conversion method based on full digital domain processing

Abstract

The invention discloses a digital down-conversion method based on full digital domain processing, which relates to the technical field of signal processing, and comprises the following steps: down-converting an input digital intermediate frequency signal to a zero intermediate frequency position by adopting a frequency mixing mode according to the input digital intermediate frequency signal; performing multi-stage filtering extraction on the signal after frequency conversion processing; and resampling is carried out, and the sampling rate of the signal is changed to adapt to a subsequent signal processing module. According to the invention, the requirement of any multiple sampling rate conversion at the rear end of equipment can be met.

Description

A digital downconversion method based on all-digital domain processing Technical Field

[0001] This invention relates to the field of signal processing technology, specifically, to a digital down-conversion method based on all-digital domain processing. Background Technology

[0002] Digital downconversion (DDC) digitizes the high-speed digital intermediate frequency (IF) signal output by an analog-to-digital converter (ADC), then converts it into a low-speed baseband signal through frequency conversion, decimation, and low-pass filtering. The traditional method is analog IF downconversion. The difference between digital downconversion and traditional analog IF downconversion lies in the fact that the quadrature conversion and baseband filtering in digital downconversion are both implemented in digital circuits. This makes digital downconversion far less sensitive to temperature and electromagnetic interference than analog circuits, avoiding parameter drift problems associated with analog components (such as capacitors and inductors). Furthermore, digital circuits allow for efficient parallel operation of multiple DDC channels. In practical applications, many quadrature conversions and baseband filters that require digital downconversion are implemented in digital circuits, such as modern software-defined radio platforms. These platforms are characterized by unified hardware. On one hand, they use an ADC for uniform sampling at the intermediate frequency (IF) and then perform arbitrary sampling rate conversions for different signal components at the back end. On the other hand, demodulation of certain special signals, such as variable modulation rate modulation (VMR), time-slot-frequency slot joint allocation multiple access (TDMA), and VMR adaptive modulation, all require arbitrary sampling rate conversions. Therefore, digital downconversion modules are typically equipped with arbitrary resampling units to accommodate subsequent processing modules. Traditional IF downconversion cannot meet this requirement. Summary of the Invention

[0003] The purpose of this invention is to provide a digital down-conversion method based on full digital domain processing, which solves the problem that analog intermediate frequency down-conversion in the prior art cannot meet the requirements of arbitrary multiple sampling rate conversion at the back end of the equipment.

[0004] The present invention solves the above problems through the following technical solution:

[0005] A method for digital down-conversion based on all-digital domain processing includes:

[0006] Step S100: Based on the input digital intermediate frequency signal, downconvert it to the zero intermediate frequency position using a mixing method;

[0007] Step S200: Perform multi-stage filtering and extraction on the frequency conversion processed signal;

[0008] Step S300: Resample the signal and change the sampling rate to adapt to the subsequent signal processing module.

[0009] Further, step S100 specifically includes:

[0010] Step S110: Calculate the sine value of the phase of each CNC local oscillator, and store the sine value data of the phase as the address according to the phase angle;

[0011] Step S120: Using the position index of the current signal data The corresponding frequency control word is obtained. Through complex multiplication, the spectrum of the input intermediate frequency signal is shifted to the zero intermediate frequency position, meaning the current signal has completed frequency conversion. The sampling period is For the initial phase, This refers to the instantaneous frequency.

[0012] Further, step S110 specifically includes:

[0013] Step S111: Received digital intermediate frequency signal for:

[0014] ;

[0015] in, It is the carrier frequency. It refers to the amplitude;

[0016] Step S112: The received digital intermediate frequency signal x(n) and the numerically controlled local oscillator The two generated quadrature local oscillator signals are multiplied to shift the digital intermediate frequency signal to baseband, resulting in the output baseband signal. :

[0017] ;

[0018] in, It is the carrier frequency. and local oscillator frequency difference, ;

[0019] Step S113, when the local oscillator frequency Fully track the carrier frequency At that time, the baseband signal y output after mixing i FC (n) is:

[0020] .

[0021] Further, step S200 specifically includes:

[0022] Step S210: Based on the input sampling rate and output sampling rate The relationship determines the decimation factor of the cascaded integrator-comb CIC decimation filter. Cascaded stages of half-band decimation filters ;

[0023] Step S220: Design a CIC decimation filter and set the decimation factor to be... Extraction;

[0024] Step S230: Design a half-band decimation filter and perform downsampling processing with a decimation factor of 2.

[0025] Further, step S220 specifically includes:

[0026] Step S221: M single-pole decimation filters form a CIC decimation filter, and the decimation factor of the single-pole decimation filter is 2. 1 ~2 8 The impulse response of the CIC decimation filter is [number] times. for:

[0027] ;

[0028] Where D is the order of the CIC decimation filter, which is also the decimation factor of the CIC decimation filter; M is the number of single-pole decimation filters.

[0029] CIC Decimation Filter Impulse Response Z-transform for:

[0030] ;

[0031] Let the integrator Comb filter Then H(z) = H1(z)H2(z);

[0032] Step S222, let ,but:

[0033] ;

[0034] ;

[0035] Step S223 For the first The input data of the first-stage CIC decimation filter is accumulated to obtain:

[0036] ;

[0037] in, It is the level index of the CIC decimation filter, i=1,2,3,...,M; It is the location index of the data. D is the order of the CIC decimation filter;

[0038] Step S224: Based on the extraction multiplier For accumulated data After performing the corresponding cumulative reduction process, then:

[0039] ;

[0040] in, These are the output data of each stage of the single-pole decimation filter;

[0041] Step S225, by and Calculate the frequency response of the CIC filter. :

[0042] ;

[0043] Among them, the definition .

[0044] Further, step S230 specifically includes:

[0045] Step S231, the half-band decimation filter is the frequency response FIR filters that satisfy the following relationship:

[0046] ;

[0047] in, It is passband tolerance. Stopband tolerance It is a passband ripple, δ p It is a stopband ripple; This is a preset value, such as 0.1, used to describe the amplitude jitter range within the passband and stopband;

[0048] The passband and stopband of a half-band decimation filter are symmetrical, that is:

[0049] ;

[0050] Step S232: The coefficients of the half-band filter have even symmetry characteristics, and their length is even. The impulse response of all even-numbered indices greater than 0... All values ​​are 0, that is:

[0051] ;

[0052] Where k is the time index;

[0053] Step S233: Since all FIR filters are symmetrical, the data output by each stage of the single-stage half-band filter... for:

[0054] ;

[0055] The index m of the output sequence takes the value of ±2. , For the input sequence index; The offset index is used for the polyphase decomposition of the input sequence under the symmetric structure of the half-band filter.

[0056] Step S234: Set the half-band decimation filter to a two-stage cascade to obtain a low-rate baseband signal. :

[0057] ;

[0058] Where A is the signal amplitude, T S φ is the sampling period, φ is the instantaneous frequency, and θ is the initial phase.

[0059] Further, step S300 specifically includes:

[0060] Step S310, for low-speed baseband signals conduct Double the interpolated zero value, denoted as ,have: ; The interpolation factor;

[0061] Step S320, design the corresponding First-order FIR low-pass filter ,in , The interpolation factor is the order of the FIR low-pass filter. Integer multiples of, i.e. ,in It is a positive integer;

[0062] Step S330, perform filtering and convolution operations, resulting in:

[0063] ;

[0064] in ; For sequence indexing;

[0065] Step S340, for the first Let the value be taken at each time point. as well as ,in If it's a floor function, then:

[0066] ;

[0067] Step S350: The above-mentioned First-order low-pass filter Divide into I groups, with c coefficients in each group, i.e.: ;in, ; ;

[0068] Step S360, the resampling output at time k is: .

[0069] Compared with the prior art, the present invention has the following advantages and beneficial effects:

[0070] (1) The present invention approximates the sampling position during the resampling process, performs a large multiple extraction on the low-pass signal with a high oversampling multiple to calculate the output signal. The extraction multiple can be an irrational number, and each extraction position is approximated to the adjacent integer position, which can meet the requirements of arbitrary multiple sampling rate transformation of the device backend.

[0071] (2) The present invention uses a two-stage cascaded half-band filter to complete the 4x decimation, and the passband and stopband positions are easy to control; it has a high computation rate and is particularly suitable for real-time processing.

[0072] (3) The digital downconversion method of full digital domain processing adopted in this invention is suitable for engineering implementation. By pre-designing CIC decimation filter, half-band filter and resampling interpolation filter designed in combination with actual accuracy requirements, the sampling rate conversion of any multiple can be realized. It can be directly pre-stored in the LUT in the FPGA for real-time calling, thereby avoiding the problem of dynamic configuration of filter parameters required for FPGA real-time signal processing to a certain extent. Attached Figure Description

[0073] Figure 1 is a schematic diagram of the present invention;

[0074] Figure 2 shows the spectrum of the input signal.

[0075] Figure 3 shows the signal spectrum when moved to the zero intermediate frequency position;

[0076] Figure 4 shows the signal spectrum after CIC, half-band filtering and integer multiple decimation;

[0077] Figure 5 is a schematic diagram of the resampling principle;

[0078] Figure 6 shows the signal spectrum after resampling;

[0079] Figure 7 is a block diagram of the principle of H(z). Detailed Implementation

[0080] The present invention will be further described in detail below with reference to embodiments, but the implementation of the present invention is not limited thereto.

[0081] Example:

[0082] Referring to Figure 1, a digital down-conversion method based on all-digital domain processing includes:

[0083] Step S100: Based on the input digital intermediate frequency signal, downconvert it to the zero intermediate frequency position using a mixing method;

[0084] Step S200: Perform multi-stage filtering and extraction on the frequency conversion processed signal;

[0085] Step S300: Resample the signal and change the sampling rate to adapt to the subsequent signal processing module.

[0086] Furthermore, in step S100, the signal input sampling rate is based on the input digital intermediate frequency signal. =28MHz, and its signal spectrum is shown in Figure 2. This invention uses a lookup table approach to downconvert it to the zero intermediate frequency position, including the following steps: specifically including:

[0087] In this invention, step S110 employs a lookup table approach, which involves calculating the sine value of the phase of each numerically controlled local oscillator and storing the sine value data of that phase using the phase angle as the address. Step S110 requires analyzing, capturing, and tracking the carrier frequency of the useful signal to control the generation of a local sine / cosine signal. ,in It is the position index of the current signal data. It is the local oscillator frequency. It refers to the sampling period. Typically, a lookup table method is used, which involves calculating the sine value of each phase of the numerically controlled local oscillator and storing the sine value data of that phase using the phase angle as the address.

[0088] Further, step S110 specifically includes:

[0089] Step S111: Received digital intermediate frequency signal for:

[0090] ;

[0091] in, A is the carrier frequency, and A is the amplitude. It is the instantaneous frequency. It is the initial phase.

[0092] Step S112, Received digital intermediate frequency signal With CNC local oscillator The two generated quadrature local oscillator signals are multiplied together to shift the digital intermediate frequency signal to the baseband.

[0093] ;

[0094] in, It is the carrier frequency. and local oscillator frequency difference, ;

[0095] Step S113, when the local oscillator frequency Fully track the carrier frequency At that time, the baseband signal y output after mixing i FC (n) is:

[0096] ;

[0097] Step S120: Using the position index of the current signal data The corresponding frequency control word is obtained. After complex multiplication, the spectrum of the input intermediate frequency signal can be shifted to the zero intermediate frequency position, that is, the current signal has completed the frequency conversion process, as shown in Figure 3. After generating a local oscillator signal and mixing it with the received digital signal, the received signal can be shifted to the zero intermediate frequency position, that is, the received signal in Figure 2 is shifted.

[0098] However, after mixing, the data rate and intermediate frequency sampling rate obtained from the frequency conversion in the previous section are... This is consistent, but subsequent resampling modules cannot achieve this processing rate. Therefore, a subsequent filtering and decimation unit is needed to reduce the signal sampling rate to a manageable range.

[0099] Further, step S200 specifically includes:

[0100] Step S210: Based on the input sampling rate and output sampling rate The relationship determines the decimation factor of the cascaded integrator-comb CIC decimation filter. Cascaded stages of half-band decimation filters ;

[0101] In this embodiment, the input sampling rate =28MHz, output sampling rate =2.72MHz, therefore a single-stage decimation factor of 2 is required. Decimation filter and two-stage half-band filter.

[0102] Step S220: Design a CIC decimation filter and set the decimation factor to be... The sampling rate of the output signal after CIC filtering and decimation. Reduce to the required sampling rate 1 times 2 times;

[0103] In step S220, the CIC integrating comb filter is a very effective unit in high-speed decimation or interpolation systems. In radio communication systems, its main function is to downsample signals at radio frequency or intermediate frequency sampling rates to baseband. The module is for performing Extraction in multiples of an integer multiple. After... After filtering and decimation, the output sampling rate of the signal Reduce to the required sampling rate 1 times 2 times.

[0104] Further, step S220 specifically includes:

[0105] Step S221: In this invention, a multi-stage cascaded CIC decimation filter is configured, and the decimation factor of a single stage is... The system can be cascaded up to 4 levels, with a clearly defined extraction multiplier. Maximum extraction multiplier Reachable A cascaded integrator-comb (CIC) filter is one whose impulse response has the following form:

[0106] ;

[0107] Where D is the order of the CIC decimation filter, which is also the decimation factor of the CIC decimation filter; M is the number of single-pole decimation filters.

[0108] According to the definition of the Z-transform, the Z-transform of the impulse response of the CIC decimation filter is:

[0109] ;

[0110] Let the integrator Comb filter ,but:

[0111] , The principle block diagram is shown in Figure 7.

[0112] Step S222: The foundation of the CIC decimation filter is perfect pole-zero cancellation. To achieve this, the integration algorithm needs to be sufficiently accurate. The filter coefficients of the CIC decimation filter can be considered as all 1s. Therefore, based on the implementation principle and the rules of filtering operations, the CIC decimation filter can be divided into integrators. and makeup filter ,make ,but:

[0113] ;

[0114] ;

[0115] Step S223 It is called an integrator because its essential implementation process involves continuously accumulating data. Therefore, corresponding to the relevant part of this invention, regarding the first... By performing the corresponding accumulation operation on the input data of the CIC decimation filter, we can obtain:

[0116] ;

[0117] in, It is the level index of the CIC decimation filter, i=1,2,3,...,M; It is the location index of the data. D is the order of the CIC decimation filter;

[0118] Step S224, then according to the extraction multiplier The accumulated data of each stage of the single-stage decimation filter obtained above. After performing the corresponding cumulative reduction process, then:

[0119] ;

[0120] in, These are the output data of each stage of the single-pole decimation filter;

[0121] Step S225, by and Calculate the frequency response of the CIC filter. :

[0122] ;

[0123] Among them, the definition .

[0124] Furthermore, because, according to calculations, single-level The filter's sidelobe level is only 13.46 dB lower than the main lobe, which means the stopband attenuation is very poor and generally unsuitable for practical applications. To reduce the sidelobe level, multi-stage filters can be used. This problem is solved by cascading filters. In this invention, a 4-stage filter system is used. Cascaded scheme, 4 levels The filter has a stopband attenuation of about 54dB, which can basically meet the requirements of practical work.

[0125] Step S230: Design a half-band decimation filter and perform downsampling processing with a decimation factor of 2.

[0126] In step S230, the second stage of the decimation filtering system is typically a half-band decimation filter that performs a fixed decimation factor of 2, thereby increasing the sampling rate of the signal output after the half-band decimation filter. Reduce to the required sampling rate 0.5 times 1x. The reason for this design is because... The attenuation performance of the transition band and stopband is poor, and multi-stage cascading is usually required to increase the attenuation of the transition band and stopband. In addition, the controllability of its passband and stopband characteristics is not strong, requiring a high integer multiple downsampling rate processing after the first stage of the filter with easily controllable passband and stopband positions.

[0127] Considering the resource consumption of half-band filters, a maximum of two cascaded half-band filters can generally be configured. From the previous steps, we know that the cascade number of half-band filters is 2. Therefore, in this example, a two-stage cascaded half-band filter is used to achieve a 4x decimation, and the passband and stopband positions are easily controlled.

[0128] Further, step S230 specifically includes:

[0129] Step S231, the half-band (HB) decimation filter has a frequency response. FIR filters that satisfy the following relationship:

[0130] ;

[0131] in, It is passband tolerance. Stopband tolerance It is a passband ripple, δ p It is a stopband ripple; This is a preset value, typically 0.1, which describes the amplitude jitter range within the passband and stopband.

[0132] It can be seen that the passband and stopband of a half-band decimation filter are symmetrical, that is:

[0133] ;

[0134] After reducing the sampling frequency by half, the frequency response H(e) of the half-band filter j(π-ω) Since the signal has a period of π, after half-band filtering and decimation by 2, there is no spectral aliasing in the signal passband.

[0135] Step S232: Because the coefficients of the half-band filter have even symmetry, their length is even (the filter order is odd), and the impulse response values ​​of all even-numbered indices greater than 0 are 0, that is:

[0136] ;

[0137] Where k is the time index, and is an integer sequence number parameter;

[0138] Therefore, when using a half-band decimation filter to implement sampling rate transformation, compared with a general linear phase FIR filter, the number of multiplication operations can be reduced by nearly half when decimated by 2, resulting in a very high computational efficiency, making it particularly suitable for real-time processing.

[0139] Step S233: Since all FIR filters are symmetrical, the data output by each stage of the single-stage half-band filter... for:

[0140] ;

[0141] The index m of the output sequence takes the value of ±2. , For the input sequence index; The offset index is used for the polyphase decomposition of the input sequence under the symmetric structure of the half-band filter.

[0142] This invention takes into account the resource consumption issues of half-band filters, and generally allows for a maximum of two cascaded half-band filters. The number of cascaded half-band filters can be obtained from the preceding steps. ,Finish Double extraction.

[0143] At this point, a high downsampling rate was achieved, and a low-pass filter was used to remove high-frequency components from the mixer output, resulting in a low-rate baseband signal. :

[0144] ;

[0145] Where A is the signal amplitude, T S φ is the sampling period, φ is the instantaneous frequency, and θ is the initial phase.

[0146] The spectrum of the low-sampling-rate signal output by the decimation filter module is shown in Figure 4. By using a multi-stage cascaded CIC filter and a half-band filter, the signal shifted to zero intermediate frequency is decimated by an integer multiple, thereby reducing the sampling rate. For example, if the sampling rate of the shifted signal is 120MHz, it can be reduced to 6MHz by using a 1-stage 5x decimation CIC filter (reducing the sampling rate to 24MHz) and a 2-stage half-band filter (reducing the sampling rate to 12MHz and 6MHz respectively).

[0147] Furthermore, because broadband intermediate frequency (IF) bandpass sampling typically uses a fixed-rate clock to directly sample the input IF signal, the clock for frequency conversion processing is uncorrelated with the clock of the received signal. During baseband signal processing, it is essential to extract the data stream based on the optimal sampling. This necessitates adding a code stream clock adjustment and corresponding resampling stage between the frequency conversion and baseband processing sections.

[0148] Therefore, resampling is performed in step S300 to change the signal sampling rate and adapt it to the subsequent signal processing module. The principle of resampling is shown in Figure 5. At this time, the ratio of the input sampling rate to the output sampling rate is not an integer multiple, resulting in the signal output time not occurring at a single signal input time, but rather between two adjacent signal input times. Furthermore, the signal output time interval is not an integer multiple of the signal input time interval. This is the input signal for the resampling module. Input sampling rate, To output the sampling rate, For input index, The output index is g(t), and the interpolation function (impulse response) is g(t).

[0149] Step S300 specifically includes:

[0150] For low-speed baseband signals conduct Double the interpolated zero value, denoted as ,have: ; The interpolation factor;

[0151] Step S320, design the corresponding First-order FIR low-pass filter ,in , The interpolation factor is the order of the FIR low-pass filter. Integer multiples of, i.e. ,in It is a positive integer;

[0152] Step S330, perform filtering and convolution operations, resulting in:

[0153] ;

[0154] in ; For sequence indexing;

[0155] Step S340: Considering the special property of I-fold interpolation zero in u(k), let the value at time k be... as well as ,in If it's a floor function, then:

[0156] ;

[0157] Step S350: The above-mentioned First-order low-pass filter Divide into I groups, with c coefficients in each group, i.e.: ;in, ; ;

[0158] Step S360: The output of the resampling module in this example is shown in Figure 6. The resampling module in this example can perform sampling rate transformation on the module input signal by any multiple, thereby extracting the optimal sampled data stream. For example, it can convert the module input signal with a sampling rate of 6MHz into a module output signal with a sampling rate of 4MHz. The resampling output at the k-th time is: .

[0159] This invention approximates the sampling position during the resampling process, performs a large-scale decimation on low-pass signals with high oversampling factors, and calculates the output signal. The decimation factor can be an irrational number, and each decimation position is approximated to an adjacent integer position, which can meet the requirements of arbitrary sampling rate transformation in the back-end of the device.

[0160] Although the present invention has been described herein with reference to illustrative embodiments, the above embodiments are merely preferred embodiments of the present invention, and the implementation of the present invention is not limited to the above embodiments. It should be understood that those skilled in the art can devise many other modifications and implementations, which will fall within the scope and spirit of the principles disclosed in this application.

Claims

1. A method for digital down-conversion based on all-digital domain processing, characterized in that, include: Step S100: Based on the input digital intermediate frequency signal, downconvert it to the zero intermediate frequency position using a mixing method; Step S200: Perform multi-level filtering and extraction on the frequency-converted signal; Step S300: Perform resampling to change the signal sampling rate to adapt to the subsequent signal processing module.

2. The digital down-conversion method based on all-digital domain processing according to claim 1, characterized in that, Step S100 specifically includes: Step S110, calculating the sine value of the phase of each CNC local oscillator, and storing the sine value data of the phase as an address according to the phase angle; Step S120, using the position index of the current signal data... The corresponding frequency control word is obtained. Through complex multiplication, the spectrum of the input intermediate frequency signal is shifted to the zero intermediate frequency position, meaning the current signal has completed frequency conversion. The sampling period is For the initial phase, This refers to the instantaneous frequency.

3. The digital down-conversion method based on all-digital domain processing according to claim 2, characterized in that, Step S110 specifically includes: Step S111, receiving the digital intermediate frequency signal. for: ;in, It is the carrier frequency. It is the amplitude; step S112, the received digital intermediate frequency signal With CNC local oscillator The two generated quadrature local oscillator signals are multiplied to shift the digital intermediate frequency signal to baseband, resulting in the output baseband signal. ： ;in, It is the carrier frequency. and local oscillator frequency The difference, Step S113: When the local oscillator frequency... Fully track the carrier frequency At that time, the baseband signal y output after mixing i FC (n) is: 。 4. The digital down-conversion method based on all-digital domain processing according to claim 1, characterized in that, The step S200 specifically includes: step S210, based on the input sampling rate and output sampling rate The relationship determines the decimation factor of the cascaded integrator-comb CIC decimation filter. Cascaded stages of half-band decimation filters Step S220: Design a CIC decimation filter and set the decimation factor to be... Extraction; Step S230: Design a half-band decimation filter and perform downsampling processing with a decimation factor of 2.

5. The digital down-conversion method based on all-digital domain processing according to claim 4, characterized in that, Step S220 specifically includes: Step S221, M single-pole decimation filters forming a CIC decimation filter, wherein the decimation factor of the single-pole decimation filter is 2. 1 ~2 8 The impulse response of the CIC decimation filter is [number] times. for: Where D is the order of the CIC decimation filter, and also the decimation factor of the CIC decimation filter; M is the number of single-pole decimation filters; and the impulse response of the CIC decimation filter is... Z-transform for: Let the integrator Comb filter Then H(z) = H1(z)H2(z); Step S222, let ,but: ； Step S223 For the first The input data of the first-stage CIC decimation filter is accumulated to obtain: ;in, It is the level index of the CIC decimation filter, i=1,2,3,...,M; It is the location index of the data. D is the order of the CIC decimation filter; Step S224: Based on the decimation factor... For accumulated data After performing the corresponding cumulative reduction process, then: ;in, It is the output data of each stage of the single-pole decimation filter; step S225, by and Calculate the frequency response of the CIC filter. ： ; where, definition 。 6. The digital down-conversion method based on all-digital domain processing according to claim 4, characterized in that, Step S230 specifically includes: Step S231, the half-band decimation filter is the frequency response. FIR filters that satisfy the following relationship: ;in, It is passband tolerance. Stopband tolerance It is a passband ripple, δ p It is a stopband ripple; These are preset values ​​used to describe the amplitude jitter range within the passband and stopband; the passband and stopband of the half-band decimation filter are symmetrical, that is: Step S232: The coefficients of the half-band filter have even symmetry characteristics, and their length is even. The impulse response of all even-numbered indices greater than 0 is... All values ​​are 0, that is: Where k is the time index; Step S233: Since all FIR filters are symmetrical, the data output by each stage of the single-stage half-band filter... for: The index m of the output sequence takes values ​​of ±2. ， For the input sequence index; The offset index is used for the polyphase decomposition of the input sequence under the symmetric structure of the half-band filter; Step S234: Set the half-band decimation filter to a two-stage cascade to obtain a low-rate baseband signal. ： Where A is the signal amplitude, and T is the signal amplitude. S φ is the sampling period, φ is the instantaneous frequency, and θ is the initial phase.

7. The digital down-conversion method based on all-digital domain processing according to claim 6, characterized in that, Step S300 specifically includes: Step S310, for low-rate baseband signals conduct Double the interpolated zero value, denoted as ,have: ； For the interpolation multiple; step S320, design the corresponding... First-order FIR low-pass filter ,in ， The interpolation factor is the order of the FIR low-pass filter. Integer multiples of, i.e. ,in For positive integers; in step S330, perform filtering and convolution operations, resulting in: ;in ； For sequence index; Step S340, for the first... Let the value be taken at each time point. as well as ,in If it's a floor function, then: Step S350: Place the above-mentioned First-order low-pass filter Divide into I groups, with c coefficients in each group, i.e.: ;in, ； Step S360, the resampling output at time k is: 。

Images