Linearization circuit and power amplifier

Abstract

The application provides a linearization circuit and a power amplifier, wherein the linearization circuit comprises an impedance adjusting circuit, a first input end of the impedance adjusting circuit is used for accessing a first control signal, a second input end of the impedance adjusting circuit is used for accessing a first radio frequency signal, and a third input end of the impedance adjusting circuit is used for accessing a second radio frequency signal; the first control signal, the first radio frequency signal and the second radio frequency signal all comprise direct current components; a voltage value accessed by the second input end of the impedance adjusting circuit changes with the change of the first radio frequency signal, and a voltage value accessed by the third input end of the impedance adjusting circuit changes with the change of the second radio frequency signal, so as to dynamically adjust the impedance of the impedance adjusting circuit. The linearization circuit of the application can compensate for the nonlinear distortion of the power amplifier, so as to improve the quality of the radio frequency signal.

Description

Technical Field

[0001] This invention relates to the field of communication technology, and in particular to a linearization circuit and a power amplifier. Background Technology

[0002] With the continuous development of wireless communication technology, its application scope is becoming wider and wider. In radio frequency communication systems, in order to achieve high communication rates, the modulation forms are becoming more and more complex, and the requirements for the linearity of power amplifiers are also becoming higher and higher.

[0003] In practical applications, radio frequency (RF) communication systems need to amplify RF signals to improve their quality. The main circuit for amplifying RF signals is the power amplifier. The power amplifier receives the RF signal, amplifies it, and then outputs it to the next node.

[0004] In the existing technology, power amplifiers are mainly implemented using active devices. However, active devices themselves have nonlinearity issues, which can cause nonlinear distortion of the radio frequency signal during the amplification process of the power amplifier, thereby affecting the quality of the radio frequency signal. Summary of the Invention

[0005] To address the shortcomings of the aforementioned related technologies, this invention proposes a linearization circuit and a power amplifier to solve the problem that nonlinear distortion occurs in the power amplifiers of related technologies during the amplification of radio frequency signals, thereby affecting the quality of radio frequency signals.

[0006] To address the aforementioned technical problems, in a first aspect, the present invention provides a linearization circuit for compensating the linearity of a power amplifier, comprising an impedance adjustment circuit, wherein a first input terminal of the impedance adjustment circuit is used to receive a first control signal, a second input terminal of the impedance adjustment circuit is used to receive a first radio frequency signal, and a third input terminal of the impedance adjustment circuit is used to receive a second radio frequency signal; the first control signal, the first radio frequency signal, and the second radio frequency signal all include a DC component.

[0007] The voltage value connected to the second input terminal of the impedance adjustment circuit changes with the change of the first radio frequency signal, and the voltage value connected to the third input terminal of the impedance adjustment circuit changes with the change of the second radio frequency signal, so as to dynamically adjust the impedance of the impedance adjustment circuit.

[0008] Preferably, the first radio frequency signal and the second radio frequency signal are inverted signals; the linearization circuit further includes a first capacitor and a first resistor; The first terminal of the first capacitor is used to receive the first radio frequency signal, and the second terminal of the first capacitor is connected to the second input terminal of the impedance adjustment circuit. The first end of the first resistor is connected to the second input end of the impedance adjustment circuit, and the second end of the first resistor is used to receive a second control signal; the second control signal includes a DC component and an AC component.

[0009] Preferably, the linearization circuit further includes a second capacitor and a second resistor; The first terminal of the second capacitor is used to receive the second radio frequency signal, and the second terminal of the second capacitor is connected to the third input terminal of the impedance adjustment circuit. The first end of the second resistor is connected to the third input terminal of the impedance adjustment circuit, and the second end of the second resistor is used to connect to the second control signal.

[0010] Preferably, the impedance adjustment circuit includes a first field-effect transistor (FET); the gate of the first FET serves as the first input terminal of the impedance adjustment circuit, one of the source and drain of the first FET serves as the second input terminal of the impedance adjustment circuit, and the other of the source and drain of the first FET serves as the third input terminal of the impedance adjustment circuit.

[0011] Preferably, the impedance adjustment circuit includes a first transistor; the base of the first transistor serves as the first input terminal of the impedance adjustment circuit, one of the collector and emitter of the first transistor serves as the second input terminal of the impedance adjustment circuit, and the other of the collector and emitter of the first transistor serves as the third input terminal of the impedance adjustment circuit.

[0012] Preferably, the first control signal is divided into a first control sub-signal and a second control sub-signal; the impedance adjustment circuit includes a second field-effect transistor and a third field-effect transistor, and the gates of the second field-effect transistor and the third field-effect transistor together serve as the first input terminal of the impedance adjustment circuit; The gate of the second field-effect transistor is used to receive the first control sub-signal, and one of the source and drain of the second field-effect transistor serves as the second input terminal of the impedance adjustment circuit. The gate of the third field-effect transistor is used to receive the second control sub-signal. One of the source and drain of the third field-effect transistor is connected to the other of the source and drain of the second field-effect transistor. The other of the source and drain of the third field-effect transistor serves as the third input terminal of the impedance adjustment circuit.

[0013] Preferably, the first control signal is divided into a first control sub-signal and a second control sub-signal; the impedance adjustment circuit includes a second transistor and a third transistor, and the base of the second transistor and the base of the third transistor together serve as the first input terminal of the impedance adjustment circuit; The base of the second transistor is used to connect to the first control sub-signal, and one of the emitter and collector of the second transistor serves as the second input terminal of the impedance adjustment circuit. The base of the third transistor is used to receive the second control sub-signal. One end of the emitter and collector of the third transistor is connected to the other end of the emitter and collector of the second transistor. The other end of the emitter and collector of the third transistor serves as the third input terminal of the impedance adjustment circuit.

[0014] Preferably, the first control signal is divided into a first control sub-signal and a second control sub-signal; the impedance adjustment circuit includes a fourth field-effect transistor and a fifth field-effect transistor, and the gates of the fourth field-effect transistor and the fifth field-effect transistor together serve as the first input terminal of the impedance adjustment circuit; The gate of the fourth field-effect transistor is used to receive the first control sub-signal. One of the source and drain of the fourth field-effect transistor serves as the second input terminal of the impedance adjustment circuit. The other of the source and drain of the fourth field-effect transistor is connected to the first terminal of the second resistor. The gate of the fifth field-effect transistor is used to receive the second control sub-signal. One of the source and drain of the fifth field-effect transistor is connected to the first terminal of the first resistor. The other of the source and drain of the fifth field-effect transistor serves as the third input terminal of the impedance adjustment circuit.

[0015] Preferably, the first control signal is divided into a first control sub-signal and a second control sub-signal; the impedance adjustment circuit includes a fourth transistor and a fifth transistor, and the base of the fourth transistor and the base of the fifth transistor together serve as the first input terminal of the impedance adjustment circuit; The base of the fourth transistor is used to receive the first control sub-signal. One of the emitter and collector of the fourth transistor serves as the second input terminal of the impedance adjustment circuit. The other of the emitter and collector of the fourth transistor is connected to the first terminal of the second resistor. The base of the fifth transistor is used to receive the second control sub-signal. One of the emitter and collector of the fifth transistor is connected to the first terminal of the first resistor. The other of the emitter and collector of the fifth transistor serves as the third input terminal of the impedance adjustment circuit.

[0016] Preferably, the first control sub-signal is the first radio frequency signal, and the second control sub-signal is the second radio frequency signal.

[0017] In a second aspect, the present invention provides a power amplifier that includes the linearization circuit described above.

[0018] Compared with related technologies, the impedance adjustment circuit in the linearization circuit of the present invention connects to the first control signal and the two radio frequency signals of the power amplifier through its three input terminals respectively. The first control signal, the first radio frequency signal, and the second radio frequency signal all include a DC component. The voltage value connected to the second input terminal of the impedance adjustment circuit changes with the change of the first radio frequency signal, and the voltage value connected to the third input terminal of the impedance adjustment circuit changes with the change of the second radio frequency signal, so as to dynamically adjust the impedance of the impedance adjustment circuit. When the linearization circuit is applied to the power amplifier, it can achieve the effect of flexibly adjusting the linearity of the power amplifier, that is, reducing the nonlinear distortion generated by the power amplifier in the process of amplifying the radio frequency signal, thereby compensating for the nonlinear distortion of the power amplifier and improving the quality of the radio frequency signal. Attached Figure Description

[0019] The present invention will now be described in detail with reference to the accompanying drawings. The above and other aspects of the present invention will become clearer and more readily understood through the detailed description following the accompanying drawings. In the drawings: Figure 1 This is a circuit diagram of the linearization circuit in a specific embodiment of the present invention; Figure 2 The circuit diagrams are shown in the second and third embodiments of the present invention. Figure 3 This is a circuit diagram of the linearization circuit in a specific embodiment four of the present invention; Figure 4 This is a circuit diagram of the linearization circuit in a specific embodiment five of the present invention; Figure 5 This is a circuit diagram of the linearization circuit in a specific embodiment six of the present invention; Figure 6 This is a circuit diagram of the power amplifier in Embodiment 7 of the present invention. Detailed Implementation

[0020] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains; the terminology used herein in the specification of the application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application; the terms "comprising" and "having," and any variations thereof, in the specification, claims, and foregoing drawings of this application, are intended to cover non-exclusive inclusion. The terms "first," "second," etc., in the specification, claims, or foregoing drawings of this application are used to distinguish different objects, not to describe a particular order.

[0021] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0022] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0023] Example 1 This invention provides a linearization circuit 100 for compensating the linearity of a power amplifier, combined with... Figures 1 to 5 As shown, it includes an impedance adjustment circuit 10. The first input terminal of the impedance adjustment circuit 10 is used to connect to a first control signal VG, the second input terminal of the impedance adjustment circuit 10 is used to connect to a first radio frequency signal VN, and the third input terminal of the impedance adjustment circuit 10 is used to connect to a second radio frequency signal VP. The first control signal VG, the first radio frequency signal VN, and the second radio frequency signal VP all include a DC component. The first radio frequency signal VN and the second radio frequency signal VP also include a radio frequency component.

[0024] The voltage value connected to the second input terminal of the impedance adjustment circuit 10 changes with the change of the first radio frequency signal VN, and the voltage value connected to the third input terminal of the impedance adjustment circuit 10 changes with the change of the second radio frequency signal VP, so as to dynamically adjust the impedance of the impedance adjustment circuit 10.

[0025] Of course, depending on actual needs, the first control signal VG can also be designed to change with the first radio frequency signal VN and / or the second radio frequency signal VP, so that the voltage value connected to the first input terminal of the impedance adjustment circuit 10 changes with the first radio frequency signal VN and / or the second radio frequency signal VP. This can also achieve the effect of dynamically adjusting the impedance of the impedance adjustment circuit 10.

[0026] In this embodiment, as Figure 1 As shown, the impedance adjustment circuit 10 includes a first field-effect transistor T1. The gate of the first field-effect transistor T1 serves as the first input terminal of the impedance adjustment circuit 10. One of the source and drain of the first field-effect transistor T1 serves as the second input terminal of the impedance adjustment circuit 10. The other of the source and drain of the first field-effect transistor T1 serves as the third input terminal of the impedance adjustment circuit 10.

[0027] The second RF signal VP is the RF ground signal, which is equivalent to its RF component being zero. At this time, only the voltage value connected to the second input terminal of the impedance adjustment circuit 10 will change, so as to dynamically adjust the impedance of the impedance adjustment circuit 10. When the linearization circuit 100 is applied to the power amplifier, it can achieve the effect of flexibly adjusting the linearity of the power amplifier, reducing the nonlinear distortion generated by the power amplifier in the process of amplifying the RF signal, thereby improving the quality of the RF signal.

[0028] If the first control signal VG needs to change with the first RF signal VN and / or the second RF signal VP, then the first control signal VG will only change with the first RF signal VN, causing the voltage value connected to the first input terminal of the impedance adjustment circuit 10 to change with the first RF signal VN. This can also achieve the effect of dynamically adjusting the impedance of the impedance adjustment circuit 10.

[0029] Compared with related technologies, the impedance adjustment circuit 10 in the linearization circuit 100 of this embodiment is connected to the first control signal VG and the two radio frequency signals of the power amplifier through its three input terminals respectively. The first control signal VG, the first radio frequency signal VN, and the second radio frequency signal VP all include DC components. The voltage value connected to the second input terminal of the impedance adjustment circuit 10 is limited to change with the change of the first radio frequency signal VN, and the voltage value connected to the third input terminal of the impedance adjustment circuit 10 changes with the change of the second radio frequency signal VP, so as to dynamically adjust the impedance of the impedance adjustment circuit 10. When the linearization circuit 100 is applied to the power amplifier, it can achieve the effect of flexibly adjusting the linearity of the power amplifier, that is, reducing the nonlinear distortion generated by the power amplifier in the process of amplifying the radio frequency signal, achieving the effect of compensating for the nonlinear distortion of the power amplifier, and thus improving the quality of the radio frequency signal.

[0030] Example 2 Unlike Example 1, as Figure 2 As shown, in the linearization circuit 200 of this embodiment, the first radio frequency signal VN and the second radio frequency signal VP are opposite signals, that is, the first radio frequency signal VN and the second radio frequency signal VP are about 180° out of phase.

[0031] The linearization circuit 200 also includes a first capacitor C1, a first resistor R1, a second capacitor C2, and a second resistor R2; The first terminal of the first capacitor C1 is used to receive the first radio frequency signal VN, and the second terminal of the first capacitor C1 is connected to the second input terminal of the impedance adjustment circuit 10.

[0032] The first end of the first resistor R1 is connected to the second input terminal of the impedance adjustment circuit 10, and the second end of the first resistor R1 is used to input the second control signal VDS. The second control signal VDS includes a DC component and an AC component, and the second control signal VDS changes with the change of the first radio frequency signal VN and / or the second radio frequency signal VP.

[0033] The first terminal of the second capacitor C2 is used to receive the second radio frequency signal VP, and the second terminal of the second capacitor C2 is connected to the third input terminal of the impedance adjustment circuit 10. The first end of the second resistor R2 is connected to the third input terminal of the impedance adjustment circuit 10, and the second end of the second resistor R2 is used to connect to the second control signal VDS.

[0034] The first capacitor C1 and the second capacitor C2 are used to block DC and contribute capacitive reactance, respectively; the first resistor R1 and the second resistor R2 are used to isolate AC.

[0035] In this embodiment, since the first control signal VG changes with the first radio frequency signal VN and / or the second radio frequency signal VP, and the second control signal VDS also changes with the first radio frequency signal VN and / or the second radio frequency signal VP, when the first radio frequency signal VN and / or the second radio frequency signal VP changes, the voltage connected to the first input terminal, the voltage connected to the second input terminal, and the voltage connected to the third input terminal of the impedance adjustment circuit 10 will also change accordingly, so as to dynamically adjust the impedance of the impedance adjustment circuit 10. That is, the effective impedance, amplitude, and phase of the first radio frequency signal VN and the second radio frequency signal VP can be dynamically adjusted, thereby compensating for the nonlinear distortion of the power amplifier, improving the overall linearity of the power amplifier, and improving the quality of the radio frequency signal.

[0036] Example 3 Based on Embodiment 2, such as Figure 2As shown, in the linearization circuit 200 of this embodiment, the impedance adjustment circuit 10 includes a first field-effect transistor T1; the gate of the first field-effect transistor T1 serves as the first input terminal of the impedance adjustment circuit 10, one of the source and drain of the first field-effect transistor T1 serves as the second input terminal of the impedance adjustment circuit 10, and the other of the source and drain of the first field-effect transistor T1 serves as the third input terminal of the impedance adjustment circuit 10.

[0037] Of course, depending on the actual needs, the first field-effect transistor T1 can also be replaced with the first transistor or other similar transistors; if the first transistor is selected, the base of the first transistor is used as the first input terminal of the impedance adjustment circuit 10, one of the collector and emitter of the first transistor is used as the second input terminal of the impedance adjustment circuit 10, and the other of the collector and emitter of the first transistor is used as the third input terminal of the impedance adjustment circuit 10.

[0038] In practical applications, by selecting appropriate bias DC voltages for the first control signal VG and the second control signal VDS, the overall effective conduction impedance of the impedance adjustment circuit 10 in this embodiment can decrease within a certain power range as the first RF signal VN and the second RF signal VP increase. Adjusting the bias DC voltages of the first control signal VG and / or the second control signal VDS as the first RF signal VN and the second RF signal VP change can also adjust the conduction impedance of the impedance adjustment circuit 10. Selecting appropriate bias DC voltages for the first control signal VG and the second control signal VDS can keep the impedance adjustment circuit 10 in a high-resistance or low-resistance state, or allow its overall effective conduction impedance to decrease as the first RF signal VN and the second RF signal VP increase. When the impedance of the impedance adjustment circuit 10 decreases as the first RF signal VN and the second RF signal VP increase, the effective impedance magnitude and phase between the first RF signal VN and the second RF signal VP also change, thereby dynamically adjusting the amplitude and phase between the first RF signal VN and the second RF signal VP.

[0039] Example 4 Based on Embodiment 2, such as Figure 3 As shown, in the linearization circuit 300 of this embodiment, the first control signal VG is divided into a first control sub-signal VGN and a second control sub-signal VGP; the impedance adjustment circuit 10 includes a second field-effect transistor T2 and a third field-effect transistor T3, and the gates of the second field-effect transistor T2 and the third field-effect transistor T3 together serve as the first input terminal of the impedance adjustment circuit 10.

[0040] The gate of the second field-effect transistor T2 is used to connect to the first control sub-signal VGN, and one of the sources and drains of the second field-effect transistor T2 serves as the second input terminal of the impedance adjustment circuit 10.

[0041] The gate of the third field-effect transistor T3 is used to connect to the second control sub-signal VGP. One end of the source and the drain of the third field-effect transistor T3 is connected to the other end of the source and the drain of the second field-effect transistor T2. The other end of the source and the drain of the third field-effect transistor T3 serves as the third input terminal of the impedance adjustment circuit 10.

[0042] Of course, depending on the actual needs, the second field-effect transistor T2 can be replaced with a second transistor or other similar transistors, and the third field-effect transistor T3 can be replaced with a third transistor or other similar transistors; if the second transistor and the third transistor are selected, the base of the second transistor and the base of the third transistor are used together as the first input terminal of the impedance adjustment circuit 10.

[0043] The base of the second transistor is used to connect to the first control sub-signal VGN, and one of the emitter and collector of the second transistor serves as the second input terminal of the impedance adjustment circuit 10. The base of the third transistor is used to connect to the second control sub-signal VGP. One end of the emitter and collector of the third transistor is connected to the emitter and collector of the second transistor, and the other end of the emitter and collector of the third transistor serves as the third input terminal of the impedance adjustment circuit 10.

[0044] Of course, depending on actual needs, it can also be designed so that the first control sub-signal VGN changes with the first RF signal VN, and the second control sub-signal VGP changes with the second RF signal VP. Since the linearization circuits 300 are all connected to the same power amplifier's RF signal, the first control sub-signal VGN and the second control sub-signal VGP only need to change with the RF signal of the connected power amplifier; it is not necessarily that the first control sub-signal VGN changes with the first RF signal VN, and the second control sub-signal VGP changes with the second RF signal VP.

[0045] In practical applications, appropriate bias DC voltages for the first control sub-signal VGN and the second control sub-signal VGP, as well as the bias DC voltage for the second control signal VDS, are selected, including radio frequency components. The first control sub-signal VGN and the second control sub-signal VGP are inverse signals, and the amplitudes of the radio frequency signals of the first control sub-signal VGN and / or the second control sub-signal VGP are not less than the amplitudes of the first radio frequency signal VN and the second radio frequency signal VP. That is, the real-time voltages of the gate and source of the second field-effect transistor T2 or the third field-effect transistor T3 decrease for a certain period of time, and the equivalent on-resistance increases at this time. This allows the overall effective on-resistance of the impedance adjustment circuit 10 in this embodiment to increase within a certain power range as the first RF signal VN and the second RF signal VP increase. Adjusting the bias DC voltages of the second control signal VDS and / or the first control sub-signal VGN and the second control sub-signal VGP as the first RF signal VN and the second RF signal VP change can also adjust the on-resistance of the impedance adjustment circuit 10. By selecting appropriate bias DC voltage values ​​for the second control signal VDS, the first control sub-signal VGN, and the second control signal VGP, the impedance adjustment circuit 10 can be kept in a low-impedance state under small RF signals, with the overall effective on-resistance increasing as the RF signal increases. This is because the second field-effect transistor T2 and the third field-effect transistor T3 are in series; as the RF power increases, the impedance of the second field-effect transistor T2 will increase for a portion of a frequency cycle. As the time decreases, the impedance of the third field-effect transistor T3 changes in the opposite direction. The series impedance of the second field-effect transistor T2 and the third field-effect transistor T3 depends on the larger impedance of the second field-effect transistor T2 and the third field-effect transistor T3. Therefore, the effective impedance will increase with the increase of the radio frequency signal. If the first control sub-signal VGN (decreases the bias DC voltage), the second control sub-signal VGP (decreases the bias DC voltage), and / or the second control signal VDS (increases the bias DC voltage) are dynamically adjusted as the radio frequency signal increases, the series impedance of the second field-effect transistor T2 and the third field-effect transistor T3 can be further increased. When the impedance of the impedance adjustment circuit 10 increases with the increase of the power of the first radio frequency signal VN and the second radio frequency signal VP, the magnitude and phase of the effective impedance between the first radio frequency signal VN and the second radio frequency signal VP will also change accordingly, thereby dynamically adjusting the amplitude and phase between the first radio frequency signal VN and the second radio frequency signal VP.

[0046] Example 5 Based on Embodiment 2, such as Figure 4As shown, in the linearization circuit 400 of this embodiment, the first control signal VG is divided into a first control sub-signal VGN and a second control sub-signal VGP; the impedance adjustment circuit 10 includes a fourth field-effect transistor T4 and a fifth field-effect transistor T5, and the gates of the fourth field-effect transistor T4 and the fifth field-effect transistor T5 together serve as the first input terminal of the impedance adjustment circuit 10.

[0047] The gate of the fourth field-effect transistor T4 is used to connect to the first control sub-signal VGN. One of the source and drain of the fourth field-effect transistor T4 serves as the second input terminal of the impedance adjustment circuit 10. The other end of the source and drain of the fourth field-effect transistor T4 is connected to the first terminal of the second resistor R2.

[0048] The gate of the fifth field-effect transistor T5 is used to connect to the second control sub-signal VGP. One of the sources and drains of the fifth field-effect transistor T5 is connected to the first terminal of the first resistor R1. The other end of the sources and drains of the fifth field-effect transistor T5 serves as the third input terminal of the impedance adjustment circuit 10.

[0049] Of course, depending on the actual needs, the fourth field-effect transistor T4 can be replaced with a fourth transistor or other similar transistors, and the fifth field-effect transistor T5 can be replaced with a fifth transistor or other similar transistors; if the fourth transistor and the fifth transistor are selected, the base of the fourth transistor and the base of the fifth transistor are used together as the first input terminal of the impedance adjustment circuit 10.

[0050] The base of the fourth transistor is used to connect to the first control sub-signal VGN. One of the emitter and collector of the fourth transistor serves as the second input terminal of the impedance adjustment circuit 10. The other end of the emitter and collector of the fourth transistor is connected to the first terminal of the second resistor R2.

[0051] The base of the fifth transistor is used to connect to the second control sub-signal VGP. One of the emitter and collector of the fifth transistor is connected to the first end of the first resistor R1. The other end of the emitter and collector of the fifth transistor serves as the third input terminal of the impedance adjustment circuit 10.

[0052] Of course, depending on actual needs, it can also be designed so that the first control sub-signal VGN changes with the first RF signal VN, and the second control sub-signal VGP changes with the second RF signal VP. Since the linearization circuits 400 are all connected to the same power amplifier's RF signal, the first control sub-signal VGN and the second control sub-signal VGP only need to change with the RF signal of the connected power amplifier; it is not necessarily that the first control sub-signal VGN changes with the first RF signal VN, and the second control sub-signal VGP changes with the second RF signal VP.

[0053] The linearization circuit 400 in this embodiment is basically the same as the linearization circuit 300 in the above embodiment four. The only difference is that the connection method has been partially modified. Therefore, its working principle is the same as that of the linearization circuit 300 in the above embodiment four, and will not be described in detail here.

[0054] In practical applications, select appropriate bias DC voltages for the first control sub-signal VGN and the second control sub-signal VGP, which contain radio frequency components, as well as the bias DC voltage for the second control signal VDS. The first control sub-signal VGN and the second control sub-signal VGP are inverse signals to each other. The impedances of the fourth field-effect transistor T4 and the fifth field-effect transistor T5 decrease as the power of the radio frequency signal increases for a portion of the time. This allows the overall effective on-resistance of the impedance adjustment circuit 10 in this embodiment to decrease as the first RF signal VN and the second RF signal VP increase within a certain power range. Adjusting the bias DC voltages of the second control signal VDS and / or the first control sub-signal VGN and the second control sub-signal VGP as the first RF signal VN and the second RF signal VP changes can also adjust the on-resistance of the impedance adjustment circuit 10. By selecting appropriate bias DC voltage values ​​for the second control signal VDS, the first control sub-signal VGN, and the second control signal VGP, the impedance adjustment circuit 10 can be kept in a high-impedance state under small RF signals, with the overall effective on-resistance decreasing as the RF signal increases. This is because the fourth field-effect transistor T4 and the fifth field-effect transistor T5 are in parallel; as the power of the RF signal increases, the impedance of the fourth field-effect transistor T4 will increase for part of a frequency cycle and decrease for part of a frequency cycle. The impedance of the fifth field-effect transistor T5 changes in the opposite direction. The parallel impedance of the fourth field-effect transistor T4 and the fifth field-effect transistor T5 depends on the smaller impedance of the fourth field-effect transistor T4 and the fifth field-effect transistor T5. Therefore, the effective impedance will decrease as the RF signal increases. If the first control sub-signal VGN (increasing the bias DC voltage and / or RF component), the second control sub-signal VGP (increasing the bias DC voltage and / or RF component), and / or the second control signal VDS (decreasing the bias DC voltage) are dynamically adjusted as the RF signal increases, the parallel impedance of the fourth field-effect transistor T4 and the fifth field-effect transistor T5 can be further reduced. When the impedance of the impedance adjustment circuit 10 decreases as the power of the first RF signal VN and the second RF signal VP increases, the magnitude and phase of the effective impedance between the first RF signal VN and the second RF signal VP will also change accordingly, thereby dynamically adjusting the amplitude and phase between the first RF signal VN and the second RF signal VP.

[0055] Example 6 Unlike Example 5, as Figure 5 As shown, in the linearization circuit 500 of this embodiment, the first control sub-signal VGN is the first radio frequency signal VN, and the second control sub-signal VGP is the second radio frequency signal VP.

[0056] The linearization circuit 500 in this embodiment is basically the same as the linearization circuit 400 in the above embodiment 5. The difference is that the first control sub-signal VGN is defined as the first radio frequency signal VN, and the second control sub-signal VGP is defined as the second radio frequency signal VP. Therefore, its working principle is the same as that of the linearization circuit 400 in the above embodiment 5, and will not be described in detail here.

[0057] In embodiments two to six above, by selecting different sizes of the devices in the impedance adjustment circuit 10 and the sizes of the first capacitor C1 and the second capacitor C2, and by using different bias DC voltages of the first control signal VG and the second control signal VDS, different nonlinear compensation characteristics can be achieved. Furthermore, by changing the voltage of the second control signal VDS, the nonlinear compensation characteristics can be changed, so that when applied to a power amplifier, it exhibits different nonlinear changes under different RF signal powers, thereby compensating for the nonlinear characteristics of the power amplifier under different powers.

[0058] When the impedance adjustment circuit 10 uses a field-effect transistor, the body of the field-effect transistor can be connected to a bias voltage through a resistor or directly to a bias voltage. This bias voltage can affect and adjust the linearity compensation effect of the circuit through the substrate bias effect.

[0059] When applied to a power amplifier, the second and third input terminals of the impedance adjustment circuit 10 can be connected to the RF signals before and after amplification by the power amplifier, respectively, or to the RF signals of the first and second input terminals of the differential power amplifier. Of course, the second and third input terminals of the impedance adjustment circuit 10 can also be connected to the RF signal of the power amplifier at one end and to the RF ground at the other end, which is equivalent to direct grounding. When the linearization circuit is connected to the power amplifier in this way, the grounded end does not need to be connected to the DC blocking capacitor and the AC blocking resistor. For example, when the second input terminal of the impedance adjustment circuit 10 is grounded, the first capacitor C1 and the first resistor R1 do not need to be connected.

[0060] When applied to power amplifiers, any two or more sets of linearization circuits can be used for linearity compensation. The selected linearization circuits can have the same or different circuit structures. If the same set of linearization circuits is used, the transistors (field-effect transistors or bipolar junction transistors), capacitors, and resistors will all be of different types. The nonlinearity compensation characteristics can be changed by altering the voltage of the second control signal VDS, thereby adjusting the linearity of the power amplifier to respond to changes in its linearity.

[0061] Example 7 This invention provides a power amplifier 600, such as... Figure 6 As shown, it includes the linearization circuit 300 in the above embodiment four.

[0062] The power amplifier 600 in this embodiment also includes a power amplifier circuit 20; the power amplifier circuit 20 includes a sixth field-effect transistor T6, a seventh field-effect transistor T7, an eighth field-effect transistor T8, and a ninth field-effect transistor T9.

[0063] The gate of the sixth field-effect transistor T6 is connected to the first terminal of the first capacitor C1.

[0064] The gate of the seventh field-effect transistor T7 is connected to the second terminal of the second capacitor C2, and the source of the seventh field-effect transistor T7 is connected to the source of the sixth field-effect transistor T6 and then grounded.

[0065] The source of the eighth field-effect transistor T8 is connected to the drain of the sixth field-effect transistor T6, and the drain of the eighth field-effect transistor T8 is used to connect the first voltage signal VD2N.

[0066] The gate of the ninth field-effect transistor T9 is connected to the gate of the eighth field-effect transistor T8 and then a bias voltage VCG is applied. The source of the ninth field-effect transistor T9 is connected to the drain of the seventh field-effect transistor T7. The drain of the ninth field-effect transistor T9 is used to apply the second voltage signal VD2P.

[0067] The sixth field-effect transistor T6 and the eighth field-effect transistor T8 form a common-source transistor, the seventh field-effect transistor T7 and the ninth field-effect transistor T9 form a common-source transistor, and the eighth field-effect transistor T8 and the ninth field-effect transistor T9 form a common-gate transistor; the sixth field-effect transistor T6 to the ninth field-effect transistor T9 form a differential common-source power amplifier circuit 20.

[0068] The gate of the second field-effect transistor T2 is connected to the drain of the sixth field-effect transistor T6 to receive the first control sub-signal VD1N, and the gate of the third field-effect transistor T3 is connected to the drain of the seventh field-effect transistor T7 to receive the second control sub-signal VD1P. At this time, the voltage signals of the gates of the second field-effect transistor T2 and the third field-effect transistor T3 change dynamically with the power of the first radio frequency signal VN and the second radio frequency signal VP.

[0069] In this embodiment, the power amplifier 600, by selecting appropriate second control signal VDS voltage and bias voltage VCG, can dynamically increase the overall effective on-resistance of the second field-effect transistor T2 connected in series with the third field-effect transistor T3 within a certain power range as the power of the first radio frequency signal VN and the second radio frequency signal VP increases. As the power of the first radio frequency signal VN and the second radio frequency signal VP increases, the bias DC voltages of the first control sub-signals VD1N and VD1P also decrease, thereby increasing the overall effective on-resistance of the second field-effect transistor T2 connected in series with the third field-effect transistor T3. Selecting appropriate second control signal VDS... The magnitude of the bias voltage VCG can make the second field-effect transistor T2 and the third field-effect transistor T3 be in a high-impedance or low-impedance state, or the overall effective on-resistance of the second field-effect transistor T2 connected in series with the third field-effect transistor T3 increases with the increase of the power of the first RF signal VN and the second RF signal VP. When the impedance of the second field-effect transistor T2 and the third field-effect transistor T3 increases with the increase of power, the magnitude and phase of the effective impedance between the first RF signal VN and the second RF signal VP will also change accordingly, thereby dynamically adjusting the amplitude and phase of the RF signal between the first RF signal VN and the second RF signal VP, and thus adjusting the linearity of the power amplifier 600.

[0070] Of course, depending on actual needs, the sixth field-effect transistor T6 to the ninth field-effect transistor T9 can also be replaced with a transistor. Correspondingly, the base, emitter, and collector of the transistor correspond to the gate, source, and drain of the field-effect transistor, respectively. Furthermore, the power amplifier 600 in this embodiment can also use other linearization circuits, which will not be described in detail here. Since the power amplifier 600 in this embodiment can use the linearization circuits from the aforementioned embodiments, it can also achieve the technical effects achieved by the corresponding linearization circuits, which will not be elaborated upon here.

[0071] It should be noted that the various embodiments described above with reference to the accompanying drawings are merely illustrative of the present invention and not intended to limit its scope. Those skilled in the art should understand that any modifications or equivalent substitutions made to the present invention without departing from its spirit and scope should be included within the scope of the present invention. Furthermore, unless the context otherwise requires, words appearing in the singular include those in the plural, and vice versa. Additionally, unless specifically stated otherwise, all or part of any embodiment may be used in conjunction with all or part of any other embodiment.

Claims

1. A linearization circuit for compensating the linearity of a power amplifier, the power amplifier comprising a sixth transistor, a seventh transistor, an eighth transistor, and a ninth transistor; wherein the sixth transistor is a sixth field-effect transistor or a sixth transistor, the seventh transistor is a seventh field-effect transistor or a seventh transistor, the eighth transistor is an eighth field-effect transistor or an eighth transistor, and the ninth transistor is a ninth field-effect transistor or a ninth transistor. The source or emitter of the seventh transistor is connected to the source or emitter of the sixth transistor and then grounded. The source or emitter of the eighth transistor is connected to the drain or collector of the sixth transistor, and the drain or collector of the eighth transistor is used to receive the first voltage signal. The gate or base of the ninth transistor is connected to the gate or base of the eighth transistor and then subjected to a bias voltage. The source or emitter of the ninth transistor is connected to the drain or collector of the seventh transistor. The drain or collector of the ninth transistor is used to receive a second voltage signal. The characteristic of this design is that... The linearization circuit includes an impedance adjustment circuit. The first input terminal of the impedance adjustment circuit is used to connect to the drain or collector of the sixth transistor and the drain or collector of the seventh transistor respectively to receive a first control signal. The second input terminal of the impedance adjustment circuit is used to receive a first radio frequency signal, and the third input terminal of the impedance adjustment circuit is used to receive a second radio frequency signal. The first control signal, the first radio frequency signal, and the second radio frequency signal all include a DC component; The voltage value connected to the second input terminal of the impedance adjustment circuit changes with the change of the first radio frequency signal, and the voltage value connected to the third input terminal of the impedance adjustment circuit changes with the change of the second radio frequency signal, so as to dynamically adjust the impedance of the impedance adjustment circuit. The first radio frequency signal and the second radio frequency signal are inverse signals; the linearization circuit further includes a first capacitor and a first resistor; The first terminal of the first capacitor is connected to the gate or base of the sixth transistor to receive the first radio frequency signal, and the second terminal of the first capacitor is connected to the second input terminal of the impedance adjustment circuit. The first end of the first resistor is connected to the second input end of the impedance adjustment circuit, and the second end of the first resistor is used to receive a second control signal; the second control signal includes a DC component and an AC component. The linearization circuit also includes a second capacitor and a second resistor; The first terminal of the second capacitor is connected to the gate or base of the seventh transistor to receive the second radio frequency signal, and the second terminal of the second capacitor is connected to the third input terminal of the impedance adjustment circuit. The first end of the second resistor is connected to the third input terminal of the impedance adjustment circuit, and the second end of the second resistor is used to connect to the second control signal. The first control signal is divided into a first control sub-signal and a second control sub-signal; the impedance adjustment circuit includes a second field-effect transistor and a third field-effect transistor, and the gate of the second field-effect transistor and the gate of the third field-effect transistor together serve as the first input terminal of the impedance adjustment circuit; The gate of the second field-effect transistor is used to connect to the drain or collector of the sixth transistor to receive the first control sub-signal, and one of the source and drain of the second field-effect transistor serves as the second input terminal of the impedance adjustment circuit. The gate of the third field-effect transistor is used to connect to the drain or collector of the seventh transistor to receive the second control sub-signal. One end of the source and the drain of the third field-effect transistor is connected to the other end of the source and the drain of the second field-effect transistor. The other end of the source and the drain of the third field-effect transistor serves as the third input terminal of the impedance adjustment circuit.

2. A linearization circuit for compensating the linearity of a power amplifier, the power amplifier comprising a sixth transistor, a seventh transistor, an eighth transistor, and a ninth transistor; wherein the sixth transistor is a sixth field-effect transistor or a sixth transistor, the seventh transistor is a seventh field-effect transistor or a seventh transistor, the eighth transistor is an eighth field-effect transistor or an eighth transistor, and the ninth transistor is a ninth field-effect transistor or a ninth transistor. The source or emitter of the seventh transistor is connected to the source or emitter of the sixth transistor and then grounded. The source or emitter of the eighth transistor is connected to the drain or collector of the sixth transistor, and the drain or collector of the eighth transistor is used to receive the first voltage signal. The gate or base of the ninth transistor is connected to the gate or base of the eighth transistor and then subjected to a bias voltage. The source or emitter of the ninth transistor is connected to the drain or collector of the seventh transistor. The drain or collector of the ninth transistor is used to receive a second voltage signal. The characteristic of this design is that... The linearization circuit includes an impedance adjustment circuit. The first input terminal of the impedance adjustment circuit is used to connect to the drain or collector of the sixth transistor and the drain or collector of the seventh transistor respectively to receive a first control signal. The second input terminal of the impedance adjustment circuit is used to receive a first radio frequency signal, and the third input terminal of the impedance adjustment circuit is used to receive a second radio frequency signal. The first control signal, the first radio frequency signal, and the second radio frequency signal all include a DC component; The voltage value connected to the second input terminal of the impedance adjustment circuit changes with the change of the first radio frequency signal, and the voltage value connected to the third input terminal of the impedance adjustment circuit changes with the change of the second radio frequency signal, so as to dynamically adjust the impedance of the impedance adjustment circuit. The first radio frequency signal and the second radio frequency signal are inverse signals; the linearization circuit further includes a first capacitor and a first resistor; The first terminal of the first capacitor is connected to the gate or base of the sixth transistor to receive the first radio frequency signal, and the second terminal of the first capacitor is connected to the second input terminal of the impedance adjustment circuit. The first end of the first resistor is connected to the second input end of the impedance adjustment circuit, and the second end of the first resistor is used to receive a second control signal; the second control signal includes a DC component and an AC component. The linearization circuit also includes a second capacitor and a second resistor; The first terminal of the second capacitor is connected to the gate or base of the seventh transistor to receive the second radio frequency signal, and the second terminal of the second capacitor is connected to the third input terminal of the impedance adjustment circuit. The first end of the second resistor is connected to the third input terminal of the impedance adjustment circuit, and the second end of the second resistor is used to connect to the second control signal. The first control signal is divided into a first control sub-signal and a second control sub-signal; the impedance adjustment circuit includes a second transistor and a third transistor, and the base of the second transistor and the base of the third transistor together serve as the first input terminal of the impedance adjustment circuit; The base of the second transistor is used to connect to the drain or collector of the sixth transistor to receive the first control sub-signal, and one of the emitter and collector of the second transistor serves as the second input terminal of the impedance adjustment circuit. The base of the third transistor is used to connect to the drain or collector of the seventh transistor to receive the second control sub-signal. One end of the emitter and collector of the third transistor is connected to the other end of the emitter and collector of the second transistor. The other end of the emitter and collector of the third transistor serves as the third input terminal of the impedance adjustment circuit.

3. A linearization circuit for compensating the linearity of a power amplifier, the power amplifier comprising a sixth transistor, a seventh transistor, an eighth transistor, and a ninth transistor; wherein the sixth transistor is a sixth field-effect transistor or a sixth transistor, the seventh transistor is a seventh field-effect transistor or a seventh transistor, the eighth transistor is an eighth field-effect transistor or an eighth transistor, and the ninth transistor is a ninth field-effect transistor or a ninth transistor. The source or emitter of the seventh transistor is connected to the source or emitter of the sixth transistor and then grounded. The source or emitter of the eighth transistor is connected to the drain or collector of the sixth transistor, and the drain or collector of the eighth transistor is used to receive the first voltage signal. The gate or base of the ninth transistor is connected to the gate or base of the eighth transistor and then subjected to a bias voltage. The source or emitter of the ninth transistor is connected to the drain or collector of the seventh transistor. The drain or collector of the ninth transistor is used to receive a second voltage signal. The characteristic of this design is that... The linearization circuit includes an impedance adjustment circuit. The first input terminal of the impedance adjustment circuit is used to connect to the drain or collector of the sixth transistor and the drain or collector of the seventh transistor respectively to receive a first control signal. The second input terminal of the impedance adjustment circuit is used to receive a first radio frequency signal, and the third input terminal of the impedance adjustment circuit is used to receive a second radio frequency signal. The first control signal, the first radio frequency signal, and the second radio frequency signal all include a DC component; The voltage value connected to the second input terminal of the impedance adjustment circuit changes with the change of the first radio frequency signal, and the voltage value connected to the third input terminal of the impedance adjustment circuit changes with the change of the second radio frequency signal, so as to dynamically adjust the impedance of the impedance adjustment circuit. The first radio frequency signal and the second radio frequency signal are inverse signals; the linearization circuit further includes a first capacitor and a first resistor; The first terminal of the first capacitor is connected to the gate or base of the sixth transistor to receive the first radio frequency signal, and the second terminal of the first capacitor is connected to the second input terminal of the impedance adjustment circuit. The first end of the first resistor is connected to the second input end of the impedance adjustment circuit, and the second end of the first resistor is used to receive a second control signal; the second control signal includes a DC component and an AC component. The linearization circuit also includes a second capacitor and a second resistor; The first terminal of the second capacitor is connected to the gate or base of the seventh transistor to receive the second radio frequency signal, and the second terminal of the second capacitor is connected to the third input terminal of the impedance adjustment circuit. The first end of the second resistor is connected to the third input terminal of the impedance adjustment circuit, and the second end of the second resistor is used to connect to the second control signal. The first control signal is divided into a first control sub-signal and a second control sub-signal; the impedance adjustment circuit includes a fourth field-effect transistor and a fifth field-effect transistor, and the gate of the fourth field-effect transistor and the gate of the fifth field-effect transistor together serve as the first input terminal of the impedance adjustment circuit; The gate of the fourth field-effect transistor is used to connect to the drain or collector of the sixth transistor to receive the first control sub-signal. One of the source and drain of the fourth field-effect transistor serves as the second input terminal of the impedance adjustment circuit, and the other of the source and drain of the fourth field-effect transistor is connected to the first terminal of the second resistor. The gate of the fifth field-effect transistor is used to connect to the drain or collector of the seventh transistor to receive the second control sub-signal. One of the source and drain of the fifth field-effect transistor is connected to the first terminal of the first resistor, and the other of the source and drain of the fifth field-effect transistor serves as the third input terminal of the impedance adjustment circuit.

4. A linearization circuit for compensating the linearity of a power amplifier, the power amplifier including a sixth transistor, a seventh transistor, an eighth transistor, and a ninth transistor; the sixth transistor is a sixth field-effect transistor or a sixth transistor, the seventh transistor is a seventh field-effect transistor or a seventh transistor, the eighth transistor is an eighth field-effect transistor or an eighth transistor, and the ninth transistor is a ninth field-effect transistor or a ninth transistor. The source or emitter of the seventh transistor is connected to the source or emitter of the sixth transistor and then grounded. The source or emitter of the eighth transistor is connected to the drain or collector of the sixth transistor, and the drain or collector of the eighth transistor is used to receive the first voltage signal. The gate or base of the ninth transistor is connected to the gate or base of the eighth transistor and then subjected to a bias voltage. The source or emitter of the ninth transistor is connected to the drain or collector of the seventh transistor. The drain or collector of the ninth transistor is used to receive a second voltage signal. The characteristic of this design is that... The linearization circuit includes an impedance adjustment circuit. The first input terminal of the impedance adjustment circuit is used to connect to the drain or collector of the sixth transistor and the drain or collector of the seventh transistor respectively to receive a first control signal. The second input terminal of the impedance adjustment circuit is used to receive a first radio frequency signal, and the third input terminal of the impedance adjustment circuit is used to receive a second radio frequency signal. The first control signal, the first radio frequency signal, and the second radio frequency signal all include a DC component; The voltage value connected to the second input terminal of the impedance adjustment circuit changes with the change of the first radio frequency signal, and the voltage value connected to the third input terminal of the impedance adjustment circuit changes with the change of the second radio frequency signal, so as to dynamically adjust the impedance of the impedance adjustment circuit. The first radio frequency signal and the second radio frequency signal are inverse signals; the linearization circuit further includes a first capacitor and a first resistor; The first terminal of the first capacitor is connected to the gate or base of the sixth transistor to receive the first radio frequency signal, and the second terminal of the first capacitor is connected to the second input terminal of the impedance adjustment circuit. The first end of the first resistor is connected to the second input end of the impedance adjustment circuit, and the second end of the first resistor is used to receive a second control signal; the second control signal includes a DC component and an AC component. The linearization circuit also includes a second capacitor and a second resistor; The first terminal of the second capacitor is connected to the gate or base of the seventh transistor to receive the second radio frequency signal, and the second terminal of the second capacitor is connected to the third input terminal of the impedance adjustment circuit. The first end of the second resistor is connected to the third input terminal of the impedance adjustment circuit, and the second end of the second resistor is used to connect to the second control signal. The first control signal is divided into a first control sub-signal and a second control sub-signal; the impedance adjustment circuit includes a fourth transistor and a fifth transistor, and the base of the fourth transistor and the base of the fifth transistor together serve as the first input terminal of the impedance adjustment circuit; The base of the fourth transistor is used to connect to the drain or collector of the sixth transistor to receive the first control sub-signal. One of the emitter and collector of the fourth transistor serves as the second input terminal of the impedance adjustment circuit. The other of the emitter and collector of the fourth transistor is connected to the first terminal of the second resistor. The base of the fifth transistor is used to connect to the drain or collector of the seventh transistor to receive the second control sub-signal. One of the emitter and collector of the fifth transistor is connected to the first terminal of the first resistor. The other of the emitter and collector of the fifth transistor serves as the third input terminal of the impedance adjustment circuit.

5. The linearization circuit as described in claim 3 or 4, characterized in that, The first control sub-signal is the first radio frequency signal, and the second control sub-signal is the second radio frequency signal.

6. A power amplifier, characterized in that, The power amplifier includes the linearization circuit as described in any one of claims 1 to 5.

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