Two-way time domain interleaving return-to-zero system applied to digital-to-analog converter

Abstract

The invention relates to a double-path time domain interleaving return-to-zero system applied to a digital-to-analog converter, which is characterized in that in a time domain interleaving parallel processing stage, a high-speed data stream is decomposed into four paths of low-rate parallel signals to be processed, so that the working frequency and the time sequence design difficulty of a rear-end digital logic circuit are remarkably reduced, and the reliability of the digital-to-analog converter is improved. The limitation of a digital system on the overall conversion rate of the digital-to-analog converter is effectively broken through; in a signal synthesis stage, a zero returning technology is introduced through a multiplexer unit, and four paths of low-rate parallel signals are combined into a double-path time domain interleaving zero returning signal, so that intersymbol interference caused by incomplete establishment of a switch transient process and a current source is inhibited, transient error energy introduced in a switch switching process is pushed to a high-frequency region, and the signal quality is improved. The spurious-free dynamic range of the digital-to-analog converter in the Nyquist range is expanded; according to the invention, the double-time-domain interleaving return-to-zero signal is designed to reserve wide time for the full establishment of the output signal, and the integrity and high linearity of the output signal are ensured while the dynamic error is effectively eliminated.

Description

A dual-channel time-domain interleaved return-to-zero system for digital-to-analog converters Technical Field

[0001] This invention relates to a dual-channel time-domain interleaved return-to-zero system for digital-to-analog converters, belonging to the field of mixed-signal integrated circuit design technology. Background Technology

[0002] High-speed digital-to-analog converters (DACs) are key components in the radio frequency (RF) signal transmission link, and their performance directly affects the signal quality and efficiency of the entire system. DACs are widely used in integrated RF transceivers, radar T / R modules, and direct digital frequency synthesizers to convert baseband or digital signals into high-quality analog signals. Therefore, the accuracy, operating frequency, and dynamic range of DACs directly impact the transmission rate, spectral purity, and overall link performance of wireless communication systems.

[0003] To meet the ever-increasing demands of 5G communication, broadband radar, and other systems for digital-to-analog converter (DAC) operating frequencies, the sampling rates of high-speed DACs are continuously improving. However, with the significant increase in conversion speed, the impact of dynamic non-ideal effects is amplified dramatically. Dynamic errors such as the finite output impedance of the current source, switching transient errors, and data-related inter-symbol interference gradually surpass the impact of random mismatch errors in the current source, becoming the main factors restricting the performance improvement of DACs. Summary of the Invention

[0004] The technical problem to be solved by the present invention is to provide a dual-channel time-domain interleaved return-to-zero system for digital-to-analog converters, which can suppress inter-symbol interference caused by switching transients and incomplete current source establishment, and effectively improve the spurious-free dynamic range of digital-to-analog converters in the Nyquist range.

[0005] To solve the above-mentioned technical problems, the present invention adopts the following technical solution: The present invention designs a dual-channel time-domain interleaved return-to-zero system for digital-to-analog converters, including a 4:2 multiplexer (MUX), a driving circuit, and four identical decoding circuits. The four parallel signals with frequencies of f0 / 4, obtained by decomposing a continuous digital signal at a preset f0 frequency, are received one-to-one by the four decoding circuits. After buffering and decoding, the corresponding decoded signals are output to the 4:2 multiplexer (MUX). Under the control of preset control signals, the 4:2 multiplexer (MUX) combines the received four decoded signals to obtain two time-domain interleaved return-to-zero signals, which are then output to the driving circuit. The driving circuit processes these signals to obtain corresponding driving signals, which are then output to the target controllable digital-to-analog converter. The target controllable digital-to-analog converter controls the analog differential current output.

[0006] As a preferred technical solution of the present invention: Based on a continuous digital signal with a preset frequency f0, the data bits in the continuous digital signal are first divided into groups of four consecutive data bits, and then each group is obtained by sequentially grouping the data bits in the continuous digital signal. Then, the data of the first data bit in each group is selected and combined to form a first parallel signal DIN_a; the data of the second data bit in each group is selected and combined to form a second parallel signal DIN_b; the data of the third data bit in each group is selected and combined to form a third parallel signal DIN_c; the data of the fourth data bit in each group is selected and combined to form a fourth parallel signal DIN_d; and the frequency of each parallel signal is f0 / 4.

[0007] As a preferred embodiment of the present invention: the 4:2 multiplexer MUX includes NMOS transistors M1, M2, M3, and M4, inverters A1 and A2, and a main switch. Main switch ,switch ,switch ,switch ,switch Among them, the main switch One end is connected to the main switch One end is connected to an external power source, the main switch The main switch is controlled by an external differential clock signal CLKN. The main switch is controlled by an external differential clock signal CLKP. The other end, the drain of NMOS transistor M4, the drain of NMOS transistor M2, and the input of inverter A2 are connected together. The gate of NMOS transistor M4 forms the input of a 4:2 multiplexer MUX, used to input the decoded signal D_d output by the corresponding decoding circuit of the fourth parallel signal DIN_d. The source of NMOS transistor M4 is connected to a switch. Grounding, switch The external clock signal CLK4 controls the input. The gate of NMOS transistor M2 forms the input of a 4:2 multiplexer MUX, used to receive the decoded signal D_b output from the corresponding decoding circuit of the second parallel signal DIN_b. The source of NMOS transistor M2 is switched... Grounding, switch The external clock signal CLK2 is used for control. The output of the inverter A2 forms one of the outputs of the 4:2 multiplexer MUX, which is used to output one of the time-domain interleaved return-to-zero signals S2.

[0008] Main switch The other end, the drain of NMOS transistor M3, the drain of NMOS transistor M1, and the input of inverter A1 are connected together. The gate of NMOS transistor M3 forms the input of a 4:2 multiplexer MUX, used to input the decoded signal D_c output from the corresponding decoding circuit of the third parallel signal DIN_c. The source of NMOS transistor M3 is connected to a switch. Grounding, switch The external clock signal CLK3 is used for control. The gate of NMOS transistor M1 forms the input terminal of a 4:2 multiplexer MUX, used to receive the decoded signal D_a output from the corresponding decoding circuit of the first parallel signal DIN_a. The source of NMOS transistor M1 is switched... Grounding, switch The external clock signal CLK1 is used for control, and the output of the inverter A1 forms another output of the 4:2 multiplexer MUX, which is used to output another time-domain interleaved return-to-zero signal S1.

[0009] As a preferred embodiment of the present invention: the frequency of the differential clock signal CLKN and the differential clock signal CLKP is f0 / 2, and the duty cycle is 50%; the frequency of the clock signals CLK1, CLK2, CLK3, and CLK4 is f0 / 4, and the duty cycle is 25%, and the phases of the clock signals CLK1, CLK2, CLK3, and CLK4 are successively different. They do not overlap.

[0010] As a preferred embodiment of the present invention: when the differential clock signal CLKN controls the connected main switch Closed, differential clock signal CLKP controls the connected main switch When disconnected, the connected switch is controlled by the clock signal CLK2. When closed, clock signal CLK4 controls the connected switch. Disconnecting the decoded signal D_b enables the output of the time-domain interleaved return-to-zero signal S2, while the time-domain interleaved return-to-zero signal S1 is returned to zero; alternatively, the connected switch can be controlled by the clock signal CLK2. Disconnect, clock signal CLK4 controls the connected switch The signal is closed, and the decoded signal D_d is used to form a time-domain interleaved return-to-zero signal S2 for output, while the time-domain interleaved return-to-zero signal S1 is returned to zero.

[0011] When the differential clock signal CLKN controls the connected main switch Disconnect, differential clock signal CLKP controls the connected main switch When closed, the connected switch is controlled by the clock signal CLK1. When closed, clock signal CLK3 controls the connected switch. Disconnection enables the decoded signal D_a to form a time-domain interleaved return-to-zero signal S1 for output, while the time-domain interleaved return-to-zero signal S2 is returned to zero; the connected switch is controlled by the clock signal CLK1. Disconnect, clock signal CLK3 controls the connected switch The signal is closed, and the decoded signal D_c is used to form a time-domain interleaved return-to-zero signal S1 for output, while the time-domain interleaved return-to-zero signal S2 is returned to zero.

[0012] As a preferred technical solution of the present invention: based on the output of time-domain interleaved return-to-zero signals S1 and S2 from the 4:2 multiplexer MUX, the return-to-zero driving signal SN1 corresponding to the time-domain interleaved return-to-zero signal S1 and its inverted return-to-zero driving signal SN1N are processed by the driving circuit and output to the target controllable digital-to-analog converter, and the return-to-zero driving signal SN2 corresponding to the time-domain interleaved return-to-zero signal S2 and its inverted return-to-zero driving signal SN2N are output to the target controllable digital-to-analog converter.

[0013] As a preferred embodiment of the present invention: the target controllable digital-to-analog converter is a four-phase switching digital-to-analog converter, including a current source I. a ,switch ,switch ,switch ,switch Among them, current source I a One end is connected to an external power source, current source I a The other end is connected to the switch respectively One end, switch One end, switch One end, switch One end, switch The switch is controlled by an external zero-reset drive signal SN2. The switch is controlled by an external inverted return-to-zero drive signal SN2N. The switch is controlled by an external zero-reset drive signal SN1. The switch is controlled by an external inverted return-to-zero drive signal SN1N. The other end is connected to the switch The other end is connected to form the positive analog signal output port I of the four-phase switch digital-to-analog converter. OUTP Used to output positive analog signals, switches The other end is connected to the switch The other end is connected to the inverted analog signal output port I of the four-phase switch digital-to-analog converter. OUTN It is used to output an inverted analog signal.

[0014] As a preferred embodiment of the present invention: when the zero-reset drive signal SN2 controls the connected switch Close, switch ,switch ,switch If the current source I is disconnected under the respective drive signals, then a The corresponding current flows in the positive direction of the analog signal output port I. OUTP ;

[0015] When the zero-reset drive signal SN1 controls the connected switch Close, switch ,switch ,switch If the current source I is disconnected under the respective drive signals, then a The corresponding current flows in the positive direction of the analog signal output port I. OUTP ;

[0016] When the inverted zero-return drive signal SN2N controls the connected switch Close, switch ,switch ,switch If the current source I is disconnected under the respective drive signals, then a The corresponding current flows to the reverse analog signal output port I. OUTN ;

[0017] When the inverted zero-return drive signal SN1N controls the connected switch Close, switch ,switch ,switch If the current source I is disconnected under the respective drive signals, then a The corresponding current flows to the reverse analog signal output port I. OUTN .

[0018] The dual-channel time-domain interleaved return-to-zero system for digital-to-analog converters described in this invention has the following technical advantages compared with existing technologies:

[0019] This invention designs a dual-channel time-domain interleaved return-to-zero system for digital-to-analog converters (DACs). The design integrates time-domain interleaving parallel processing with return-to-zero technology, achieving simultaneous improvement in conversion rate and dynamic performance. In the time-domain interleaving parallel processing stage, the high-speed data stream is decomposed into four lower-speed parallel signals for processing, significantly reducing the operating frequency and timing design difficulty of the back-end digital logic circuits, thus effectively overcoming the limitations imposed by the digital system on the overall conversion rate of the DAC. In the signal synthesis stage, a 4:2 multiplexer unit is used to introduce return-to-zero technology, merging the four lower-speed parallel signals into two high-speed return-to-zero signals, i.e., dual-channel time-domain interleaved return-to-zero signals. This not only significantly suppresses inter-symbol interference caused by switching transients and incomplete current source establishment, but also pushes the transient error energy introduced during switching to the high-frequency region, thereby greatly improving the spurious-free dynamic range of the DAC within the Nyquist range. The dual time-domain interleaved return-to-zero signal in this invention provides ample time for the output signal to fully establish, avoiding the problems of output signal energy loss and insufficient signal establishment time that may be caused by conventional return-to-zero techniques. While effectively eliminating dynamic errors, it ensures the integrity and high linearity of the output signal. Attached Figure Description

[0020] Figure 1 is a structural block diagram of the dual-channel time-domain interleaved return-to-zero system designed for digital-to-analog converters according to the present invention;

[0021] Figure 2 is a circuit diagram of the 4:2 multiplexer MUX designed in this invention;

[0022] Figure 3 is a timing diagram of the 4:2 multiplexer MUX designed in this invention;

[0023] Figure 4 is a circuit diagram of the four-phase switch digital-to-analog converter designed in this invention. Detailed Implementation

[0024] The specific embodiments of the present invention will be further described in detail below with reference to the accompanying drawings.

[0025] This invention designs a dual-channel time-domain interleaved return-to-zero system for digital-to-analog converters. In practical application, as shown in Figure 1, the specific design includes a 4:2 multiplexer (MUX), a driver circuit, and four identical decoding circuits. Four parallel signals with frequencies of f0 / 4, obtained by decomposing a continuous digital signal at a preset f0 frequency, are received one-to-one by the four decoding circuits. After buffering and decoding, the corresponding decoded signals are output to the 4:2 multiplexer (MUX). Under the control of preset control signals, the 4:2 multiplexer (MUX) combines the received four decoded signals to obtain two time-domain interleaved return-to-zero signals, which are then output to the driver circuit. The driver circuit processes these signals to obtain corresponding drive signals and outputs them to the target controllable digital-to-analog converter, enabling analog differential current output.

[0026] Applying the above design scheme to practice, as shown in Figure 1, the first stage is the time-domain interleaved parallel processing stage. Specifically, for the continuous digital signal with a preset frequency of f0, the data bits in the continuous digital signal are divided into groups of four consecutive data bits. Each group is then selected, and the data of the first data bit in each group is combined to form the first parallel signal DIN_a; the data of the second data bit in each group is selected to form the second parallel signal DIN_b; the data of the third data bit in each group is selected to form the third parallel signal DIN_c; and the data of the fourth data bit in each group is selected to form the fourth parallel signal DIN_d. The frequency of each parallel signal is f0 / 4.

[0027] Next, as shown in Figure 1, the first parallel signal DIN_a, the second parallel signal DIN_b, the third parallel signal DIN_c, and the fourth parallel signal DIN_d are sent to each decoding circuit in turn. Each decoding circuit performs buffering and decoding processing on the received parallel signal and outputs the corresponding decoded signal, namely decoded signal D_a, decoded signal D_b, decoded signal D_c, and decoded signal D_d, which are then further sent to the 4:2 multiplexer MUX.

[0028] Regarding the 4:2 multiplexer MUX, in practical applications, as shown in Figure 2, it includes NMOS transistors M1, M2, M3, and M4, inverters A1 and A2, and a main switch. Main switch ,switch ,switch ,switch ,switch Among them, the main switch One end is connected to the main switch One end is connected to an external power source, the main switch The main switch is controlled by an external differential clock signal CLKN. The main switch is controlled by an external differential clock signal CLKP. The other end, the drain of NMOS transistor M4, the drain of NMOS transistor M2, and the input of inverter A2 are connected together. The gate of NMOS transistor M4 forms the input of a 4:2 multiplexer MUX, used to input the decoded signal D_d output by the corresponding decoding circuit of the fourth parallel signal DIN_d. The source of NMOS transistor M4 is connected to a switch. Grounding, switch The external clock signal CLK4 controls the input. The gate of NMOS transistor M2 forms the input of a 4:2 multiplexer MUX, used to receive the decoded signal D_b output from the corresponding decoding circuit of the second parallel signal DIN_b. The source of NMOS transistor M2 is switched... Grounding, switch The external clock signal CLK2 is used for control. The output of the inverter A2 forms one of the outputs of the 4:2 multiplexer MUX, which is used to output one of the time-domain interleaved return-to-zero signals S2.

[0029] As shown in Figure 2, the main switch The other end, the drain of NMOS transistor M3, the drain of NMOS transistor M1, and the input of inverter A1 are connected together. The gate of NMOS transistor M3 forms the input of a 4:2 multiplexer MUX, used to input the decoded signal D_c output from the corresponding decoding circuit of the third parallel signal DIN_c. The source of NMOS transistor M3 is connected to a switch. Grounding, switch The external clock signal CLK3 is used for control. The gate of NMOS transistor M1 forms the input terminal of a 4:2 multiplexer MUX, used to receive the decoded signal D_a output from the corresponding decoding circuit of the first parallel signal DIN_a. The source of NMOS transistor M1 is switched... Grounding, switch The external clock signal CLK1 is used for control, and the output of the inverter A1 forms another output of the 4:2 multiplexer MUX, which is used to output another time-domain interleaved return-to-zero signal S1.

[0030] Based on the designed 4:2 multiplexer MUX structure and the reception of each decoded signal, in the specific signal processing, the frequency of the differential clock signal CLKN and the differential clock signal CLKP is f0 / 2, with a duty cycle of 50%; the frequency of the clock signals CLK1, CLK2, CLK3, and CLK4 is f0 / 4, with a duty cycle of 25%, and the phases of the clock signals CLK1, CLK2, CLK3, and CLK4 are successively different. The multiplexers do not overlap. In practical applications, the timing diagram of the 4:2 multiplexer (MUX) is shown in Figure 3.

[0031] When the differential clock signal CLKN controls the connected main switch Closed, differential clock signal CLKP controls the connected main switch When disconnected, the connected switch is controlled by the clock signal CLK2. When closed, clock signal CLK4 controls the connected switch. Disconnecting the decoded signal D_b enables the output of the time-domain interleaved return-to-zero signal S2, while the time-domain interleaved return-to-zero signal S1 is returned to zero; alternatively, the connected switch can be controlled by the clock signal CLK2. Disconnect, clock signal CLK4 controls the connected switch The signal is closed, and the decoded signal D_d is used to form the time-domain interleaved return-to-zero signal S2 for output, while the time-domain interleaved return-to-zero signal S1 is returned to zero.

[0032] When the differential clock signal CLKN controls the connected main switch Disconnect, differential clock signal CLKP controls the connected main switch When closed, the connected switch is controlled by the clock signal CLK1. When closed, clock signal CLK3 controls the connected switch. Disconnection enables the decoded signal D_a to form a time-domain interleaved return-to-zero signal S1 for output, while the time-domain interleaved return-to-zero signal S2 is returned to zero; the connected switch is controlled by the clock signal CLK1. Disconnect, clock signal CLK3 controls the connected switch The signal is closed, and the decoded signal D_c is used to form a time-domain interleaved return-to-zero signal S1 for output, while the time-domain interleaved return-to-zero signal S2 is returned to zero.

[0033] In practice, the above design scheme is implemented by obtaining time-domain interleaved return-to-zero signals S1 and S2, which are then sent to the drive circuit. In specific applications, the drive circuit processes and outputs the return-to-zero drive signal SN1 corresponding to the time-domain interleaved return-to-zero signal S1 and its inverted return-to-zero drive signal SN1N to the target controllable digital-to-analog converter, and outputs the return-to-zero drive signal SN2 corresponding to the time-domain interleaved return-to-zero signal S2 and its inverted return-to-zero drive signal SN2N to the target controllable digital-to-analog converter.

[0034] The above design yielded SN1, SN1N, SN2, and SN2N, which will then be used to control the target controllable digital-to-analog converter. In practical applications, the target controllable digital-to-analog converter specifically adopts a four-phase switching digital-to-analog converter, as shown in Figure 4, which specifically includes current source I. a ,switch ,switch ,switch ,switch Among them, current source I a One end is connected to an external power source, current source I a The other end is connected to the switch respectively One end, switch One end, switch One end, switch One end, switch The switch is controlled by an external zero-reset drive signal SN2. The switch is controlled by an external inverted return-to-zero drive signal SN2N. The switch is controlled by an external zero-reset drive signal SN1. The switch is controlled by an external inverted return-to-zero drive signal SN1N. The other end is connected to the switch The other end is connected to form the positive analog signal output port I of the four-phase switch digital-to-analog converter. OUTP Used to output positive analog signals, switches The other end is connected to the switch The other end is connected to the inverted analog signal output port I of the four-phase switch digital-to-analog converter. OUTN It is used to output an inverted analog signal.

[0035] The control of the target controllable digital-to-analog converter by SN1, SN1N, SN2, and SN2N is as follows.

[0036] When the zero-reset drive signal SN2 controls the connected switch Close, switch ,switch ,switch If the current source I is disconnected under the respective drive signals, then a The corresponding current flows in the positive direction of the analog signal output port I. OUTP .

[0037] When the zero-reset drive signal SN1 controls the connected switch Close, switch ,switch ,switch If the current source I is disconnected under the respective drive signals, then a The corresponding current flows in the positive direction of the analog signal output port I. OUTP .

[0038] When the inverted zero-return drive signal SN2N controls the connected switch Close, switch ,switch ,switch If the current source I is disconnected under the respective drive signals, then aThe corresponding current flows to the reverse analog signal output port I. OUTN .

[0039] When the inverted zero-return drive signal SN1N controls the connected switch Close, switch ,switch ,switch If the current source I is disconnected under the respective drive signals, then a The corresponding current flows to the reverse analog signal output port I. OUTN .

[0040] The aforementioned technical solution, applied to a dual-channel time-domain interleaved return-to-zero system for digital-to-analog converters, employs a synergistic design of time-domain interleaving parallel processing and return-to-zero technology. This achieves simultaneous improvement in conversion rate and dynamic performance. Specifically, in the time-domain interleaving parallel processing stage, the high-speed data stream is decomposed into four lower-speed parallel signals for processing, significantly reducing the operating frequency and timing design difficulty of the back-end digital logic circuits, thereby effectively overcoming the limitations imposed by the digital system on the overall conversion rate of the digital-to-analog converter. In the signal synthesis stage, a 4:2 multiplexer unit is used to introduce return-to-zero technology, merging the four lower-speed parallel signals into two high-speed return-to-zero signals, i.e., dual-channel time-domain interleaved return-to-zero signals. This not only significantly suppresses inter-symbol interference caused by the switching transient process and incomplete current source establishment, but also pushes the transient error energy introduced during switching to the high-frequency region, thereby greatly improving the spurious-free dynamic range of the digital-to-analog converter within the Nyquist range. The dual time-domain interleaved return-to-zero signal in this invention provides ample time for the output signal to fully establish, avoiding the problems of output signal energy loss and insufficient signal establishment time that may be caused by conventional return-to-zero techniques. While effectively eliminating dynamic errors, it ensures the integrity and high linearity of the output signal.

[0041] The embodiments of the present invention have been described in detail above with reference to the accompanying drawings. However, the present invention is not limited to the above embodiments. Within the scope of knowledge possessed by those skilled in the art, various changes can be made without departing from the spirit of the present invention.

Claims

1. A dual-channel time-domain interleaved return-to-zero system for digital-to-analog converters, characterized in that: The system includes a 4:2 multiplexer (MUX), a driver circuit, and four identical decoding circuits. Four parallel signals at frequencies of f0 / 4, obtained by decomposing a continuous digital signal at a preset f0 frequency, are received one-to-one by the four decoding circuits. After buffering and decoding, each circuit outputs a corresponding decoded signal to the 4:2 multiplexer (MUX). Under the control of preset control signals, the 4:2 multiplexer (MUX) combines the received four decoded signals to obtain two time-domain interleaved return-to-zero signals, which are then output to the driver circuit. The driver circuit processes these signals to obtain corresponding drive signals, which are then output to the target controllable digital-to-analog converter (DAC). The DAC controls the output of analog differential current.

2. The dual-channel time-domain interleaved return-to-zero system for digital-to-analog converters according to claim 1, characterized in that: Based on a continuous digital signal with a preset frequency of f0, the signal is first divided into groups of four consecutive data bits. Then, the data bits in each group are sequentially grouped to obtain each group. Next, the first data bit from each group is selected to form the first parallel signal DIN_a; the second data bit from each group is selected to form the second parallel signal DIN_b; the third data bit from each group is selected to form the third parallel signal DIN_c; and the fourth data bit from each group is selected to form the fourth parallel signal DIN_d. The frequency of each parallel signal is f0 / 4.

3. The dual-channel time-domain interleaved return-to-zero system for digital-to-analog converters according to claim 1, characterized in that: The 4:2 multiplexer MUX includes NMOS transistors M1, M2, M3, and M4, inverters A1 and A2, and a main switch. Main switch ,switch ,switch ,switch ,switch Among them, the main switch One end is connected to the main switch One end is connected to an external power source, the main switch The main switch is controlled by an external differential clock signal CLKN. The main switch is controlled by an external differential clock signal CLKP. The other end, the drain of NMOS transistor M4, the drain of NMOS transistor M2, and the input of inverter A2 are connected together. The gate of NMOS transistor M4 forms the input of a 4:2 multiplexer MUX, used to input the decoded signal D_d output by the corresponding decoding circuit of the fourth parallel signal DIN_d. The source of NMOS transistor M4 is connected to a switch. Grounding, switch The external clock signal CLK4 controls the input. The gate of NMOS transistor M2 forms the input of a 4:2 multiplexer MUX, used to receive the decoded signal D_b output from the corresponding decoding circuit of the second parallel signal DIN_b. The source of NMOS transistor M2 is switched... Grounding, switch The external clock signal CLK2 is used for control. The output of inverter A2 forms one of the outputs of a 4:2 multiplexer MUX, used to output one of the time-domain interleaved return-to-zero signals S2; the main switch... The other end, the drain of NMOS transistor M3, the drain of NMOS transistor M1, and the input of inverter A1 are connected together. The gate of NMOS transistor M3 forms the input of a 4:2 multiplexer MUX, used to input the decoded signal D_c output from the corresponding decoding circuit of the third parallel signal DIN_c. The source of NMOS transistor M3 is connected to a switch. Grounding, switch The external clock signal CLK3 is used for control. The gate of NMOS transistor M1 forms the input terminal of a 4:2 multiplexer MUX, used to receive the decoded signal D_a output from the corresponding decoding circuit of the first parallel signal DIN_a. The source of NMOS transistor M1 is switched... Grounding, switch The external clock signal CLK1 is used for control, and the output of the inverter A1 forms another output of the 4:2 multiplexer MUX, which is used to output another time-domain interleaved return-to-zero signal S1.

4. The dual-channel time-domain interleaved return-to-zero system for digital-to-analog converters according to claim 3, characterized in that: The differential clock signals CLKN and CLKP have a frequency of f0 / 2 and a duty cycle of 50%; the clock signals CLK1, CLK2, CLK3, and CLK4 have a frequency of f0 / 4 and a duty cycle of 25%, and the clock signals CLK1, CLK2, CLK3, and CLK4 are sequentially phase-dependent. They do not overlap.

5. A dual-channel time-domain interleaved return-to-zero system for digital-to-analog converters according to claim 4, characterized in that: When the differential clock signal CLKN controls the connected main switch Closed, differential clock signal CLKP controls the connected main switch When disconnected, the connected switch is controlled by the clock signal CLK2. When closed, clock signal CLK4 controls the connected switch. Disconnecting the decoded signal D_b allows it to form a time-domain interleaved return-to-zero signal S2 for output, while the time-domain interleaved return-to-zero signal S1 is returned to zero; alternatively, the connected switch can be controlled by the clock signal CLK2. Disconnect, clock signal CLK4 controls the connected switch When closed, the decoded signal D_d forms the time-domain interleaved return-to-zero signal S2 for output, and the time-domain interleaved return-to-zero signal S1 is returned to zero; when the differential clock signal CLKN controls the connected main switch Disconnect, differential clock signal CLKP controls the connected main switch When closed, the connected switch is controlled by the clock signal CLK1. When closed, clock signal CLK3 controls the connected switch. Disconnection enables the decoded signal D_a to form a time-domain interleaved return-to-zero signal S1 for output, while the time-domain interleaved return-to-zero signal S2 is returned to zero; the connected switch is controlled by the clock signal CLK1. Disconnect, clock signal CLK3 controls the connected switch The signal is closed, and the decoded signal D_c is used to form a time-domain interleaved return-to-zero signal S1 for output, while the time-domain interleaved return-to-zero signal S2 is returned to zero.

6. The dual-channel time-domain interleaved return-to-zero system for digital-to-analog converters according to claim 1, characterized in that: Based on the output of the 4:2 multiplexer MUX, the time-domain interleaved return-to-zero signals S1 and S2 are processed by the drive circuit to output the return-to-zero drive signal SN1 corresponding to the time-domain interleaved return-to-zero signal S1 and its inverted return-to-zero drive signal SN1N to the target controllable digital-to-analog converter, and the return-to-zero drive signal SN2 corresponding to the time-domain interleaved return-to-zero signal S2 and its inverted return-to-zero drive signal SN2N to the target controllable digital-to-analog converter.

7. A dual-channel time-domain interleaved return-to-zero system for digital-to-analog converters according to claim 6, characterized in that: The target controllable digital-to-analog converter is a four-phase switching digital-to-analog converter, including a current source I. a ,switch ,switch ,switch ,switch Among them, current source I a One end is connected to an external power source, current source I a The other end is connected to the switch respectively One end, switch One end, switch One end, switch One end, switch The switch is controlled by an external zero-reset drive signal SN2. The switch is controlled by an external inverted return-to-zero drive signal SN2N. The switch is controlled by an external zero-reset drive signal SN1. The switch is controlled by an external inverted return-to-zero drive signal SN1N. The other end is connected to the switch The other end is connected to form the positive analog signal output port I of the four-phase switch digital-to-analog converter. OUTP Used to output positive analog signals, switches The other end is connected to the switch The other end is connected to the inverted analog signal output port I of the four-phase switch digital-to-analog converter. OUTN It is used to output an inverted analog signal.

8. A dual-channel time-domain interleaved return-to-zero system for digital-to-analog converters according to claim 7, characterized in that: When the zero-reset drive signal SN2 controls the connected switch Close, switch ,switch ,switch If the current source I is disconnected under the respective drive signals, then a The corresponding current flows in the positive direction of the analog signal output port I. OUTP When the zero-reset drive signal SN1 controls the connected switch Close, switch ,switch ,switch If the current source I is disconnected under the respective drive signals, then a The corresponding current flows in the positive direction of the analog signal output port I. OUTP ; When the inverted zero-return drive signal SN2N controls the connected switch Close, switch ,switch ,switch If the current source I is disconnected under the respective drive signals, then a The corresponding current flows to the reverse analog signal output port I. OUTN When the inverted return-to-zero drive signal SN1N controls the connected switch Close, switch ,switch ,switch If the current source I is disconnected under the respective drive signals, then a The corresponding current flows to the reverse analog signal output port I. OUTN .

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