Customized capacitive DAC with on-chip automatic calibration for high resolution successive approximation register ADC

Abstract

The invention relates to a custom capacitive DAC with on-chip automatic calibration for a high resolution successive approximation register type ADC. The ADC includes a capacitive digital-to-analog converter (DAC) including a binary weighted capacitor array, and a bridge capacitor dividing the binary weighted capacitor array into a first switched capacitor array connected to a first node and a second switched capacitor array connected to a second node, a first terminal of the bridge capacitor being connected to the first node, and a second terminal of the bridge capacitor being connected to the second node. And a second terminal of the bridge capacitor is connected to the second node. A multi-purpose capacitor is connected to the first node, the multi-purpose capacitor acting both as a termination capacitor of the first switched capacitor array and as a shield between the first node and the bridge capacitor. The dummy capacitor is connected to the second node and functions as a shield between the second node and the bridge capacitor.

Description

Custom-designed capacitor DAC with on-chip autocalibration for high-resolution successive approximation register-type ADCs. Technical Field

[0001] This disclosure relates to analog-to-digital converters (ADCs), specifically high-resolution, low-power successive approximation register (SAR) ADCs. More specifically, this disclosure relates to an improved capacitive DAC design and self-calibration technique for SAR ADCs used in medical applications involving high precision and energy efficiency. Background Technology

[0002] High-resolution applications such as medical imaging, precision instruments, and high-speed communication systems require extremely high signal-to-noise ratios (SNR) to accurately capture and process analog signals. In these applications, analog-to-digital converters (ADCs) are used to convert analog inputs into digital data while minimizing fidelity loss. It is highly desirable that the noise introduced by the ADC be minimized to a level negligible compared to the noise from the preceding analog signal chain. Capacitive successive approximation register (SAR) ADCs are widely used in these systems due to their balance of speed, accuracy, and power efficiency. However, in capacitive SAR ADCs, both noise and nonlinearity significantly reduce the effective number of bits (ENOB), which is directly related to SNDR. Therefore, strategies for reducing noise and mismatch are needed to improve ADC performance in these demanding applications.

[0003] One of the components of interest in a capacitive SAR ADC is the capacitive digital-to-analog converter (DAC). The performance of the DAC significantly affects the overall noise and linearity of the ADC. In a basic fully differential capacitive SAR ADC, the sampling phase, common-mode voltage, and input switch closure are considered. This configuration, together with the input capacitor, forms a first-order filter, which introduces thermal noise (commonly referred to as...). (Noise). This noise component should be much lower than the quantization noise to maintain a high SNR. Used to reduce... The most direct way to reduce noise is to increase the total capacitance C, but this results in a larger footprint on the chip, which may be impractical for high-resolution ADCs. Furthermore, a larger sampling capacitor requires more dissipative drivers for both the input and reference voltages, further complicating the design and increasing power consumption.

[0004] Reducing noise within the ADC can improve the signal-to-noise ratio (SNR), which is particularly important for high-fidelity signal conversion. However, to increase the effective number of bits (ENOB), both noise and distortion should be minimized, as ENOB is directly related to the signal-to-noise ratio (SNDR). ENOB can be calculated using the following formula: The signal-to-noise ratio (SNDR) is defined as follows: Where P s P represents signal power. n P represents noise power. d This represents the distortion power. Improving linearity can reduce P. d This increases ENOB.

[0005] In high-resolution capacitive SAR ADCs, achieving low... Noise levels require a large total input capacitance. Traditional designs use binary-weighted capacitive digital-to-analog converters (DACs), which are organized into multiple columns of capacitors corresponding to each bit of the ADC resolution. Each column represents a specific bit weight and contains equal to 2... x Multiple unit capacitors, where x is the bit position of the least significant bit (LSB) starting from zero.

[0006] For example, in a 16-bit capacitor DAC: the most significant bit (MSB) (i.e., bit 15) needs 2 in its column. 15 =32768 unit capacitors; the next valid bit (MSB-1, bit 14) will require 2 14 =16384 unit capacitors; and this mode continues until LSB, which requires 2 0 = 1 unit capacitor.

[0007] This exponential growth means that higher rank positions contain a large number of unit capacitors. The cumulative effect results in a large total number of capacitors, leading to significant area consumption on the integrated circuit. Such extensive area requirements make the implementation of high-resolution ADCs challenging and costly.

[0008] To address the area issue, existing solutions introduce attenuation capacitors placed between the lower and upper capacitor arrays. This technique effectively reduces the capacitance required at higher bits, decreasing the total number of unit capacitors needed to achieve the desired DAC behavior. However, to meet the stringent matching requirements for high linearity, designers often add dummy capacitors around the active capacitor arrays. These dummy capacitors mitigate edge effects and system mismatch, but this increases the overall area footprint, partially offsetting the area savings achieved through the use of attenuation capacitors.

[0009] Another challenge for high-resolution ADCs is parasitic coupling caused by interconnects. Capacitive DACs must exhibit high linearity, which depends on precise matching between the various capacitor elements. While increasing the area of ​​a unit capacitor can improve matching, careful layout design is required to minimize system errors. In existing designs, the upper plate of each capacitor is connected by both horizontal and vertical metal wires, while the lower plate is connected only via a vertical line. This configuration, due to the vertical connection, results in additional parasitic coupling between the upper and lower plates, effectively increasing the unit capacitance value. This unintended increase causes the reference and input buffers to consume more power and can introduce system errors disproportionate to the number of elements in the column. These errors manifest as integral nonlinearity (INL) and differential nonlinearity (DNL), degrading the overall performance of the ADC.

[0010] Figure 1 illustrates a known SAR ADC 10, designed to address some of the previously mentioned drawbacks in high-resolution analog-to-digital conversion. The SAR ADC 10 includes a comparator 11, a sampling switch 12, a capacitive digital-to-analog converter (DAC) 13, and SAR logic 16. The inverting input of comparator 11 is connected to the output of sampling switch 12, which samples the input voltage VIN. The non-inverting input of comparator 11 is connected to the capacitive DAC 13. The output of comparator 11 is fed into SAR logic 16, which generates a control word to operate the switch within the capacitive DAC 13.

[0011] The capacitive DAC 13 is constructed around two main nodes: a left half-node Nl and a right half-node Nr, separated by a bridge capacitor Cub. The right half-node Nr is directly connected to the non-inverting input of comparator 11. The DAC includes two sets of switched capacitor circuits: 15(1) to 15(m) connected to Nr and 14(1) to 14(k) connected to Nl. Each of these circuits contains a unit capacitor Cu or multiple unit capacitors (kCu or mCu), which can be switched between a reference voltage Vref and ground based on a control signal from SAR logic 16.

[0012] To address the parasitic coupling issue, the design employs two dummy capacitive elements: Cdr connected between node Nr and ground, and Cdl connected between node Nl and ground. As shown in Figure 3 (described below), these elements are essentially a vertically formed row of dummy capacitors in the substrate, used to isolate the terminals of the bridge capacitor Cub from the bottoms of capacitor kCu in 14(k) and capacitor Cu in 15(0). This arrangement aims to mitigate the effects of parasitic capacitances Cp4 and Cp5, which represent unintended capacitive coupling between the bridge capacitors and the switching nodes. By reducing this coupling, the design maintains better linearity during successive approximation, as switching of the capacitor on either side of the bridge capacitor Cub can cause undesirable voltage fluctuations across the capacitor.

[0013] Figure 2 provides a top-down schematic of the capacitor array layout in a capacitive DAC, illustrating the actual implementation of the design. The layout is organized in a grid structure, with each square element representing an individual unit capacitor. The central section features a bridge capacitor Cub, flanked by dummy capacitors Cdl and Cdr. On either side are larger capacitor arrays representing switched capacitor circuits 14(1) to 14(k) and 15(1) to 15(m). This symmetrical and regular arrangement is crucial for maintaining high linearity and minimizing mismatch in the DAC.

[0014] Figure 3 provides a cross-sectional view of this layout, focusing on the arrangement of capacitors 14(k), Cdl, Cub, Cdr, and 15(1). This figure illustrates the complex interconnect scheme used in this prior art design. The capacitors are constructed using a multi-layered metal stack, for example, consisting of six metal layers M1 to M6. Each capacitor element is formed by M6, M2, and M1, where a portion of M2 and M1 form a base plate, while portions of M4, M5, and M3 form a top plate. The metal used to connect all the top plates is an extension of the plates forming the capacitor itself, ensuring that interconnects for signals do not pass through a single capacitor element.

[0015] In this configuration, the upper plates of the capacitors are connected by both horizontal and vertical metal lines, which are extensions of the top plate itself, while the lower plates are connected by vertical lines in the sixth metal layer M6. This arrangement generates a small parasitic capacitance between these metal layers, slightly increasing the unit capacitance value beyond the intended design. The most significant bit (MSB) capacitors of the lower array 14(k) of the switched capacitor circuits 14(1), ..., 14(k) and the least significant bit (LSB) capacitors 15(1) of the upper array of the switched capacitor circuits 15(1), ..., 15(m) are shown on both sides of the central bridge capacitor Cub and the dummy capacitors Cdl and Cdr, illustrating the symmetry of the layout.

[0016] While this configuration effectively solves the parasitic coupling problem, it comes at the cost of increased die area due to the addition of a dummy capacitor column. Furthermore, as mentioned above, the interconnect scheme shown in Figure 3 introduces its own set of parasitic capacitances Cp4 and Cp5.

[0017] Due to these large effective capacitances, the reference voltage source and input buffer must be designed to drive large equivalent capacitive loads. This necessity leads to increased current consumption to meet the settling time specifications required for high-resolution operation. Therefore, while this prior art design successfully addresses some issues, it still faces limitations in terms of area efficiency and power consumption, primarily due to its complex interconnect scheme and extensive use of dummy capacitors.

[0018] Therefore, an improved capacitive SAR ADC design is needed in the field of high-resolution analog-to-digital conversion. Such a design should simultaneously address several challenges: minimizing noise and nonlinearity, reducing die footprint, and mitigating parasitic coupling. These improvements will collectively enhance ADC performance in high-resolution applications such as medical imaging, precision instruments, and high-speed communication systems, where signal integrity and conversion accuracy are critical. This solution aims to maintain or improve the speed, accuracy, and power efficiency that make SAR ADCs attractive, while overcoming the limitations of current designs in terms of area efficiency and parasitic effects. Therefore, further development is required. Summary of the Invention

[0019] A successive approximation register (SAR) analog-to-digital converter (ADC) includes a capacitive digital-to-analog converter (DAC) with a binary weighted capacitor array. A bridge capacitor divides the binary weighted capacitor array into a first switched capacitor array connected to a first node and a second switched capacitor array connected to a second node. The bridge capacitor has a first terminal connected to the first node and a second terminal connected to the second node. A multipurpose capacitor is connected to the first node to serve both as a terminating capacitor for the first switched capacitor array and as a shield between the first node and the bridge capacitor. A dummy capacitor is connected to the second node to serve as a shield between the second node and the bridge capacitor.

[0020] Capacitive DACs can have metal layers. Multipurpose capacitors and bridge capacitors can be formed from plates in a second, third, fourth, fifth, and sixth metal layer. The plates of the multipurpose capacitors and bridge capacitors in the fifth and third metal layers can be connected to each other.

[0021] The upper plates of the bridge capacitor and the dummy capacitor can be connected via horizontal plates in the sixth metal layer. The dummy capacitor may include horizontal plates in the fifth metal layer that are vertically connected to the horizontal plates of the dummy capacitor in the sixth metal layer.

[0022] The dummy capacitor can be connected to the first capacitor in the second switched capacitor array. The horizontal plate in the fifth metal layer of the dummy capacitor can be connected to the corresponding horizontal plate in the fifth metal layer of the first capacitor.

[0023] A capacitive DAC can have a layout with a bridge capacitor in the center, a multipurpose capacitor positioned on the first side adjacent to the bridge capacitor, a dummy capacitor positioned on the second side adjacent to the bridge capacitor, and a first switching capacitor array and a second switching capacitor array positioned on either side of the bridge capacitor in the center.

[0024] The layout may include tunnels created within columns containing dummy capacitors, and vertical metal lines passing through the tunnels to connect the upper plates of the capacitors across different columns of the binary weighted capacitor array.

[0025] Vertical metal lines can be formed in the fifth metal layer, and tunnels can provide isolation between the vertical metal lines and the capacitor plates.

[0026] Each of the first and second switched capacitor arrays may have multiple columns of capacitor elements. Each column of capacitor elements may be formed by multiple unit capacitors. Columns representing higher significant bits may have a larger number of unit capacitors compared to columns representing lower significant bits.

[0027] A capacitive DAC can have multiple metal layers. A multi-purpose capacitor and a bridge capacitor can be formed from conductive structures in at least three metal layers. At least two of the conductive structures in the multi-purpose capacitor and bridge capacitor, which are not in adjacent metal layers, can be electrically connected to each other.

[0028] The upper conductive structure of a bridge capacitor and a dummy capacitor can be electrically connected in the uppermost metal layer. A dummy capacitor may include a conductive structure in a metal layer located below the uppermost metal layer, which is electrically connected to the upper conductive structure via a vertical conductive element.

[0029] The dummy capacitor can be electrically connected to the first capacitor in the second switched capacitor array. The conductive structure of the dummy capacitor in the metal layer below the topmost metal layer can be electrically connected to the corresponding conductive structure of the first capacitor in the same metal layer.

[0030] The SAR ADC may include a first calibration DAC connected to a first node, a second calibration DAC connected to a second node, and automatic calibration logic for controlling the injection of error correction signals into the first and second calibration DACs during analog-to-digital conversion.

[0031] The automatic calibration logic can evaluate capacitance errors for multiple most important capacitors in a binary weighted capacitor array and generate calibration coefficients based on the evaluated capacitance errors.

[0032] To assess capacitance error, one can test each of the most important capacitors in sequence, take N readings for each capacitor under test (where N is a positive integer), and calculate the error value for each capacitor under test based on the N readings.

[0033] A SAR ADC may include registers for storing the generated calibration coefficients. Automatic calibration logic can apply the stored calibration coefficients as static correction during subsequent analog-to-digital conversion.

[0034] The SAR ADC may include ADC phase control circuitry that enables automatic calibration logic to perform calibration when the SAR ADC switches from an idle state to an operational state, and manages the calibration phase sequence for evaluating errors in the most important capacitors in the binary weighted capacitor array.

[0035] The most important capacitors include nine of the most important capacitors in the binary weighted capacitor array. Attached Figure Description

[0036] Figure 1 shows a prior art SAR ADC design, illustrating a basic structure with a separate dummy capacitor column for shielding;

[0037] Figure 2 provides a top-down schematic of the capacitor array layout in the prior art capacitive DAC of Figure 1, showing the arrangement of active and dummy capacitors.

[0038] Figure 3 depicts a cross-sectional view of the prior art capacitor layout of Figure 1, highlighting the metal layer arrangement and parasitic capacitance.

[0039] Figure 4 shows the improved SAR ADC design disclosed in this paper, which uses capacitors as both terminating capacitors and shielding components, eliminating the need for a separate dummy column.

[0040] Figure 5 shows the metal layer arrangement of the improved design in Figure 4, illustrating how the interconnect scheme reduces parasitic capacitance;

[0041] Figure 6 provides a top view of the capacitor layout in the design of Figure 4, showing the modified dummy column that creates tunnels for the vertical line M5, thereby improving linearity;

[0042] Figure 7 shows a block diagram of a complete ADC system, which includes the ADC disclosed herein and the digital blocks required to implement the self-calibration techniques disclosed herein.

[0043] Figure 8 is a schematic diagram of an ADC including calibration functionality, showing the main DAC and the calibration DAC;

[0044] Figure 9 is a timing diagram showing the calibration workflow managed by the ADC phase control block, which illustrates the sequence of calibration phases;

[0045] Figure 10 shows the drive signals used for both the positive and negative arrays during the calibration phase used to evaluate the error of the C16 capacitor.

[0046] Figure 11 shows the drive signals used for the positive and negative arrays during the calibration phase used to evaluate the error of the C15 capacitor;

[0047] Figure 12 shows the drive signals used for the positive and negative arrays during the calibration phase used to evaluate the error of the C14 capacitor;

[0048] Figure 13 shows the drive signals used for the positive and negative arrays during the calibration phase used to evaluate the error of the C9 capacitor; and

[0049] Figure 14 shows the drive signals used for the positive and negative arrays during the calibration phase used to evaluate the error of the C8 capacitor. Detailed Implementation

[0050] The following disclosure enables those skilled in the art to make and use the subject matter described herein. The general principles outlined in this disclosure can be applied to embodiments and applications other than those described in detail above without departing from the spirit and scope of this disclosure. It is not intended to limit this disclosure to the embodiments shown, but rather to impose upon it the widest scope consistent with the principles and features disclosed or suggested herein.

[0051] Note that in the following description, unless otherwise stated, any resistor or resistor mentioned is a discrete device, not merely an electrical wire between two points. Therefore, any resistor or resistor connected between two points has a higher resistance than a lead between those two points, and such a resistor or resistor cannot be interpreted as a lead. Similarly, unless otherwise stated, any capacitor or capacitor mentioned is a discrete device and is not a parasitic element. Furthermore, unless otherwise stated, any inductor or inductor mentioned is a discrete device and is not a parasitic element.

[0052] The SAR ADC 10' is now described with reference to Figure 4, which addresses the aforementioned drawbacks of the designs in Figures 2-3. The SAR ADC 10' comprises a fully differential architecture with two identical capacitive DACs, each connected to one input of the differential comparator 11. The SAR ADC 10' also includes SAR logic 16, similar to the prior art designs described above. However, the capacitive DACs 13' and 33' in the SAR ADC 10' are modified to improve performance and reduce area consumption.

[0053] Each capacitive DAC (13' and 33') includes a left half-node (Nl+ and Nl-, respectively) and a right half-node (Nr+ and Nr-, respectively), which are separate from each other and electrically coupled through a bridge capacitor Cub. The right half-nodes Nr+ and Nr- are connected to the non-inverting input and the inverting input of comparator 11, respectively.

[0054] DAC 13' includes two sets of switched capacitor circuits: 15(1) to 15(m) connected to node Nr+ and 14(1) to 14(k) connected to node Nl+. Similarly, the capacitive DAC 33' includes two sets of switched capacitor circuits: 35(1) to 35(m) connected to node Nr- and 34(1) to 34(k) connected to node Nl-.

[0055] Each of these circuits contains one unit capacitor Cu or multiple unit capacitors (kCu or mCu), which can be switched between a reference voltage Vref and ground based on a control signal from SAR logic 16. More specifically, the multiple can be a multiple of 2; for example, if k=5, a capacitor of 14(1) or 34(1) will have a capacitance of Cu, a capacitor of 14(2) or 34(2) will have a capacitance of 2Cu, a capacitor of 14(3) or 34(3) will have a capacitance of 4Cu, a capacitor of 14(4) or 34(4) will have a capacitance of 8Cu, and a capacitor of 14 (k=5) or 34 (k=5) will have a capacitance of 16Cu. Similarly, for m=5, a capacitor of 15(1) or 35(1) will have a capacitance of Cu, a capacitor of 15(2) or 35(2) will have a capacitance of 2Cu, a capacitor of 15(3) or 35(3) will have a capacitance of 4Cu, a capacitor of 15(4) or 35(4) will have a capacitance of 8Cu, and a capacitor of 15(m=5) or 35(m=5) will have a capacitance of 16Cu.

[0056] In this design, it is noteworthy that capacitor Cu2 is used at the left half node Nl+ of capacitive DAC 13' and at the left half node Nl- of capacitive DAC 33'. Unlike Figure 1, where such capacitors are absent, these capacitors Cu2 in Figure 4 have several important functions—they can be considered multi-purpose capacitors. First, they form part of the binary weighted capacitor arrays 14(1), ..., 14(k) and 34(1), ..., 34(k). Furthermore, these capacitors Cu2 serve as grounding termination capacitors, and they act as shielding between nodes Nl+, Nl-, and the bridge capacitor Cub.

[0057] This versatile approach to capacitor Cu2 allows for the elimination of a separate dummy capacitor column (Cdl in Figure 1) while still maintaining the necessary shielding effect. In the prior art design of Figure 1, the dummy capacitor column Cdl is used solely as a shielding element, occupying valuable chip area. By reusing capacitor Cu2 (an existing and necessary component of the binary weighted DAC structure) as a shield, the new design improves area efficiency without compromising functionality.

[0058] At the right-hand nodes Nr+ and Nr-, each DAC retains a single dummy capacitor Cdum, similar to the prior art design showing capacitor Cdr. These dummy capacitors ensure proper shielding to the right of the bridge capacitor Cub and maintain the symmetry of the overall DAC structure.

[0059] Compared to the prior art design in Figure 1, this configuration effectively solves the parasitic coupling problem while significantly reducing the overall area of ​​the DAC. By eliminating the need for separate dummy columns on both sides of the bridge capacitor (as shown by dummy capacitor columns Cdl and Cdr in Figures 1-3), this design achieves considerable area savings, especially in fully differential ADCs with separate DACs for inverting and non-inverting signal paths.

[0060] Figure 5 illustrates the improved metal layer arrangement. Cu2 is reused from the binary weighted capacitor array and also used as a shield. The highest effective potential capacitor 14 (k) is not explicitly shown in the figure. The interconnect scheme has been optimized to reduce parasitic capacitance. The lower plates of the capacitors are primarily connected via vertical metal lines in the sixth metal layer M6, while the upper plates are connected via horizontal lines in metal layers M3 and M5. This arrangement minimizes overlap between different metal layers, thereby reducing unwanted parasitic capacitance.

[0061] This method achieves the same shielding effect as the previous design, while parasitic capacitances Cp4 and Cp5 remain referenced to a fixed potential. Therefore, switching the capacitors to the right and left sides of the bridge capacitor does not cause unwanted voltage fluctuations on the floating electrodes. The result is a more area-efficient design that maintains the linearity and performance advantages of the previous method.

[0062] This design achieves considerable area savings by eliminating the need for multiple dummy columns (four in the case of a fully differential ADC, with separate DACs for main conversion and mismatch calibration). The dual use of capacitor Cu2 as a shield reduces the number of capacitors without compromising the functionality of the DAC 13' and 33' or the binary weighted structure. The retention of capacitor Cdum on the right side provides balanced operation while minimizing additional area requirements.

[0063] This reduction in area not only improves the overall efficiency of the ADC 10', but also reduces manufacturing costs and power consumption, making it particularly suitable for high-resolution applications where space and power consumption are both critical.

[0064] Figure 6 provides a top view of the 3D structure shown in Figure 5 as a cross-sectional top view of the capacitor layout of DAC 13' and 33', illustrating the compact arrangement of the capacitor elements of DAC 13' and 33'; in other words, Figure 5 shows a cross-sectional view of Figure 6 taken along line AA. The bridge capacitor Cub is shown in the center, with the terminating capacitor Cu2 on the left and the dummy capacitor Cdum on the right. An array of active switched capacitors is positioned on either side of this central structure.

[0065] This design solves the problem of parasitic paths, as described below. The horizontal lines M5 and M3 form the upper plates of the capacitor and are short-circuited to each other, connecting the upper part of each unit element. These are not paired with the vertical lines M6 and M4, which form the lower plates of the capacitor (also short-circuited) and connect the lower parts of the elements in the same column. By eliminating the vertical M5 / M3 lines extending along M6, this arrangement significantly reduces parasitic coupling compared to the prior art designs described in the background art.

[0066] Reducing parasitic coupling offers several advantages. It allows for lower power consumption in the driver and reduces mismatches between various parasitic elements. By reducing the absolute value of these parasitic elements, their impact on mismatches caused by technology changes is proportionally reduced, even at the same level of process mismatch.

[0067] The single vertical line of M5 is used to connect the tops of elements across different columns.

[0068] As shown in Figure 6, a tunnel is created within the dummy column for the vertical line M5 to pass through. This helps ensure that the M5 line is no longer adjacent to the bottom of the capacitor column associated with capacitor mCu.

[0069] In DACs 13' and 33', the column associated with capacitor mCu is formed by eight elements, for example, each element is 40fF, and the total expected capacitance is, for example, 320fF. Therefore, the capacitance value of all MSB columns is consistent, improving the linearity of the DAC.

[0070] Figure 7 shows a block diagram of an ADC system designed for medical applications requiring low-power, high-resolution analog-to-digital conversion. The ADC system is divided into two main blocks: ADC 10 and digital block 20.

[0071] ADC 10 represents the aforementioned analog-to-digital converter. It contains SAR logic 16, which implements the successive approximation register algorithm for the operation of ADC 10. SAR logic 16 controls the conversion process and interacts with other parts of the system. ADC 10 outputs two signals: ADC_D<16:1>, which is a 16-bit digital output representing the converted analog input; and ADC_EOC, which indicates the end of the conversion when ADC 10 completes a conversion cycle.

[0072] Digital block 20 includes digital control and processing elements for ADC operation and calibration. Within digital block 20, ADC phase control 21 manages the overall operation of the ADC. It generates several control signals: ADC_EN, for enabling or disabling ADC 10; ADC_START, for initiating a conversion cycle; and ADC_TEST_CAPS, for testing the capacitors in ADC 10' as part of the calibration process. ADC phase control 21 also generates ADC_CAL_On to enable automatic calibration logic 18. Digital block 20 also includes registers 22 for storing calibration coefficients and other data used for ADC operation. These registers 22 are updated during the self-calibration process described below to correct for nonlinear errors in ADC 10.

[0073] Digital block 20 receives the ADC_D<16:1> and ADC_EOC signals from ADC 10' to process and coordinate the operation of ADC 10'. Digital block 20 outputs the DAC_ERR_Cx signal, which represents the calibration coefficients sent to ADC 10 to correct for nonlinear errors in the capacitive DACs 13 and 33''. To achieve the high level of linearity required for efficient ENOB (such as 14 bits), an automatic calibration technique described below has been implemented. This technique compensates for both DAC and comparator nonlinearities, enabling the ADC to achieve ENOB up to 14 bits.

[0074] The automatic calibration process evaluates calibration coefficients, which are then stored in register 22. This calibration is performed automatically each time the device switches from idle to operational mode. By doing so, the system can correct for aging effects and slow temperature changes without manual intervention or increased test time. This approach not only maintains the high performance of the ADC over time but also reduces operating costs by eliminating the need for frequent manual calibrations.

[0075] By incorporating this self-calibration mechanism, the ADC 10 achieves the signal-to-noise ratio (SNDR) required for high-resolution performance, overcoming the limitations of relying solely on precise capacitive DAC layouts. This design approach is particularly suitable for medical applications requiring low power consumption and high-resolution analog-to-digital conversion. The ability to automatically compensate for various factors that can degrade performance over time makes this ADC system especially valuable in medical devices that require consistent, high-precision measurements.

[0076] An example implementation of the ADC 10'', including calibration functionality, is now described with reference to Figure 8. The ADC 10'' includes a fully differential architecture with four capacitive DACs: main DACs 13'' and 33'', and two calibration DACs 43 and 53.

[0077] The first main DAC 13'' comprises a left half-node Nl+ and a right half-node Nr+, which are separated from each other and electrically coupled via a bridge capacitor Cu. The right half-node Nr+ is connected to the non-inverting input of the comparator. A first set of switched capacitor circuits 14(1) to 14(7) are connected to Nl+, and a second set of switched capacitor circuits 15(8) to 15(16) are connected to Nr+. Each of these circuits contains a binary weighted capacitor array, with the capacitance range of 14(1) to 14(7) from Cu to 64Cu, and the capacitance range of 15(8) to 15(16) from Cu to 128Cu. Each capacitor in the switched capacitor circuits 14(1) to 14(7) can be switched between being connected to a common-mode voltage Vcm, a reference voltage Vref, and ground. Each capacitor in the switched capacitor circuits 15(1) to 15(7) can be switched between being connected to a common-mode voltage Vcm, a reference voltage Vref, ground, and an input voltage Vin.

[0078] The second main DAC 33'' comprises a left half-node Nl- and a right half-node Nr-, which are separated from each other and electrically coupled by a bridge capacitor Cu. The right half-node Nr is connected to the inverting input of the comparator. A first set of switched capacitor circuits 34(1) to 34(7) are connected to Nl-, and a second set of switched capacitor circuits 35(8) to 35(16) are connected to Nr-. Each of these circuits contains a binary weighted capacitor array, with the capacitance range of 34(1) to 34(7) from Cu to 64Cu and the capacitance range of 35(8) to 35(16) from Cu to 128Cu. Each capacitor in the switched capacitor circuits 34(1) to 34(7) can be switched between being connected to a common-mode voltage Vcm, a reference voltage Vref, and ground. Each capacitor in the switched capacitor circuits 35(1) to 35(7) can be switched between being connected to a common-mode voltage Vcm, a reference voltage Vref, ground, and an input voltage Vin.

[0079] The first calibration DAC 43 is connected to node Nc+ and includes a series of switched capacitor circuits 16(1) to 16(7) with capacitance ranging from Cu / 2 to 16Cu. A terminating capacitor with a capacitance of 32Cu is connected between node Nc+ and ground. An additional capacitor Cu / 4 is connected between node Nc+ and node Nr+. Each capacitor in capacitor circuits 16(1) to 16(7) can be switched between a reference voltage Vref and ground.

[0080] The second calibration DAC 53 is connected to node Nc- and includes a series of switched capacitor circuits 36(1) to 36(7) with capacitance ranging from Cu / 2 to 16Cu. A terminating capacitor with a capacitance of 32Cu is connected between node Nc- and ground. An additional capacitor Cu / 4 is connected between node Nc- and node Nr-. Each capacitor in capacitor circuits 36(1) to 36(7) can be switched between a reference voltage Vref and ground.

[0081] ADC 10'' also includes comparator 11, which receives inputs from the right half nodes Nr+ and Nr- of main DACs 13'' and 33''. The output of comparator 11 is fed into SAR logic 17, which generates control signals for the switched capacitor circuitry in main DACs 13'' and 33''. Automatic calibration logic block 18 also receives the output of comparator 11 and generates control signals for the switched capacitor circuitry in calibration DACs 43 and 53.

[0082] The calibration workflow will now be described, but first note that the following symbols will be used.

[0083] In the main DAC 13'', the capacitor in 14(1) will be called capacitor C1p (with capacitance Cu), the capacitor in 14(2) will be called capacitor C2p (with capacitance 2Cu), the capacitor in 14(3) will be called capacitor C3p (with capacitance 4Cu), the capacitor in 14(4) will be called capacitor C4p (with capacitance 8Cu), the capacitor in 14(5) will be called capacitor C5p (with capacitance 16Cu), the capacitor in 14(6) will be called capacitor C6p (with capacitance 32Cu), the capacitor in 14(7) will be called capacitor C7p (with capacitance 64Cu), the capacitor in 15(8) will be called capacitor C8p (with capacitance Cu), and in 15(9) The capacitor in 15(10) will be called capacitor C9p (with capacitance Cu), the capacitor in 15(11) will be called capacitor C10p (with capacitance 2Cu), the capacitor in 15(12) will be called capacitor C11p (with capacitance 4Cu), the capacitor in 15(12) will be called capacitor C12p (with capacitance 8Cu), the capacitor in 15(13) will be called capacitor C13p (with capacitance 16Cu), the capacitor in 15(14) will be called capacitor C14p (with capacitance 32Cu), the capacitor in 15(15) will be called capacitor C15p (with capacitance 64Cu), and the capacitor in 15(16) will be called capacitor C16p (with capacitance 128Cu).

[0084] In the main DAC 33'', the capacitor in 34(1) will be called capacitor C1n (with capacitance Cu), the capacitor in 34(2) will be called capacitor C2n (with capacitance 2Cu), the capacitor in 34(3) will be called capacitor C3n (with capacitance 4Cu), the capacitor in 34(4) will be called capacitor C4n (with capacitance 8Cu), the capacitor in 34(5) will be called capacitor C5n (with capacitance 16Cu), the capacitor in 34(6) will be called capacitor C6n (with capacitance 32Cu), the capacitor in 34(7) will be called capacitor C7n (with capacitance 64Cu), the capacitor in 35(8) will be called capacitor C8n (with capacitance Cu), and in 35(9) The capacitor in 35(10) will be called capacitor C9n (with capacitance Cu), the capacitor in 35(11) will be called capacitor C11n (with capacitance 4 Cu), the capacitor in 35(12) will be called capacitor C12n (with capacitance 8 Cu), the capacitor in 35(13) will be called capacitor C13n (with capacitance 16 Cu), the capacitor in 35(14) will be called capacitor C14n (with capacitance 32 Cu), the capacitor in 35(15) will be called capacitor C15n (with capacitance 64 Cu), and the capacitor in 35(16) will be called capacitor C16n (with capacitance 128 Cu).

[0085] The calibration workflow is managed by ADC phase control block 21 (see Figure 7), which enables SAR logic 17 and automatic calibration logic 18 at specific phases, as shown in the timing diagram of Figure 9. The calibration process focuses on evaluating and correcting errors in the most critical capacitors, namely C16p to C8p in the positive array (DAC 13'') and C16n to C8n in the negative array (DAC 33''), as these capacitors have the greatest impact on nonlinearity errors.

[0086] After calibration is enabled, error evaluation will be performed through a series of phases: ADC_TEST_CAP <16> ADC_TEST_CAP <15> ADC_TEST_CAP <14> ADC_TEST_CAP <13> ADC_TEST_CAP <12> ADC_TEST_CAP <11> ADC_TEST_CAP <10> ADC_TEST_CAP <9> and ADC_TEST_CAP <8> During each of these phases, N readings (e.g., N=8) of the corresponding capacitance being evaluated are acquired.

[0087] During these calibration phases, the voltage behavior across the capacitors in both the positive and negative arrays is shown in Figures 10 to 14. These figures illustrate the trends of the voltages V_C1_p to V_C16_p across capacitors C1p to C16p in the positive array, and the trends of the voltages V_C1_n to V_C16_n across capacitors C1n to C16n in the negative array.

[0088] Figure 10 shows the evaluation of the error of capacitor C16. It shows the calibration phase ADC_TEST_CAP <16> The driving signals for both the positive array (left) and the negative array (right) during the period. Similarly, Figure 11 shows the evaluation of the C15 capacitor error, which illustrates the calibration phase ADC_TEST_CAP. <15> The driving signals for the positive array (left) and negative array (right) during the period are shown. Additionally, Figure 12 illustrates the evaluation of the C14 capacitor error, which shows the calibration phase ADC_TEST_CAP. <14> The driving signals for the positive array (left) and negative array (right) during the period are shown. Additionally, Figure 13 illustrates the evaluation of the C9 capacitor error, which shows the calibration phase ADC_TEST_CAP. <9> The driving signals for the positive array (left) and negative array (right) during the period are shown. Additionally, Figure 14 illustrates the evaluation of the C8 capacitor error, showing the calibration phase ADC_TEST_CAP. <8> The driving signals for the positive array (left) and negative array (right) during the period.

[0089] Based on the waveforms shown in Figures 10-14, the capacitor is driven, and the following equation for error evaluation is presented: in:

[0090] A concrete example will now be provided. Suppose we want to calibrate the following error:

[0091] Then, the calibration value DCAL obtained from the calibration becomes:

[0092] Based on these DCAL values, the capacitance error can be calculated as follows:

[0093] Inserting the previously calculated DCAL value for each capacitor, we get:

[0094] The calibration results are consistent with the expected unknowns. These results indicate that the calibration process successfully estimated the error of the DAC capacitors. Equations for DACerr_C8 to DACerr_C16 show how the error of each capacitor is determined according to... Quantize with ΔC.

[0095] In the implementation, these quantities are quantized by the ADC without loss of correction accuracy, using 7 bits for each capacitor. The ADC phase control circuit 21 provides the ADC_TEST_CAPS signal, which enables estimation of MSB, MSB-1, and up to MSB-8 errors. The total number of bits required for DACerr_C8 to DACerr_C16 is 63 bits, calculated by multiplying 7 bits by 9 capacitors. These 63 bits, calculated according to the equations explained above, are stored in register 22 at the end of the calibration process. During operational use, these stored bits are provided to ADC 10 for static correction.

[0096] The successive approximation process begins with the most significant bit (MSB) and proceeds through several steps. In the first approximation, capacitor C16p in the switched capacitor circuit 15 (16) of DAC 13'', which is associated with the MSB and controlled by ADC_D<16:1>, and capacitor C16n in the switched capacitor circuit 35 (16) of DAC 33'', which corresponds to the full scale of ADC 10'', are connected to VREF. Simultaneously, the calibration of DACs 43 and 53 is injected with a correction equal to DACerr_C16. This, together with the rest of the matrix, forms a capacitive 1:1 voltage divider, resulting in a voltage at the input of comparator 11 equal to -Vin + VREF / 2. Comparator 11 then returns a value of 1 or 0 depending on whether Vin is greater than or less than VREF / 2, and ADC_D<16:1> is set to that binary value.

[0097] In the second approximation, capacitor C15p in the switched capacitor circuit 15 (15) of DAC 13'', which is associated with MSB-1 and controlled by ADC_D<15:1>, and capacitor C15n in the switched capacitor circuit 35 (15) of DAC 33'', are connected to VREF / 2. The calibration of DAC 43 and 53 injections is equal to the correction of DACerr_C15, which depends on the result of ADC_D<16:1>, i.e., the result of the previous approximation.

[0098] This pattern continues in the following approximations. At each step, the corresponding capacitor is connected to a progressively decreasing fraction of VREF: VREF / 4 for the third approximation, VREF / 8 for the fourth, and so on. Calibration of the DAC 43 and 53 injections depends on corrections to all previous approximation results (DACerr_C14, DACerr_C13, etc.).

[0099] Through the eighth approximation, capacitor C9p in the switched capacitor circuit 15(9) of DAC 13'', associated with MSB-7 and controlled by ADC_D<9:1>, and capacitor C9n in the switched capacitor circuit 35(9) of DAC 33'', are connected to VREF / 128. Calibration of DAC 43 and 53 is injected equal to the correction of DACerr_C9, depending on the results of ADC_D<16:1> to ADC_D<10:1>. For the remaining approximations, from the ninth to the sixteenth, capacitors C8p to C1p in the switched capacitor circuits 15(8) to 14(1) of DAC 13'', associated with MSB-8 to LSB, and capacitors C8n to C1n in the switched capacitor circuits 35(8) to 34(1) of DAC 33'', are controlled by ADC_D<8:1> to ADC_D<1:1>. These voltage ranges range from VREF / 256 of the ninth approximation to VREF / 32768 of the sixteenth approximation. Meanwhile, calibration DACs 43 and 53 continue to work in conjunction with main DACs 13'' and 33'' to apply appropriate corrections in these final approximation steps.

[0100] Note that while these capacitors (C8p to C1p and C8n to C1n) participate in the conversion process, they are not individually calibrated. Instead, in these final steps, calibrating DACs 43 and 53 injects a common correction equal to DACerr_C8 for all these lower significant bits. This correction depends on the result of ADC_D<16:1> to ADC_D<9:1>, i.e., the result of the decision for the eight most significant bits.

[0101] In this 10'' ADC design, individual linear corrections are applied only to the eight most critical capacitors (C16p to C9p and C16n to C9n), while a common correction factor is used for the remaining less critical capacitors. This balances accuracy and efficiency during calibration, as it has been found to be sufficient to achieve the desired performance, while simplifying the calibration process and reducing the amount of calibration data that needs to be stored.

[0102] This method ensures that the most influential errors (errors in the most significant bits) are accurately corrected, while still providing some degree of correction for the less significant bits. The result is an optimized balance between conversion accuracy and calibration complexity.

[0103] Finally, it is obvious that modifications and changes may be made to the content described and shown herein without departing from the scope of this disclosure.

[0104] While this disclosure has been described with a limited number of embodiments, those skilled in the art who benefit from it will envision other embodiments without departing from the scope of the disclosure. Furthermore, those skilled in the art will envision various combinations of embodiments that can represent the embodiments disclosed herein in various ways.

Claims

1. A successive approximation register-type SAR analog-to-digital converter (ADC), comprising: Capacitive digital-to-analog converter (DAC), including a binary weighted capacitor array; A bridge capacitor divides the binary weighted capacitor array into a first switched capacitor array connected to a first node and a second switched capacitor array connected to a second node. The first terminal of the bridge capacitor is connected to the first node, and the second terminal of the bridge capacitor is connected to the second node. And a multipurpose capacitor connected to the first node, wherein the multipurpose capacitor serves as a terminating capacitor of the first switched capacitor array and as a shield between the first node and the bridge capacitor; And a dummy capacitor, connected to the second node, and used as a shield between the second node and the bridge capacitor.

2. The SAR ADC of claim 1, wherein the capacitive DAC includes a metal layer, and wherein: The multipurpose capacitor is formed by plates in the second, third, fourth, fifth and sixth metal layers of the metal layers; The bridge capacitor is formed by plates in the second metal layer, the third metal layer, the fourth metal layer, the fifth metal layer, and the sixth metal layer of the metal layers; Furthermore, the plates of the multipurpose capacitor and the bridge capacitor in the fifth metal layer and the third metal layer are connected to each other.

3. The SAR ADC according to claim 2, wherein: The upper plates of the bridge capacitor and the dummy capacitor are connected by a horizontal plate in the sixth metal layer; and the dummy capacitor includes a horizontal plate in the fifth metal layer that is vertically connected to the horizontal plate of the dummy capacitor in the sixth metal layer.

4. The SAR ADC according to claim 3, wherein: The dummy capacitor is connected to the first capacitor of the second switched capacitor array; Furthermore, the horizontal plate in the fifth metal layer of the dummy capacitor is connected to the corresponding horizontal plate in the fifth metal layer of the first capacitor.

5. The SAR ADC of claim 1, wherein the capacitive DAC includes a centrally located bridge capacitor, the multipurpose capacitor is positioned adjacent to a first side of the bridge capacitor, the dummy capacitor is positioned adjacent to a second side of the bridge capacitor, and the first switched capacitor array and the second switched capacitor array are positioned on either side of the centrally located bridge capacitor.

6. The SAR ADC of claim 5, wherein the layout further comprises: The tunnel is created within the column containing the dummy capacitor; And vertical metal wires pass through the tunnel to connect the upper plates of the capacitors across different columns of the binary weighted capacitor array.

7. The SAR ADC according to claim 6, wherein: The vertical metal wire is formed in the fifth metal layer; and the tunnel provides isolation between the vertical metal wire and the capacitor plates.

8. The SAR ADC according to claim 5, wherein: Each of the first switched capacitor array and the second switched capacitor array includes multiple rows of capacitor elements; Each column of capacitor elements is formed by multiple unit capacitors; Furthermore, compared to columns representing lower significant bits, columns representing higher significant bits include a larger number of unit capacitors.

9. The SAR ADC of claim 1, wherein the capacitive DAC comprises a plurality of metal layers, and wherein: The multipurpose capacitor is formed by conductive structures in at least three of the metal layers; the bridge capacitor is formed by conductive structures in at least three of the metal layers; and at least two of the conductive structures of the multipurpose capacitor and the bridge capacitor in non-adjacent metal layers are electrically connected to each other.

10. The SAR ADC according to claim 9, wherein: The upper conductive structure of the bridge capacitor and the dummy capacitor is electrically connected in the uppermost metal layer of the plurality of metal layers; and the dummy capacitor includes a conductive structure in a metal layer below the uppermost metal layer, the conductive structure being electrically connected to the upper conductive structure via a vertical conductive element.

11. The SAR ADC of claim 10, wherein: The dummy capacitor is electrically connected to the first capacitor of the second switched capacitor array; Furthermore, the conductive structure of the dummy capacitor in the metal layer below the uppermost metal layer is electrically connected to the corresponding conductive structure of the first capacitor in the same metal layer.

12. The SAR ADC according to claim 1, further comprising: The first calibration DAC is connected to the first node; The second calibration DAC is connected to the second node; And automatic calibration logic, configured to control the first calibration DAC and the second calibration DAC to inject error correction signals during analog-to-digital conversion.

13. The SAR ADC of claim 12, wherein the automatic calibration logic is configured to: evaluate capacitance error for a plurality of the most important capacitors in the binary weighted capacitor array; and generate calibration coefficients based on the evaluated capacitance error.

14. The SAR ADC of claim 13, wherein evaluating the capacitance error comprises: Test each of the plurality of most important capacitors in turn; For each capacitor being tested, N readings are taken, where N is a positive integer; And based on the N readings, an error value is calculated for each capacitor being tested.

15. The SAR ADC of claim 14, further comprising: A register is configured to store the generated calibration coefficients; and the automatic calibration logic is further configured to apply the stored calibration coefficients as static correction during subsequent analog-to-digital conversion.

16. The SAR ADC of claim 12, further comprising ADC phase control circuitry configured to: enable the automatic calibration logic to perform calibration when the SAR ADC switches from an idle state to an operational state; and manage a sequence of calibration phases for evaluating errors in the most important capacitors in the binary weighted capacitor array.

17. The SAR ADC of claim 13, wherein the plurality of most important capacitors comprises the nine most important capacitors in the binary weighted capacitor array.

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