Clock data multiplexing optical fiber transmission system

Abstract

The invention discloses a clock data multiplexing optical fiber transmission system, which comprises a transmitting end unit, a receiving end unit and an optical fiber link, and is characterized in that the transmitting end unit generates a first working clock required by parallel-serial conversion of a digital signal to be transmitted into a high-speed serial signal through a system synchronization clock; the high-speed serial signal is converted to an optical domain and then is output to an optical fiber link; and the receiving end unit is used for converting an optical signal received from the optical fiber link into an electric signal, recovering a digital signal to be transmitted through serial-to-parallel conversion, and extracting a first working clock and obtaining a system synchronous clock at the same time. In the invention, the system synchronous clock is used as the working clock for converting the digital signal to be transmitted into the high-speed serial signal, so that the architecture of the optical transmission system is simplified, the power consumption, the volume, the weight and the cost are correspondingly reduced, and the optical transmission system has a wide application prospect.

Description

Clock data multiplexing fiber optic transmission system Technical Field

[0001] This invention belongs to the field of optical fiber transmission, and in particular relates to a clock data multiplexing optical fiber transmission system. Background Technology

[0002] Existing synchronous clock and high-speed data multiplexed fiber optic transmission equipment often multiplexes digitized high-speed data signals and analog synchronous clock signals using wavelength division multiplexing (WDM) for transmission over a single-core fiber. The digitized high-speed data signal typically occupies one WDM channel, while the analog synchronous clock occupies another. This necessitates WDM for single-core fiber multiplexing transmission, leading to complex fiber optic transmission equipment and higher costs for the analog signal photoelectric conversion modules used to transmit the analog synchronous clock, thus increasing overall equipment costs. Summary of the Invention

[0003] In view of the shortcomings of the prior art, the technical problem to be solved by the present invention is to provide a clock data multiplexing optical fiber transmission system.

[0004] To solve the above-mentioned technical problems, the present invention provides the following technical solution: a clock data multiplexing optical fiber transmission system, including an optical fiber link for connecting a transmitting unit and a receiving unit; a transmitting unit for providing a first working clock required to convert the digital signal to be transmitted into a high-speed serial signal through parallel-to-serial conversion via a system synchronization clock, and outputting the high-speed serial signal to the optical fiber link after conversion to the optical domain; and a receiving unit for converting the optical signal received from the optical fiber link into the electrical signal domain, recovering the digital signal to be transmitted through serial-to-parallel conversion, and simultaneously extracting the first working clock and obtaining the system synchronization clock.

[0005] Furthermore, the transmitting unit includes a frequency conversion module for converting the frequency of the system synchronization clock to the frequency required by the parallel-to-serial processing module, thereby obtaining a first working clock and sending it to the working clock input port of the parallel-to-serial processing module; a parallel-to-serial processing module for using the first working clock as a clock signal to convert the digital signal to be transmitted from a parallel signal to a high-speed serial signal; and a photoelectric conversion module for converting the high-speed serial signal to the optical domain to obtain a transmission optical signal and outputting it to the optical fiber link.

[0006] Furthermore, the parallel-to-serial processing module is a first FPGA chip.

[0007] Furthermore, the input terminal of the frequency conversion module is used to input the system synchronization clock, and the output terminal is connected to the working clock input port of the first FPGA chip; the input terminal of the first FPGA chip is used to input the digital signal to be transmitted, and the output terminal is connected to the electrical port of the photoelectric conversion module, and the optical port of the photoelectric conversion module is connected to the optical fiber link.

[0008] Furthermore, the frequency conversion module is a frequency multiplier module.

[0009] Furthermore, the frequency conversion module is a frequency division module.

[0010] Furthermore, the receiving unit includes an electro-optical conversion module for converting the transmitted optical signal received by the optical fiber link into the electrical signal domain to recover the high-speed serial signal; a crystal oscillator for providing a working clock to the serial-parallel processing module; and a serial-parallel processing module for processing the high-speed serial signal to obtain the digital signal to be transmitted and the corresponding first working clock, and performing frequency division processing on the first working clock to obtain a digital clock signal with the same frequency as the system synchronization clock.

[0011] Furthermore, the serial-to-parallel processing module is a second FPGA chip.

[0012] Furthermore, the optical port of the electro-optical conversion module is connected to the optical fiber link, the electrical port is connected to the input terminal of the second FPGA chip, the operating clock input port of the second FPGA chip is connected to the crystal oscillator, the first output port is used to output the restored digital signal to be transmitted, and the second output port is used to output the digital clock signal.

[0013] Furthermore, the receiving unit also includes a clock phase-locked module, which is used to lock the input digital clock signal into phase and output a low-phase-noise analog clock with the same phase as the system synchronization clock.

[0014] In this invention, the system synchronization clock, which would normally require transmission via an analog photoelectric conversion module, is used as the working clock for converting the digital signal to be transmitted from parallel to serial to a high-speed serial signal. This simplifies the architecture of the original optical transmission system while maintaining the same device functionality, reduces the number of analog signal electro-optic conversion modules, wavelength division multiplexing (WDM) modules, and de-WDM modules. Furthermore, the optical transmission system correspondingly reduces power consumption, size, weight, and cost, and has broad application prospects. Attached Figure Description

[0015] The accompanying drawings, which are included to provide a further understanding of this application and form part of this application, illustrate exemplary embodiments of this application and are used to explain this application, but do not constitute an undue limitation of this application. In the drawings: Figure 1 is a structural block diagram of a prior art optical fiber transmission system with clock data multiplexing.

[0016] Figure 2 is a structural block diagram of an embodiment of the clock data multiplexing optical fiber transmission system of the present invention. Detailed Implementation

[0017] The following specific examples illustrate the implementation of the present invention. The illustrations provided in the following embodiments are only schematic representations of the basic concept of the present invention. Unless otherwise specified, the following embodiments and features can be combined with each other.

[0018] Referring to Figure 1, the transmitting unit of a prior art clock-data multiplexed fiber optic transmission system includes an FPGA chip, a crystal oscillator, an electro-optic conversion module (for electro-optic conversion of digital signals), an analog signal electro-optic conversion module (for electro-optic conversion of analog signals), and a wavelength division multiplexing (WDM) module. The receiving unit includes an FPGA chip, a crystal oscillator, two opto-optic conversion modules (for opto-optic conversion of digital signals), and a de-WDM module. The crystal oscillator provides the operating clock for the FPGA chip.

[0019] In the transmitting unit, the externally sent digital signal to be transmitted (e.g., the digital signal to be transmitted can be generated by the A / D sampling module) is converted into a high-speed serial signal through parallel-to-serial processing in the FPGA chip, and then converted into optical signal 1 through the electro-optic conversion module. The externally sent system synchronization clock (e.g., the system synchronization clock can be generated by the frequency source) is converted into optical signal 2 through the analog signal electro-optic conversion module. Optical signal 1 and optical signal 2 are multiplexed into one optical signal through the wavelength division multiplexing module and sent to the optical fiber link.

[0020] In the receiving unit, the demultiplexing module demultiplexes the optical signal received from the fiber optic link to obtain optical signal 1 and optical signal 2. These signals are then converted to electrical signals by two photoelectric conversion modules (for photoelectric conversion of digital signals). A low-phase-noise clock is then recovered by a clock phase-locked loop module. The signal converted from optical signal 1 is processed by an FPGA chip and restored to obtain the digital signal to be transmitted. For example, the restored two signals can be output to a digital signal processing device.

[0021] The above structure results in a large number of modules in both the transmitting and receiving units, requires a wavelength division multiplexing channel for transmission, and also increases the cost of the analog signal photoelectric conversion module, thus raising the overall equipment cost.

[0022] Please refer to Figure 2, which is a structural block diagram of an embodiment of the clock data multiplexing optical fiber transmission system of the present invention. The clock data multiplexing optical fiber transmission system of this embodiment includes a transmitting unit, a receiving unit, and an optical fiber link, which connects the transmitting unit and the receiving unit. The transmitting unit provides a first operating clock required to convert the digital signal to be transmitted from parallel to serial to a high-speed serial signal via a system synchronization clock, and outputs the high-speed serial signal to the optical domain after conversion to the optical fiber link. The receiving unit converts the optical signal received from the optical fiber link to the electrical signal domain, recovers the digital signal to be transmitted through serial-to-parallel conversion, and simultaneously extracts the first operating clock to obtain the system synchronization clock.

[0023] The transmitting unit may include a frequency conversion module, a parallel-to-serial processing module, and a photoelectric conversion module. The frequency conversion module is used to convert the frequency of the system synchronization clock to the frequency required by the parallel-to-serial processing module, thereby obtaining a first working clock and sending it to the working clock input port of the parallel-to-serial processing module.

[0024] The parallel-to-serial processing module is used to convert the digital signal to be transmitted from a parallel signal to a high-speed serial signal, using a first operating clock as the clock signal. The photoelectric conversion module is used to convert the high-speed serial signal to the optical domain, obtain a transmission optical signal, and output it to the optical fiber link.

[0025] In this embodiment, the parallel-serial processing module is an FPGA chip, specifically the first FPGA chip. An FPGA (Field-Programmable Gate Array) chip is a powerful semiconductor device. Unlike CPUs / GPUs, it does not have a fixed instruction set; instead, it allows users to "cast" a dedicated digital circuit according to specific needs. FPGA chips combine software flexibility with hardware speed and efficiency. Their core function is to provide ultimate hardware programmability and parallel processing capabilities, enabling engineers to "tailor-make" a parallel, high-speed, real-time dedicated digital circuit system for specific tasks. It is this unique attribute that makes FPGA chips a key technology for achieving high-performance, low-latency, and energy-efficient computing in a wide range of fields, from edge computing to data centers.

[0026] The core essence of an FPGA chip is reconfigurable hardware. The chip is covered with numerous programmable logic units, routing resources, and dedicated modules, allowing circuit functions to be defined using hardware description languages ​​(such as Verilog / VHDL). Development tools can be used to "compile" the design results into a bitstream file, which can then be downloaded to the FPGA chip. This allows for the configuration of the connections and functions between these logic units, effectively "building" a dedicated hardware circuit within the chip. Once completed, the FPGA chip can operate at the speed of a hardware circuit.

[0027] The main functions and advantages of FPGA chips are as follows: (1) Parallel processing capability (the core difference between CPU / GPU) CPU: sequential execution of instructions, good at complex control flow and general computing.

[0028] GPU: Large-scale data parallelism, adept at regular graphics / floating-point computation.

[0029] FPGA: True hardware-level parallelism. Multiple circuit modules in a design can operate simultaneously and independently. For example, a video processing pipeline can complete pixel reception, filtering, encoding, and transmission within the same clock cycle, without the overhead of software thread switching.

[0030] Advantages: It offers unparalleled speed and determinism for scenarios with extremely high requirements for data stream processing and real-time performance.

[0031] (2) Hardware acceleration This is one of the most important application areas of FPGA chips. By designing dedicated hardware accelerators for computationally intensive and time-consuming bottleneck parts of software (such as image processing, encryption and decryption, neural network inference, financial calculation, etc.), the energy efficiency ratio can usually be improved by tens or even thousands of times, while significantly reducing latency.

[0032] (3) High real-time performance and deterministic delay: In FPGA chips, the delay of a signal from input to output is fixed and can be accurately predicted (determined by logic gate and wiring delays). This is crucial for systems requiring hard real-time performance, such as industrial control, automotive electronics, and aerospace.

[0033] (4) Interface and Protocol Flexibility: The I / O pins of the FPGA can be programmed to support almost any digital electrical standard and communication protocol, thus serving as the "connection center" or "protocol converter" of the system, bridging devices of different standards and speeds.

[0034] (5) Prototype verification and rapid iteration: Before fabricating dedicated chips, using FPGA to build a prototype system for functional, performance and power consumption verification can greatly reduce risks and costs. After design modifications, only recompiling and downloading are required, and iteration can be completed in a few hours.

[0035] The input terminal of the frequency conversion module is used to input the system synchronization clock, and the output terminal is connected to the working clock input port of the first FPGA chip; the input terminal of the first FPGA chip is used to input the digital signal to be transmitted, and the output terminal is connected to the electrical port of the photoelectric conversion module, and the optical port of the photoelectric conversion module is connected to the optical fiber link.

[0036] When the frequency of the system synchronization clock is lower than the frequency of the operating clock required by the first FPGA chip, the frequency conversion module is a frequency multiplier module. When the frequency of the system synchronization clock is higher than the frequency of the operating clock required by the first FPGA chip, the frequency conversion module is a frequency divider module. Of course, when the frequency of the system synchronization clock is equal to the frequency of the operating clock required by the first FPGA chip, the frequency conversion module is not needed, that is, the frequency conversion module is a direct path. In this embodiment, the frequency of the system synchronization clock is 20MHz, and the frequency of the operating clock required by the first FPGA chip is 100MHz. Therefore, the frequency conversion module is a frequency multiplier module with a five-fold frequency multiplication function.

[0037] The receiving unit includes an electro-optical conversion module, a crystal oscillator, and a serial-to-parallel processing module. The electro-optical conversion module converts the transmitted optical signal received by the fiber optic link into the electrical signal domain to recover the high-speed serial signal. The crystal oscillator provides the operating clock for the serial-to-parallel processing module.

[0038] The serial-to-parallel processing module processes the high-speed serial signal to obtain the digital signal to be transmitted and the corresponding first working clock, and performs frequency division processing on the first working clock to obtain a digital clock signal with the same frequency as the system synchronization clock. In this embodiment, the serial-to-parallel processing module is also an FPGA chip, i.e., a second FPGA chip.

[0039] When an FPGA chip converts a digital signal into a high-speed serial signal, it incorporates the frequency information of its operating clock. The principle is as follows: Inside the transmitting FPGA chip (i.e., the first FPGA chip), the first operating clock is the transmission clock of the parallel-to-serial conversion module. It determines the exact moment when each bit "leaves" the FPGA chip pin. At the transmitting end, parallel data is sequentially shifted out by the serializer under the control of the transmission clock (i.e., the first operating clock). During this process, the length of the "time window" occupied by each bit is strictly fixed, and the reciprocal of this time window is the serial baud rate. That is, the bit period T_bit = 1 / baud rate, and the baud rate is the frequency of the transmission clock. Therefore, the frequency of the transmission clock directly defines the width of the bit. This width information is "imprinted" into the duration of each data bit.

[0040] Furthermore, all high-speed serial protocols employ encoding schemes to ensure transition density, preventing the receiver from missing transitions in special cases (such as long periods of "0" or "1" data). The most classic example is 8b / 10b encoding. 8b / 10b encoding maps 8 bits of data to 10 bits of symbols, ensuring that the number of 0s and 1s is approximately equal, avoiding charge accumulation. Even when transmitting consecutive "0"s or "1"s, the encoded sequence guarantees a transition after a maximum of 5 identical bits. Through this forced, regular transition, the receiver has a continuous "phase reference point," allowing it to continuously align its local clock with this reference point and extract precise frequency information from the transmitting clock.

[0041] The clock data recovery circuit of the receiving FPGA chip (i.e., the second FPGA chip) is essentially a phase-locked loop (PLL). Its function is to track the rhythm of the transition edges in the received high-speed serial data and inversely lock onto the "source" of this rhythm—the frequency of the transmitting clock. The specific process is as follows: After the high-speed serial signal enters the receiving FPGA chip, it is compared with the local reference clock (i.e., the clock provided by the crystal oscillator). The frequency of the local reference clock is very close to the nominal baud rate of the high-speed serial signal. The data stream of the high-speed serial signal first passes through a phase detector in the receiving FPGA chip. The phase detector continuously compares the arrival time of the data transition edges with the phase of the sampling clock generated by the local voltage-controlled oscillator in the receiving FPGA chip. If the data transition edge arrives earlier than the clock edge, it indicates that the clock phase is "slow"; otherwise, it is "fast." Afterward, the phase detector outputs a "lead" or "lag" signal proportional to the phase difference. This signal passes through a loop filter to remove high-frequency jitter and noise, generating a smooth control voltage. The control voltage is applied to the voltage-controlled oscillator (VCO) or numerically controlled oscillator (CNC) in the FPGA chip at the receiving end, fine-tuning the frequency and phase of its output clock to align it with the data transition edge. The fine-tuned output clock is the recovered transmit clock, whose frequency is equal to the serial baud rate of the data. This recovered clock passes through a 90-degree phase shifter to generate a sampling clock whose edge is aligned with the center of the data bit, thus sampling occurs at the moment when the data is most stable. The above process forms a negative feedback closed loop that runs continuously, dynamically tracking minute frequency shifts and phase jitters in the data stream, maintaining a locked state.

[0042] Therefore, in this embodiment, although the first operating clock information is not "sent" as an independent signal, it is "embedded" in the structure of the high-speed serial signal data stream itself in a time-regular manner. Thus, the transmission clock can be recovered by observing and measuring the rhythm of the transition edges. These are inherent functions of the FPGA, thus eliminating the need for additional hardware structures.

[0043] The process by which the second FPGA chip performs frequency multiplication or division on the first operating clock is the reverse of that of the frequency conversion module. In this embodiment, since the frequency of the first operating clock is 100MHz, the second FPGA chip performs a five-fold frequency division process after extracting the first operating clock, thereby obtaining a digital clock signal with a frequency of 20MHz.

[0044] The optical port of the electro-optical conversion module is connected to the optical fiber link, and the electrical port is connected to the input terminal of the second FPGA chip. The operating clock input port of the second FPGA chip is connected to the crystal oscillator. The first output port is used to output the restored digital signal to be transmitted, and the second output port is used to output a digital clock signal with the same frequency as the system synchronization clock.

[0045] To convert the digital clock signal into an analog signal, the receiving unit may further include a clock phase-locked module. This module locks the input digital clock signal into phase and outputs a low-phase-noise analog clock with the same phase as the system synchronization clock. The input of the clock phase-locked module is connected to the second output port of the second FPGA chip, and its output is used to output a low-phase-noise analog clock (i.e., a low-phase-noise system synchronization clock).

[0046] In this embodiment, the system synchronization clock, which would normally be transmitted via an analog photoelectric conversion module, is used as the master clock of the GTP (High-Speed ​​Serial Transceiver) IP in the first FPGA chip. This ensures that the transmitted data has a common clock source. The first FPGA chip converts the transmitted data into a high-speed serial signal via the GTP IP, and then converts it into an optical signal via an optical module for transmission to the remote end. At the remote end, the high-speed optical signal is converted into an electrical signal via a photoelectric conversion module, and the data and synchronization clock are recovered via the GTP IP inside the second FPGA chip. This simplifies the system architecture, eliminates the analog electro-optical signal conversion module, reduces wavelength division multiplexing (WDM) and de-WDM modules, decreases power consumption, saves system costs, and reduces equipment size. Furthermore, the optical transmission system correspondingly reduces power consumption, size, weight, and cost, and has broad application prospects.

[0047] The above embodiments merely illustrate preferred implementations of the present invention, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of the invention. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these all fall within the protection scope of the present invention. Therefore, the protection scope of this invention should be determined by the appended claims.

Claims

1. A clock-data multiplexed optical fiber transmission system, characterized in that: Includes fiber optic links used to connect the transmitting unit and the receiving unit; The transmitting unit is used to provide a first operating clock required to convert the digital signal to be transmitted into a high-speed serial signal through the system synchronization clock, and to output the high-speed serial signal to the optical link after converting it to the optical domain; and the receiving unit is used to convert the optical signal received from the optical link to the electrical signal domain, and to recover the digital signal to be transmitted through serial-to-parallel conversion, while extracting the first operating clock and obtaining the system synchronization clock.

2. The clock data multiplexing optical fiber transmission system as described in claim 1, characterized in that: The transmitting unit includes a frequency conversion module, which is used to convert the frequency of the system synchronization clock into the frequency of the working clock required by the parallel-serial processing module, and then obtain the first working clock and send it to the working clock input port of the parallel-serial processing module; the parallel-serial processing module is used to convert the digital signal to be transmitted from a parallel signal into a high-speed serial signal using the first working clock as the clock signal. And a photoelectric conversion module, used to convert the high-speed serial signal to the optical domain, obtain a transmission optical signal and output it to the optical fiber link.

3. The clock data multiplexing optical fiber transmission system as described in claim 2, characterized in that: The parallel-to-serial processing module is the first FPGA chip.

4. The clock data multiplexing optical fiber transmission system as described in claim 3, characterized in that: The input terminal of the frequency conversion module is used to input the system synchronization clock, and the output terminal is connected to the working clock input port of the first FPGA chip; the input terminal of the first FPGA chip is used to input the digital signal to be transmitted, and the output terminal is connected to the electrical port of the photoelectric conversion module, and the optical port of the photoelectric conversion module is connected to the optical fiber link.

5. The clock data multiplexing optical fiber transmission system as described in claim 2, characterized in that: The frequency conversion module is a frequency multiplier module.

6. The clock data multiplexing optical fiber transmission system as described in claim 2, characterized in that: The frequency conversion module is a frequency division module.

7. The clock data multiplexing optical fiber transmission system according to any one of claims 1 to 6, characterized in that: The receiving unit includes an electro-optic conversion module, which is used to convert the transmitted optical signal received by the optical fiber link into the electrical signal domain and recover the high-speed serial signal. A crystal oscillator is used to provide a working clock for the serial-parallel processing module; and the serial-parallel processing module is used to process the high-speed serial signal to obtain the digital signal to be transmitted and the corresponding first working clock, and to perform frequency division processing on the first working clock to obtain a digital clock signal with the same frequency as the system synchronization clock.

8. The clock data multiplexing optical fiber transmission system as described in claim 7, characterized in that: The serial-to-parallel processing module is a second FPGA chip.

9. The clock data multiplexing optical fiber transmission system as described in claim 8, characterized in that: The optical port of the electro-optical conversion module is connected to the optical fiber link, the electrical port is connected to the input terminal of the second FPGA chip, the operating clock input port of the second FPGA chip is connected to the crystal oscillator, the first output port is used to output the restored digital signal to be transmitted, and the second output port is used to output the digital clock signal.

10. The clock data multiplexing optical fiber transmission system as described in claim 9, characterized in that: The receiving unit also includes a clock phase-locked module, which is used to lock the input digital clock signal into phase and output a low-phase-noise analog clock with the same phase as the system synchronization clock.

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