Timing synchronization system and method of low-orbit satellite baseband, computer equipment and medium

Abstract

The invention discloses a timing synchronization system and method of a low-orbit satellite baseband, computer equipment and a medium, the timing synchronization system communicates with a digital signal processor and a baseband processing unit, and the timing synchronization system comprises a timer configured to receive timing configuration data sent by the digital signal processor, starting counting according to the timing configuration data so as to synchronize with the time of the digital signal processor; the instruction cache module receives and stores the timing instruction sets sent by the digital signal processor in sequence; the instruction analysis and execution module is connected with the instruction cache module and the timer, and is used for reading the timing instruction to be executed in the instruction cache module and timing data of the timer, analyzing instruction execution time of the timing instruction to be executed, and executing the timing instruction to be executed on time according to the timing data and the instruction execution time; therefore, data interaction between the digital signal processor and the baseband processing unit is completed. According to the invention, high precision, low power consumption and high real-time performance can be considered, and the flexibility of a timing system is improved.

Description

Timing synchronization system, method, computer equipment and media for low-Earth orbit satellite baseband Technical Field

[0001] This application relates to the field of low-Earth orbit satellite communication technology, specifically to a timing synchronization system, method, computer equipment, and medium for low-Earth orbit satellite baseband. Background Technology

[0002] In low-Earth orbit (LEO) satellite communication and navigation integrated systems, the baseband, as the core of signal processing, requires high-precision timing synchronization to ensure the accuracy of signal transmission and reception timing and the reliability of data interaction. Due to their low orbital altitude and high speed, LEO satellites are susceptible to Doppler frequency deviation, dynamic changes in propagation delay, and space electromagnetic interference, placing stringent requirements on the real-time performance and stability of baseband timing synchronization.

[0003] Existing low-Earth orbit (LEO) satellite baseband timing schemes mostly rely on a single hardware clock or simple software calibration, which has significant drawbacks: Firstly, hardware clocks are susceptible to crystal oscillator temperature drift and space radiation during long-term operation, leading to accumulated timing deviations and requiring frequent external navigation pulse calibration, with synchronization failures easily occurring during calibration intervals. Secondly, timing commands are mostly issued directly by the digital signal processor (DSP) in real time, lacking buffering and parsing mechanisms. Under high load, the DSP is prone to command delays, causing signal transmission and reception to miss satellite windows, affecting communication and navigation functions. Therefore, existing timing systems have low flexibility and struggle to simultaneously meet the comprehensive requirements of high precision, low power consumption, and high real-time performance. Summary of the Invention

[0004] The purpose of this application is to provide a timing synchronization system, method, computer equipment, and computer-readable storage medium for low-Earth orbit satellite baseband, in order to solve the problems of low flexibility and difficulty in meeting the comprehensive requirements of high precision, low power consumption, and high real-time performance in existing timing systems.

[0005] To achieve the above objectives, the first aspect of this application provides a timing synchronization system for a low-Earth orbit satellite baseband. The timing synchronization system communicates with a digital signal processor (DSP) and a baseband processing unit. The timing synchronization system includes: a timer configured to receive timing configuration data sent by the DSP and start counting according to the timing configuration data to synchronize with the DSP's time; an instruction cache module configured to receive and sequentially store a set of timing instructions sent by the DSP, the timing instruction set including signal reception instructions, signal transmission instructions, and hardware configuration instructions; and an instruction parsing and execution module connected to the instruction cache module and the timer, configured to read the pending timing instructions and the timer's timing data from the instruction cache module, parse the instruction execution time of the pending timing instructions, and execute the pending timing instructions on time according to the timing data, thereby completing the data interaction between the DSP and the baseband processing unit.

[0006] In this embodiment of the application, the timing synchronization system further includes: a data caching module, configured to receive and store the interaction data between the digital signal processor and the baseband processing unit, the interaction data including signal data to be transmitted, signal data to be received, hardware configuration data to be transmitted, and hardware status data to be received.

[0007] In this embodiment, the instruction parsing and execution module includes: an instruction queue parsing unit connected to the instruction cache module, configured to read the timed instruction to be executed from the instruction cache module according to the first-in-first-out principle, and parse out the instruction execution time and instruction parameters of the timed instruction to be executed; a time comparison unit connected to the instruction queue parsing unit and the timer respectively, configured to receive the instruction execution time output by the instruction queue parsing unit and the current time output by the timer, compare the instruction execution time and the current time, and output a trigger instruction output pulse if the instruction execution time and the current time are the same; an instruction output unit connected to the instruction queue parsing unit and the time comparison unit respectively, configured to receive the instruction parameters output by the instruction queue parsing unit and the trigger instruction output pulse output by the time comparison unit, and combine the instruction parameters and the trigger instruction output pulse to generate an execution instruction; and an instruction execution unit connected to the instruction output unit, configured to receive the execution instruction output by the instruction output unit and execute the corresponding operation.

[0008] In this embodiment, the timing instruction set includes signal receiving instructions and signal sending instructions. The instruction execution unit is also connected to the data buffer module and the baseband processing unit. The instruction execution unit is further configured to: transfer signal data from the baseband processing unit to the data buffer module when the timing instruction to be executed is a signal receiving instruction; transfer signal data from the data buffer module to the baseband processing unit when the timing instruction to be executed is a signal sending instruction; and transfer corresponding hardware configuration data from the data buffer module to the baseband processing unit when the timing instruction to be executed is a hardware configuration instruction.

[0009] In this embodiment of the application, the instruction queue parsing unit is further configured to: after the timed instruction to be executed is triggered, continue to obtain the next instruction to be executed from the instruction cache module and parse it.

[0010] In this embodiment, the timer includes a timer snapshot unit, which is configured to: maintain timing counting when the timing synchronization system is in low-power mode; and output a snapshot value after the timing synchronization system exits low-power mode, so that the timer can restore time synchronization according to the snapshot value.

[0011] In this embodiment, the timer is further configured to: receive a navigation timing synchronization pulse output by a navigation receiver; detect the pulse edge of the navigation timing synchronization pulse; and, if the pulse edge is detected, calibrate the timer's counting deviation according to the pulse edge so that the timer's time is synchronized with the time of the global satellite navigation system.

[0012] The second aspect of this application provides a timing synchronization method for a low-Earth orbit (LEO) satellite baseband system, applied to a LEO satellite baseband timing synchronization system. The timing synchronization system communicates with a digital signal processor (DSP). The timing synchronization system includes a timer and an instruction cache module. The timer is synchronized with the DSP. The method includes: acquiring a timing instruction set sent by the DSP and storing the timing instruction set in the instruction cache module; reading the timing instruction to be executed from the instruction cache module according to the first-in-first-out (FIFO) principle; parsing the instruction execution time of the timing instruction to be executed; acquiring the current time of the timer; and executing the timing instruction to be executed if the instruction execution time is the same as the current time.

[0013] A third aspect of this application provides a computer device, including a memory and a processor. The memory stores a computer program, and the processor executes the computer program to implement the aforementioned low-Earth orbit satellite baseband timing synchronization method.

[0014] The fourth aspect of this application provides a machine-readable storage medium on which a program or instruction is stored, and when the program or instruction is executed by a processor, it implements the above-described low-Earth orbit satellite baseband timing synchronization method.

[0015] The above technical solution provides a timing synchronization system for a low-Earth orbit satellite baseband. The timing synchronization system communicates with both a digital signal processor (DSP) and a baseband processing unit. The system includes a timer, an instruction cache module, and an instruction parsing and execution module. The timer receives timing configuration data from the DSP and starts counting according to the data to synchronize with the DSP's time. The instruction cache module receives and sequentially stores a set of timing instructions sent by the DSP. The instruction parsing and execution module is connected to the instruction cache module and the timer. It reads the timing instructions to be executed from the instruction cache module and the timer's timing data, parses the execution time of the timing instructions to be executed, and executes the instructions precisely according to the timing data to complete the data interaction between the DSP and the baseband processing unit. This application, through synchronized timers, ordered instruction caching, and timely parsing and execution, balances high precision, low power consumption, and high real-time performance, improving the flexibility of the timing system and meeting the efficient interaction requirements of the DSP and the baseband processing unit.

[0016] Other features and advantages of the embodiments of this application will be described in detail in the following detailed description section. Attached Figure Description

[0017] The accompanying drawings are provided to further illustrate the embodiments of this application and constitute a part of the specification. They are used together with the following detailed description to explain the embodiments of this application, but do not constitute a limitation on the embodiments of this application. In the drawings: Figure 1 is a structural block diagram of a low-Earth orbit satellite baseband timing synchronization system provided in an embodiment of this application; Figure 2 is a structural block diagram of a low-Earth orbit satellite baseband timing synchronization system provided in another embodiment of this application; Figure 3 is a flowchart illustrating a low-Earth orbit satellite baseband timing synchronization method provided in an embodiment of this application; Figure 4 is a schematic diagram illustrating a timer synchronization principle provided in a specific embodiment of this application; Figure 5 is a flowchart illustrating a timing instruction execution process provided in a specific embodiment of this application.

[0018] Among them, 100-timed synchronization system; 200-digital signal processor; 300-baseband processing unit; 110-timer; 111-timer snapshot unit; 120-instruction cache module; 130-instruction parsing and execution module; 131-instruction queue parsing unit; 132-time comparison unit; 133-instruction output unit; 134-instruction execution unit; 140-data cache module. Detailed Implementation

[0019] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are only for illustration and explanation of the embodiments of this application and are not intended to limit the embodiments of this application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0020] It should be noted that if the embodiments of this application involve directional indicators (such as up, down, left, right, front, back, etc.), the directional indicators are only used to explain the relative positional relationship and movement of each component in a certain specific posture (as shown in the figure). If the specific posture changes, the directional indicators will also change accordingly.

[0021] Furthermore, if the embodiments of this application involve descriptions such as "first" or "second," these descriptions are for descriptive purposes only and should not be construed as indicating or implying their relative importance or implicitly specifying the number of technical features indicated. Therefore, features defined with "first" or "second" may explicitly or implicitly include at least one of those features. Additionally, the technical solutions of various embodiments can be combined with each other, but this must be based on the ability of those skilled in the art to implement them. If the combination of technical solutions is contradictory or impossible to implement, it should be considered that such a combination of technical solutions does not exist and is not within the scope of protection claimed in this application.

[0022] The high-speed movement of low-Earth orbit (LEO) satellites leads to dynamic changes in signal propagation delay and significant Doppler frequency shift. Without precise timing coordination, data interaction between the digital signal processor (DSP) and the baseband processing unit (BBU) is prone to timing misalignment, potentially causing communication interruptions or navigation / positioning errors. To address this, this application provides a timing synchronization system for LEO satellite baseband, assisting the DSP on the LEO satellite communication side in real-time signal transmission and reception, time synchronization maintenance, and hardware timing configuration, enabling rapid completion of system time synchronization. Since the DSP only needs to operate during specific bursts of signal transmission, the receiver system's bandwidth requirements for the DSP are significantly reduced, thereby improving the real-time performance of signal processing and enhancing the DSP's overall performance.

[0023] Figure 1 is a structural block diagram of a low-orbit satellite baseband timing synchronization system provided in an embodiment of this application. As shown in Figure 1, this application embodiment provides a timing synchronization system 100 for a low-Earth orbit satellite baseband. The timing synchronization system 100 communicates with a digital signal processor 200 and a baseband processing unit 300, respectively. The timing synchronization system 100 includes: a timer 110 configured to receive timing configuration data sent by the digital signal processor 200 and start counting according to the timing configuration data to synchronize with the time of the digital signal processor 200; an instruction cache module 120 configured to receive and sequentially store a set of timing instructions sent by the digital signal processor 200, the timing instruction set including signal receiving instructions, signal sending instructions, and hardware configuration instructions; and an instruction parsing and execution module 130 connected to the instruction cache module 120 and the timer 110, configured to read the timing instructions to be executed in the instruction cache module 120 and the timing data of the timer 110, parse the instruction execution time of the timing instructions to be executed, and execute the timing instructions to be executed on time according to the instruction execution time based on the timing data to complete the data interaction between the digital signal processor 200 and the baseband processing unit 300.

[0024] In this embodiment, the digital signal processor 200 is a microprocessor specifically designed for real-time digital signal processing. In this system, it is responsible for the acquisition, tracking, and decoding of downlink signals from low-Earth orbit (LEO) satellites, the encoding, framing, and modulation of uplink information, and the implementation of related upper-layer protocols. The baseband processing unit 300 is the core hardware unit in the LEO satellite baseband system responsible for physical layer signal processing, including signal modulation, demodulation, and radio frequency processing. The timing synchronization system 100 in this embodiment can communicate with both the digital signal processor 200 and the baseband processing unit 300 to enable data interaction between them.

[0025] Specifically, in this embodiment, the timing synchronization system 100 includes a timer 110, which is the core time reference of the timing synchronization system 100. This timing synchronization navigation system can use a composite timer 110 with 32-bit phase accumulation and 24-bit sample counting. In the scenario of integrated communication and navigation of low-Earth orbit satellites, the digital signal processor 200 and the baseband processing unit 300 need to unify their time scales to ensure the timing consistency of signal transmission and reception and data interaction. If the time reference deviation is too large, it will cause the uplink signal to miss the satellite reception window and the downlink signal to fail to acquire. Therefore, in this embodiment, the digital signal processor 200 can send timing configuration data to the timer 110 through the System on Chip (SOC) bus or the Advanced Dextensible Interface (AXI). The timing configuration data is a set of parameters sent by the DSP to the timer 110, which usually includes the initial phase, phase accumulation word, initial count value, start, pause or clear control instructions, etc. In this way, the configurable timing parameters can be adapted to the signal rate requirements of different low-orbit satellites, while the 32-bit + 24-bit composite timing mode can ensure nanosecond-level time accuracy, thereby meeting the stringent time synchronization requirements of integrated communication and navigation systems.

[0026] In one example, the DSP sends adjustment commands via the SOC bus based on the time offset results captured by the downlink signal from the low-Earth orbit satellite, adjusting the phase and count value of timer 110 in real time or at regular intervals.

[0027] Furthermore, considering that low-Earth orbit satellites need to handle multiple types of tasks, such as periodic signal transmission and reception and sudden hardware configuration, if instructions are directly issued by the DSP in real time, bus congestion can easily lead to instruction delays or out-of-order execution, thus affecting the operating timing of the baseband processing unit 300. To address this, the timing synchronization system 100 also includes an instruction cache module 120 to ensure orderly instruction execution. Specifically, the digital signal processor 200 can generate corresponding timing instructions according to system operating requirements. Each instruction includes information such as instruction execution time, instruction type, and instruction parameters. Through the SOC bus interface, the timing instructions are written one by one into the instruction cache module 120 according to a specific communication protocol. The instruction cache module 120 uses a first-in, first-out (FIFO) storage structure to store the received timing instruction set to ensure the order of instructions. The timing instruction set is the set of operation instructions generated by the DSP according to business requirements, including signal reception instructions, signal transmission instructions, hardware configuration instructions, null instructions, and jump instructions. The core execution target of hardware configuration instructions is the radio frequency chip; null instructions are used for timing alignment, such as inserting a null instruction between two signal transmission / reception instructions to avoid operational conflicts; jump instructions are used for flow control, such as jumping to error correction instructions when hardware configuration is incorrect. Thus, by adopting a queue-style instruction storage method, the sequential execution of instructions is ensured, avoiding instruction execution chaos and guaranteeing the timing accuracy of the system.

[0028] The timing synchronization system 100 in this embodiment further includes an instruction parsing and execution module 130. The instruction parsing and execution module 130 is connected to both the timer 110 and the instruction cache module 120. The instruction parsing and execution module 130 reads the timing instruction to be executed from the instruction cache module 120 according to a first-in-first-out (FIFO) principle, then parses the instruction execution time through hardware logic circuits. Simultaneously, it receives timing data output by the timer 110 and executes the timing instruction to be executed precisely according to the instruction execution time based on this timing data, thereby completing the data interaction between the digital signal processor 200 and the baseband processing unit 300. Thus, by employing an instruction caching mechanism, batch issuance and buffering of instructions are achieved, while sequential reading and parsing of instructions ensures the sequentiality of instruction execution, meets the system's timing requirements, reduces real-time interaction between the DSP and the timing synchronization circuit, and improves the DSP's working efficiency.

[0029] In summary, the timing synchronization system, through the collaborative work of the timer, instruction cache module, and instruction parsing and execution module, constructs a complete timing control link of time synchronization, ordered instruction, and precise execution. This effectively solves the problems of excessive DSP load, large timing deviation, and poor multi-task compatibility in traditional systems, providing core support for the stable realization of low-orbit satellite communication and navigation integrated functions.

[0030] The above technical solution provides a timing synchronization system for a low-Earth orbit satellite baseband. The timing synchronization system communicates with both a digital signal processor (DSP) and a baseband processing unit. The system includes a timer, an instruction cache module, and an instruction parsing and execution module. The timer receives timing configuration data from the DSP and starts counting according to the data to synchronize with the DSP's time. The instruction cache module receives and sequentially stores a set of timing instructions sent by the DSP. The instruction parsing and execution module is connected to the instruction cache module and the timer. It reads the timing instructions to be executed from the instruction cache module and the timer's timing data, parses the execution time of the timing instructions to be executed, and executes the instructions precisely according to the timing data to complete the data interaction between the DSP and the baseband processing unit. This application, through synchronized timers, ordered instruction caching, and timely parsing and execution, balances high precision, low power consumption, and high real-time performance, improving the flexibility of the timing system and meeting the efficient interaction requirements of the DSP and the baseband processing unit.

[0031] Figure 2 is a structural block diagram of a timing synchronization system for a low-Earth orbit satellite baseband according to another embodiment of this application. As shown in Figure 2, in this embodiment of the application, the timing synchronization system 100 may further include: a data buffer module 140, configured to receive and store interactive data between the digital signal processor 200 and the baseband processing unit 300, the interactive data including signal data to be transmitted, signal data to be received, hardware configuration data to be transmitted, and hardware status data to be received.

[0032] It is understandable that, considering the differences in operating speed and timing requirements between the DSP and BBU, direct data interaction could easily lead to data loss or bus congestion due to speed mismatch, thereby affecting the real-time performance of signal transmission and reception and hardware configuration. To address this, the timing synchronization system 100 of this embodiment further includes a data buffer module 140, used to receive and store the interaction data between the digital signal processor 200 and the baseband processing unit 300, thereby ensuring efficient and conflict-free data interaction between the digital signal processor 200 and the baseband processing unit 300. The data buffer module 140, acting as an intermediate buffer, enables asynchronous data transmission between the DSP and the baseband processing unit 300, improving the system's parallelism and operating efficiency.

[0033] In this embodiment, the interactive data includes signal data to be transmitted, signal data to be received, hardware configuration data to be transmitted, and hardware status data to be received. The signal data to be transmitted is digital signal data generated by the DSP after encoding, framing, and modulation of uplink information; it needs to be transmitted to the BBU for digital-to-analog conversion before transmission. The signal data to be received is digital signal data generated by the BBU after performing analog-to-digital conversion and demodulation of the satellite downlink RF signal; it needs to be temporarily stored before being acquired, tracked, and decoded by the DSP. The hardware configuration data to be transmitted is instruction data generated by the DSP according to system requirements for configuring BBU parameters. The hardware status data to be received is real-time feedback of the BBU's own operating status information, such as the BBU's current RF chip operating mode, phase-locked loop status, filter parameters, and RF gain.

[0034] In one example, the data cache module 140 can be divided into four independent storage areas, corresponding to the area for signal data to be transmitted, the area for signal data to be received, the area for hardware configuration data to be transmitted, and the area for hardware status data to be received, respectively. The DSP writes the data to be transmitted into the corresponding area of ​​the data cache according to the corresponding format and address via the SOC bus. When the baseband processing unit 300 needs to obtain the data to be transmitted, it reads it from the corresponding area of ​​the data cache module 140; the baseband processing unit 300 writes the processed data to be received into the corresponding area of ​​the data cache module 140, and the DSP reads the data to be received from these areas via the SOC bus for subsequent processing. Thus, by classifying and storing data, the management of different types of data becomes clearer, avoiding data confusion and conflicts.

[0035] Preferably, the data cache module 140 is implemented using a dual-port RAM, which supports parallel access by the DSP and the baseband processing unit 300, thereby improving the data transmission rate.

[0036] As shown in Figure 2, in this embodiment, the instruction parsing and execution module 130 may include: an instruction queue parsing unit 131, connected to the instruction cache module 120, configured to read the timed instruction to be executed from the instruction cache module 120 according to the first-in-first-out principle, and parse out the instruction execution time and instruction parameters of the timed instruction to be executed; a time comparison unit 132, connected to the instruction queue parsing unit 131 and the timer 110 respectively, configured to receive the instruction execution time output by the instruction queue parsing unit 131 and the current time output by the timer 110, compare the instruction execution time and the current time, and output a trigger instruction output pulse when the instruction execution time and the current time are the same; an instruction output unit 133, connected to the instruction queue parsing unit 131 and the time comparison unit 132 respectively, configured to receive the instruction parameters output by the instruction queue parsing unit 131 and the trigger instruction output pulse output by the time comparison unit 132, and combine the instruction parameters and the trigger instruction output pulse to generate an execution instruction; and an instruction execution unit 134, connected to the instruction output unit 133, configured to receive the execution instruction output by the instruction output unit 133 and execute the corresponding operation.

[0037] In this embodiment, the instruction queue parsing unit 131 is connected to the instruction cache module 120 via a SOC bus or an advanced scalable interface. Following a first-in, first-out (FIFO) principle, it reads the timed instructions to be executed from the instruction cache module 120 and parses out the instruction execution time and instruction parameters of the timed instructions to ensure that the subsequent instruction execution order is consistent with the order in which the DSP issues instructions. The instruction execution time is the time point at which the instruction needs to be triggered for execution, corresponding to the 32-bit phase accumulation value or the 24-bit sample count value of the timer 110. Instruction parameters refer to additional information related to the instruction, used to specify the specific details of instruction execution, such as signal reception length and hardware configuration data length.

[0038] In one example, the digital signal processor 200 can configure the operating parameters of the instruction queue parsing unit 131 via the SOC bus, such as setting the instruction read position, starting or stopping instruction parsing, etc.

[0039] In another example, the digital signal processor 200 can obtain the current operating status of the instruction queue parsing unit 131 through the SOC bus, including the current parsing instruction position, whether parsing is in progress, and whether an error has occurred.

[0040] In this embodiment of the application, the instruction queue parsing unit 131 can also be configured to: after the timed instruction to be executed is triggered, continue to obtain the next instruction to be executed from the instruction cache module 120 and parse it, so as to realize the continuous processing of instructions.

[0041] Furthermore, the time comparison unit 132 is connected to both the instruction queue parsing unit 131 and the timer 110. It receives the instruction execution time from the instruction queue parsing unit 131 and the current time from the timer 110, and then uses a high-speed comparator circuit to compare the data, specifically the instruction execution time and the current time. When the instruction execution time and the current time are the same, the time comparison unit 132 outputs a fixed-width trigger instruction output pulse, typically one system clock cycle, to ensure that the instruction output unit 133 can stably capture the trigger signal. If the two are not equal, the comparison continues until the times match.

[0042] Furthermore, the instruction execution unit 134 is connected to the instruction queue parsing unit 131 and the time comparison unit 132, respectively. After receiving the trigger instruction output pulse from the time comparison unit 132 and the instruction parameters from the instruction queue parsing unit 131, it combines the instruction type, instruction parameters, and other information into a complete execution instruction. The instruction execution unit 134 is connected to the instruction output unit 133 and is configured to execute the corresponding operation according to the instruction type after receiving the execution instruction output by the instruction output unit 133. Instruction types include signal reception instructions, signal transmission instructions, hardware configuration instructions, etc.

[0043] In one example, the instruction execution unit 134 has an internal status register that records its own operating status in real time. The DSP reads this register through the SOC bus to obtain the current operating status of the instruction execution unit 134. This facilitates the timely detection and handling of abnormal situations during instruction execution, improving the reliability of the system.

[0044] In this embodiment, the timing instruction set may include signal receiving instructions and signal sending instructions. As shown in FIG2, the instruction execution unit 134 is also connected to the data buffer module 140 and the baseband processing unit 300. The instruction execution unit 134 may also be configured to: transfer signal data from the baseband processing unit 300 to the data buffer module 140 when the timing instruction to be executed is a signal receiving instruction; transfer signal data from the data buffer module 140 to the baseband processing unit 300 when the timing instruction to be executed is a signal sending instruction; and transfer corresponding hardware configuration data from the data buffer module 140 to the baseband processing unit 300 when the timing instruction to be executed is a hardware configuration instruction.

[0045] In one example, when the timing instruction to be executed is a signal receiving instruction, the instruction execution unit 134 first parses the data length parameter in the instruction, and then reads the downlink signal data after the BBU has completed analog-to-digital conversion and demodulation through a dedicated data interface connected to the BBU. The read data is then written sequentially into the signal data area to be received in the data buffer module 140.

[0046] In another example, when the timing instruction to be executed is a signal transmission instruction, the instruction execution unit 134 first parses the data start address and data length parameters in the instruction, then reads the data with the corresponding address and length in the signal data area to be transmitted in the data buffer module 140, and then transmits the read data to the BBU. After the BBU completes the digital-to-analog conversion, it is transmitted to the satellite through the radio frequency module.

[0047] In another example, when the timer instruction to be executed is a hardware configuration instruction, the instruction execution unit 134 parses the configuration data address and configuration register address in the instruction, reads the hardware configuration data at the corresponding address through the data cache module 140, and then writes the configuration data into the designated configuration register of the BBU to complete the BBU parameter update.

[0048] In this way, by clearly defining the instruction type and operation mapping, the direction of data interaction and hardware configuration operations are ensured to be accurate and error-free, avoiding resource waste caused by misaligned data transmission. At the same time, by entrusting the data interaction and hardware configuration tasks to the instruction execution unit, the real-time intervention of the DSP is greatly reduced, the data processing bandwidth requirements of the DSP are reduced, and the DSP can focus on core algorithm processing such as signal acquisition, tracking, and decoding, thereby improving the working efficiency and stability of the entire communication and navigation integrated system.

[0049] As shown in Figure 2, in this embodiment of the application, the timer 110 includes a timer snapshot unit 111. The timer snapshot unit 111 can be configured to: maintain timing counting when the timing synchronization system 100 is in low power mode; and output a snapshot value after the timing synchronization system 100 exits the low power mode, so that the timer 110 can restore time synchronization according to the snapshot value.

[0050] It is understandable that, considering that low-Earth orbit satellite terminals rely on solar power and need to frequently enter low-power mode to save energy, without this unit, a power outage of the baseband would cause the timer 110 to lose its counting data. After exiting low-power mode, it would need to resynchronize with the digital signal processor 200 or the navigation system, which would be time-consuming and affect the real-time performance of signal processing. To address this, this embodiment of the application can set a timer snapshot unit 111 in the timer 110 to ensure that timing information is not lost in low-power mode and to quickly restore time synchronization after exiting low-power mode.

[0051] In this embodiment, timer 110 employs a composite timing method combining 32-bit phase accumulation and 24-bit sample counting. The 32-bit phase accumulation records nanosecond-level high-precision time offset, while the 24-bit sample counting counts the number of signal samples. Together, they achieve accurate timing. Low-power mode refers to a working mode where the timing synchronization system 100, to reduce energy consumption, shuts down high-power modules in the baseband section, retaining only the core timing and storage units powered on. This is commonly seen in scenarios such as when a satellite enters Earth's shadow or when there is no service demand. The snapshot value is the current counting data of timer 110 continuously updated and stored by the timer snapshot unit 111 in low-power mode, containing the real-time values ​​of the 32-bit phase accumulation value and the 24-bit sample count.

[0052] In one example, the timer snapshot unit 111 can employ a low-power timing circuit and a non-volatile memory architecture. The low-power timing circuit uses an ultra-low-power crystal oscillator as its clock source, replacing the master clock in low-power mode to provide the basic clock signal for counting, ensuring continuous updates of the 32-bit phase accumulation and 24-bit sample count, and avoiding timing interruptions due to the master clock being turned off; the non-volatile memory stores the updated 32-bit phase accumulation value and 24-bit sample count of the timing circuit in real time, forming a snapshot value.

[0053] Specifically, when entering the power mode, the main clock of timer 110 is turned off, and the low-power timing circuit of timer snapshot unit 111 is started, updating the snapshot value in non-volatile memory every second to ensure that the snapshot value deviates from the actual time by no more than 1 second. When the timing synchronization system 100 exits the low-power mode, timer snapshot unit 111 reads the latest snapshot value stored in non-volatile memory through the internal data interface, and then directly loads the read snapshot value into the 32-bit phase accumulator register and 24-bit sample count register of timer 110, overwriting the default initial value of the register, so that timer 110 continues to count from the time point corresponding to the snapshot value, instead of starting from zero, so as to achieve rapid recovery of time synchronization.

[0054] Thus, by using the timer 110 snapshot mechanism in low-power mode, the time synchronization is quickly restored, reducing the time overhead and synchronization error caused by mode switching, while also reducing the system's energy consumption in low-power mode.

[0055] In this embodiment, the timer 110 can also be configured to: receive navigation timing synchronization pulses output by the navigation receiver; detect the pulse edge of the navigation timing synchronization pulses; and, if the pulse edge is detected, calibrate the counting deviation of the timer 110 according to the pulse edge so that the time of the timer 110 is synchronized with the time of the global satellite navigation system.

[0056] It is understandable that the timing synchronization of low-orbit satellite baseband needs to be aligned with the standard time of the global satellite navigation system. Without this calibration mechanism, the timer is prone to counting deviations due to factors such as crystal oscillator temperature drift and space radiation, resulting in misalignment of communication signal transmission and reception timing and a decrease in navigation and positioning accuracy.

[0057] In this embodiment, the navigation receiver is a device capable of receiving signals from the Global Navigation Satellite System (GNSS) and outputting time synchronization information. Its output navigation timing synchronization pulse is typically a second pulse, meaning it outputs a fixed-width pulse signal per second, with the corresponding time being the standard time of the GNSS. In this embodiment, the timer also integrates a pulse receiving interface, a pulse edge detection circuit, and counting calibration logic. The pulse receiving interface uses a differential signal interface design, which effectively suppresses spatial electromagnetic interference and ensures stable transmission of the navigation timing synchronization pulse to the timer. The pulse edge detection circuit uses a high-speed comparator and an edge-triggered flip-flop. The high-speed comparator monitors the level change of the pulse signal in real time. When it detects a transition from low to high (rising edge), it triggers the flip-flop to output a synchronization signal, marking the arrival time of the pulse edge. After receiving the synchronization signal, the counting calibration logic clears the 32-bit phase accumulation value and the 24-bit sample count to zero. Thus, by synchronizing the timer's count with this pulse edge, the timer's time base is kept consistent with the globally unified time base, thereby achieving high-precision time synchronization for the entire system.

[0058] Preferably, the above calibration process can be a one-time procedure or a periodic procedure to ensure that the timer maintains high time accuracy during long-term operation.

[0059] Figure 3 is a flowchart illustrating a timing synchronization method for a low-Earth orbit (LEO) satellite baseband according to an embodiment of this application. As shown in Figure 3, this application also provides a timing synchronization method for a LEO satellite baseband, applied to the LEO satellite baseband timing synchronization system in the above embodiments. The timing synchronization system communicates with a digital signal processor (DSP). The timing synchronization system includes a timer and an instruction cache module. The timer is synchronized with the DSP. The method includes: step S101, acquiring a timing instruction set sent by the DSP and storing the timing instruction set in the instruction cache module.

[0060] It is understood that the timing synchronization method in this application uses the timing synchronization system described above, which includes components such as a timer, an instruction cache module, and an instruction parsing and execution module. The timer employs a composite timing method of 32-bit phase accumulation and 24-bit sample counting, achieving time synchronization with the DSP via the SOC bus. The timing instruction set is a collection of operation instructions issued by the DSP, including signal receiving instructions, signal sending instructions, hardware configuration instructions, etc., with each instruction carrying its execution time and parameters. Specifically, after receiving the timing instruction set sent by the digital signal processor, the timing synchronization system stores it in the instruction cache module to prevent instruction loss and lay the foundation for subsequent orderly execution.

[0061] Step S102: Read the timed instruction to be executed from the instruction cache module according to the first-in-first-out principle.

[0062] It is understandable that, in order to ensure the order of instruction execution, the timing synchronization system reads the timed instructions to be executed from the instruction cache module according to the first-in-first-out principle, ensuring that the order of instruction execution is consistent with the order of DSP issuance, and preventing timing chaos caused by multiple out-of-order instructions.

[0063] Step S103: parse the instruction execution time of the timer instruction to be executed.

[0064] Specifically, the timing synchronization system can parse the read timed instructions to be executed, separate the instruction execution time from the timed instructions, and provide a basis for subsequent time comparison.

[0065] Step S104: Obtain the current time of the timer.

[0066] Specifically, the timer uses 32-bit phase accumulation and 24-bit sample counting. The system reads its current count data as the current time, providing a standard for determining whether the instruction has reached its execution time.

[0067] Step S105: If the instruction execution time is the same as the current time, execute the scheduled instruction to be executed.

[0068] Specifically, after obtaining the instruction execution time and the current time of the timer, the two are compared. If the instruction execution time is the same as the current time, the timed instruction to be executed is executed to ensure the precise timing of the interaction between the DSP and the baseband processing unit.

[0069] In this embodiment, the timing synchronization system also communicates with the baseband processing unit. When the instruction execution time is the same as the current time, the execution of the timing instruction to be executed includes: if the timing instruction to be executed is a signal receiving instruction, transferring signal data from the baseband processing unit to the data buffer module; if the timing instruction to be executed is a signal transmitting instruction, transferring signal data from the data buffer module to the baseband processing unit; and if the timing instruction to be executed is a hardware configuration instruction, transferring corresponding hardware configuration data from the data buffer module to the baseband processing unit.

[0070] It is understood that the timing synchronization method for low-Earth orbit satellite baseband provided in this application embodiment is applied to the timing synchronization system for low-Earth orbit satellite baseband in the above embodiments. The timing synchronization method can realize all the functions of the timing synchronization system, and is the same as the above embodiments, so it will not be described again here.

[0071] Figure 4 is a schematic diagram of a timer synchronization principle provided in a specific embodiment of this application. As shown in Figure 4, the timer synchronization process may include the following steps: S11: The digital signal processor (DSP) enables the pulse detection module through the AXI bus.

[0072] S12: If the pulse detection module detects the second pulse edge of the navigation PPS, the timer is cleared to the 32-bit phase accumulation value and the 24-bit sample count to achieve navigation time synchronization.

[0073] S13: The digital signal processor (DSP) acquires the downlink signal from the low-Earth orbit satellite and obtains the current signal time offset. The DSP adjusts the 32-bit phase accumulation value and 24-bit sample count of the timer in real time or at regular intervals through the AXI bus to achieve acquisition time synchronization.

[0074] S14: Before the baseband is powered off in low-power mode, the digital signal processor (DSP) saves the 32-bit phase accumulation value and 24-bit sample count of the timer to a snapshot of the 32-bit phase accumulation value and 24-bit sample count via the AXI bus.

[0075] S15: After exiting low-power mode, the digital signal processor (DSP) reloads the 32-bit phase accumulation value and 24-bit sample count snapshot to the 32-bit phase and 24-bit sample count of the timer via the AXI bus to achieve low-power time synchronization.

[0076] Figure 5 is a schematic diagram of a timing instruction execution flow provided in a specific embodiment of this application. As shown in Figure 5, the timing instruction execution flow may include the following steps: S21: The digital signal processor writes the queue of instructions to be executed into a 256-depth instruction cache through the AXI bus. The maximum number of instructions to be executed written at one time is 256, and the instruction width is 64 bits.

[0077] S22: The digital signal processor writes the total number of instructions to be executed into the total number of instructions to be executed module via the AXI bus.

[0078] S23: The digital signal processor writes the start position of the instruction queue to be executed into the read instruction start position module through the AXI bus, with a value range of 1-256.

[0079] S24: The digital signal processor starts parsing the instruction at the beginning of the instruction cache by reading the instruction from the current 64-bit instruction module via the AXI bus.

[0080] S25: Parse the current 64-bit instruction module by parsing the lower 24 bits of the 64-bit instruction into the instruction execution time and the higher 40 bits into the instruction parameters.

[0081] S26: The 24-bit comparator is used to compare the 24-bit sample counter of the timer with the current instruction execution time in real time. If they are equal, it outputs a pulse to trigger the instruction output module to output the instruction.

[0082] S27: After receiving the instruction, the instruction execution module executes the current instruction and increments the instruction execution count by 1.

[0083] S28: Assuming the current instruction is a signal receiving instruction, the instruction execution module will move the specified length of signal data from the baseband processing unit to the 1024 data buffer.

[0084] S29: The digital signal processor reads baseband signal data from the 1024 data buffer via the AXI bus for digital signal processing.

[0085] S210: The instruction count comparator is used to compare the current instruction count with the total number of instructions to be executed in real time. If they are equal, the current 64-bit instruction parsing module stops working; otherwise, steps S25 to S210 continue to be executed.

[0086] In summary, this application provides a timing synchronization system for low-Earth orbit (LEO) satellite baseband, assisting the digital signal processor on the LEO satellite communication side in tasks such as real-time signal reception and transmission processing, time synchronization maintenance, and hardware timing configuration. It also supports synchronization with navigation timing pulses, enabling rapid completion of system time synchronization processing. Furthermore, the digital signal processor only needs to operate during specific bursts of time, significantly reducing the receiver system's data processing bandwidth requirements, thereby improving the real-time performance of signal processing and enhancing the performance of the digital signal processor.

[0087] This application also provides a computer device, including a memory and a processor. The memory stores a computer program, and the processor executes the computer program to implement the low-orbit satellite baseband timing synchronization method described in the above embodiments.

[0088] This application also provides a machine-readable storage medium on which a program or instruction is stored. When the program or instruction is executed by a processor, it implements the low-orbit satellite baseband timing synchronization method described in the above embodiments.

[0089] Those skilled in the art will understand that embodiments of this application can be provided as methods, systems, or computer program products. Therefore, this application can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, this application can take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0090] This application is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of this application. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in one or more flowchart illustrations and / or one or more block diagrams.

[0091] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means that implement the functions specified in one or more flowcharts and / or one or more block diagrams.

[0092] These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer-implemented process, such that the instructions, which execute on the computer or other programmable apparatus, provide steps for implementing the functions specified in one or more flowcharts and / or one or more block diagrams.

[0093] In a typical configuration, a computing device includes one or more processors (CPU), input / output interfaces, network interfaces, and memory.

[0094] Memory may include non-persistent memory in computer-readable media, such as random access memory (RAM) and / or non-volatile memory, such as read-only memory (ROM) or flash RAM. Memory is an example of computer-readable media.

[0095] Computer-readable media includes both permanent and non-permanent, removable and non-removable media that can store information using any method or technology. Information can be computer-readable instructions, data structures, modules of programs, or other data. Examples of computer storage media include, but are not limited to, phase-change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technologies, CD-ROM, digital versatile optical disc (DVD) or other optical storage, magnetic tape, magnetic disk storage or other magnetic storage devices, or any other non-transferable medium that can be used to store information accessible by a computing device. As defined herein, computer-readable media does not include transient computer-readable media, such as modulated data signals and carrier waves.

[0096] It should also be noted that the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0097] The above are merely embodiments of this application and are not intended to limit the scope of this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of the claims of this application.

Claims

1. A timing synchronization system for a low-Earth orbit satellite baseband, characterized in that, The timing synchronization system communicates with both the digital signal processor (DSP) and the baseband processing unit. The system includes: a timer configured to receive timing configuration data sent by the DSP and start counting according to the timing configuration data to synchronize with the DSP's time; an instruction cache module configured to receive and sequentially store a set of timing instructions sent by the DSP, the set including signal receiving instructions, signal sending instructions, and hardware configuration instructions; and an instruction parsing and execution module connected to the instruction cache module and the timer, configured to read the pending timing instructions and the timer's timing data from the instruction cache module, parse the instruction execution time of the pending timing instructions, and execute the pending timing instructions on time according to the timing data, thereby completing the data interaction between the DSP and the baseband processing unit.

2. The timing synchronization system according to claim 1, characterized in that, The timing synchronization system further includes a data caching module configured to receive and store the interaction data between the digital signal processor and the baseband processing unit, wherein the interaction data includes signal data to be transmitted, signal data to be received, hardware configuration data to be transmitted, and hardware status data to be received.

3. The timing synchronization system according to claim 2, characterized in that, The instruction parsing and execution module includes: an instruction queue parsing unit, connected to the instruction cache module, configured to read the timed instruction to be executed from the instruction cache module according to the first-in-first-out principle, and parse out the instruction execution time and instruction parameters of the timed instruction to be executed; a time comparison unit, connected to the instruction queue parsing unit and the timer respectively, configured to receive the instruction execution time output by the instruction queue parsing unit and the current time output by the timer, compare the instruction execution time and the current time, and output a trigger instruction output pulse if the instruction execution time and the current time are the same; an instruction output unit, connected to the instruction queue parsing unit and the time comparison unit respectively, configured to receive the instruction parameters output by the instruction queue parsing unit and the trigger instruction output pulse output by the time comparison unit, and combine the instruction parameters and the trigger instruction output pulse to generate an execution instruction; and an instruction execution unit, connected to the instruction output unit, configured to receive the execution instruction output by the instruction output unit and execute the corresponding operation.

4. The timing synchronization system according to claim 3, characterized in that, The timing instruction set includes signal receiving instructions and signal sending instructions; the instruction execution unit is also connected to the data buffer module and the baseband processing unit, and the instruction execution unit is further configured to: when the timing instruction to be executed is the signal receiving instruction, move signal data from the baseband processing unit to the data buffer module; when the timing instruction to be executed is the signal sending instruction, move signal data from the data buffer module to the baseband processing unit; when the timing instruction to be executed is the hardware configuration instruction, move the corresponding hardware configuration data from the data buffer module to the baseband processing unit.

5. The timing synchronization system according to claim 3, characterized in that, The instruction queue parsing unit is further configured to: after the scheduled instruction to be executed is triggered, continue to retrieve the next instruction to be executed from the instruction cache module and parse it.

6. The timing synchronization system according to claim 1, characterized in that, The timer includes a timer snapshot unit, which is configured to: maintain timing counting when the timing synchronization system is in low-power mode; and output a snapshot value after the timing synchronization system exits the low-power mode, so that the timer can restore time synchronization according to the snapshot value.

7. The timing synchronization system according to claim 1, characterized in that, The timer is also configured to: receive a navigation timing synchronization pulse output by a navigation receiver; detect the pulse edge of the navigation timing synchronization pulse; and, if the pulse edge is detected, calibrate the counting deviation of the timer according to the pulse edge so that the timer time is synchronized with the time of the Global Navigation Satellite System.

8. A timing synchronization method for a low-Earth orbit satellite baseband, characterized in that, A timing synchronization system for a low-Earth orbit satellite baseband according to any one of claims 1 to 7, the timing synchronization system communicating with a digital signal processor, the timing synchronization system including a timer and an instruction cache module, the timer being time-synchronized with the digital signal processor, the method comprising: acquiring a timing instruction set sent by the digital signal processor and storing the timing instruction set in the instruction cache module; reading a timing instruction to be executed from the instruction cache module according to a first-in-first-out principle; parsing the instruction execution time of the timing instruction to be executed; acquiring the current time of the timer; and executing the timing instruction to be executed if the instruction execution time is the same as the current time.

9. A computer device comprising a memory and a processor, wherein the memory stores a computer program, characterized in that, When the processor executes the computer program, it implements the timing synchronization method for low-orbit satellite baseband as described in claim 8.

10. A machine-readable storage medium on which a program or instructions are stored, characterized in that, When the program or the instructions are executed by the processor, the timing synchronization method for low-orbit satellite baseband according to claim 8 is implemented.

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