Junction-free transistor with planar core-shell structure

Abstract

The invention provides a junction-free transistor with a planar core-shell structure, which comprises a substrate, a core layer, a shell layer, a source-drain region, a grid electrode and a first side wall, the substrate, the core layer, the shell layer and the source-drain region are sequentially stacked along the stacking direction, the grid electrode and the first side wall are arranged on the same layer, the first side wall is arranged between the grid electrode and the source-drain region, and the first dielectric constant of the first side wall is greater than 7.5. In the stacking direction, the projection area of the shell layer in the plane where the substrate is located at least covers the projection areas of the grid electrode and the side wall in the plane where the substrate is located. By arranging the first side wall with a relatively high dielectric constant, the trend that the threshold voltage drops along with the shortening of the channel length can be slowed down, the roll-off of the threshold voltage can be inhibited, and the first side wall with the relatively high dielectric constant can also enhance the control capability of the grid electrode on the channel, improve the switching characteristic and inhibit the subthreshold swing degradation. And the modulation of the leakage voltage on the threshold voltage can be effectively suppressed, the leakage induced barrier lowering effect is weakened, and the suppression effect on the short channel effect is realized.

Description

Technical Field

[0001] This application relates to the field of transistors, and in particular to a planar core-shell junctionless transistor. Background Technology

[0002] The core-shell junctionless transistor (CS-JL) is fabricated by creating an ultrathin undoped shell layer above a heavily doped core layer. It achieves normally-off operation, high charge density, excellent mobility, and extremely high drive current, while eliminating the three major defects of traditional junctionless field-effect transistors (JL FETs): low mobility, negative threshold voltage, and random dopant fluctuations (RDF).

[0003] However, as device dimensions continue to shrink to the deep submicron level, short-channel effects (SCE) have become a key bottleneck restricting the performance of CS-JL transistors. That is, the gate's electrostatic control capability over the channel weakens as the channel length shortens, which can easily lead to problems such as threshold voltage roll-off (Vt roll-off), drain-induced barrier reduction (DIBL), and subthreshold swing (SS) degradation, resulting in increased off-state leakage current and deterioration of switching characteristics.

[0004] Therefore, how to improve the short-channel effect of CS-JL transistors has become an urgent technical problem to be solved. Summary of the Invention

[0005] In view of this, the purpose of this application is to provide a planar core-shell junctionless transistor that suppresses short-channel effects by suppressing threshold voltage roll-off, suppressing subthreshold swing degradation, and reducing drain-induced barrier reduction. The specific solution is as follows:

[0006] On one hand, this application provides a planar core-shell junctionless transistor, comprising:

[0007] A substrate, a core layer, a shell layer, and source / drain regions are stacked sequentially along the stacking direction, wherein the doping concentration of the core layer is greater than a preset doping concentration;

[0008] A gate and a first sidewall are located on the side of the shell away from the core layer. The gate and the first sidewall are disposed on the same layer. The first sidewall is located between the gate and the source / drain region. The first dielectric constant of the first sidewall is greater than 7.5 and less than or equal to 20. In the stacking direction, the projection area of ​​the shell in the plane of the substrate at least covers the projection areas of the gate and the first sidewall in the plane of the substrate.

[0009] In one possible implementation, the planar core-shell junctionless transistor further includes:

[0010] A second sidewall is disposed on the same layer as the first sidewall, the first sidewall is located between the second sidewall and the gate, and the second dielectric constant of the second sidewall is less than the first dielectric constant of the first sidewall.

[0011] In one possible implementation, the second dielectric constant of the second sidewall is greater than or equal to 3.9 and less than or equal to 7.5.

[0012] In one possible implementation, the first dielectric constant of the first sidewall is greater than or equal to 10 and less than or equal to 20.

[0013] In one possible implementation, in the direction from the first sidewall to the gate, the sum of the first thickness of the first sidewall and the second thickness of the second sidewall is greater than or equal to 6 nm and less than or equal to 10 nm.

[0014] In one possible implementation, the planar core-shell junctionless transistor further includes:

[0015] The dielectric constants of the first sidewall, the second sidewall, and the third sidewall, which are disposed on the same layer as the first sidewall, decrease sequentially in the direction from the gate to the third sidewall.

[0016] In one possible implementation, in the direction from the first sidewall to the gate, the first thickness of the first sidewall is greater than or equal to 6 nm and less than or equal to 10 nm.

[0017] In one possible implementation, the material of the first sidewall is hafnium dioxide.

[0018] In one possible implementation, the planar core-shell junctionless transistor further includes:

[0019] The buried oxide layer is located between the substrate and the core layer;

[0020] The gate oxide layer located between the gate and the shell layer;

[0021] In the stacking direction, the projection area of ​​the shell layer in the plane of the substrate covers the projection areas of the gate and the first sidewall in the plane of the substrate, as well as the projection area of ​​the source / drain region in the plane of the substrate.

[0022] In one possible implementation, the shell is an undoped film.

[0023] This application provides a planar core-shell junctionless transistor, including a substrate, a core layer, a shell layer, and source / drain regions stacked sequentially along a stacking direction. The doping concentration of the core layer is greater than a preset doping concentration. A gate and a first sidewall are located on the side of the shell layer away from the core layer, and the gate and the first sidewall are disposed on the same layer. The first sidewall is located between the gate and the source / drain regions. The first dielectric constant of the first sidewall is greater than 7.5 and less than or equal to 20. In the stacking direction, the projection area of ​​the shell layer in the plane of the substrate at least covers the projection areas of the gate and the sidewall in the plane of the substrate. By setting a first sidewall with a high dielectric constant, this application can regulate the edge electric field distribution, which can slow down the trend of threshold voltage decreasing with channel length shortening, suppress threshold voltage roll-off, and enhance the gate's control capability over the channel, improve switching characteristics, and suppress subthreshold swing degradation. It can also effectively suppress the modulation of threshold voltage by drain voltage and weaken the drain-induced barrier reduction effect. In summary, this application achieves the suppression of short-channel effects by suppressing threshold voltage roll-off, suppressing subthreshold swing degradation, and reducing leakage-induced barrier reduction effects. Attached Figure Description

[0024] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0025] Figure 1 This illustration shows a cross-sectional schematic diagram of a planar core-shell junctionless transistor according to an embodiment of this application;

[0026] Figure 2 This paper shows a graph illustrating the relationship between drain current and gate voltage for CS-JL transistors with different channel lengths and first sidewalls of different dielectric constants, according to an embodiment of this application.

[0027] Figure 3 This illustration shows a schematic diagram of the effect of a first sidewall with different dielectric constants on a short channel of a device, according to an embodiment of this application.

[0028] Figure 4A cross-sectional view of a CS-JL transistor with inner and outer walls provided in an embodiment of this application is shown;

[0029] Figure 5 This paper shows the SS variation diagram under different combinations of inner and outer walls with different dielectric constants, as provided in an embodiment of this application.

[0030] Figure 6 This paper shows a DIBL variation diagram under different combinations of inner and outer walls with different dielectric constants, as provided in an embodiment of this application.

[0031] Figure 7 This paper shows a diagram illustrating the switching characteristics of different combinations of inner and outer walls with varying dielectric constants, as provided in an embodiment of this application.

[0032] Figure 8 This paper shows the on-state and off-state current variations under different combinations of inner and outer walls with different dielectric constants, as provided in an embodiment of this application.

[0033] Figure 9 The diagram illustrates the variation of the maximum gate capacitance under different combinations of inner and outer walls with different dielectric constants, as provided in an embodiment of this application. Detailed Implementation

[0034] To make the above-mentioned objectives, features and advantages of this application more apparent and understandable, the specific embodiments of this application will be described in detail below with reference to the accompanying drawings.

[0035] Many specific details are set forth in the following description in order to provide a full understanding of this application. However, this application may also be implemented in other ways different from those described herein. Those skilled in the art can make similar extensions without departing from the spirit of this application. Therefore, this application is not limited to the specific embodiments disclosed below.

[0036] Secondly, this application provides a detailed description in conjunction with schematic diagrams. When detailing the embodiments of this application, for ease of explanation, the cross-sectional views illustrating the device structure may be partially enlarged, not adhering to the usual scale. Furthermore, the schematic diagrams are merely examples and should not limit the scope of protection of this application. In addition, actual fabrication should include three-dimensional spatial dimensions of length, width, and depth.

[0037] As described in the background section, junctionless transistors have become a research hotspot in the field of low-power devices in recent years due to their simple manufacturing process, low thermal budget, high potential for three-dimensional integration, and ability to effectively suppress short-channel effects. Their core principle is to achieve carrier depletion and conduction by controlling the source-drain-channel regions with the same type of doping through the gate potential. This eliminates the traditional PN junction fabrication steps, simplifies the process flow, and makes them particularly suitable for the integration of extremely small-sized devices. They also exhibit advantages in multi-threshold voltage regulation and low noise, making them highly promising for low-power applications and analog circuits.

[0038] To further optimize junctionless transistor performance, planar core-shell junctionless transistors (CS-JL) have been proposed. However, as device dimensions continue to shrink to the deep submicron level, short-channel effects (SCE) have become a key bottleneck restricting the performance of CS-JL transistors. Existing SCE suppression schemes mostly focus on channel engineering (such as ultra-thin body design) or gate engineering (such as high-k dielectric / metal gate), but the optimization of the gate spacer, a crucial structure, has not received sufficient attention.

[0039] The inventors discovered that the gate sidewalls, located on both sides of the gate, not only define the source and drain regions but also directly influence the gate's ability to control the edge electric field of the channel through spatial isolation and dielectric properties, making them an important potential control node for suppressing SCE (Self-Cut Effect). However, current gate sidewall designs for CS-JL transistors still use conventional materials (such as single SiO2 or Si3N4) found in traditional planar transistors and employ a uniform relative permittivity. The dielectric constant of the material With a thickness of approximately 3.9 (SiO2) or 7.5 (Si3N4), this sidewall design defaults to the electric field distribution model of traditional planar transistors, failing to consider the influence of the gate edge electric field on the core layer extending to both ends of the device in the core-shell structure. It only achieves basic process isolation functions through conventional sidewalls. It is difficult to adapt to the electric field distribution characteristics of the core-shell structure, resulting in limited suppression of surface-caused emissions (SCEs).

[0040] Specifically, sidewalls with a single dielectric constant result in insufficient control over the electric field at the gate edge, making it difficult to match the difference in electric field distribution between the Core layer (highly doped, strong electric field shielding) and the Shell layer (undoped, weak electric field response) in a core-shell structure. This leads to electric field concentration at the gate edge, causing "electric field penetration" in the near-source / drain region of the channel, exacerbating the DIBL effect and Vt rolloff. Furthermore, there is a lack of modulation of the longitudinal electric field in the channel. Conventional sidewalls only act in the horizontal direction (gate width direction), without considering the introduction of longitudinal (channel depth direction) electric field modulation through material or structural optimization. This fails to coordinate the longitudinal electric field distribution of the core-shell structure to suppress non-ideal carrier transport (such as hot carrier injection).

[0041] Based on the above technical problems, this application provides a planar core-shell junctionless transistor, including a substrate, a core layer, a shell layer, and source / drain regions stacked sequentially along the stacking direction. The doping concentration of the core layer is greater than a preset doping concentration. A gate and a first sidewall are located on the side of the shell layer away from the core layer, and the gate and the first sidewall are disposed on the same layer. The first sidewall is located between the gate and the source / drain regions. The first dielectric constant of the first sidewall is greater than 7.5 and less than or equal to 20. In the stacking direction, the projection area of ​​the shell layer in the plane of the substrate at least covers the projection areas of the gate and the sidewall in the plane of the substrate. By setting a first sidewall with a high dielectric constant, this application can regulate the edge electric field distribution, which can slow down the trend of threshold voltage decreasing with the shortening of the channel length, suppress threshold voltage roll-off, and enhance the gate's control capability over the channel, improve switching characteristics, and suppress subthreshold swing degradation. It can also effectively suppress the modulation of the threshold voltage by the drain voltage and weaken the drain-induced barrier reduction effect. In summary, this application achieves the suppression of short-channel effects by suppressing threshold voltage roll-off, suppressing subthreshold swing degradation, and reducing leakage-induced barrier reduction effects.

[0042] For ease of understanding, the following detailed description, in conjunction with the accompanying drawings, provides an embodiment of a planar core-shell junctionless transistor provided in this application.

[0043] refer to Figure 1 The diagram shown is a cross-sectional schematic of a planar core-shell junctionless transistor provided in an embodiment of this application. The planar core-shell junctionless transistor may include a substrate 101, a core layer 103, a shell layer 104, a source-drain region 108, a gate 106, and a first sidewall 107.

[0044] The substrate 101, core layer 103, shell layer 104, and source / drain regions 108 are stacked sequentially along the stacking direction, which refers to the stacking direction of the film layers, for example, vertically upward. The doping concentration of the core layer 103 is greater than the preset doping concentration, that is, the core layer 103 is usually a heavily doped film layer.

[0045] The gate 106 and the first sidewall 107 are located on the side of the shell 104 away from the core layer 103, and the gate 106 and the first sidewall 107 are disposed on the same layer. The first sidewall 107 is located between the gate 106 and the source / drain region 108.

[0046] In the stacking direction, the projection area of ​​the shell 103 in the plane of the substrate 101 at least covers the projection areas of the gate 106 and the first sidewall 107 in the plane of the substrate 101. That is, the shell 103 includes at least the portion located directly below the gate 106 and the first sidewall 107. At this time, due to the influence of the first sidewall 107, the gate 106 has a weaker control over the shell 103 directly below the first sidewall 107, which affects charge transport.

[0047] Based on this, this application sets the first dielectric constant of the first sidewall 107 to be greater than 7.5 and less than or equal to 20. Compared with the current setting of the first dielectric constant of the first sidewall 107 being less than 7.5, this application sets a higher first dielectric constant to enhance the control capability of the gate 106 over the shell 103 directly below the first sidewall 107.

[0048] In principle, according to the electric field boundary conditions, the electric displacement at the gate-sidewall-channel interface must be continuous, i.e., εox*Eox = εsp*Esp. When the sidewall dielectric constant εsp increases, the electric field Esp within the sidewall will decrease accordingly to maintain this equation, thereby sharing more of the voltage drop and reducing the channel edge electric field Eedge. In other words, increasing the sidewall dielectric constant can adjust the lateral electric field distribution, suppress the edge concentration phenomenon caused by uneven electric field distribution at the core-shell interface, extend the electric field more uniformly to the shell layer, reduce the edge electric field spikes caused by the electric field shielding effect of the core layer, and thus effectively alleviate DIBL and Vt roll-off.

[0049] The following simulation results will be used to illustrate this in detail.

[0050] refer to Figure 2 The figure shown is a graph illustrating the relationship between drain current and gate voltage for CS-JL transistors with different channel lengths and first sidewalls of different dielectric constants, according to an embodiment of this application. Figure 2 (a) in the diagram corresponds to a long-channel CS-JL transistor with a channel length (Lgate, Lg) of 200 nm. Figure 2 (b) in the diagram corresponds to a short-channel CS-JL transistor with a channel length of 20 nm. It can be seen that, with... Increasing the value from 1 to 20 increases the on-state current (drain current) for both long-channel and short-channel devices. Furthermore, for short-channel devices, the off-state current increases with... The decrease in leakage current as the value increases indicates that the leakage current of short-channel devices has been improved.

[0051] refer to Figure 3 The diagram shown illustrates the effect of a first sidewall with different dielectric constants on a short channel of a device, according to an embodiment of this application. Figure 3 Figure (a) shows a schematic diagram illustrating the variation of the threshold voltage Vt of the Core layer with the channel length Lg. Under conditions of 1 F / m (approximately vacuum), as Lg shortens, Vt decreases significantly, exhibiting typical SCE (Self-Cyclic Emission Cycle). When the dielectric constant is increased to different values ​​such as 20, 15, and 7.5, the plateau value and roll-off amplitude show differences, indicating that increasing the dielectric constant can slow down the trend of the threshold voltage decreasing as the channel shortens, significantly alleviate Vt roll-off, and thus suppress SCE.

[0052] Figure 3 Figure (b) shows the curve of SS as a function of Lg, under the same conditions. Under these conditions, SS deviates significantly from the ideal value (60mV / dec) in short-channel conditions, and The smaller the value, the more severe the deterioration of SS; when When boosted to 20, even with a short channel at 20nm, SS can remain at a level close to 75mV / dec, far lower than low. The values ​​at that time reflect that the sidewalls with high dielectric constants can enhance the gate's control over the channel and improve switching characteristics.

[0053] Figure 3 (c) shows the curve of DIBL as a function of Lg in short-channel applications. It decreases and then increases sharply, for example, at Lg=20nm. =1F / m corresponds to a DIBL close to 100mV / V, while When the voltage is 20, it can drop to below about 30mV / V, indicating that the high dielectric constant sidewall can effectively suppress the modulation of the threshold voltage by the leakage voltage and weaken the leakage-induced barrier reduction effect.

[0054] In other words, increasing the relative permittivity of the gate sidewall can not only significantly alleviate Vt roll-off, but also improve SS and DIBL indicators, thereby maintaining good device performance under short-channel conditions and achieving SCE suppression.

[0055] In summary, this application, by setting a first sidewall with a high dielectric constant, regulates the edge electric field distribution, thereby mitigating the decreasing trend of threshold voltage as channel length shortens and suppressing threshold voltage roll-off. The high dielectric constant of the first sidewall also enhances the gate's control over the channel, improves switching characteristics, and suppresses subthreshold swing degradation. Furthermore, it effectively suppresses the modulation of threshold voltage by drain voltage, reducing the drain-induced barrier reduction effect. In conclusion, this application achieves suppression of short-channel effects by suppressing threshold voltage roll-off, suppressing subthreshold swing degradation, and reducing the drain-induced barrier reduction effect.

[0056] In one possible implementation, the planar core-shell junctionless transistor may further include a buried oxide layer 102 located between the substrate 101 and the core layer 103; a gate oxide layer 105 located between the gate 106 and the shell layer 104; and in the stacking direction, the projection area of ​​the shell layer 104 in the plane of the substrate 101 covers the projection areas of the gate 106 and the first sidewall 107 in the plane of the substrate 101, as well as the projection area of ​​the source / drain region 108 in the plane of the substrate 101.

[0057] In other words, reference Figure 1 As shown, a buried oxide layer 102 can be disposed between the substrate 101 and the core layer 103, and a gate oxide layer 105 can be disposed between the shell layer 104 and the gate 106. The shell layer 104 can completely cover the surface of the core layer 103, thereby realizing the complete fabrication of a junctionless transistor with a planar core-shell structure.

[0058] In one possible implementation, the shell 104 is an undoped film layer. Of course, it can also be a lightly doped film layer, and this application does not limit it in this regard.

[0059] In one possible implementation, the first thickness of the first sidewall 107 in the direction pointing to the gate can be greater than or equal to 6 nm and less than or equal to 10 nm, thereby avoiding quantum tunneling caused by the sidewall thickness being too thin, and also avoiding unnecessary waste of sidewall material caused by the sidewall thickness being too thick.

[0060] In one possible implementation, the material of the first sidewall 107 is hafnium dioxide, but it can also be other high-k dielectric materials, as long as the dielectric constant is within the required range. By using hafnium dioxide as the sidewall, the device manufacturing cost can be reduced and unnecessary process steps can be avoided.

[0061] In order to ensure the suppression of short-channel effects while avoiding the introduction of excessive parasitic losses due to high gate capacitance, in one possible implementation, the planar core-shell junctionless transistor may further include a second sidewall 109 disposed on the same layer as the first sidewall 107, the first sidewall 107 being located between the second sidewall 109 and the gate, and the second dielectric constant of the second sidewall 109 being less than the first dielectric constant of the first sidewall 107.

[0062] In other words, this application can provide multiple sidewalls, with the sidewall located in the inner layer, i.e., near the gate, denoted as the first sidewall 107. The first dielectric constant of the first sidewall 107 can also be denoted as... The sidewall located on the outer layer, i.e., near the source / drain region, is designated as the second sidewall 109. The second dielectric constant of the second sidewall 109 can be denoted as: By differentiating the dielectric constants of the inner and outer sidewalls, with the inner sidewall having a higher first dielectric constant and the outer sidewall having a relatively lower second dielectric constant, the device performance can be improved while suppressing SCE.

[0063] In principle, the gate electrostatic control capability is reflected in the modulation efficiency of the gate voltage on the channel potential, and the channel edge electric field Eedge is the main path for the formation of DIBL. This application employs gradient dielectric constant sidewalls, meaning the dielectric constants of the inner and outer sidewalls satisfy... > According to the electric field boundary conditions *Ein = *Eout*, the higher dielectric constant of the inner sidewalls reduces Ein, thus compressing the electric field lines to converge laterally towards the gate, making the electric field more perpendicular to the channel. This is equivalent to increasing the effective control area of ​​the gate, thereby reducing the short-channel effect. Quantitatively, the channel edge potential φedge is modulated by both the gate voltage Vg and the drain voltage Vd, approximately as φedge ≈ [Cox / (Cox+Csp)]Vg + [Csp / (Cox+Csp)]Vd, where Csp ∝ εsp / tsp. Increasing the sidewall dielectric constant εsp increases Csp, making φedge more easily modulated by Vg and reducing Vd coupling, thereby enhancing gate control and suppressing the short-channel effect. Therefore, using a high dielectric constant on the inner sidewalls and a suitable dielectric constant on the outer sidewalls can optimize the edge electric field distribution, converting part of the lateral electric field into longitudinal modulation, and improving the gate's electrostatic control capability.

[0064] As an example, refer to Figure 4 The figure shown is a cross-sectional view of a CS-JL transistor with inner and outer side walls provided in an embodiment of this application, showing a second side wall 109 located on the outer side and a first side wall 107 located on the inner side.

[0065] Next, based on the simulation results below, the device performance of the double-sided wall CS-JL transistor will be characterized and explained.

[0066] refer to Figure 5 The figure shows the SS variation diagram under different inner and outer wall combinations with different dielectric constants according to an embodiment of this application. From the subthreshold characteristic analysis, when the first dielectric constant... When fixed, as As the amplitude increases, SSlin (subthreshold swing in the linear region) exhibits a pattern of first improving and then stabilizing within a certain range: for different (1, 5, 10, 15, 20), in As the concentration increases, SSlin generally approaches or stabilizes at a lower value (approximately 85 mV / dec), especially When the values ​​are large (e.g., 15, 20), SSlin is in most cases The lower part remains at a better level, indicating that the inner side is high. With suitable dielectric constant on the outside This combination can significantly improve the gate's switching control over the channel, making the subthreshold characteristics closer to the ideal value.

[0067] refer to Figure 6 The figure shown is a DIBL variation diagram under different inner and outer wall combinations with different dielectric constants provided in an embodiment of this application. It can be found that under the same... Down, The higher the value (e.g., 15, 20), the more significant the DIBL suppression effect, reducing DIBL from approximately 130 mV / V in conventional structures to 85 mV / V or even lower. This also indicates that proper combination of [various technologies] can significantly improve DIBL suppression. and This can significantly enhance the device's immunity to SCE.

[0068] refer to Figure 7 The figure shown is a switching characteristic variation diagram under different inner and outer wall combinations with different dielectric constants according to an embodiment of this application. The on-state current is Ion, the off-state current is Ioff, and the Ion / Ioff ratio varies with... Changes for different The distribution characteristics exhibiting approximately horizontal patterns indicate that in the selected... Within this range, the on / off ratio can be stably maintained at a high level (approximately 1E+6 to 1E+7), especially When the value is large, it can maintain a low Ioff even at a high Ion, achieving excellent switching performance and energy efficiency.

[0069] refer to Figure 8 The figure shows the on-state and off-state current variations under different inner and outer wall combinations with varying dielectric constants, as provided in an embodiment of this application. As Ion increases, Ioff shows an upward trend, but the variations differ... The corresponding curve distribution shows that the inner side is higher. It can maintain a low Ioff even at a high Ion, thereby reducing static power consumption while ensuring driving capability.

[0070] A higher dielectric constant leads to a higher gate capacitance, therefore, gate capacitance analysis is necessary. (Reference) Figure 9 The figure shows the variation of the maximum gate capacitance under different combinations of inner and outer walls with different dielectric constants according to an embodiment of this application. The maximum gate capacitance Cggmax varies with... The overall trend is upward, but different The corresponding increase differs from the absolute value. (Inner high) (e.g., 20) in combination with the outer middle While obtaining sufficient gate control capability, Cggmax can be controlled within a reasonable range to avoid excessive parasitic losses due to excessive capacitance, thereby maintaining good performance in high-frequency applications.

[0071] In one possible implementation, the second dielectric constant of the second sidewall 109 can be greater than or equal to 3.9 and less than or equal to 7.5. This avoids the second dielectric constant being too small, which would prevent effective suppression of SCE, and also avoids the second dielectric constant being too large, which would result in a large gate capacitance, introduce too much parasitic loss, and reduce device quality.

[0072] In one possible implementation, the first dielectric constant of the first sidewall 107 can be greater than or equal to 10 and less than or equal to 20, thereby enabling the inner sidewall to have a higher dielectric constant and ensuring the suppression effect on SCE.

[0073] In one possible implementation, in the direction of the first sidewall 107 pointing towards the gate, the sum of the first thickness of the first sidewall 107 and the second thickness of the second sidewall 109 is greater than or equal to 6 nm and less than or equal to 10 nm, for example, it can be 8 nm, thereby avoiding quantum tunneling caused by the sidewall thickness being too thin, and also avoiding unnecessary waste of sidewall material caused by the sidewall thickness being too thick.

[0074] To further enhance the structural richness of the device design, in one possible implementation, the planar core-shell junctionless transistor may also include a third sidewall disposed on the same layer as the first sidewall 107, wherein the dielectric constants of the first sidewall 107, the second sidewall 109, and the third sidewall decrease sequentially from the gate to the third sidewall.

[0075] In other words, the gate sidewalls can be configured not only with two layers, but also with three or four layers. From the inside out, the dielectric constant of each sidewall gradually decreases, so that the higher dielectric constant on the inside can suppress SCE, and the lower dielectric constant on the outside can avoid introducing a large gate capacitance. Through the mutual cooperation of the dielectric constants of more sidewalls, the device performance can be further improved.

[0076] In summary, the gate sidewall optimized structure of this application significantly enhances the gate's ability to control the edge electric field of the channel by changing the relative permittivity of the sidewalls and the differentiated design of the inner and outer sides, effectively suppressing SCE (such as DIBL, Vt roll-off, SS degradation). At the same time, the synergistic design of the high dielectric constant on the inner side and the suitable dielectric constant on the outer side improves the device's on-state current and switching characteristics (significantly improving the Ion / Ioff ratio) while suppressing SCE. Furthermore, the dielectric material used is compatible with existing CMOS processes, requiring no additional equipment and facilitating large-scale application.

[0077] The terms “first,” “second,” “third,” “fourth,” etc. (if present) in the specification and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this application described herein can be implemented, for example, in orders other than those illustrated or described herein. Furthermore, the terms “comprising” and “having,” and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0078] The various embodiments in this specification are described in a progressive manner. Similar or identical parts between embodiments can be referred to mutually. Each embodiment focuses on its differences from other embodiments. In particular, the apparatus embodiments are basically similar to the method embodiments, so the description is relatively simple; relevant parts can be referred to the descriptions of the method embodiments.

[0079] The above description is merely a preferred embodiment of this application. Although this application has disclosed preferred embodiments above, it is not intended to limit this application. Any person skilled in the art can make many possible variations and modifications to the technical solutions of this application using the methods and techniques disclosed above, or modify them into equivalent embodiments with equivalent changes, without departing from the scope of the technical solutions of this application. Therefore, any simple modifications, equivalent changes, and modifications made to the above embodiments based on the technical essence of this application without departing from the content of the technical solutions of this application shall still fall within the protection scope of the technical solutions of this application.

Claims

1. A planar core-shell junctionless transistor, characterized in that, include: A substrate, a core layer, a shell layer, and source / drain regions are stacked sequentially along the stacking direction, wherein the doping concentration of the core layer is greater than a preset doping concentration; A gate and a first sidewall are located on the side of the shell away from the core layer. The gate and the first sidewall are disposed on the same layer. The first sidewall is located between the gate and the source / drain region. The first dielectric constant of the first sidewall is greater than 7.5 and less than or equal to 20. In the stacking direction, the projection area of ​​the shell in the plane of the substrate at least covers the projection areas of the gate and the first sidewall in the plane of the substrate.

2. The planar core-shell junctionless transistor according to claim 1, characterized in that, The planar core-shell junctionless transistor also includes: A second sidewall is disposed on the same layer as the first sidewall, the first sidewall is located between the second sidewall and the gate, and the second dielectric constant of the second sidewall is less than the first dielectric constant of the first sidewall.

3. The planar core-shell junctionless transistor according to claim 2, characterized in that, The second dielectric constant of the second sidewall is greater than or equal to 3.9 and less than or equal to 7.

5.

4. The planar core-shell junctionless transistor according to claim 3, characterized in that, The first dielectric constant of the first sidewall is greater than or equal to 10 and less than or equal to 20.

5. The planar core-shell junctionless transistor according to claim 2, characterized in that, In the direction from the first sidewall to the gate, the sum of the first thickness of the first sidewall and the second thickness of the second sidewall is greater than or equal to 6 nm and less than or equal to 10 nm.

6. The planar core-shell junctionless transistor according to claim 2, characterized in that, The planar core-shell junctionless transistor also includes: The dielectric constants of the first sidewall, the second sidewall, and the third sidewall, which are disposed on the same layer as the first sidewall, decrease sequentially in the direction from the gate to the third sidewall.

7. The planar core-shell junctionless transistor according to claim 1, characterized in that, In the direction from the first sidewall to the gate, the first thickness of the first sidewall is greater than or equal to 6 nm and less than or equal to 10 nm.

8. The planar core-shell junctionless transistor according to claim 1, characterized in that, The material of the first sidewall is hafnium dioxide.

9. The planar core-shell junctionless transistor according to claim 1, characterized in that, The planar core-shell junctionless transistor also includes: The buried oxide layer is located between the substrate and the core layer; The gate oxide layer located between the gate and the shell layer; In the stacking direction, the projection area of ​​the shell layer in the plane of the substrate covers the projection areas of the gate and the first sidewall in the plane of the substrate, as well as the projection area of ​​the source / drain region in the plane of the substrate.

10. The planar core-shell junctionless transistor according to claim 9, characterized in that, The shell layer is an undoped film layer.

Images