GCT chip with overvoltage short circuit breakdown structure
By introducing an overvoltage short-circuit breakdown region at the center of the GCT chip, the problem of mezzanine terminal failure under blocking conditions is solved, achieving reliable rated voltage protection and stable blocking characteristics.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- ZHUZHOU CRRC TIMES SEMICON CO LTD
- Filing Date
- 2024-10-21
- Publication Date
- 2026-05-01
AI Technical Summary
When the existing GCT chip is in a blocked state, the platform terminal is prone to failure, resulting in instability in the blocked state.
An overvoltage short-circuit breakdown region is introduced at the center of the GCT chip, including an N+ short-circuit isolation region and a high-injection-efficiency N0′ buffer layer, forming a J12 junction to regulate the breakdown voltage and ensure that the avalanche leakage location forms a high-density current channel at the center of the chip, thus achieving a reliable short circuit.
When blocking avalanche, the chip forms a current path in the central breakdown region to ensure reliable rated voltage protection and avoid mesa terminal failure, while not affecting the chip's on-state and off-state characteristics.
Smart Images
Figure CN121968664A_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of semiconductor technology, specifically relating to a GCT chip with an overvoltage short-circuit breakdown structure. Background Technology
[0002] The main vertical structure of existing asymmetric GCT chips consists of four PNPN layers, such as... Figure 1 As shown. Based on the degree of doping, it can be further subdivided into P... + 、N′、N - P, P + N + Six layers, corresponding to the P+ transparent emitting anode region, N′ buffer layer, and N... - base region, P base region, P + short base region and N + Emitter region (also known as cathode comb). There are 3 PN junctions inside the device, which are J1 junction (anode transparent junction), J2 junction (blocking voltage main junction) and J3 junction (gate cathode junction) from anode to cathode. The cathode and gate are connected by a trench to form a step.
[0003] Viewed horizontally, a GCT chip consists of numerous radially arranged "strip cathodes," commonly referred to as cathode combs. These cathode combs are evenly distributed within a wafer, using sector arcs or circles. Depending on the GCT's turn-off current, the gate leads are located at the center of the wafer (center gate), or at the center or periphery (intermediate ring gate or edge ring gate). At the outermost edge of the chip, a mesa design is used, and passivation materials are applied to protect the terminal surface, ensuring the chip's blocking capability.
[0004] When the GCT chip is in a blocking state, a reverse bias voltage (or short circuit) of less than -20V must first be applied to the gate-cathode junction to prevent a significant reduction in the device's breakdown voltage due to the forward bias injection effect of the J3 junction. Applying a forward bias voltage VDC between the anode and cathode puts the device in a forward blocking state, where the blocking voltage is primarily borne by the reverse-biased J2 junction. At this point, the maximum electric field within the chip is distributed at the mesa terminal. When the applied voltage exceeds the chip's withstand capability, an avalanche phenomenon will occur at this location, potentially leading to blocking failure. Furthermore, since the dynamic avalanche occurs at the terminal in the blocking state, most blocking failures occur at the mesa terminal, potentially causing the device to fail in a blocking state. Summary of the Invention
[0005] The technical problem to be solved by the present invention is to provide a GCT chip with an overvoltage short-circuit breakdown structure, which solves the problem that the existing GCT blocking state is in a blocking state when the platform terminal fails.
[0006] This invention provides a GCT chip with an overvoltage short-circuit breakdown structure, comprising: an anode, a P, and a P-type anode arranged sequentially. + Transparent emitting anode region, N′ buffer layer, N - base region, P base region, P + base region, N + Emitting region and cathode; The chip has an overvoltage short-circuit breakdown region at its center, and the overvoltage short-circuit breakdown region is located at N. - Between the base region and the anode, the overvoltage short-circuit breakdown region includes: N + Short circuit isolation zone, part of P + Transparent emitting anode region and located in N + The N0′ buffer layer inside the short-circuit isolation zone has a higher injection efficiency than the N′ buffer layer, and the P + An anode J is formed between the transparent emitting anode region and the N0′ buffer layer to regulate the breakdown voltage of the overvoltage short-circuit breakdown region. 12 Knot.
[0007] Optionally, the planar shape of the N+ short-circuit isolation region is annular or polygonal.
[0008] Optionally, the distance between the outer side of the overvoltage short-circuit breakdown region and the chip center does not exceed 10mm, and the lateral width of the NO' buffer layer does not exceed 2mm. + The distance between the outer side of the short-circuit isolation area and the center of the chip should not exceed 8mm.
[0009] Optionally, the doping concentration of the N′ buffer layer is 1E15~1E17 cm⁻¹. -3 The diffusion depth is 20μm~60μm.
[0010] Optionally, the doping concentration of the NO′ buffer layer is 5E13~1E15 cm⁻¹. -3 The diffusion depth is 20μm~50μm, and the diffusion depth of the N0′ buffer layer is lower than that of the N′ buffer layer.
[0011] Optionally, the N + The doping concentration of the short-circuit isolation region is 1E19~1E21cm. -3 The diffusion depth is 20μm~60μm.
[0012] Optionally, the P + The doping concentration of the transparent emitting anode region is 1E17~1E19 cm⁻¹ -3 The diffusion depth is 0.2μm~5μm.
[0013] Optionally, the doping concentration of the P-based region is 1E14~2E16 cm⁻¹. -3The junction depth is 50μm~200μm.
[0014] Optionally, the P + The base region doping concentration is 1E15~1E18 cm⁻¹ -3 The diffusion depth is 40μm~100μm.
[0015] Optionally, the N + The doping concentration of the emitter region is 1E19~1E21 cm⁻¹ -3 The diffusion depth is 5μm~40μm.
[0016] The beneficial effects of this invention are that by introducing an overvoltage short-circuit breakdown region at the center of the GCT chip, the location of avalanche leakage during overvoltage blocking is adjusted to the center of the chip. When the GCT chip exceeds the rated blocking voltage, a high-density current channel is formed at the center of the chip, and this leakage occurs first in the BD breakdown region. This ensures that when the GCT blocks avalanche, it will fail at the center of the chip, resulting in a reliable short circuit. This allows the chip to form a current channel in the BD breakdown region during avalanche blocking, leading to breakdown and short circuit at that location through electric field avalanche thermal failure. In application, this achieves reliable rated voltage protection, thus solving the problem of existing GCTs remaining in a blocking state when the mesa terminal fails. Simultaneously, this BD breakdown region does not occupy the effective usable area of the chip, therefore it does not reduce the chip's on-state, off-state, and blocking characteristics. Attached Figure Description
[0017] Figure 1 This is a schematic cross-sectional view of the GCT chip provided by the present invention. Figure 2 This is a graph showing the effect of the lateral width R1 of the N0′ buffer layer of the GCT chip of the present invention on the CP-GCT transition voltage. Figure 3 This is a diagram showing the electric field distribution at CP and GCT of the GCT chip of the present invention under a 4500V blocking state.
[0018] In the diagram: 10, anode, 20, P + Transparent emitting anode region; 30, N′ buffer layer; 40, N - Base region; 50, P base region; 60, P + Base region; 70, N + Emitter region; 80, cathode; 90, gate; 100, N + Short-circuit isolation zone; 110, N0′ buffer layer; 120, J1 junction; 130, J2 junction; 140, J3 junction; 150, J 12 Knot; 160, N + Short circuit ring. Detailed Implementation
[0019] like Figure 1 As shown, the present invention provides a GCT chip with an overvoltage short-circuit breakdown structure, comprising: an anode 10 and a P10 arranged sequentially. + Transparent emitting anode region 20, N′ buffer layer 30, N - Base region 40, P base region 50, P + Base region 60, N + Emitter 70 and cathode 80; an overvoltage short-circuit breakdown region is provided at the center of the chip, and the overvoltage short-circuit breakdown region is located at N. - The overvoltage short-circuit breakdown region between base region 40 and anode 10 includes: N + Short circuit isolation zone 100, part of P + Transparent emitting anode region 20 and located in N + The N0′ buffer layer 110 inside the short-circuit isolation region 100 has a higher injection efficiency than the N′ buffer layer 30. + A J-shaped structure is formed between the transparent emitting anode region 20 and the NO′ buffer layer 110 to regulate the breakdown voltage of the overvoltage short-circuit breakdown region. 12 150.
[0020] Compared to existing technologies, the GCT chip provided by this invention introduces an overvoltage short-circuit breakdown (BD) region at the center of the GCT chip. This adjusts the location of avalanche leakage during overvoltage blocking to the chip center. When the rated blocking voltage is exceeded, a high-density current channel forms at the center of the chip, and "blocking breakdown" first occurs in the BD breakdown region. This ensures that when the GCT fails to block overvoltage, it will be in a reliable short-circuit state at the chip center. This allows the chip to form a current channel in the BD breakdown region during avalanche blocking, leading to breakdown and short circuit at that location through electric field avalanche thermal failure. In application, this achieves reliable rated voltage protection, thus solving the problem of existing GCTs being in a blocking state when the mesa terminal fails. Furthermore, this BD breakdown region does not occupy the effective usable area of the chip, therefore it does not reduce the chip's on-state, off-state, and blocking characteristics.
[0021] It should be noted that the "platform terminal" refers to the voltage-resistant structure at the edge of the chip.
[0022] The GCT chip of this invention also contains three PN junctions, which are J1 junction 120 (anode transparent junction), J2 junction 130 (blocking voltage main junction), and J3 junction 140 (gate cathode junction) from the anode 10 to the cathode 80. Among them, the J1 junction 120 is located in the P... + Transparent emitting anode with N′ buffer layer 30 or N - Between base regions 40, junction J1 120 is used to adjust the on-state and off-state performance of the device, and junction J2 130 exists in N.- Between base region 40 and P base region 50, J3 junction 140 exists in N. + Launch Zone 70 and P + Between base region 60.
[0023] The N of the GCT chip of this invention + The short-circuit isolation region 100 has a planar shape that is either circular or polygonal, with the polygonal shape being preferably a regular polygonal shape.
[0024] The distance R between the outer side of the overvoltage short-circuit breakdown region and the center of the chip shall not exceed 10 mm; the lateral width R1 of the N0′ buffer layer 110 shall not exceed 2 mm, depending on the avalanche breakover voltage V. BOD Under the same structural design conditions, within a certain range, the avalanche breakover voltage typically decreases as R1 increases; N + The distance R2 between the outer side of the short-circuit isolation region 100 and the center of the chip should not exceed 8mm. The design width depends on the design of the BD breakdown voltage. R = R1 + ΔR2 (ring width). R1 is usually related to the blocking design and its value is optimized based on experimental results.
[0025] It should be noted that, such as N + The short-circuit isolation zone 100 has a planar shape of a regular polygon, where R refers to the distance from the center point to a vertex of the regular polygon. Therefore, the design of a circular R is also applicable to the design of a regular polygonal ring structure, and thus it is not specifically mentioned in the text.
[0026] The doping concentration of the N′ buffer layer 30 in the GCT chip of this invention is 1E15~1E17 cm⁻¹ -3 The diffusion depth is 20μm~60μm, and the diffusion depth X jN The value ranges from 20μm to 60μm, depending on the trade-off design between the chip's blocking, on-state, and off-state characteristics.
[0027] The doping concentration of the NO′ buffer layer 110 in the GCT chip of this invention is 5E13~1E15 cm⁻¹ -3 The diffusion depth is 20μm~50μm, and the diffusion depth of the N0′ buffer layer 110 is lower than that of the N′ buffer layer 30.
[0028] The N of the GCT chip of this invention + The doping concentration of the short-circuit isolation region 100 is 1E19~1E21cm. -3 The diffusion depth is 20μm~60μm, and the specific parameters depend on the trade-off design between the chip's blocking, on-state, and off-state characteristics. + The short-circuit isolation region 100 has a high doping concentration and can interact with N. + Launch area 70, N +The short-circuit ring 160 structure is formed simultaneously, while avoiding P without selective diffusion. + The transparent emitting anode region 20 is inverted, thus simplifying the manufacturing process. The junction depth design is the same as the N′ buffer layer 30, depending on the BD breakdown voltage design. For N... + A short-circuit isolation region 100 structure is inserted between two buffer layer structures with different injection efficiencies, and N + There must be no P-type anode structure above the short-circuit isolation region 100 to prevent the carrier amplification effect generated by the PNP transistor formed by the parallel high-doped / low-doped buffer layers, thereby avoiding affecting the static and dynamic performance of the non-BD region of the GCT chip.
[0029] The N of the GCT of this invention - The doping concentration and width of base region 40 depend on the chip blocking voltage level.
[0030] The P of the GCT chip of this invention + The doping concentration of the transparent emitting anode region 20 is 1E17~1E19 cm⁻¹ -3 The diffusion depth is 0.2μm~5μm.
[0031] The doping concentration of the P-base region 50 in the GCT chip of this invention is 1E14~2E16 cm⁻¹ -3 The junction depth is 50μm~200μm, and the specific parameters are designed according to the chip blocking voltage.
[0032] The P of the GCT chip of this invention + The doping concentration of the base region 60 is 1E15~1E18 cm⁻¹ -3 The diffusion depth is 40μm~100μm, and the specific parameters depend on the trade-off design between the device's turn-off characteristics and trigger characteristics.
[0033] The N of the GCT chip of this invention + The doping concentration of emitter region 70 is 1E19~1E21 cm⁻¹ -3 The diffusion depth is 5μm~40μm.
[0034] The present invention GCT chip P + The top of the base region 60 is connected to a gate 90 metal layer, and the gate 90 has a groove depth of 0μm~40μm, i.e., N. + The top surface of launch area 70 and P + The height difference of the top surface of the base region 60 is optimized by compromise based on the device's triggering characteristics, shutdown characteristics and GK characteristics.
[0035] The N of the GCT chip of this invention + Short-circuit isolation region 100 cannot have a P-type doped layer designed on its surface. +The short-circuit isolation region 100 must be a PN diode structure. If the surface is P-type doped, it is a PNP transistor (which has the function of amplifying current), which will amplify the leakage current in the overvoltage leakage region, thereby reducing the blocking capability of the device.
[0036] The P of the overvoltage short-circuit breakdown region of this invention + The structural design of the transparent emitting anode region 20, including its surface doping concentration and diffusion depth, depends on the design of the BD breakdown voltage.
[0037] like Figure 2 As shown, in the overvoltage short-circuit breakdown region of the GCT chip of this invention, R2=2mm, R=<2+R1>mm, and R1 are 0.4mm, 2.0mm, and 1.2mm respectively. Experimental results on the influence of these values on the CP-GCT turnaround voltage are presented. Figure 3 As shown, in the overvoltage short-circuit breakdown region of the GCT chip of the present invention, R1=2mm, R2=2mm, R=<2+R1>mm, the electric field distribution at the CP point and the GCT point (non-CP point) under a 4500V blocking state is illustrated. This demonstrates that the problem of existing GCTs remaining in a blocking state when the platform terminal fails is solved.
[0038] Those skilled in the art should understand that the discussion of any of the above embodiments is merely exemplary and is not intended to imply that the scope of protection of this application is limited to these examples; within the framework of this application, the technical features of the above embodiments or different embodiments can also be combined, the steps can be implemented in any order, and there are many other variations of different aspects of one or more embodiments of this application as described above, which are not provided in detail for the sake of brevity.
[0039] One or more embodiments in this application are intended to cover all such substitutions, modifications, and variations that fall within the broad scope of this application. Therefore, any omissions, modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of one or more embodiments in this application should be included within the protection scope of this application.
Claims
1. A GCT chip with an overvoltage short-circuit breakdown structure, characterized in that, include: The anode (10) and P are set in sequence. + Transparent emitting anode region (20), N′ buffer layer (30), N - Base region (40), P base region (50), P + Base region (60), N + Emitting region (70) and cathode (80); The chip has an overvoltage short-circuit breakdown region at its center, and the overvoltage short-circuit breakdown region is located at N. - Between the base region (40) and the anode (10), the overvoltage short-circuit breakdown region includes: N + Short-circuit isolation zone (100), part of P + Transparent emitting anode region (20) and located in N + The N0′ buffer layer (110) inside the short-circuit isolation region (100) has a higher injection efficiency than the N′ buffer layer (30). + A J-shaped buffer layer is formed between the transparent emitting anode region (20) and the NO′ buffer layer (110) to regulate the breakdown voltage of the overvoltage short-circuit breakdown region. 12 Knot (150).
2. The GCT chip according to claim 1, characterized in that, The N+ short-circuit isolation region (100) has a planar shape that is either circular or polygonal.
3. The GCT chip according to claim 2, characterized in that, The distance between the outer side of the overvoltage short-circuit breakdown region and the center of the chip does not exceed 10mm, and the lateral width of the NO′ buffer layer (110) does not exceed 2mm. + The distance between the outer side of the short-circuit isolation region (100) and the center of the chip does not exceed 8mm.
4. The GCT chip according to claim 1, characterized in that, The doping concentration of the N′ buffer layer (30) is 1E15~1E17 cm⁻¹ -3 The diffusion depth is 20μm~60μm.
5. The GCT chip according to claim 4, characterized in that, The doping concentration of the NO′ buffer layer (110) is 5E13~1E15 cm⁻¹. -3 The diffusion depth is 20μm~50μm, and the diffusion depth of the N0′ buffer layer (110) is lower than that of the N′ buffer layer (30).
6. The GCT chip according to any one of claims 1-5, characterized in that, The N + The doping concentration of the short-circuit isolation region (100) is 1E19~1E21cm. -3 The diffusion depth is 20μm~60μm.
7. The GCT chip according to any one of claims 1-5, characterized in that, The P + The doping concentration of the transparent emitting anode region (20) is 1E17~1E19 cm⁻¹ -3 The diffusion depth is 0.2μm~5μm.
8. The GCT chip according to any one of claims 1-5, characterized in that, The doping concentration of the P-based region (50) is 1E14~2E16 cm⁻¹ -3 The junction depth is 50μm~200μm.
9. The GCT chip according to any one of claims 1-5, characterized in that, The P + The doping concentration of the base region (60) is 1E15~1E18 cm⁻¹ -3 The diffusion depth is 40μm~100μm.
10. The GCT chip according to any one of claims 1-5, characterized in that, The N + The doping concentration of the emitter region is 1E19~1E21 cm⁻¹ -3 The diffusion depth is 5μm~40μm.