Ring gate nanosheet field effect transistor and preparation method

Abstract

The invention discloses a ring gate nanosheet field effect transistor (100) and a preparation method. The nanosheet field effect transistor (100) comprises a substrate (10) and a semiconductor bulge (11) arranged on the surface of the substrate (10), the insulating layers (12) are formed on the two sides of the semiconductor protrusions (11) and cover the surface of the substrate (10), and the height of the surfaces of the insulating layers (12) is smaller than that of the semiconductor protrusions (11); the plurality of nanosheets (13) are formed above the semiconductor bumps (11) at intervals; by adopting the structure of the nanosheet field effect transistor (100), the leakage current of the nanosheet field effect transistor (100) can be reduced, and the switching speed of the nanosheet field effect transistor (100) can be improved.

Description

Ring-gate nanosheet field-effect transistor and its fabrication method

[0001] This application is a divisional application. The original application has the application number 202080103377.3 and the original application date is October 22, 2020. The entire contents of the original application are incorporated herein by reference. Technical Field

[0002] This application relates to the field of semiconductor device technology, and in particular to the structure and fabrication method of a gate-ring nanosheet field-effect transistor. Background Technology

[0003] As electronic devices evolve towards lower power consumption and higher operating speeds, the requirements for field-effect transistors (FETs), the cornerstone of electronic devices, are becoming increasingly stringent. FETs are gradually transitioning from planar FETs to three-dimensional FETs. Among them, three-dimensional FETs, such as FinFETs (Fin Field-Effect Transistors) and Gate-All-Around Nanosheet (GAA-NS) FETs, employ multi-gate structures to improve gate control capabilities and suppress short-channel effects.

[0004] Typically, during the deposition of gate material to form the gate in a gate-to-ring (GNR) nanosheet field-effect transistor (FET), a portion of the gate material is deposited directly onto the silicon substrate. This results in the formation of a parasitic channel between the gate material and the silicon substrate. This parasitic channel becomes a current leakage path, resulting in a high leakage current when the GNR is in the off state, thus affecting its performance. In conventional techniques, to reduce the leakage current of the parasitic channel, a reverse bias voltage is usually applied to the silicon substrate during the use of the GNR, which increases the complexity of the GNR's operation. Therefore, how to reduce the leakage current of the GNR while minimizing its operational complexity, thereby improving its switching speed, becomes a problem that needs to be solved. Summary of the Invention

[0005] The gate-ring nanosheet field-effect transistor and its fabrication method provided in this application can reduce the leakage current of the gate-ring nanosheet field-effect transistor while reducing the complexity of its use, thereby improving the switching speed of the gate-ring nanosheet field-effect transistor.

[0006] To achieve the above objectives, this application adopts the following technical solution: In a first aspect, embodiments of this application provide a gate-ring nanosheet field-effect transistor, which includes: a substrate; a semiconductor bump disposed on the surface of the substrate; an insulating layer formed on both sides of the semiconductor bump and covering the surface of the substrate, wherein the height of the surface of the insulating layer is less than the height of the semiconductor bump; and a plurality of nanosheets formed above the semiconductor bump.

[0007] In this embodiment, by setting the height of the insulating layer surface to be less than the height of the semiconductor bump, both sides of the semiconductor bump are exposed. This allows both the surface of the semiconductor bump and the exposed sides to contact the gate material, forming a three-sided gate ring structure. This improves gate control capability, rapidly removing charge carriers from the parasitic channel when the transistor is turned off, reducing leakage current in the gate ring nanosheet field-effect transistor, and thus improving its performance.

[0008] Based on the first aspect, in one possible implementation, the gate-ring nanosheet field-effect transistor further includes a gate material that encapsulates the plurality of nanosheets, fills the gaps between the plurality of nanosheets, and fills the gaps between the plurality of nanosheets and the semiconductor bump.

[0009] Based on the first aspect, in one possible implementation, the gate material covers a portion of the semiconductor protrusion that is above the surface of the insulating layer.

[0010] Based on the first aspect, in one possible implementation, the difference between the height of the semiconductor bump and the height of the surface of the insulating layer is less than or equal to the thickness of one of the plurality of nanosheets.

[0011] By setting the difference between the height of the semiconductor bump and the height of the surface of the insulating layer to be less than or equal to the thickness of one of the nanosheets, the portion of the semiconductor bump above the surface of the insulating layer can be equivalent to a nanosheet that is in contact with the gate material on three sides, which is beneficial to improving the performance of the gate-around nanosheet field-effect transistor.

[0012] Based on the first aspect, in one possible implementation, each of the plurality of nanosheets extends along a first direction and penetrates the source region, drain region, and channel region of the gate-around nanosheet field-effect transistor; and along the first direction, each of the plurality of nanosheets includes a first portion located in the source region, a second portion located in the drain region, and a third portion located in the channel region; wherein, along the height direction of the semiconductor bump, the thickness of the third portion is less than the thickness of the first portion, and the thickness of the third portion is less than the thickness of the second portion.

[0013] By setting the thickness of the third part of the nanosheet to be less than the thickness of the first part or less than the thickness of the second part, the distance between each pair of nanosheets in the channel region can be increased, thereby allowing more gate material to be filled between each pair of nanosheets. This is beneficial for further improving the gate control capability and thus increasing the switching speed of the gate-around nanosheet field-effect transistor.

[0014] Based on the first aspect, in one possible implementation, the thickness of the third portion of each of the plurality of nanosheets ranges from 4 nm to 7 nm.

[0015] Based on the first aspect, in one possible implementation, the semiconductor bumps include a plurality of semiconductor bumps, which are sequentially spaced apart along the width direction of each of the plurality of nanosheets; and an insulating layer is disposed between every two semiconductor bumps.

[0016] Based on the first aspect, in one possible implementation, the spacing between every two nanosheets located in the channel region of the plurality of nanosheets ranges from 11 nm to 14 nm.

[0017] Based on the first aspect, in one possible implementation, the gate-around nanosheet field-effect transistor further includes a plurality of sidewall structures; a first sidewall structure of the plurality of sidewall structures is disposed between the source region and the channel region, and a second sidewall structure of the plurality of sidewall structures is disposed between the channel region and the drain region; each of the plurality of sidewall structures spans across the semiconductor bump and each of the plurality of nanosheets.

[0018] Based on the first aspect, in one possible implementation, the gate-ring nanosheet field-effect transistor further includes a plurality of semiconductor structures for forming a source and a drain; a first semiconductor structure of the plurality of semiconductor structures is formed in a first portion of the plurality of nanosheets; and a second semiconductor structure of the plurality of semiconductor structures is formed in a second portion of the plurality of nanosheets.

[0019] In a second aspect, embodiments of this application provide an electronic device comprising a gate-ring nanosheet field-effect transistor as described in the first aspect.

[0020] Specifically, electronic devices can be bare, unpackaged chips.

[0021] The electronic device can also be an electronic component, and the nanosheet field-effect transistor shown in the embodiments of this application can be encapsulated in a package. The package can include, but is not limited to, a plastic package, a metal package (e.g., a gold package, a nickel package), etc., with the source, drain, and gate of the nanosheet field-effect transistor led out on the outer surface of the package.

[0022] In addition, electronic devices can also be integrated circuit products (such as system-on-a-chip), wherein, in addition to the nanosheet field-effect transistors described in the embodiments of this application, the integrated circuit products may also include other integrated circuits, so that the nanosheet field-effect transistors shown in the embodiments of this application can cooperate with other integrated circuits to realize various circuit functions.

[0023] Thirdly, embodiments of this application provide a method for fabricating a nanosheet field-effect transistor. The method includes: providing a substrate and forming a semiconductor bump on the substrate; depositing a first insulating material on both sides of the semiconductor bump on the substrate to form an insulating layer, wherein the height of the surface of the insulating layer is less than the height of the semiconductor bump; and forming a plurality of nanosheets spaced apart above the semiconductor bump.

[0024] Based on the third aspect, in one possible implementation, forming a plurality of nanosheets on the semiconductor bump includes: sequentially and alternately depositing a first semiconductor material and a second semiconductor material on the semiconductor bump; and etching the first semiconductor material to form the plurality of nanosheets.

[0025] Based on the third aspect, in one possible implementation, the method further includes: depositing a second insulating material on the substrate, the semiconductor bump, and the nanosheet; etching the second insulating material to form a plurality of mutually separated sidewall structures, each of the plurality of sidewall structures spanning the semiconductor bump and the nanosheet to separate the nanosheet and the semiconductor bump into a plurality of portions.

[0026] Based on the third aspect, in one possible implementation, the plurality of sidewall structures includes two oppositely arranged sidewall structures; and the method further includes: etching a nanosheet located between the two oppositely arranged sidewall structures such that the thickness of the nanosheet located between the two oppositely arranged sidewall structures is less than the thickness of the nanosheet located at both ends of the two oppositely arranged sidewall structures.

[0027] Based on the third aspect, in one possible implementation, the method further includes: depositing a gate material between the two opposing sidewall structures to form a gate structure; wherein the gate material encapsulates the plurality of nanosheets, fills the gaps between the plurality of nanosheets, and fills the gaps between the plurality of nanosheets and the semiconductor bump.

[0028] Based on the third aspect, in one possible implementation, the gate material covers a portion of the semiconductor protrusion that is above the surface of the insulating layer. Attached Figure Description

[0029] To more clearly illustrate the technical solutions of the embodiments of this application, the drawings used in the description of the embodiments of this application will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0030] Figure 1 is a schematic diagram of the structure of the gate ring nanosheet field-effect transistor provided in the embodiment of this application.

[0031] Figure 2 is a schematic diagram of the structure of a ring-gate nanosheet field-effect transistor provided in the present application, as shown in Figure 1, in which only semiconductor protrusions are provided on the substrate.

[0032] Figure 3 is a cross-sectional view along AA' of the gate ring nanosheet field-effect transistor shown in Figure 1 provided in an embodiment of this application.

[0033] Figure 4 is a schematic diagram of the structure of the nanosheets exposed in the channel region provided in the embodiment of this application.

[0034] Figure 5 is a cross-sectional view of a gate-around nanosheet field-effect transistor in a conventional technology.

[0035] Figure 6 is a cross-sectional view along CC' of the gate ring nanosheet field-effect transistor shown in Figure 1 provided in an embodiment of this application.

[0036] Figure 7 is a schematic diagram of the semiconductor structure grown in the gate ring nanosheet field-effect transistor provided in the embodiments of this application.

[0037] Figure 8 is a schematic diagram of the overall structure of the gate ring nanosheet field-effect transistor provided in the embodiment of this application.

[0038] Figure 9 is another structural schematic diagram of the gate ring nanosheet field-effect transistor provided in the embodiments of this application.

[0039] Figure 10 is a schematic diagram of the structure of a ring-gate nanosheet field-effect transistor provided in the present application, as shown in Figure 9, in which only semiconductor protrusions are provided on the substrate.

[0040] Figure 11 is a flowchart of the fabrication method of the ring gate nanosheet field-effect transistor as shown in Figure 8, provided in an embodiment of this application.

[0041] Figures 12A to 12H are schematic diagrams of various structures in the fabrication process of the ring-gate nanosheet field-effect transistor, as shown in Figure 8. Detailed Implementation

[0042] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0043] The terms "first," "second," and similar terms used in this article do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Similarly, "one" or similar terms do not indicate a quantity limitation, but rather indicate the existence of at least one.

[0044] In the embodiments of this application, the terms "exemplary" or "for example" are used to indicate examples, illustrations, or descriptions. Any embodiment or design described as "exemplary" or "for example" in the embodiments of this application should not be construed as being more preferred or advantageous than other embodiments or design solutions. Specifically, the use of terms such as "exemplary" or "for example" is intended to present the relevant concepts in a specific manner. In the description of the embodiments of this application, unless otherwise stated, "multiple" means two or more. For example, multiple nanosheets refer to two or more nanosheets.

[0045] Please refer to Figure 1, which shows a schematic diagram of the structure of a gate-around nanosheet field-effect transistor provided in an embodiment of this application. In Figure 1, the gate-around nanosheet field-effect transistor 100 includes a substrate 10, semiconductor bumps 11, an insulating layer 12, and a plurality of nanosheets 13 stacked together.

[0046] The substrate 10 and the semiconductor bump 11 can be formed of the same semiconductor material. The semiconductor materials typically used for the substrate 10 and the semiconductor bump 11 may include, but are not limited to: silicon (Si), gallium nitride (GaN), gallium arsenide (GaAs), aluminum nitride (AlN), silicon carbide (SiC), indium phosphide (InP), zinc selenide (ZnSe), or other group VI, group III-V, or group II-VI semiconductor materials.

[0047] A semiconductor bump 11 is disposed on the substrate 10, extending along the first direction X, i.e., the length direction of the semiconductor bump, and penetrating the source region A1, channel region A2, and drain region A3 of the gate-around nanosheet field-effect transistor 100. The source region A1 and drain region A3 can be regions on the substrate 10 where a semiconductor structure 16, as shown in FIG. 8, is formed. This semiconductor structure 16 contains dopants to form the source or drain, respectively. Furthermore, contact metal 19, as shown in FIG. 8, is typically formed within the source region A1 and drain region A3, and this contact metal 19 is used to lead out the source or drain. The materials and shapes of the semiconductor structure 16 and contact metal 19 can be referred to in the specific description below. The channel region A2 is located between the source region A1 and drain region A3 and can be a region where gate material is deposited to form the gate structure 15. Along the third direction Z, as shown in FIG. 1, i.e., the height direction of the semiconductor bump 11, the semiconductor bump 11 protrudes from the side closer to the substrate 10 to the side farther from the substrate 10. Along the second direction Y, that is, the width direction of the semiconductor bump 11, the semiconductor bump 11 divides the upper surface of the substrate 10 into multiple parts. These multiple parts include not only the portion where the semiconductor bump 11 is located, but also multiple non-communicating portions located on both sides of the semiconductor bump 11. Figure 2 schematically illustrates the structure when only the semiconductor bump 11 is provided on the substrate 10. In Figure 2, the upper surface of the substrate 10 is divided into the portion where the semiconductor bump 11 is located, and portions 101 and 102 located on both sides of the semiconductor bump 11. In the specific process, the semiconductor bump 11 is formed by etching the substrate 10.

[0048] In this embodiment, the insulating layer 12 is deposited on the upper surface of the substrate 10, on the portion where the semiconductor bump 11 is not formed, i.e., on portions 101 and 102 of the substrate 10 as shown in FIG. 2. The material of the insulating layer 12 includes, but is not limited to, silicon oxide, sapphire, or any combination thereof. The thickness h2 of the insulating layer 12 along the third direction Z is less than the height h1 of the semiconductor bump 11 protruding outward from the substrate 10. That is, along the third direction Z, the surface 111 of the semiconductor bump 11 on the side away from the substrate 10, as shown in FIG. 1, is higher than the surface 121 of the insulating layer 12 on the side away from the substrate 10, as shown in FIG. 3. FIG. 3 is a cross-sectional view of the gate-ring nanosheet field-effect transistor 100 taken along AA' shown in FIG. 1.

[0049] The gate-ring nanosheet field-effect transistor 100 shown in Figure 1 further includes a plurality of stacked, non-contacting nanosheets 13. The nanosheets 13 are disposed on the side of the semiconductor bump 11 away from the substrate 10 and do not contact either the semiconductor bump 11 or the substrate 10. The material of each nanosheet 13 can be the same as the material forming the substrate 10 and the material forming the semiconductor bump 11. Each nanosheet 13 extends along a first direction X and penetrates the source region A1, the channel region A2, and the drain region A3, as shown in Figure 4, which schematically shows a structural diagram of the channel region A2 before the gate structure is provided, exposing the nanosheets 13. Each nanosheet 13 can have the same size. The orthogonal projection of the nanosheet 13 onto the semiconductor bump 11 falls within the area covered by the surface 111 of the semiconductor bump 11, or the orthogonal projection of the nanosheet 13 onto the semiconductor bump 11 coincides with the surface 111 of the semiconductor bump 11.

[0050] In specific process practice, before the gate material is deposited in the channel region A2, there are gaps between every two nanosheets 13 and between the nanosheet 13 closest to the semiconductor bump 11, as shown in Figure 4. After the gate material is deposited in the channel region, the gaps between every two nanosheets 13 and between the nanosheet 13 and the semiconductor bump 11 are filled with gate material, as shown in Figure 3. Before the gaps are formed, a semiconductor structure is formed between every two nanosheets 13 and between the nanosheet 13 closest to the substrate 10 and the semiconductor bump 11. The material used for this semiconductor structure is different from the semiconductor material used to form the nanosheets 13. For example, the semiconductor material used to form the nanosheets 13 is silicon, while the material used to form the semiconductor structure is germanium-silicon. After the semiconductor structure is etched, the surface 111 of the semiconductor bump 11 is usually exposed. When the gate material is deposited in the channel region A2 shown in Figure 4, in addition to filling the gaps between every two nanosheets 13, some of the gate material is deposited on the surface 111 of the semiconductor bump 11. In this way, a parasitic channel is formed at the point where the gate material contacts the semiconductor bump 11. In the structure of a conventional gate-to-gate nanosheet field-effect transistor, the surface of the semiconductor bump 11 away from the substrate 10 is flush with the upper surface of the insulating layer 12 away from the substrate 10, as shown in Figure 5, which is a cross-sectional view of a conventional gate-to-gate nanosheet field-effect transistor. This results in the deposited gate material contacting the semiconductor bump 11 only on one side in the structure of the conventional gate-to-gate nanosheet field-effect transistor, causing current leakage in the parasitic channel even when the transistor is turned off.

[0051] In this embodiment, by setting the surface of the insulating layer 12 to be less than the height of the upper surface of the semiconductor bump 11 protruding outward from the substrate 10, the two side portions of the semiconductor bump 11 are exposed. This allows both the surface 111 of the semiconductor bump 11 and the exposed side portions to contact the gate material, forming a three-sided gate ring structure. This improves gate control capability; when the transistor is turned off, carriers are rapidly removed from the parasitic channel, reducing the leakage current of the gate ring nanosheet field-effect transistor and thus improving its performance.

[0052] In one possible implementation, the difference between the height h1 of the semiconductor bump 11 protruding outward from the substrate 10 and the thickness h2 of the insulating layer 12 deposited on the substrate 10 is less than or equal to the thickness h3 of the nanosheet 13 along the third direction Z, as shown in Figure 3.

[0053] Please continue referring to Figure 1. In Figure 1, there is a certain spacing between each pair of nanosheets. This spacing is determined based on the type of device in which the gate-to-ring nanosheet field-effect transistor 100 is applied. Specifically, when the gate-to-ring nanosheet field-effect transistor 100 is applied to devices such as processor cores or SRAM, the spacing between each pair of nanosheets set in a conventional gate-to-ring nanosheet field-effect transistor 100 can be used. This spacing can be, for example, 11 nm, in which case the thickness of each nanosheet along the third direction Z can be 7 nm. When the gate-to-ring nanosheet field-effect transistor 100 is applied to devices such as I / O, higher switching speeds are usually required. In order to improve the gate's control over the charge carriers in the nanosheets, more gate material needs to be filled between each pair of nanosheets in the channel region. In this case, the distance between each pair of nanosheets in the channel region can be increased. For example, the distance between each pair of nanosheets in the channel region can be set to 14 nm. In specific process practice, in order to ensure the stress of the nanosheet 13 located in the source region A1 and the drain region A3 for the growth of the source semiconductor material and the drain semiconductor material, after the semiconductor material is epitaxially grown on the portion of the nanosheet 13 located in the source region A1 and the portion located in the drain region A2, the thickness of the nanosheet located in the channel region A2 along the third direction Z can be reduced to increase the distance between each two nanosheets in the channel region. For example, the thickness of the nanosheet located in the channel region A2 along the third direction Z can be reduced to 4 nm. Of course, the embodiments of this application are not limited to this and are determined according to the needs of the actual product. For example, the thickness of the nanosheet located in the channel region A2 along the third direction Z can also be reduced to 5 nm or 6 nm. In this case, the distance between each two nanosheets in the channel region A2 can be 13 nm or 12 nm. Specifically comparing Figure 2 and Figure 6, Figure 6 is a cross-sectional view of the ring-gate nanosheet field-effect transistor 100 taken along CC' shown in Figure 1. As can be seen from Figures 2 and 6, the thickness of the nanosheet located in the channel region A2 along the third direction Z is less than the thickness of the nanosheet located in the source region A1 and the drain region A2 along the third direction Z.

[0054] It should be noted that in actual products, such as the gate ring nanosheet field-effect transistor 100 shown in Figure 1, the nanosheet 13 has semiconductor structures forming the source and drain regions in the source region A1 and the drain region A3, respectively (semiconductor structure 16 shown in Figure 7). In order to better illustrate the semiconductor bump 11 and the nanosheet 13, the semiconductor structure grown on the nanosheet is not shown in Figure 1.

[0055] Furthermore, in Figure 1, the gate-around nanosheet field-effect transistor 100 also includes a plurality of sidewall structures 14. These sidewall structures 14 are disposed between the source region A1 and the channel region A2, and between the channel region A2 and the drain region A3. The sidewall structures 14 in the gate-around nanosheet field-effect transistor 100 are deposited on the aforementioned insulating layer 12, semiconductor bumps 11, and nanosheets 13, and the sidewall structures 14 span the semiconductor bumps 11 and nanosheets 13 along the second direction Y. As can be seen from Figure 1, in the third direction Z, the height of the sidewall structures 14 is greater than the stacked height of the nanosheets 13. The materials forming the sidewall structures 14 can include, but are not limited to, silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, or any combination thereof. Furthermore, the sidewall structures 14 can also be, for example, structures formed of multiple layers. For example, a silicon oxide layer may be present on the side closer to the channel region, and a silicon nitride layer may be present on the side farther from the channel region.

[0056] In this embodiment, the gate-ring nanosheet field-effect transistor 100 further includes a gate structure 15, which is formed in the channel region A2, as shown in FIG1. ​​The gate structure 15 encloses the portion of the nanosheet 13 located in the channel region. Here, "enclosed" means that each surface of the nanosheet extending along the first direction X is covered by the gate material. Thus, the gate-ring nanosheet field-effect transistor 100 forms a gate-ring structure. Specifically, the gate structure 15 may include a gate dielectric layer and a gate metal layer. The gate dielectric layer is deposited on the semiconductor bump 11, the insulating layer 12, and the nanosheet 13 in the channel region A2. The gate dielectric layer may be a high-k dielectric layer, and its specific materials may include, but are not limited to, lanthanum oxide (LaO), aluminum oxide (ALO), zirconium oxide (ZrO), titanium oxide (TiO), silicon oxide (SiO), etc. The gate metal layer is deposited on the gate dielectric layer, and the gate metal layer may include an N-gate metal layer forming an N-type field-effect transistor, or a P-gate metal layer forming a P-type field-effect transistor. The materials for the N-gate metal layer can include, but are not limited to: titanium (Ti), silver (Ag), aluminum (Al), titanium aluminum nitride (TiAlN), tantalum carbon nitride (TaCN), tantalum silicon nitride (TaSiN), manganese (Mn), etc.; the materials for the P-gate metal layer can include, but are not limited to: titanium nitride (TiN), tantalum nitride (TaN), ruthenium (Ru), molybdenum (Mo), aluminum (Al), tungsten nitride (WN), etc. The top surface of the gate metal layer is flush with the top surface of the sidewall structure 14, as shown in Figure 7.

[0057] In this embodiment, the source and drain electrodes can be formed by epitaxially growing semiconductor materials on nanosheets 13 located in the source region A1 and drain region A3. The semiconductor material can be, for example, a single-element semiconductor material such as germanium (Ge) or silicon (Si), a mixed semiconductor material of germanium and silicon, a compound semiconductor material such as gallium arsenide (GaAs) or aluminum gallium arsenide (AlGaAs), or a semiconductor alloy such as silicon-germanium (SiGe) or gallium arsenide phosphide (GaAsP). When epitaxially growing the semiconductor material, the source and drain electrodes can be formed by in-situ doping. For example, boron ions can be doped in-situ to form a P-type gate ring nanosheet field-effect transistor 100, or phosphorus ions or arsenic ions can be doped in-situ to form an N-type gate ring nanosheet field-effect transistor 100. The semiconductor structure 16 formed by epitaxially growing the semiconductor material on the nanosheets 13 located in the source region A1 and drain region A3 is shown in Figure 7.

[0058] The gate-around nanosheet field-effect transistor 100 also includes an insulating structure 17. The insulating structure 17 is deposited around the epitaxially grown semiconductor structure 16 to protect the semiconductor structure 16. The material used to form the insulating structure 17 may include, but is not limited to, silicon oxide, silicon nitride, and silicon oxynitride. Furthermore, the exposed outer surface of the gate structure 15 is also covered with an insulating material to form an insulating layer 18 to protect the gate structure 15. This insulating layer 18 may be the same insulating material used to form the insulating structure 17. Along the third direction Z, the bottom surface of the insulating structure 17 contacts the insulating layer 12, and its top surface is flush with the upper surface of the insulating layer 18, as shown in Figure 8.

[0059] Furthermore, the gate-around nanosheet field-effect transistor 100 also includes contact metal 19 and contact metal 20. Contact metal 19 is deposited on the epitaxially grown semiconductor structure 16 and is used to lead out the source and drain. As shown in FIG8, the bottom of contact metal 19 contacts the semiconductor structure 16 (e.g., wraps around the top surface of the semiconductor structure 16), and the top surface of contact metal 19 is flush with the insulating layer 18. Contact metal 20 contacts the gate structure 15 through a via provided in the insulating layer 18 to lead out the gate. The materials of contact metal 19 and contact metal 20 may include, but are not limited to, metallic copper, nickel, aluminum, or alloys formed by any combination thereof.

[0060] In the gate-to-ring nanosheet field-effect transistor 100 shown in Figures 1 to 8, a single semiconductor bump 11 is schematically illustrated. In other possible implementations of this application, multiple semiconductor bumps 11 may be provided. Please continue to refer to Figures 9-10, which show a structural schematic diagram of another embodiment of the gate-to-ring nanosheet field-effect transistor 100 provided in this application. As shown in Figures 9-10, two semiconductor bumps 11 are schematically illustrated. These two semiconductor bumps 11 are arranged sequentially at intervals along the second direction Y shown in Figure 9, that is, the width direction of the semiconductor bumps 11. These two semiconductor bumps 11 divide the upper surface of the substrate 10 into multiple portions, including portions 101, 102, and 103 located on both sides of the semiconductor bump 11 as shown in Figure 10. Figure 10 schematically shows a structural schematic diagram when only semiconductor bumps 11 are provided on the substrate 10. Similar to the gate-ring nanosheet field-effect transistor 100 shown in Figure 1, the portion of the upper surface of the substrate 10 shown in Figure 9 where the semiconductor bump 11 is not formed is deposited with an insulating layer 12. The thickness of the insulating layer 12 along the third direction Z is less than the height of the semiconductor bump 11 protruding outward from the substrate 10. Furthermore, the gate-ring nanosheet field-effect transistor 100 shown in Figure 9 also includes nanosheet groups 131 and 132. Each nanosheet group includes multiple nanosheets 13 stacked together. One group of stacked nanosheets 13 is disposed on one of the semiconductor bumps 11, and its orthographic projection onto the semiconductor bump 11 lies within the area covered by the upper surface of the semiconductor bump 11 or coincides with the upper surface of the semiconductor bump 11; another group of stacked nanosheets 13 is disposed on another semiconductor bump 11, and its orthographic projection onto the semiconductor bump 11 lies within the area covered by the upper surface of the semiconductor bump 11 or coincides with the upper surface of the semiconductor bump 11. Furthermore, the ring-gate nanosheet field-effect transistor 100 shown in Figure 9 may also include a semiconductor structure epitaxially grown on the nanosheet 13, with the semiconductor structures grown on the same side of the nanosheet 13 all connected together. The epitaxially grown semiconductor structure is not shown in Figure 9. Further, the ring-gate nanosheet field-effect transistor 100 shown in Figure 9 may also include a sidewall structure 14, an insulating structure 17, an insulating layer 18, a contact metal 19, and a contact metal 20, as shown in Figure 8, all of which are not shown in Figure 9. The relative positions of the structures and the materials used are specifically described in the relevant descriptions of the ring-gate nanosheet field-effect transistor 100 shown in Figures 1 to 8, and will not be repeated here.

[0061] This application also includes an electronic device comprising the gate-to-ring (GNR) nanosheet field-effect transistor (FET) described in the embodiments above. Specifically, the electronic device can be an unpackaged bare chip or an electronic component. The GNR nanosheet FET shown in this application can be packaged in a housing. This housing can include, but is not limited to, a plastic-encapsulated housing or a metal housing (e.g., a gold or nickel housing), with the source, drain, and gate of the GNR nanosheet FET exposed on the outer surface of the housing. Furthermore, the electronic device can also be an integrated circuit product (e.g., a system-on-a-chip). This integrated circuit product, in addition to including the GNR nanosheet FET described in this application, may also include other integrated circuits, thereby enabling the GNR nanosheet FET shown in this application to cooperate with other integrated circuits to achieve various circuit functions.

[0062] Based on the structures of the various gate-around nanosheet field-effect transistors described above, this application embodiment also provides a method for fabricating gate-around nanosheet field-effect transistors. The fabrication process of the gate-around nanosheet field-effect transistor is described in detail below, taking the structure of the fabricated gate-around nanosheet field-effect transistor as shown in Figure 8 as an example, and in conjunction with the process flow 1100 shown in Figure 11. This process flow 1100 includes the following steps: Step 1101, providing a substrate and forming semiconductor bumps 11 on the substrate.

[0063] The substrate can be a semiconductor material, which may include, but is not limited to: silicon (Si), gallium nitride (GaN), gallium arsenide (GaAs), aluminum nitride (AlN), silicon carbide (SiC), indium phosphide (InP), zinc selenide (ZnSe), or other group VI, group III-V, or group II-VI semiconductor materials.

[0064] In the specific process, a patterned mask layer can be formed on the substrate 10. Using this patterned mask layer as a mask, the substrate 10 is etched, and the unetched portion forms a semiconductor bump 11, as shown in Figure 2. Specifically, various etching methods such as dry etching or wet etching can be used to etch the substrate 10 to form the semiconductor bump 11.

[0065] Then, insulating material is deposited on the portion of the substrate 10 located on both sides of the semiconductor bump 11 to form an insulating layer 12, as shown in FIG12A.

[0066] Specifically, the thickness of the insulating material deposited on both sides of the semiconductor bump 11 along the third direction Z is less than the height of the semiconductor bump 11 protruding outward from the substrate 10. In one possible implementation, the height difference along the third direction Z between the surface of the semiconductor bump 11 away from the substrate 10 and the surface of the insulating material 12 away from the substrate 10 is less than or equal to the thickness of the nanosheet set in subsequent processes. In a specific implementation, the deposited insulating material can be etched back to achieve this height difference.

[0067] Step 1102: Sequentially deposit the first semiconductor material and the second semiconductor material on the semiconductor bump.

[0068] Through step 1102, a structure in which the semiconductor structure 21 and the nanosheet 13 are sequentially stacked can be formed, as shown in Figure 12B. The first semiconductor material and the second semiconductor material are different. In a specific implementation, the second semiconductor material has the same structure as the semiconductor bump 11. For example, the first semiconductor material can be germanium-silicon, and the second semiconductor material can be silicon.

[0069] Step 1103: Form a pseudo-gate structure and a sidewall structure on the semiconductor bump, the semiconductor structure, and the insulating layer.

[0070] Specifically, semiconductor materials such as polycrystalline silicon can be deposited in the middle of the semiconductor bump 11 and the stacked semiconductor structure 21 and nanosheet 13 to form a pseudo-gate structure 151. It should be noted that since the polycrystalline silicon material needs to be etched and a metal gate deposited later, the gate formed by the deposited polycrystalline silicon material is referred to as the pseudo-gate.

[0071] Then, a sidewall structure 14 is formed on the sidewall of the dummy gate structure 151. The material of the sidewall structure 14 can be, but is not limited to, silicon nitride, silicon carbide, silicon oxynitride, etc. The sidewall structure 14 can be formed by dielectric deposition and etching processes. The sidewall structure 14 can include two parts spanning the semiconductor bump 11 and the stacked semiconductor structure 21 and nanosheet 13, one part of which is used to block the source region A1 forming the source electrode and the dummy gate structure 151, and the other part is used to block the drain region A2 forming the drain electrode and the dummy gate structure 151. As shown in Figure 12C.

[0072] Step 1104: Growing a semiconductor structure on the exposed portions of the semiconductor bumps and nanosheets.

[0073] Specifically, after forming the dummy gate structure 151 and the sidewall structure 14, the exposed semiconductor structure 21 can be etched to create gaps between every two exposed nanosheets 13 for growing semiconductor material, as shown in FIG12D. Then, internal insulating material is disposed on the left and right sides of the semiconductor structure 21 and nanosheets 13 located within the portion enclosed by the sidewall structure 14 along the second direction Y. In practice, insulating material can be covered on each exposed portion except the substrate 10, allowing the insulating material to flow into the portion enclosed by the sidewall structure 14 through the gaps between every two nanosheets 13. The insulating material covering the nanosheets 13 is then etched, thereby forming an insulating material between the semiconductor structure 21 and nanosheets 13 enclosed by the sidewall structure 14.

[0074] Finally, semiconductor material is grown on the exposed semiconductor bumps 11 and nanosheets 13 to form a semiconductor structure 16. The formed semiconductor structure 16 is shown in Figure 12E. The semiconductor material can be, for example, a single-element semiconductor material such as germanium (Ge) or silicon (Si), a compound semiconductor material such as gallium arsenide (GaAs) or aluminum gallium arsenide (AlGaAs), or a semiconductor alloy such as silicon germanium (SiGe) or gallium arsenide phosphide (GaAsP).

[0075] In one possible implementation, the semiconductor material can be grown by in-situ doping and then annealed at high temperature to form a semiconductor structure 16.

[0076] In another possible implementation, a semiconductor material can be grown first in an undoped manner, and then ions can be implanted into the semiconductor material using an ion implantation method. After the semiconductor material is doped with ions, it is annealed at high temperature to form a semiconductor structure 16.

[0077] When the formed ring-gate nanosheet field-effect transistor device is P-type, the doped ions can be trivalent ions such as boron ions; when the formed ring-gate nanosheet field-effect transistor device is N-type, the doped ions can be pentavalent ions such as phosphorus ions.

[0078] Step 1105: Deposit insulating material in the source region and the drain region respectively to form an insulating structure.

[0079] Specifically, the insulating material can include, but is not limited to, materials such as silicon oxide or oxynitrides. The insulating material can be deposited using techniques such as chemical vapor deposition (CVD), physical vapor deposition (PVD), and atomic layer deposition (ALD).

[0080] Then, excess insulating material can be removed by a chemical mechanical polishing (CMP) process to form an insulating structure 17. This insulating structure 17 is flush with the side of the dummy gate structure 151 away from the substrate, as shown in Figure 12F.

[0081] Step 1106: Etch the pseudo-gate structure to expose the nanosheets and semiconductor structure located in the channel region.

[0082] A patterned mask layer is formed on the insulating structure 17 and the dummy gate structure 151. The dummy gate structure 151 shown in FIG12F is etched to expose the nanosheet 13 and the semiconductor structure 21 located in the channel region. In addition, after etching the dummy gate structure 151, the bottom insulating layer 12 is exposed.

[0083] Step 1107: Etch the semiconductor structure of the channel region to create gaps between the nanosheets.

[0084] Step 1108: Etch the exposed nanosheet structure to reduce the thickness of the nanosheet portion located in the channel region.

[0085] In the specific process, a patterned mask layer can be formed on the exposed nanosheet portion, and the nanosheet can be etched using methods such as dry etching and wet etching. The structure of the nanosheet after etching in the channel region is shown in Figure 12G.

[0086] In this embodiment, the nanosheet 13 is not completely etched; the purpose of etching is to reduce the thickness of the nanosheet 13 along the third direction Z. Therefore, in a preferred implementation, atomic layer etching (ALE) is used to etch the nanosheet structure. This allows for precise control of the etching amount of the nanosheet 13, thereby reducing the thickness of the nanosheet 13 along the third direction Z while also reducing the etching amount along the second direction Y.

[0087] Step 1109: Form a gate structure in the channel region.

[0088] In the specific process, an HK dielectric layer can be deposited first in the channel region. The specific materials of the HK dielectric layer can include, but are not limited to, materials such as Lao, AlO, ZrO, TiO, and SiO.

[0089] Then, metal is deposited on the HK dielectric layer using methods such as PVD and CVD. Excess metal material is then removed using a CMP process, making the metal flush with the sidewall structure 14 away from the substrate, thereby forming the gate structure 15, as shown in Figure 12H. This metal material can include an N-gate metal material for forming an N-type field-effect transistor, or a P-gate metal material for forming a P-type field-effect transistor. The N-gate metal material can include, but is not limited to, Ti, Ag, Al, TiAlN, TaCN, TaSiN, Mn, etc.; the P-gate metal material can include, but is not limited to, TiN, TaN, Ru, Mo, Al, WN, etc.

[0090] Step 1110: Etch the insulating structure, deposit the metal material, and form contact metal to bring out the source and drain.

[0091] The insulating structure 17 on the semiconductor structure 16 is etched to expose the upper surface of the semiconductor structure 16 away from the substrate.

[0092] Then, a metal material is deposited on the exposed semiconductor structure 16, and excess metal material is removed using a CMP process to form contact metal 19. The side of the contact metal 19 that is not in contact with the semiconductor structure 16 can be flush with the sidewall structure 13.

[0093] Step 1111: Cover the exposed surface of the gate structure with an insulating structure to form an insulating layer.

[0094] An insulating material is deposited on the exposed surface of the gate structure 15, which completely covers the surface of the gate structure 15, thereby protecting the gate structure 15.

[0095] Step 1112: Etch the insulating layer to bring out the gate.

[0096] The insulating layer 18 covering the gate structure 15 can be etched to form vias penetrating the upper and lower surfaces of the insulating layer. Metal material is deposited on the surface of the insulating layer away from the gate structure and in the vias to form contact metal. The contact metal 20 contacts the gate structure 15 through the vias in the insulating layer 18 to bring out the gate.

[0097] After steps 1110-1112, the prepared ring-gate nanosheet field-effect transistor is shown in Figure 8.

[0098] It should be noted that the gate-ring nanosheet field-effect transistor fabricated by process flow 1100 as shown in Figure 11 can be applied to components such as I / O to improve switching speed. In other implementations, when the fabricated gate-ring nanosheet field-effect transistor is applied to components such as processor cores, the process steps shown in step 1108 can be omitted to simplify the process flow.

[0099] In this embodiment, by setting the thickness of the insulating layer 12 to be less than the height of the semiconductor bump 11 protruding outward from the substrate 10, the two side portions of the semiconductor bump 11 are exposed. This allows both the upper surface of the semiconductor bump 11 and the exposed side portions to contact the gate material, forming a three-sided gate ring structure. This improves gate control capability; when the transistor is turned off, carriers are rapidly removed from the parasitic channel, reducing the leakage current of the gate ring nanosheet field-effect transistor and thus improving its performance.

[0100] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. A chip, characterized in that, The device includes a first gate-ring nanosheet field-effect transistor and a second gate-ring nanosheet field-effect transistor. The first gate-ring nanosheet field-effect transistor is used for a processor core, and the second gate-ring nanosheet field-effect transistor is used for an I / O device. The spacing between adjacent nanosheets in the channel region of the first gate-ring nanosheet field-effect transistor is smaller than the spacing between adjacent nanosheets in the channel region of the second gate-ring nanosheet field-effect transistor.

2. The chip as described in claim 1, characterized in that, The thickness of the nanosheets located in the channel region of the first ring-gate nanosheet field-effect transistor is greater than the thickness of the nanosheets located in the channel region of the second ring-gate nanosheet field-effect transistor.

3. The chip as described in claim 1, characterized in that, Both the first gate-around nanosheet field-effect transistor and the second gate-around nanosheet field-effect transistor include: a plurality of nanosheets stacked at intervals; a source and a drain at opposite ends of the stacked nanosheets; and a gate material that encapsulates the plurality of nanosheets and fills the gaps between them, wherein the channel region is located between the source and the drain.

4. The chip as described in claim 3, characterized in that, The first ring-gate nanosheet field-effect transistor further includes: a substrate; a semiconductor bump disposed on the surface of the substrate; an insulating layer formed on both sides of the semiconductor bump and covering the surface of the substrate, wherein the height of the surface of the insulating layer is less than the height of the semiconductor bump, and the plurality of nanosheets are spaced above the semiconductor bump.

5. The chip as described in claim 3, characterized in that, The second ring-gate nanosheet field-effect transistor further includes: a substrate; semiconductor bumps disposed on the surface of the substrate; an insulating layer formed on both sides of the semiconductor bumps and covering the surface of the substrate, wherein the height of the surface of the insulating layer is less than the height of the semiconductor bumps, and the plurality of nanosheets are spaced above the semiconductor bumps.

6. A chip, characterized in that, The device includes multiple gate-around nanosheet field-effect transistors (GOTMTs), some of which are used for processor cores, while others are used for I / O devices. The spacing between adjacent nanosheets in the channel region of the GOTMTs used for processor cores is smaller than the spacing between adjacent nanosheets in the channel region of the GOTMTs used for I / O devices.

7. The chip as described in claim 6, characterized in that, The thickness of the nanosheets located in the channel region of the first ring-gate nanosheet field-effect transistor is greater than the thickness of the nanosheets located in the channel region of the second ring-gate nanosheet field-effect transistor.

8. The chip as described in claim 6, characterized in that, Both the first gate-around nanosheet field-effect transistor and the second gate-around nanosheet field-effect transistor include: a plurality of nanosheets stacked at intervals; a source and a drain at opposite ends of the stacked nanosheets; and a gate material that encapsulates the plurality of nanosheets and fills the gaps between them, wherein the channel region is located between the source and the drain.

9. The chip as described in claim 8, characterized in that, The first ring-gate nanosheet field-effect transistor further includes: a substrate; a semiconductor bump disposed on the surface of the substrate; an insulating layer formed on both sides of the semiconductor bump and covering the surface of the substrate, wherein the height of the surface of the insulating layer is less than the height of the semiconductor bump, and the plurality of nanosheets are spaced above the semiconductor bump.

10. The chip as described in claim 8, characterized in that, The second ring-gate nanosheet field-effect transistor further includes: a substrate; semiconductor bumps disposed on the surface of the substrate; an insulating layer formed on both sides of the semiconductor bumps and covering the surface of the substrate, wherein the height of the surface of the insulating layer is less than the height of the semiconductor bumps, and the plurality of nanosheets are spaced above the semiconductor bumps.

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