Solid-state imaging device and electronic apparatus

Abstract

[Problem] To avoid the influence of feed-through when a plurality of conversion efficiency switching transistors and a plurality of floating diffusion regions are provided. [Solution] A solid-state imaging device is provided with: a photoelectric conversion element that generates a charge in accordance with the amount of incident light; a plurality of conversion efficiency switching transistors that perform switching to mutually different photoelectric conversion efficiencies; a plurality of floating diffusion regions each holding at least a portion of a charge generated by the photoelectric conversion element in accordance with switching control of ON / OFF of the plurality of conversion efficiency switching transistors; and a reset transistor discharging held charges of the plurality of floating diffusion regions to a reference voltage node. The reset transistor discharges held charges of two or more floating diffusion regions among the plurality of floating diffusion regions to the reference voltage node without passing through the plurality of conversion efficiency switching transistors.

Description

Solid-state imaging devices and electronic equipment Technical Field

[0001] This disclosure relates to a solid-state imaging device and an electronic device. Background Technology

[0002] A technique for extending dynamic range is known by setting conversion efficiency to switch transistors, changing sensitivity, and reading out pixel signals multiple times (see Patent Document 1).

[0003] By setting multiple conversion efficiency switching transistors and multiple floating diffusion regions (floating diffusion sections) in each pixel, the dynamic range can be further extended.

[0004] Citation List

[0005] Patent documents

[0006] Patent Document 1: Japanese Patent Application Publication No. 2023-11858 Summary of the Invention

[0007] The problem the invention aims to solve

[0008] When multiple conversion efficiency switching transistors and multiple floating diffusion regions are set in each pixel, it is necessary to sequentially retain the charge generated in the photoelectric conversion element in each floating diffusion region via a transfer transistor, and to discharge the charge held in the multiple floating diffusion regions to the power supply voltage node via a reset transistor. Therefore, it is conceivable to adopt a configuration in which the conversion efficiency switching transistors and floating diffusion regions are alternately connected in series between the reset transistor and the transfer transistor.

[0009] However, when the efficiency switching transistor or the reset transistor is off, there is a problem with the floating diffusion region, located further away from the power supply voltage node connected to the drain of the reset transistor: the potential variation width (hereinafter referred to as the FD range) of each floating diffusion region (hereinafter referred to as the floating diffusion region) decreases due to the feed-through effect of each efficiency switching transistor. Feed-through refers to the phenomenon where, when the efficiency switching transistor switches from on to off, the voltage level of the floating diffusion region decreases due to the decrease in the gate voltage of the efficiency switching transistor, and the amount of charge that can be maintained in the floating diffusion region decreases.

[0010] Therefore, this disclosure provides a solid-state imaging device and electronic device that can avoid the effects of feedthrough when multiple conversion efficiency switching transistors and multiple floating diffusion regions are provided.

[0011] Solution to the problem

[0012] To address the aforementioned problems, according to this disclosure, a solid-state imaging device is provided, comprising:

[0013] A photoelectric conversion element that generates an electric charge based on the amount of incident light;

[0014] Multiple conversion efficiency switching transistors perform switching to different photoelectric conversion efficiencies from one another;

[0015] Multiple floating diffusion regions, which respectively maintain at least a portion of the charge generated by the photoelectric conversion element according to the switching control of the multiple conversion efficiency switching transistors; and

[0016] A reset transistor that discharges the holding charge from the plurality of floating diffused regions to the reference voltage node.

[0017] The reset transistor discharges the hold charge of two or more of the plurality of floating diffusion regions to the reference voltage node without passing through the plurality of conversion efficiency switching transistors.

[0018] It may include two or more charge transport regions that connect the reset transistor and each of the two or more floating diffusion regions.

[0019] The reset transistor may include two or more sources, and

[0020] The two or more charge transport regions may include two or more diffusion regions that connect the two or more sources and the two or more floating diffusion regions.

[0021] The reset transistor may include two or more sources, and

[0022] At least one of the two or more charge transport regions may include two or more metal components that connect the two or more source electrodes and the two or more floating diffusion regions.

[0023] The metal component may include:

[0024] A first contact member is connected to the source of the reset transistor;

[0025] The second contact member is connected to the floating diffusion region; and

[0026] A metal wiring layer that connects a first contact member and a second contact member at a height different from the height of the source of the reset transistor and the floating diffusion region.

[0027] The reset transistor may include a single gate corresponding to the two or more sources.

[0028] The reset transistor may include:

[0029] Two or more gates corresponding to the two or more sources and configured separately from each other; and

[0030] A metal component that enables the two or more gates to conduct to each other.

[0031] The reset transistor may include two or more drains connected to the reference voltage node.

[0032] The reset transistor may include a single drain connected to the reference voltage node.

[0033] This may include a transfer transistor that sequentially transfers the charge photoelectrically converted by the photoelectric conversion element to the plurality of floating diffusion regions, and

[0034] The reset transistor can discharge the retained charge of two or more of the floating diffusion regions other than the floating diffusion region that initially transfers charge from the transfer transistor to the reference voltage node without passing through the plurality of conversion efficiency switching transistors.

[0035] This may include a transfer transistor that transfers the charge photoelectrically converted by the photoelectric conversion element to the plurality of floating diffusion regions, and

[0036] The reset transistor can discharge the retained charge of two or more of the floating diffusion regions, including the floating diffusion region that initially transferred charge from the transfer transistor, to the reference voltage node without passing through the plurality of conversion efficiency switching transistors.

[0037] It may include pixels having two or more of the aforementioned photoelectric conversion elements.

[0038] The plurality of floating diffusion regions may include two or more floating diffusion regions that retain the charge generated by the two or more photoelectric conversion elements, and

[0039] The reset transistor can discharge the hold charge of the two or more floating diffusion regions to the reference voltage node without passing through other floating diffusion regions.

[0040] The two or more photoelectric conversion elements can have different light receiving areas.

[0041] It can include:

[0042] A pixel, in a single exposure operation, alters its sensitivity by switching multiple conversion efficiency switching transistors on and off, thereby outputting pixel signals multiple times.

[0043] The signal processing unit converts the pixel signal into a digital signal and performs dual data sampling (DDS) to detect the difference between the signal level and the reset level of the pixel signal.

[0044] The pixel may include the photoelectric conversion element, the plurality of conversion efficiency switching transistors, the plurality of floating diffusion regions, and the reset transistor.

[0045] It can include:

[0046] A pixel, in a single exposure operation, alters its sensitivity by switching multiple conversion efficiency switching transistors on and off, thereby outputting pixel signals multiple times.

[0047] The signal processing unit converts the pixel signal into a digital signal and performs correlated double sampling (CDS) to detect the difference between the reset level and the signal level of the pixel signal.

[0048] The pixel may include the photoelectric conversion element, the plurality of conversion efficiency switching transistors, the plurality of floating diffusion regions, and the reset transistor.

[0049] According to this disclosure, an electronic device is provided, comprising:

[0050] Solid-state imaging devices that generate images based on the amount of incident light; and

[0051] The processing unit processes the image.

[0052] The solid-state imaging device includes:

[0053] A photoelectric conversion element that generates an electric charge based on the amount of incident light;

[0054] Multiple conversion efficiency switching transistors perform switching to different photoelectric conversion efficiencies from one another;

[0055] Multiple floating diffusion regions, which respectively maintain at least a portion of the charge generated by the photoelectric conversion element according to the switching control of the multiple conversion efficiency switching transistors; and

[0056] A reset transistor that discharges the holding charge from the plurality of floating diffused regions to a reference voltage node, and

[0057] The reset transistor discharges the holding charge of two or more of the plurality of floating diffusion regions to the reference voltage node without passing through the plurality of conversion efficiency switching transistors. Attached Figure Description

[0058] Figure 1 is a block diagram of an electronic device according to a first embodiment of the present disclosure.

[0059] Figure 2 is a block diagram illustrating a schematic configuration of a solid-state imaging apparatus according to one embodiment of the present disclosure.

[0060] Figure 3 is a block diagram showing the configuration around the vertical signal line of the solid-state imaging device according to the present disclosure.

[0061] Figure 4 is a circuit diagram of each pixel of a solid-state imaging device according to one embodiment.

[0062] Figure 5 is a planar layout diagram of pixels according to one implementation scheme.

[0063] Figure 6A is a potential diagram of a pixel according to one embodiment.

[0064] Figure 6B is a potential diagram when the FDG transistor is further disconnected.

[0065] Figure 6C is a potential diagram when the RST transistor is further disconnected.

[0066] Figure 7 is a circuit diagram based on a pixel of a comparative example.

[0067] Figure 8 is a planar layout diagram of pixels based on a comparative example.

[0068] Figure 9A is a potential diagram of a pixel based on a comparative example.

[0069] Figure 9B is a potential diagram with the FDG transistor off.

[0070] Figure 9C is a potential diagram when the FCG transistor is further disconnected.

[0071] Figure 9D is a potential diagram when the RST transistor is further disconnected.

[0072] Figure 10 is a planar layout diagram of pixels according to a first variant of an implementation scheme.

[0073] Figure 11 is a circuit diagram of a pixel according to a second variation of an implementation scheme.

[0074] Figure 12 is a planar layout diagram of pixels according to a second variation of an implementation scheme.

[0075] Figure 13 is a circuit diagram of a pixel according to a third variation of an implementation scheme.

[0076] Figure 14A is a planar layout diagram of pixels according to a third variation of an embodiment.

[0077] Figure 14B is a planar layout diagram with three RST transistors.

[0078] Figure 15 is a planar layout diagram of pixels according to a fourth variation of an implementation scheme.

[0079] Figure 16 is a circuit diagram of a pixel according to a fifth variation of an implementation scheme.

[0080] Figure 17 is a planar layout diagram of pixels according to a fifth variation of an implementation scheme.

[0081] Figure 18 is a planar layout diagram of pixels according to a sixth variation of an implementation scheme.

[0082] Figure 19 is a block diagram illustrating an example of a schematic configuration of a vehicle control system.

[0083] Figure 20 is an example diagram illustrating the installation location of the vehicle exterior information detection unit and the imaging unit.

[0084] Figure 21 is a block diagram illustrating an example of a schematic configuration of an endoscopic surgical system.

[0085] Figure 22 is a block diagram illustrating an example of the functional configuration of a camera and camera control unit (CCU). Detailed Implementation

[0086] In the following description, embodiments of the solid-state imaging apparatus and electronic device will be illustrated with reference to the accompanying drawings. The main components of the solid-state imaging apparatus and electronic device will be described primarily below; however, the solid-state imaging apparatus may have components and functions not shown or described. The following description is not intended to exclude components and functions not shown or described.

[0087] Figure 1 is a block diagram of an electronic device 10 according to a first embodiment of the present disclosure. The electronic device 10 has the function of generating an image based on the brightness of the incident light. The electronic device 10 in Figure 1 includes a solid-state imaging device 1, an imaging lens 2, an image processing unit 3, a recording unit 4, and a control unit 5. Although the electronic device 10 can be applied to, for example, surveillance cameras, cameras mounted on industrial robots, general-purpose cameras, etc., the specific application and configuration of the electronic device 10 are arbitrary.

[0088] Imaging lens 2 collects incident light and guides it to solid-state imaging device 1. Solid-state imaging device 1 images the incident light. Solid-state imaging device 1 is equipped with a function to photoelectrically convert light within a predetermined wavelength range (such as visible light or infrared light) to generate a captured image. The captured image generated by solid-state imaging device 1 is sent to image processing unit 3 and recording unit 4.

[0089] The image processing unit 3 performs predetermined image processing on the captured image, such as color or brightness adjustment, image compression, image recognition, tracking, or analysis. The image processed by the image processing unit 3 is output to, for example, the recording unit 4.

[0090] The recording unit 4 records the image output from the solid-state imaging device 1 or the image processing unit 3. The recording unit 4 can be configured on a server or the like connected via a network. In the electronic device 10 according to this embodiment, at least one of the image processing unit 3 and the recording unit 4 of FIG1 can be omitted.

[0091] The control unit 5 controls the operation of the solid-state imaging device 1. Furthermore, although not explicitly shown in Figure 1, the control unit 5 can control the image processing unit 3 and the recording unit 4.

[0092] Figure 2 is a block diagram illustrating a schematic configuration of a solid-state imaging apparatus 1 according to one embodiment of the present disclosure. As shown in Figure 2, the solid-state imaging apparatus 1 according to one embodiment includes a pixel array unit 11. Furthermore, the solid-state imaging apparatus 1 includes, for example, a vertical driving unit 12, a column processing unit 13, a horizontal driving unit 14, and a system control unit 15. The solid-state imaging apparatus 1 also includes a signal processing unit 16 and a data storage unit 17. The signal processing unit 16 and the data storage unit 17 can be mounted on the same substrate as the pixel array unit 11, the vertical driving unit 12, etc., or they can be disposed on a different substrate. Furthermore, the processing of the signal processing unit 16 and the data storage unit 17 can be performed by an external signal processing unit disposed in a semiconductor chip different from the solid-state imaging apparatus 1, such as a digital signal processor (DSP) circuit.

[0093] The pixel array section 11 is configured such that pixels 21 are arranged in a matrix-like two-dimensional configuration in both the row and column directions. Each pixel 21 has a photoelectric conversion element that generates and accumulates a charge corresponding to the amount of received light. Here, the row direction refers to the pixel row of the pixel array section 11, i.e., the horizontal arrangement direction, and the column direction refers to the pixel column of the pixel array section 11, i.e., the vertical arrangement direction. The specific circuit configuration of the pixel 21 will be described later. Pixel 21 may also be referred to as a unit pixel, but it is referred to as pixel 21 in this document.

[0094] In the pixel array section 11, pixel drive lines 22, which serve as row signal lines, are routed along the row direction for each pixel row, and vertical signal lines VSL, which serve as column signal lines, are routed along the column direction for each pixel column. Each pixel drive line 22 transmits a drive signal used for driving when a signal is read from each pixel 21. In FIG. 2, each pixel drive line 22 is shown as a single line, but the number is not limited to one. One end of each pixel drive line 22 is connected to an output terminal corresponding to each row of the vertical drive section 12.

[0095] The vertical drive unit 12 includes a shift register, an address decoder, etc., and drives each pixel 21 of the pixel array unit 11 simultaneously for all pixels on a row-by-row basis. The vertical drive unit 12, together with the system control unit 15, constitutes a drive unit that controls the operation of each pixel 21 of the pixel array unit 11. Although the specific configuration of the vertical drive unit 12 is not shown, it typically includes two scanning systems: a readout scanning system and a scanout scanning system.

[0096] In order to read out signals from each pixel 21, the readout scanning system sequentially selects and scans the pixels 21 of the pixel array section 11 row by row. The signals read out from each pixel 21 are analog signals. For the readout row that will be read out by the readout scanning system, the scanout scanning system performs a scanout scan with an exposure time ahead of that readout scan.

[0097] By scanning outwards using the scanning system, unwanted charges are removed from the photoelectric conversion elements of the readout rows of pixels 21, thereby resetting the photoelectric conversion elements of each pixel 21. Then, when the scanning system removes (resets) unwanted charges, a so-called electronic shutter operation is performed. Here, the electronic shutter operation refers to the operation of expelling the charges from the photoelectric conversion elements and restarting exposure (starting to accumulate charges).

[0098] The signal read out by the readout operation of the readout scanning system corresponds to the amount of light received after a previous readout operation or electronic shutter operation. Then, the period from the readout timing of the previous readout operation or the scan timing of the electronic shutter operation to the readout timing of the current readout operation is the exposure period in pixel 21.

[0099] The signals output from each pixel 21 of the pixel row selectively scanned by the vertical drive unit 12 are input to the column processing unit 13 for each pixel column via the vertical signal line VSL. The column processing unit 13 performs predetermined signal processing on the signals output from each pixel 21 of the selected row via the vertical signal line VSL for each pixel column of the pixel array unit 11, and temporarily holds the processed pixel signals.

[0100] Specifically, as signal processing, the column processing unit 13 performs at least noise removal processing, such as correlated double sampling (CDS) processing or dual data sampling (DDS) processing. For example, through CDS processing, reset noise and pixel-inherent fixed-pattern noise, such as threshold variations of AMP transistors within a pixel, are removed. In addition to noise removal processing, the column processing unit 13 also has, for example, an analog-to-digital (AD) conversion function to convert analog pixel signals into digital signals and output the digital signals.

[0101] The horizontal drive unit 14 includes a shift register, an address decoder, etc., and sequentially selects unit circuits corresponding to the pixel columns in the column processing unit 13. As a result of the selective scanning of the horizontal drive unit 14, pixel signals that have undergone signal processing for each unit circuit in the column processing unit 13 are sequentially output.

[0102] The system control unit 15 includes a timing generator that generates various timing signals, and performs drive control of the vertical drive unit 12, column processing unit 13, horizontal drive unit 14, etc. based on the various timing signals generated by the timing generator.

[0103] The signal processing unit 16 has at least calculation processing capabilities and performs various signal processing operations, such as calculation processing, on the pixel signals output from the column processing unit 13. The data storage unit 17 temporarily stores the data required for signal processing in the signal processing unit 16. The pixel signals processed in the signal processing unit 16 are converted into a predetermined format and output from the output unit 18 to the outside of the solid-state imaging device 1.

[0104] Figure 3 is a block diagram showing the configuration around the vertical signal line VSL of the solid-state imaging apparatus 1 according to the present disclosure. As shown in Figure 3, a vertical signal line VSL is provided for each pixel column of the pixel array section 11. Each pixel 21 included in the pixel column includes a photoelectric conversion element and a pixel circuit, which will be described later. The photoelectric conversion element generates a charge according to the amount of incident light. The pixel circuit reads out the charge generated by the photoelectric conversion element multiple times during a single exposure operation and outputs a pixel signal with a signal level that changes to multiple levels according to the read-out charge to the signal line.

[0105] Current source 24 and column processing unit 13 are connected to each vertical signal line VSL. Although a current source 24 is provided for each vertical signal line VSL, all vertical signal lines VSL are connected to column processing unit 13.

[0106] Current source 24 generates current flowing through the corresponding vertical signal line VSL. The current flowing through each vertical signal line VSL is led out to the ground node through the corresponding current source 24. By allowing current to flow through the vertical signal line VSL via current source 24, the settling time of the pixel signal voltage level on the vertical signal line can be shortened.

[0107] A digital-to-analog converter (DAC) 27 is connected to the column processing unit 13. The column processing unit 13 includes a comparator 28 and a counter 29 for each vertical signal line VSL.

[0108] Each comparator 28 compares the pixel signal on the corresponding vertical signal line VSL with the reference signal output from the DAC 27. When the signal levels of the pixel signal and the reference signal match, the signal level of the output signal of the comparator 28 changes. The counter 29 starts counting in response to a start signal from the system control unit 15 shown in FIG. 2, and stops counting when the signal level of the output signal of each comparator 28 changes. The count value of the counter 29 is obtained by performing an AD conversion on the signal level of the pixel signal.

[0109] Figure 4 is a circuit diagram of each pixel 21 of a solid-state imaging device 1 according to one embodiment. As shown in Figure 4, the pixel 21 according to this disclosure includes a photoelectric conversion element PD, a transmission transistor 31, a reset transistor 32, an AMP transistor 33, a SEL transistor 34, a first conversion efficiency switching transistor 35, a second conversion efficiency switching transistor 36, a first floating diffusion region FD1, a second floating diffusion region FD2, and a third floating diffusion region FD3. In the following, the transmission transistor 31 is referred to as TG transistor 31, the reset transistor 32 as RST transistor 32, the AMP transistor 33 as AMP transistor 33, the SEL transistor 34 as SEL transistor 34, the first conversion efficiency switching transistor 35 as FDG transistor 35, and the second conversion efficiency switching transistor 36 as FCG transistor 36.

[0110] Although Figure 4 shows two symbols 32a and 32b representing RST transistor 32, it is actually composed of a single RST transistor 32 comprising at least two sources. In the following text, one of the two sources of RST transistor 32 is referred to as the first source, and the other as the second source.

[0111] The first source is connected to the drain of FDG transistor 35, which is the second floating diffusion region FD2. The second source is connected to the drain of FCG transistor 36, which is the third floating diffusion region FD3.

[0112] Figure 4 shows an example of an RST transistor 32 (32a, 32b) including two drains, but as will be discussed later, a variant including a single drain can also be considered. Both drains are connected to the power supply voltage VDD node.

[0113] RST transistor 32 discharges the hold charge of two or more floating diffusion regions (e.g., the second floating diffusion region FD2 and the third floating diffusion region FD3) within pixel 21 to the reference voltage (e.g., the power supply voltage VDD) node without passing through multiple conversion efficiency switching transistors (e.g., FDG transistor 35 and FCG transistor 36). In the example of FIG4, RST transistor 32 discharges the hold charge in the second and third floating diffusion regions FD2 and FD3 directly to the power supply voltage VDD node.

[0114] The photoelectric conversion element PD is, for example, a photodiode. The anode of the photoelectric conversion element PD is connected to the ground node, and the cathode is connected to the source of the transmission transistor 31.

[0115] The drain of FDG transistor 35 is connected to the second floating diffusion region FD2, the source of FCG transistor 36, and the first source of RST transistor 32. A first charge holding section C1 can be connected to the second floating diffusion region FD2. The first charge holding section C1 is, for example, a metal-oxide-semiconductor (MOS) capacitor, a metal-insulator-metal (MIM) capacitor, or a wiring capacitor.

[0116] The drain of FCG transistor 36 is connected to the third floating diffusion region FD3 and the second source of RST transistor 32. The second charge holding section C2 can be connected to the third floating diffusion region FD3. The second charge holding section C2 is, for example, a MOS capacitor, a MIM capacitor, or a wiring capacitor.

[0117] AMP transistor 33 and SEL transistor 34 form a source follower circuit. The drain of AMP transistor 33 is connected to the power supply voltage VDD node, and its source is connected to the drain of SEL transistor 34. The source of SEL transistor 34 is connected to the vertical signal line VSL.

[0118] The TG signal is input to the gate of TG transistor 31, the FDG signal is input to the gate of FDG transistor 35, the FCG signal is input to the gate of FCG transistor 36, the RST signal is input to the gate of RST transistor 32, and the SEL signal is input to the gate of SEL transistor 34.

[0119] Figure 5 is a planar layout diagram of pixel 21 according to one embodiment. RST transistor 32, FCG transistor 36, FDG transistor 35, and TG transistor 31 are sequentially arranged in the column direction between the power supply voltage VDD node and the photoelectric conversion element PD. More specifically, the drain, gate, and source of RST transistor 32, the drain, gate, and source of FCG transistor 36, the drain, gate, and source of FDG transistor 35, and the drain, gate, and source of TG transistor 31 are arranged in this order from the power supply voltage VDD node to the photoelectric conversion element PD.

[0120] The gate of each transistor is made of a metal material such as copper (Cu) or polysilicon. The drain and source of each transistor are diffusion regions obtained by implanting impurity ions into a silicon layer, which serves as the substrate material, and then diffusing the implanted impurity ions. These diffusion regions are referred to herein as active regions (AA).

[0121] As shown in Figure 4, the RST transistor 32 according to one embodiment includes two drains (first drain 32d1 and second drain 32d2) and two sources (first source 32s1 and second source 32s2). As will be described later, a configuration in which the drains are not divided into two drains 32d1 and 32d2 can also be adopted.

[0122] The first source 32s1 and the second floating diffusion region FD2 are connected at the active region AA1, which includes the diffusion region. The second source 32s2 and the third floating diffusion region FD3 are connected at the active region AA2, which includes the diffusion region. The active region AA1 connected to the first source 32s1 and the active region AA2 connected to the second source 32s2 are configured separately so as not to contact each other. A component isolation region, including an insulating material such as SiO2, is configured between the active regions AA1 and AA2. The active regions AA1 and AA2 are charge transport regions for discharging the retained charge in the second floating diffusion region FD2 and the third floating diffusion region FD3 to the power supply voltage VDD node via the RST transistor 32.

[0123] In pixel 21 according to one embodiment, the FCG transistor 36 does not need to be turned on when the held charge in the first to third floating diffusion regions FD1 to FD3 is discharged to the power supply voltage VDD node. Therefore, the feedthrough effect generated when the FCG transistor 36 switches from on to off is eliminated, and the reduction of the amount of held charge in the first and second floating diffusion regions FD2 can be suppressed.

[0124] Figures 6A, 6B, and 6C are potential diagrams of pixel 21 according to one embodiment. Figure 6A is a potential diagram when TG transistor 31, FDG transistor 35, and RST transistor 32 are all turned on while FCG transistor 36 is turned off. As described above, since the first source 32s1 of RST transistor 32 is connected to the second floating diffusion region FD2, even if FCG transistor 36 is turned off, the retention charge in the first floating diffusion region FD1 and the second floating diffusion region FD2 can be discharged to the power supply voltage VDD node.

[0125] Figure 6B is a potential diagram when the FDG transistor 35 is further turned off. When the FDG transistor 35 is turned off, the first floating diffusion region FD1 is in a floating state, and the voltage level of the first floating diffusion region FD1 decreases as the gate voltage of the FDG transistor 35 decreases. That is, the potential of the first floating diffusion region FD1 increases.

[0126] Figure 6C is a potential diagram when the RST transistor 32 is further disconnected. When the RST transistor 32 is disconnected, the first floating diffusion region FD1, the second floating diffusion region FD2, and the third floating diffusion region FD3 are in a floating state, and the potentials of the first to third floating diffusion regions FD1 to FD3 increase as the gate voltage of the RST transistor 32 decreases.

[0127] For simplicity, Figures 6B and 6C illustrate the gradual increase in potential of the first to third floating diffusion regions FD1 to FD3 due to feedthrough when either FDG transistor 35 or RST transistor 32 is turned off. Under the influence of feedthrough caused by both FDG transistor 35 and RST transistor 32 being turned off, the potential of the first floating diffusion region FD1 increases by two levels. Since the second floating diffusion region FD2 and the third floating diffusion region FD3 are only affected by feedthrough caused by RST transistor 32 being turned off, their potentials increase by one level.

[0128] As described above, in one embodiment, when the holding charge in the first to third floating diffusion regions FD1 to FD3 is discharged to the power supply voltage VDD node, it is not necessary to turn on the FCG transistor 36. The FDG transistor 35 can be turned off first, and then only the RST transistor 32 needs to be turned off. Therefore, when the FCG transistor 36 changes from on to off, there is no feedthrough effect, and the reduction of the holding charge in the first to third floating diffusion regions FD1 to FD3 can be suppressed.

[0129] Figure 7 is a circuit diagram of pixel 21 according to the comparative example. In pixel 21 according to the comparative example, the source of RST transistor 32 is connected only to the drain of FCG transistor 36 and the third floating diffusion region FD3, and not to the second floating diffusion region FD2. Other connections are similar to those in Figure 4. Therefore, in pixel 21 according to the comparative example, the held charge in the first floating diffusion region FD1 and the second floating diffusion region FD2 cannot be directly transferred to RST transistor 32, and FCG transistor 36 needs to be turned on to discharge the held charge in the first floating diffusion region FD1 and the second floating diffusion region FD2. Subsequently, when FCG transistor 36 is turned off, the amount of held charge in the first floating diffusion region FD1 and the second floating diffusion region FD2 decreases due to the effect of feedthrough.

[0130] Figure 8 is a planar layout diagram of pixel 21 according to the comparative example. As shown in Figure 8, in pixel 21 according to the comparative example, the drain, gate and source of RST transistor 32, the drain, gate and source of FCG transistor 36, the drain, gate and source of FDG transistor 35 and the drain, gate and source of TG transistor 31 are arranged in this order in the column direction between the power supply voltage VDD node and the photoelectric conversion element PD.

[0131] Figures 9A, 9B, 9C, and 9D are potential diagrams of pixel 21 according to the comparative example. In pixel 21 according to the comparative example, the FCG transistor 36 needs to be turned on to discharge the retention charge in the first floating diffusion region FD1 and the second floating diffusion region FD2.

[0132] Figure 9A is a potential diagram with all transistors TG 31, FDG 35, FCG 36 and RST 32 turned on.

[0133] Figure 9B is a potential diagram with FDG transistor 35 off. In this case, since the first floating diffusion region FD1 is in a floating state, the potential of the first floating diffusion region FD1 increases as the gate voltage of FDG transistor 35 decreases.

[0134] Figure 9C is a potential diagram when the FCG transistor 36 is further disconnected. In this case, since the first floating diffusion region FD1 and the second floating diffusion region FD2 are in a floating state, the potentials of the first floating diffusion region FD1 and the second floating diffusion region FD2 increase as the gate voltage of the FCG transistor 36 decreases.

[0135] Figure 9D is a potential diagram when the RST transistor 32 is further disconnected. In this case, since the first to third floating diffusion regions FD1 to FD3 are in a floating state, the potential of the first to third floating diffusion regions FD1 to FD3 increases as the gate voltage of the RST transistor 32 decreases.

[0136] By comparing Figures 9A-9D with Figures 6A-6C, it can be seen that in one comparative example, due to the effect of disconnecting the feedthrough of FCG transistor 36, the potentials of the first to third floating diffusion regions FD1 to FD3 increase progressively compared to one embodiment. Therefore, in pixel 21 according to one comparative example, compared to pixel 21 according to one embodiment, it is possible to maintain a smaller amount of charge in the first to third floating diffusion regions FD1 to FD3 and a narrower dynamic range.

[0137] Figure 10 is a planar layout diagram of pixel 21 according to a first variation of an embodiment. In pixel 21 according to the first variation, the structure of RST transistor 32 differs from that in Figure 5. The RST transistor 32 according to the first variation includes two reset transistors 32a and 32b. Reset transistor 32a includes a first gate 32g1, a first drain 32d1, and a first source 32s1. Reset transistor 32b includes a second gate 32g2, a second drain 32d2, and a second source 32s2. The first drain 32d1 and the second drain 32d2 are connected to the power supply voltage VDD node.

[0138] Similar to Figure 5, the first source 32s1 is connected to the drain of the FDG transistor 35 and the second floating diffusion region FD2, and the second source 32s2 is connected to the drain of the FCG transistor 36 and the third floating diffusion region FD3.

[0139] The metal component 41 connecting the first gate 32g1 and the second gate 32g2 of the RST transistor 32 may include the same metal material as the first gate 32g1 and the second gate 32g2, or may include different metal materials.

[0140] In pixel 21 according to the first variant, since the RST transistor 32 includes two small RST transistors 32a and 32b, and the gates 32g1 and 32g2 are connected via the metal member 41, the two RST transistors 32a and 32b can be turned on and off simultaneously. Furthermore, similar to FIG. 5, the two sources (first source 32s1 and second source 32s2) included in the two RST transistors 32a and 32a can be connected to different floating diffusion regions FD2 and FD3. Therefore, the retained charge in the second floating diffusion region FD2 and the third floating diffusion region FD3 can be directly discharged via the RST transistor 32.

[0141] Figure 11 is a circuit diagram of pixel 21 according to a second variation of an embodiment. Figure 12 is a plan view of pixel 21 according to a second variation of an embodiment. The difference between pixel 21 according to the second variation and that in Figure 4 is that the first source 32s1 of the RST transistor 32 is connected to the first floating diffusion region FD1 instead of the second floating diffusion region FD2. The other circuit configurations are similar to those in Figure 4.

[0142] The first floating diffusion region FD1 is connected to the gate of the AMP transistor 33, and it is desirable to retain the charge as noise-free as possible. Therefore, it is desirable that the second source 32s2 of the RST transistor 32 is not connected to the first floating diffusion region FD1. However, in cases where pixel signal accuracy is less critical, the second source 32s2 of the RST transistor 32 can be connected to the first floating diffusion region FD1. In this case, the retaining charge in the second floating diffusion region FD2 can be drained by turning on the FDG transistor 35.

[0143] As shown in Figure 12, in the second variant, the first source 32s1 and the first floating diffusion region FD1 of the RST transistor 32 are connected through an active region AA1 including the diffusion region. Similarly to Figure 5, the second source 32s2 and the third floating diffusion region FD3 of the RST transistor 32 are connected through an active region AA2 including the diffusion region.

[0144] In the second variation, the holding charge in the first floating diffusion region FD1 and the second floating diffusion region FD2 can be discharged to the power supply voltage VDD node without turning on the FCG transistor 36. Therefore, the potential rise of the first to third floating diffusion regions FD1 to FD3 caused by feedthrough when the RST transistor 32 is turned off can be suppressed, and the holding charge in the first to third floating diffusion regions FD1 to FD3 increases compared to the comparative example.

[0145] Figure 13 is a circuit diagram of pixel 21 according to a third variation of an embodiment. In addition to the configuration of pixel 21 in Figure 4, pixel 21 according to the third variation also includes a third conversion efficiency switching transistor 37 and a fourth floating diffusion region FD4, and the RST transistor 32 includes three sources (hereinafter referred to as the first to third sources). A third charge holding section C3 can be connected to the fourth floating diffusion region FD4. The third charge holding section C3 includes, for example, a MOS capacitor, a MIM capacitor, or a wiring capacitor. Hereinafter, the first conversion efficiency switching transistor 35 is referred to as FDG transistor 35, the second conversion efficiency switching transistor 36 is referred to as FCG1 transistor 36, and the third conversion efficiency switching transistor is referred to as FCG2 transistor 37.

[0146] The first source 32s1 of the RST transistor 32 is connected to the second floating diffusion region FD2, the second source 32s2 is connected to the third floating diffusion region FD3, and the third source 32s3 is connected to the fourth floating diffusion region.

[0147] Figures 14A and 14B are planar layout diagrams of pixel 21 according to a third variation of one embodiment. As shown in Figures 13 and 14A, since the second floating diffusion region FD2 and the third floating diffusion region FD3 are directly connected to the RST transistor 32, the retained charge in the first to fourth floating diffusion regions can be discharged to the power supply voltage VDD node without turning on the FCG2 transistor 37.

[0148] Regarding the potentials of the first to fourth floating diffusion regions FD1 to FD4 when RST transistor 32 is off, only the potential of the first floating diffusion region FD1 rises by two levels, while the potentials of the second to fourth floating diffusion regions FD2 to FD4 rise by only one level. Therefore, the potential rise and reduction of the remaining charge in the first to fourth floating diffusion regions FD1 to FD4 caused by feedthrough when FCG transistor 36 and RST transistor 32 are off can be suppressed.

[0149] Although Figure 14A shows an example of a single gate configured in association with the first to third sources of RST transistor 32, Figure 14B shows an example of a configuration where the first to third gates are configured in association with the first to third sources. Figure 14B shows an example in which three small RST transistors 32a, 32b, and 32c are configured and the gates of each RST transistor 32a, 32b, and 32c are connected to each other by, for example, a metal member 41.

[0150] Figure 14A simplifies the structure of the RST transistor 32, thus facilitating the manufacturing process. On the other hand, with a large area of ​​a single gate, it is difficult to apply a uniform voltage across the entire gate area. In the case of Figure 14B, the structure of the RST transistor 32 is more complex than that in Figure 14A, but since the RST transistor 32 includes three small RST transistors, it is easy to make the electrical characteristics uniform.

[0151] Figure 15 is a planar layout diagram of pixel 21 according to a fourth variation of an embodiment. Pixel 21 according to the fourth variation has a circuit configuration similar to that in Figure 4. The difference between pixel 21 according to the fourth variation and the planar layout in Figure 5 is that the first source 32s1 and the second floating diffusion region FD2 of the RST transistor 32 are connected via a metal member 42, rather than via an active region including the diffusion region.

[0152] The metal component 42 is constructed using, for example, contacts and a metal wiring layer. More specifically, the metal component 42 includes a first contact connected to the first source electrode 32s1 and extending upward (or downward), a second contact connected to the second floating diffusion region FD2 and extending upward or downward, and a metal wiring layer connected to the upper (or lower) end of the first contact and the lower (or upper) end of the second contact. The first contact, the second contact, and the metal wiring layer are formed using, for example, copper (Cu) or aluminum (Al).

[0153] Note that, similarly in Figures 12, 14A, and 14B, the first source 32s1 or the second source 32s2 of the RST transistor 32 and the second floating diffusion region FD2 or the third floating diffusion region FD3 can be connected by a metal component 42 similar to that in Figure 15, rather than in the active region.

[0154] Figure 16 is a circuit diagram of pixel 21 according to a fifth modification of an embodiment. Pixel 21 according to the fifth modification includes multiple photoelectric conversion elements PD. Hereinafter, an example will be described where two photoelectric conversion elements (first photoelectric conversion element PD1 and second photoelectric conversion element PD2), two transmission transistors (TG1 transistor 31a and TG2 transistor 31b), and two conversion efficiency switching transistors (FDG1 transistor 35a and FDG2 transistor 35b) are provided within pixel 21. However, more than three photoelectric conversion elements PD can be provided within pixel 21. The first photoelectric conversion element PD1 and the second photoelectric conversion element PD2 may have different light-receiving areas.

[0155] As shown in Figure 16, the pixel 21 according to the fifth modification includes an RST transistor 32 (32b), an FDG1 transistor 35a, and a TG1 transistor 31a connected in series between the power supply voltage VDD node and the cathode of the first photoelectric conversion element PD1, and an RST transistor 32 (32b), an FDG2 transistor 35b, and a TG2 transistor 31b connected in series between the voltage VDD node and the cathode of the first photoelectric conversion element PD1. The first source of the RST transistor 32 (32a) is connected to the first floating diffusion region FD1.

[0156] Figure 17 is a planar layout diagram of pixel 21 according to a fifth variation of an embodiment. The RST transistor 32 includes a first source 32s1 and a second source 32s2. The first source 32s1 and a first floating diffusion region FD1 are connected through an active region AA1 including the diffusion region. The second source 32s2 and a third floating diffusion region FD3 are connected through an active region AA2 including the diffusion region.

[0157] In pixel 21 according to the fifth variation, since the first floating diffusion region FD1 and the third floating diffusion region FD3 are directly connected to the RST transistor 32, the holding charge in the first floating diffusion region FD1 and the third floating diffusion region FD3 can be discharged to the power supply voltage VDD node without turning on the FDG1 transistor 35a and the FDG2 transistor 35b. Furthermore, the potential rise and reduction of holding charge in the first to third floating diffusion regions FD1 to FD3 caused by feedthrough when the FDG1 transistor 35a, the FDG2 transistor 35b, or the RST transistor 32 is turned off can be suppressed.

[0158] Figure 18 is a plan view of pixel 21 according to a sixth variation of an embodiment. Pixel 21 according to the sixth variation has a circuit configuration similar to that in Figure 4.

[0159] The pixel 21 according to the sixth variation is characterized in that the channel under the gate of the RST transistor 32 has a left-right symmetrical structure. Therefore, the first source 32s1 and the second source 32s2 included in the RST transistor 32 are arranged symmetrically left-right, and a single drain is provided on the axis of symmetry and connected to the power supply voltage VDD node. This symmetrical structure facilitates layout design. In the pixel 21 according to the sixth variation, similar to FIG. 5, the first source 32s1 is connected to the second floating diffusion region FD2 via the active region AA1, and the second source 32s2 is connected to the third floating diffusion region FD3 via the active region AA2.

[0160] The pixel 21 according to one embodiment described above and the pixel 21 according to the first to sixth variations are specific examples of the pixel 21 according to this disclosure, and various variations are conceived. For example, the number of conversion efficiency switching transistors included in the pixel 21 can be any number, more than two. Furthermore, multiple pixels 21 can share multiple conversion efficiency switching transistors 35, multiple floating diffusion regions (FD), and RST transistors 32. The circuit configuration of the pixel 21 is also not limited to the circuit configuration shown in FIG4, etc.

[0161] As described above, in the solid-state imaging apparatus 1 according to one embodiment, the retaining charge in two or more of the multiple floating diffusion regions FD disposed within the pixel 21 can be directly discharged via the RST transistor 32 without passing through the multiple conversion efficiency switching transistors 35. Therefore, even when the gate voltage decreases when the conversion efficiency switching transistors 35 are turned off, it is unlikely to be affected by feedthrough, and the potential rise of the multiple floating diffusion regions FD and the reduction of the retaining charge can be suppressed.

[0162] <Examples of applications of moving objects>

[0163] The technology disclosed herein (the Technology) can be applied to a variety of products. For example, the Technology disclosed herein can be implemented as a device to be installed on any type of mobile body such as a car, electric car, hybrid electric car, motorcycle, bicycle, personal mobility device, airplane, unmanned aerial vehicle, ship or robot.

[0164] Figure 19 is a block diagram of a schematic configuration example of a vehicle control system, which is an example of a mobile body control system to which the technology according to the embodiments of the present disclosure is applicable.

[0165] The vehicle control system 12000 includes multiple electronic control units interconnected via a communication network 12001. In the example shown in FIG19, the vehicle control system 12000 includes a drive system control unit 12010, a main system control unit 12020, an external information detection unit 12030, an internal information detection unit 12040, and an integrated control unit 12050. Furthermore, as functional components of the integrated control unit 12050, a microcomputer 12051, a sound / image output unit 12052, and an in-vehicle network interface (I / F) 12053 are shown.

[0166] The drive system control unit 12010 controls the operation of devices related to the vehicle's drive system according to various programs. For example, the drive system control unit 12010 is used as a control device for such as a drive force generating device for generating drive force for a vehicle such as an internal combustion engine or a drive motor, a drive force transmission mechanism for transmitting drive force to the wheels, a steering mechanism for adjusting the vehicle's steering angle, and a braking device for generating braking force for the vehicle.

[0167] The main system control unit 12020 controls the operation of various devices installed on the vehicle body according to various programs. For example, the main system control unit 12020 is used as a control device for keyless entry systems, smart key systems, power windows, or various lights such as headlights, taillights, brake lights, turn signals, and fog lights. In this case, radio waves transmitted from a portable device or signals from various switches, used instead of buttons, can be input to the main system control unit 12020. The main system control unit 12020 receives the input radio waves or signals and controls the vehicle's door locking devices, power windows, lights, etc.

[0168] The exterior information detection unit 12030 detects information related to the exterior of the vehicle, including information from the vehicle control system 12000. For example, the exterior information detection unit 12030 is connected to the imaging unit 12031. The exterior information detection unit 12030 causes the imaging unit 12031 to capture images of the exterior of the vehicle and receives the captured images. Based on the received images, the exterior information detection unit 12030 can perform processing such as detecting objects like people, cars, obstacles, signs, and text on the road, or detecting their distance.

[0169] The imaging unit 12031 is an optical sensor that receives light and outputs an electrical signal corresponding to the amount of light received. The imaging unit 12031 can output an electrical signal as an image, or it can output an electrical signal as information related to the measured distance. In addition, the light received by the imaging unit 12031 can be visible light, or it can be invisible light such as infrared light.

[0170] The in-vehicle information detection unit 12040 detects information related to the interior of the vehicle. For example, the in-vehicle information detection unit 12040 is connected to a driver state detection unit 12041 that detects the driver's state. For example, the driver state detection unit 12041 includes a camera that captures images of the driver. Based on the detection information input from the driver state detection unit 12041, the in-vehicle information detection unit 12040 can calculate the driver's fatigue level or concentration level, or determine whether the driver is asleep in a seated position.

[0171] The microcomputer 12051 can calculate control target values ​​for the drive force generating device, steering mechanism, or braking device based on information about the vehicle's interior and exterior obtained by the external information detection unit 12030 or the internal information detection unit 12040, and can output control commands to the drive system control unit 12010. For example, the microcomputer 12051 can perform coordinated control to realize the functions of an advanced driver assistance system (ADAS), including collision avoidance or collision mitigation, following distance-based driving, vehicle speed maintenance, vehicle collision warning, and vehicle lane departure warning.

[0172] In addition, the microcomputer 12051 can coordinate and control the drive force generating device, steering mechanism, braking device, etc., based on information about the exterior or interior of the vehicle obtained by the external information detection unit 12030 or the internal information detection unit 12040, so as to realize autonomous driving, where the vehicle drives itself without relying on the operation of the driver.

[0173] Furthermore, the microcomputer 12051 can output control commands to the main system control unit 12030 based on information about the vehicle's external environment obtained by the external information detection unit 12030. For example, the microcomputer 12051 can control the headlights according to the position of the vehicle in front or oncoming vehicles detected by the external information detection unit 12030 to perform coordinated control, thereby achieving glare prevention such as switching from high beams to low beams.

[0174] The audio / image output unit 12052 transmits at least one of audio and image output signals to an output device capable of visually or audibly informing vehicle occupants or the outside of the vehicle of information. In the example of FIG19, an audio speaker 12061, a display unit 12062, and a dashboard 12063 are shown as output devices. For example, the display unit 12062 may include at least one of an in-vehicle display and a head-up display.

[0175] Figure 20 is a diagram showing an example of the mounting position of the imaging unit 12031.

[0176] In Figure 20, the imaging unit 12031 includes imaging units 12101, 12102, 12103, 12104 and 12105.

[0177] Imaging units 12101, 12102, 12103, 12104, and 12105 are installed, for example, at the front of vehicle 12100, in the side mirrors, rear bumper, and rear door, as well as on the upper side of the windshield inside the vehicle. Imaging unit 12101 in the front of the vehicle and imaging unit 12105 on the upper side of the windshield inside the vehicle primarily acquire images of the front of vehicle 12100. Imaging units 12102 and 12103 in the side mirrors primarily acquire images of the sides of vehicle 12100. Imaging unit 12104 in the rear bumper or rear door primarily acquires images of the rear of vehicle 12100. Imaging unit 12105 on the upper side of the windshield inside the vehicle is mainly used to detect vehicles, pedestrians, obstacles, traffic signals, traffic signs, lanes, etc., ahead.

[0178] Incidentally, Figure 20 shows an example of the imaging range of imaging units 12101-12104. Imaging range 12111 represents the imaging range of imaging unit 12101 located at the front of the vehicle. Imaging ranges 12112 and 12113 represent the imaging ranges of imaging units 12102 and 12103 located in the side mirrors, respectively. Imaging range 12114 represents the imaging range of imaging unit 12104 located in the rear bumper or rear door. For example, by superimposing the image data captured by imaging units 12101-12104 onto each other, a bird's-eye view of the vehicle 12100 as seen from above is obtained.

[0179] At least one of the imaging units 12101 to 12104 may have the function of acquiring distance information. For example, at least one of the imaging units 12101 to 12104 may be a stereo camera composed of multiple imaging elements, or may be an imaging element having pixels for phase difference detection.

[0180] For example, based on distance information obtained from imaging units 12101-12104, microcomputer 12051 can determine the distance to each three-dimensional object within the imaging range 12111-12114 and the time change of that distance (relative speed relative to vehicle 12100), thereby extracting the three-dimensional object located on the driving path of vehicle 12100, particularly the closest three-dimensional object, that is traveling in approximately the same direction as vehicle 12100 at a predetermined speed (e.g., 0 km / h or more), as the vehicle ahead. Furthermore, microcomputer 12051 can set a pre-determined distance between vehicles in front of the vehicle ahead and can perform automatic braking control (including tracking stop control), automatic acceleration control (including tracking start control), etc. Therefore, coordinated control for autonomous driving, etc., aimed at autonomous vehicle operation without relying on driver operation, is possible.

[0181] For example, based on distance information obtained from imaging units 12101-12104, microcomputer 12051 can classify three-dimensional object data into three-dimensional object data of two-wheeled vehicles, ordinary vehicles, large vehicles, pedestrians, utility poles, and other three-dimensional objects, extract the classified three-dimensional object data, and use the extracted three-dimensional object data to automatically avoid obstacles. For example, microcomputer 12051 identifies obstacles around vehicle 12100 as obstacles that the driver of vehicle 12100 can visually recognize and obstacles that the driver of vehicle 12100 cannot visually recognize. Then, microcomputer 12051 determines the collision risk, indicating the degree of danger of collision with each obstacle. When the collision risk is equal to or higher than a set value and there is a possibility of collision, microcomputer 12051 outputs a warning to the driver via audio speaker 12061 and display unit 12062, or performs forced deceleration or evasive steering via drive system control unit 12010. Microcomputer 12051 can assist driving to avoid collisions.

[0182] At least one of the imaging units 12101-12104 can be an infrared camera that detects infrared light. For example, the microcomputer 12051 can identify a pedestrian by determining whether a pedestrian exists in the images captured by the imaging units 12101-12104. For example, pedestrian identification is performed by extracting feature points from the images captured by the imaging units 12101-12104, which are infrared cameras, and by performing pattern matching processing on a series of feature points indicating the outline of an object to determine whether the object is a pedestrian. When the microcomputer 12051 determines that a pedestrian exists in the images captured by the imaging units 12101-12104 and thereby identifies the pedestrian, the sound / image output unit 12052 controls the display unit 12062 to display a quadrilateral outline for emphasis, superimposed on the identified pedestrian. The sound / image output unit 12052 can also control the display unit 12062 to display an icon or similar indicating the pedestrian at a desired location.

[0183] Examples of vehicle control systems to which the technology according to this disclosure can be applied have been described above. For example, the technology according to this disclosure can be applied to the imaging unit 12031 in the above-described configuration. Specifically, the solid-state imaging device 1 according to this embodiment can be applied to the imaging unit 12031, etc. By applying the technology according to this disclosure to the imaging unit 12031, captured images that are easier to view can be obtained, thereby reducing driver fatigue.

[0184] <Examples of Applications of Endoscopic Surgical Systems>

[0185] The technology disclosed herein (the Technology) can be applied to a variety of products. For example, the Technology disclosed herein can be applied to endoscopic surgical systems.

[0186] Figure 21 is a diagram illustrating an example of a schematic configuration of an endoscopic surgical system to which the technology (the technology) according to an embodiment of the present disclosure can be applied.

[0187] Figure 21 illustrates a surgeon (physician) 11131 performing surgery on a patient 11132 on a bed 11133 using an endoscopic surgical system 11000. As shown, the endoscopic surgical system 11000 includes an endoscope 11100, other surgical instruments 11110 such as a pneumoperitoneum tube 11111 and an energy delivery device 11112, a support arm assembly 11120 supporting the endoscope 11100 thereon, and a trolley 11200 on which various devices for endoscopic surgery are mounted.

[0188] Endoscope 11100 includes a lens tube 11101 having a region at a predetermined distance distal to its end that is inserted into a body cavity of patient 11132, and a camera 11102 connected to the proximal end of the lens tube 11101. In the example shown in the figures, an endoscope 11100 comprising a rigid endoscope with a rigid lens tube 11101 is illustrated. However, endoscope 11100 may also include a flexible endoscope with a flexible lens tube 11101.

[0189] The lens tube 11101 has an opening at its distal end into which an objective lens is fitted. A light source device 11203 is connected to the endoscope 11100, such that light generated by the light source device 11203 is guided through a light guide extending inside the lens tube 11101 to the distal end of the lens tube, and then directed via the objective lens toward the object being observed within the body cavity of the patient 11132. Note that the endoscope 11100 can be a direct-viewing endoscope, or it can be an oblique-viewing endoscope or a side-viewing endoscope.

[0190] An optical system and an imaging element are housed inside the camera 11102, so that reflected light from the observed object (observation light) is focused onto the imaging element by the optical system. The observation light is photoelectrically converted by the imaging element to generate an electrical signal corresponding to the observation light, that is, an image signal corresponding to the observed image. The image signal is transmitted as RAW data to the camera control unit (CCU) 11201.

[0191] The CCU 11201 includes a central processing unit (CPU), a graphics processing unit (GPU), etc., and comprehensively controls the operation of the endoscope 11100 and the display device 11202. Furthermore, for example, the CCU 11201 receives image signals from the camera 11102 and performs various types of image processing, such as image processing (de-mosaic processing), to display an image based on the image signal.

[0192] The display device 11202 displays an image based on an image signal that has been image-processed by the CCU 11201 under the control of the CCU 11201.

[0193] For example, the light source device 11203 includes a light source such as a light-emitting diode (LED) and supplies illumination light to the endoscope 11100 when photographing the surgical area.

[0194] Input device 11204 is an input interface for endoscopic surgical system 11000. Users can input various types of information or commands into endoscopic surgical system 11000 via input device 11204. For example, users can input commands to change the imaging conditions of endoscope 11100 (type of illumination light, magnification, focal length, etc.).

[0195] The treatment device control unit 11205 controls the drive of the energy treatment device 11112 for purposes such as tissue cauterization or incision, and sealing of blood vessels. The pneumoperitoneum device 11206 injects gas into the patient's body cavity 11132 via the pneumoperitoneum tube 11111 to inflate the cavity, ensuring the field of vision of the endoscope 11100 and ensuring the surgeon's working space. The recorder 11207 is a device capable of recording various types of information related to the surgery. The printer 11208 is a device capable of printing various types of information related to the surgery in various formats such as text, images, and graphics.

[0196] Note that, for example, the light source device 11203 supplied to the endoscope 11100 when photographing the surgical area may include an LED, a laser light source, or a combination thereof as a white light source. In the case where the white light source includes a combination of red, green, and blue (RGB) laser light sources, the white balance adjustment of the captured image can be performed by the light source device 11203 because the output intensity and timing of each color (wavelength) can be controlled with high precision. Furthermore, in this case, if lasers from each RGB laser source are emitted onto the object of observation in a time-division manner and the driving of the imaging element of the camera 11102 is controlled synchronously with the emission timing, images corresponding to RGB colors can be captured in a time-division manner. According to this method, color images can be obtained even if a color filter is not provided for the imaging element.

[0197] Furthermore, the light source device 11203 can be controlled to change the intensity of the light to be output at various preset intervals. By controlling the driving of the imaging element of the camera 11102 in sync with the timing of the change in light intensity to acquire and synthesize images in a time-segmented manner, high dynamic range images without underexposed shadows or overexposed highlights can be generated.

[0198] Furthermore, the light source device 11203 can supply light in a predetermined wavelength band corresponding to special light observation. In special light observation, for example, narrow-band imaging (narrow-band imaging) is performed by emitting light with a narrow band range compared to the illumination light used in ordinary observation (i.e., white light) by utilizing the wavelength dependence of light absorption in body tissues. Additionally, in special light observation, fluorescence observation is performed to obtain images from fluorescence generated by emitting excitation light. In fluorescence observation, for example, excitation light can be irradiated onto body tissue to observe fluorescence from the body tissue (autofluorescence observation), or a reagent such as indocyanine green (ICG) can be locally injected into the body tissue and excitation light corresponding to the fluorescence wavelength of the reagent can be emitted to obtain a fluorescence image. The light source device 11203 can supply narrow-band light and / or excitation light suitable for the aforementioned special light observation.

[0199] Figure 22 is a block diagram illustrating an example of the functional configuration of the camera 11102 and CCU 11201 shown in Figure 21.

[0200] Camera 11102 includes a lens unit 11401, an imaging unit 11402, a driving unit 11403, a communication unit 11404, and a camera control unit 11405. CCU 11201 includes a communication unit 11411, an image processing unit 11412, and a control unit 11413. Camera 11102 and CCU 11201 are connected via a transmission cable 11400 for communication with each other.

[0201] Lens unit 11401 is an optical system disposed at the connection portion with lens barrel 11101. Observation light received from the distal end of lens barrel 11101 is guided to camera 11102 and incident on lens unit 11401. Lens unit 11401 includes a combination of multiple lenses, including zoom lenses and focal lenses.

[0202] Imaging unit 11402 includes imaging elements. The number of imaging elements included in imaging unit 11402 can be one (single-plate type) or multiple (multi-plate type). When imaging unit 11402 is configured as multi-plate type, for example, image signals corresponding to each RGB are generated by the imaging elements, and a color image can be obtained by synthesizing the image signals. Alternatively, imaging unit 11402 can also be configured to have a pair of imaging elements for acquiring image signals for the right and left eyes for three-dimensional (3D) display. If 3D display is performed, the surgeon 11131 can more accurately grasp the depth of body tissue in the surgical site. Note that when imaging unit 11402 is configured as multi-plate type, multiple lens units 11401 are provided corresponding to each imaging element.

[0203] Furthermore, the imaging unit 11402 does not necessarily have to be mounted on the camera 11102. For example, the imaging unit 11402 can be mounted directly behind the objective lens inside the lens barrel 11101.

[0204] The drive unit 11403 includes an actuator, and under the control of the camera control unit 11405, moves the zoom lens and focus lens of the lens unit 11401 a predetermined distance along the optical axis. Therefore, the magnification and focus of the image captured by the imaging unit 11402 can be appropriately adjusted.

[0205] The communication unit 11404 includes a communication device for transmitting and receiving various types of information to and from the CCU 11201. The communication unit 11404 transmits image signals acquired from the imaging unit 11402 as RAW data to the CCU 11201 via the transmission cable 11400.

[0206] Additionally, the communication unit 11404 receives control signals from the CCU 11201 for controlling the camera 11102 and supplies these control signals to the camera control unit 11405. The control signals include information related to imaging conditions, such as information specifying the frame rate of the captured image, information specifying the exposure value during imaging, and / or information specifying the magnification and focus of the captured image.

[0207] Note that imaging conditions such as frame rate, exposure value, magnification, and focus can be appropriately specified by the user, or can be automatically set by the control unit 11413 of CCU 11201 based on the acquired image signal. In the latter case, the automatic exposure (AE) function, automatic focus (AF) function, and automatic white balance (AWB) function are integrated into the endoscope 11100.

[0208] The camera control unit 11405 controls the driving of the camera 11102 based on the control signal received from the CCU 11201 via the communication unit 11404.

[0209] The communication unit 11411 includes a communication device for transmitting and receiving various types of information to and from the camera 11102. The communication unit 11411 receives image signals transmitted from the camera 11102 via a transmission cable 11400.

[0210] In addition, the communication unit 11411 transmits control signals for controlling the camera 11102 to the camera 11102. Image signals and control signals can be transmitted via electrical communication, optical communication, etc.

[0211] The image processing unit 11412 performs various types of image processing on the image signal in RAW data form transmitted from the camera 11102.

[0212] The control unit 11413 performs various types of control related to imaging the surgical area, etc., via the endoscope 11100 and displaying the images captured by imaging the surgical area, etc. For example, the control unit 11413 generates control signals for controlling the drive of the camera 11102.

[0213] Furthermore, the control unit 11413 controls the display device 11202 to display captured images of the surgical area, etc., based on image signals that have already been processed by the image processing unit 11412. In this case, the control unit 11413 can identify various objects within the captured images using various image recognition techniques. For example, the control unit 11413 can detect the edge shape and / or color of objects contained in the captured images to identify surgical instruments such as forceps, specific living body sites, bleeding, fog when using the energy treatment device 11112, etc. When controlling the display device 11202 to display the captured images, the control unit 11413 can use the recognition results to make the display device 11202 display various types of surgical support information with images of the surgical area in an overlay manner. When surgical support information is displayed in an overlay and presented to the surgeon 11131, the burden on the surgeon 11131 can be reduced, and the surgeon 11131 can perform the surgery reliably.

[0214] The transmission cable 11400 that connects the camera 11102 and the CCU 11201 to each other is an electrical signal cable for communication of electrical signals, an optical fiber for communication of optical signals, or a composite cable for both electrical signals and optical communication.

[0215] Here, in the example shown in the attached figure, communication is performed via wired communication using transmission cable 11400, but communication between camera 11102 and CCU 11201 can be performed wirelessly.

[0216] Examples of endoscopic surgical systems to which the technology of this disclosure is applicable have been described above. For example, the technology of this disclosure can be applied to the endoscope 11100, the camera 11102 (imaging unit 11402), the CCU 11201 (image processing unit 11412), etc., as described above. Specifically, the solid-state imaging device 1 according to this embodiment can be applied to the imaging unit 10402. For example, by applying the technology of this disclosure to the imaging unit 10402, a clearer image of the surgical site can be obtained, allowing the surgeon to reliably examine the surgical site.

[0217] Note that although the endoscopic surgical system is used as an example here, the technology according to this disclosure can be applied to systems such as microscopic surgical systems.

[0218] Note that this technology can have the following configuration.

[0219] (1) A solid-state imaging device, comprising:

[0220] A photoelectric conversion element that generates an electric charge based on the amount of incident light;

[0221] Multiple conversion efficiency switching transistors perform switching to different photoelectric conversion efficiencies from one another;

[0222] Multiple floating diffusion regions, which respectively maintain at least a portion of the charge generated by the photoelectric conversion element according to the switching control of the multiple conversion efficiency switching transistors; and

[0223] A reset transistor that discharges the holding charge from the plurality of floating diffused regions to the reference voltage node.

[0224] The reset transistor discharges the holding charge of two or more of the plurality of floating diffusion regions to the reference voltage node without passing through the plurality of conversion efficiency switching transistors.

[0225] (2) The solid-state imaging device according to (1) further includes

[0226] Two or more charge transport regions that connect the reset transistor and each of the two or more floating diffusion regions.

[0227] (3) The solid-state imaging device according to (2), wherein

[0228] The reset transistor includes two or more sources, and

[0229] The two or more charge transport regions include two or more diffusion regions that connect the two or more sources and the two or more floating diffusion regions.

[0230] (4) The solid-state imaging device according to (2), wherein

[0231] The reset transistor includes two or more sources, and

[0232] At least one of the two or more charge transport regions includes two or more metal components that connect the two or more source electrodes and the two or more floating diffusion regions.

[0233] (5) The solid-state imaging device according to (4), wherein

[0234] The metal component includes:

[0235] A first contact member is connected to the source of the reset transistor;

[0236] The second contact member is connected to the floating diffusion region; and

[0237] A metal wiring layer that connects a first contact member and a second contact member at a height different from the height of the source of the reset transistor and the floating diffusion region.

[0238] (6) The solid-state imaging apparatus according to any one of (3) to (5), wherein

[0239] The reset transistor includes a single gate corresponding to the two or more sources.

[0240] (7) The solid-state imaging apparatus according to any one of (3) to (5), wherein

[0241] The reset transistor includes:

[0242] Two or more gates corresponding to the two or more sources and configured separately from each other; and

[0243] A metal component that enables the two or more gates to conduct to each other.

[0244] (8) The solid-state imaging apparatus according to any one of (1) to (7), wherein

[0245] The reset transistor includes two or more drains connected to the reference voltage node.

[0246] (9) The solid-state imaging apparatus according to any one of (1) to (7), wherein

[0247] The reset transistor includes a single drain connected to the reference voltage node.

[0248] (10) The solid-state imaging apparatus according to any one of (1) to (9) further includes

[0249] The transfer transistor sequentially transfers the charge photoelectrically converted by the photoelectric conversion element to the plurality of floating diffusion regions.

[0250] The reset transistor discharges the retained charge of two or more of the floating diffusion regions other than the floating diffusion region from which the transfer transistor initially transfers charge to the reference voltage node without passing through the plurality of conversion efficiency switching transistors.

[0251] (11) The solid-state imaging apparatus according to any one of (1) to (9) further includes

[0252] The transfer transistor transfers the charge photoelectrically converted by the photoelectric conversion element to the plurality of floating diffusion regions.

[0253] The reset transistor discharges the retained charge of two or more of the multiple floating diffusion regions, including the floating diffusion region that initially transferred charge from the transfer transistor, to the reference voltage node without passing through the multiple conversion efficiency switching transistors.

[0254] (12) The solid-state imaging apparatus according to any one of (1) to (11) further includes

[0255] A pixel having two or more of the aforementioned photoelectric conversion elements,

[0256] The plurality of floating diffusion regions includes two or more floating diffusion regions that retain the charge generated by the two or more photoelectric conversion elements, and

[0257] The reset transistor discharges the hold charge of the two or more floating diffusion regions to the reference voltage node without passing through other floating diffusion regions.

[0258] (13) The solid-state imaging device according to (12), wherein

[0259] The two or more photoelectric conversion elements have different light receiving areas.

[0260] (14) The solid-state imaging apparatus according to any one of (1) to (13) further includes:

[0261] A pixel, which, during a single exposure operation, alters its sensitivity by switching the multiple conversion efficiency switching transistors on or off, thereby outputting pixel signals multiple times; and

[0262] The signal processing unit converts the pixel signal into a digital signal and performs dual data sampling (DDS) to detect the difference between the signal level and the reset level of the pixel signal.

[0263] The pixel includes the photoelectric conversion element, the plurality of conversion efficiency switching transistors, the plurality of floating diffusion regions, and the reset transistor.

[0264] (15) The solid-state imaging apparatus according to any one of (1) to (13) further comprises:

[0265] A pixel, which, during a single exposure operation, alters its sensitivity by switching the multiple conversion efficiency switching transistors on or off, thereby outputting pixel signals multiple times; and

[0266] The signal processing unit converts the pixel signal into a digital signal and performs correlated double sampling (CDS) to detect the difference between the reset level and the signal level of the pixel signal.

[0267] The pixel includes the photoelectric conversion element, the plurality of conversion efficiency switching transistors, the plurality of floating diffusion regions, and the reset transistor.

[0268] (16) An electronic device comprising:

[0269] Solid-state imaging devices that generate images based on the amount of incident light; and

[0270] The processing unit processes the image.

[0271] The solid-state imaging device includes:

[0272] A photoelectric conversion element that generates an electric charge based on the amount of incident light;

[0273] Multiple conversion efficiency switching transistors perform switching to different photoelectric conversion efficiencies from one another;

[0274] Multiple floating diffusion regions, which respectively maintain at least a portion of the charge generated by the photoelectric conversion element according to the switching control of the multiple conversion efficiency switching transistors; and

[0275] A reset transistor that discharges the holding charge from the plurality of floating diffused regions to a reference voltage node, and

[0276] The reset transistor discharges the holding charge of two or more of the plurality of floating diffusion regions to the reference voltage node without passing through the plurality of conversion efficiency switching transistors.

[0277] This disclosure is not limited to the various embodiments described above, but includes various modifications that can be conceived by those skilled in the art, and the effects of this disclosure are not limited to the foregoing. In other words, various additions, changes, and partial deletions can be made without departing from the conceptual idea and spirit of this disclosure derived from the matters defined in the claims and their equivalents.

[0278] List of reference numerals

[0279] 1 Solid-state imaging device

[0280] 2 Imaging Lens

[0281] 3 Image Processing Department

[0282] 4. Records Department

[0283] 5. Control Department

[0284] 10 Electronic devices

[0285] 11-pixel array

[0286] 12 Vertical Drive Unit

[0287] 13 processing units

[0288] 14 Horizontal drive unit

[0289] 15 System Control Department

[0290] 16. Signal Processing Department

[0291] 17 Data Storage Department

[0292] 18 Output Section

[0293] 21 pixels

[0294] 22-pixel driver wiring

[0295] 24 Current Source

[0296] 28 comparators

[0297] 29 Counter

[0298] 31TG transistor

[0299] 32 RST transistors

[0300] 32a RST transistor

[0301] 32b RST transistor

[0302] 32c RST transistor

[0303] 32d1 First Drain

[0304] 32d2 Second Drain

[0305] 32g1 First Gate

[0306] 32g2 Second Gate

[0307] 32s1 First Source

[0308] 32s2 Second Source

[0309] 32s3 Third Source Pole

[0310] 33 AMP transistors

[0311] 34 SEL transistors

[0312] 35 FDG transistors

[0313] 36 FCG transistors

[0314] 37 FCG1 transistors

[0315] 41 Metal components

[0316] 42 Metal components

[0317] AA active area

[0318] AA1 Active Area

[0319] AA2 Active Area

[0320] C1 First charge holding section

[0321] C2 Second charge holding section

[0322] C3 Third charge holding part

[0323] FD floating diffusion region

[0324] FD1 First Floating Diffusion Region

[0325] FD2 Second Floating Diffusion Region

[0326] FD3 Third Floating Diffusion Region

[0327] FD4 Fourth Floating Diffusion Region

[0328] FDG1 RST transistor

[0329] FDG2 RST transistor

[0330] PD photoelectric conversion element

[0331] PD1 First photoelectric conversion element

[0332] PD2 Second Photoelectric Conversion Element

[0333] VSL Vertical Signal Line

Claims

1. A solid-state imaging device, comprising: A photoelectric conversion element that generates an electric charge based on the amount of incident light; Multiple conversion efficiency switching transistors perform switching to different photoelectric conversion efficiencies from one another; Multiple floating diffusion regions, which respectively maintain at least a portion of the charge generated by the photoelectric conversion element according to the switching control of the multiple conversion efficiency switching transistors to turn on or off; and a reset transistor that discharges the holding charge of the plurality of floating diffusion regions to a reference voltage node, wherein the reset transistor discharges the holding charge of two or more of the plurality of floating diffusion regions to the reference voltage node without passing through the plurality of conversion efficiency switching transistors.

2. The solid-state imaging device according to claim 1 further includes two or more charge transport regions connected to the reset transistor and each of the two or more floating diffusion regions.

3. The solid-state imaging device according to claim 2, wherein the reset transistor includes two or more sources, and the two or more charge transport regions include two or more diffusion regions connecting the two or more sources and the two or more floating diffusion regions.

4. The solid-state imaging device according to claim 2, wherein the reset transistor includes two or more sources, and at least one of the two or more charge transport regions includes two or more metal components connecting the two or more sources and the two or more floating diffusion regions.

5. The solid-state imaging device according to claim 4, wherein the metal component comprises: A first contact member is connected to the source of the reset transistor; A second contact member is connected to the floating diffusion region; A metal wiring layer, which connects the first contact member and the second contact member at a height different from the height of the source of the reset transistor and the floating diffusion region.

6. The solid-state imaging device of claim 3, wherein the reset transistor includes a single gate corresponding to the two or more sources.

7. The solid-state imaging device according to claim 3, wherein the reset transistor comprises: Two or more gates that correspond to the two or more sources and are configured separately from each other; And a metal component that enables the two or more gates to conduct to each other.

8. The solid-state imaging apparatus of claim 1, wherein the reset transistor includes two or more drains connected to the reference voltage node.

9. The solid-state imaging apparatus of claim 1, wherein the reset transistor includes a single drain connected to the reference voltage node.

10. The solid-state imaging apparatus of claim 1, further comprising a transfer transistor that sequentially transfers the charge photoelectrically converted by the photoelectric conversion element to the plurality of floating diffusion regions, wherein the reset transistor discharges the retained charge of two or more of the plurality of floating diffusion regions other than the floating diffusion region from which the transfer transistor initially transfers charge to the reference voltage node without passing through the plurality of conversion efficiency switching transistors.

11. The solid-state imaging apparatus of claim 1, further comprising a transfer transistor that transfers charge photoelectrically converted by the photoelectric conversion element to the plurality of floating diffusion regions, wherein the reset transistor discharges the retained charge of two or more of the plurality of floating diffusion regions, including the floating diffusion region from which the transfer transistor initially transferred charge, to the reference voltage node without passing through the plurality of conversion efficiency switching transistors.

12. The solid-state imaging apparatus of claim 1, further comprising a pixel having two or more of the photoelectric conversion elements, wherein the plurality of floating diffusion regions include two or more floating diffusion regions that retain the charge generated by the two or more photoelectric conversion elements, and the reset transistor discharges the retained charge of the two or more floating diffusion regions to the reference voltage node without passing through other floating diffusion regions.

13. The solid-state imaging device according to claim 12, wherein the two or more photoelectric conversion elements have different light-receiving areas.

14. The solid-state imaging device according to claim 1, further comprising: A pixel, in a single exposure operation, changes its sensitivity by switching the multiple conversion efficiency switching transistors on or off to output pixel signals multiple times. The signal processing unit converts the pixel signal into a digital signal and performs dual data sampling (DDS) to detect the difference between the signal level and the reset level of the pixel signal, wherein the pixel includes the photoelectric conversion element, the plurality of conversion efficiency switching transistors, the plurality of floating diffusion regions and the reset transistor.

15. The solid-state imaging device according to claim 1, further comprising: A pixel, in a single exposure operation, changes its sensitivity by switching the multiple conversion efficiency switching transistors on or off to output pixel signals multiple times. The signal processing unit converts the pixel signal into a digital signal and performs correlated double sampling (CDS) to detect the difference between the reset level and the signal level of the pixel signal, wherein the pixel includes the photoelectric conversion element, the plurality of conversion efficiency switching transistors, the plurality of floating diffusion regions and the reset transistor.

16. An electronic device comprising: A solid-state imaging device that generates an image based on the amount of incident light; A processing unit that processes the image, wherein the solid-state imaging device includes: a photoelectric conversion element that generates charge according to the amount of incident light; a plurality of conversion efficiency switching transistors that perform switching to different photoelectric conversion efficiencies; a plurality of floating diffusion regions that retain at least a portion of the charge generated by the photoelectric conversion element according to the switching control of the multiple conversion efficiency switching transistors; and a reset transistor that discharges the retained charge of the multiple floating diffusion regions to a reference voltage node, and the reset transistor discharges the retained charge of two or more of the multiple floating diffusion regions to the reference voltage node without passing through the multiple conversion efficiency switching transistors.

Images