Time interval measurement method and device, semiconductor test equipment and storage medium

Abstract

The invention is suitable for the technical field of semiconductor chip testing, and provides a time interval measuring method and device, semiconductor testing equipment and a storage medium, and the method comprises the steps: obtaining a measured start signal and a stop signal; counting the number of clock cycles spanned between the start signal and the stop signal through a system clock to obtain integer time; controlling the initial signal to be transmitted through a carry delay chain, latching the output of the carry delay chain at a trigger edge of a system clock, and counting the number of delay units at a preset level in a latching result; a delay lookup table is accessed, corresponding path time is looked up according to the number of delay units and the delay lookup table, decimal time is obtained, and the delay lookup table is predetermined based on a time sequence analysis result of the carry delay chain; and determining a time interval measurement result between the start signal and the stop signal according to the integer time and the decimal time. According to the scheme, the precision and stability of time interval measurement can be improved.

Description

Technical Field

[0001] This application belongs to the field of semiconductor chip testing technology, and particularly relates to a time interval measurement method, apparatus, semiconductor testing equipment and storage medium. Background Technology

[0002] Semiconductor testing equipment often requires high-precision measurement of the time interval between the start and stop signals of the measured signal. Existing time-to-digital converters (TD-SCDMA) mostly employ a combination of system clock counting and microstepping delay interpolation, where the microstepping delay typically relies on the internal delay structure of the programmable logic device (PLD). Because the internal delay of the device is affected by process technology, temperature, voltage, and layout routing, the linearity and consistency of the microstepping delay are difficult to guarantee, leading to nonlinear errors in the measurement results. Furthermore, achieving high accuracy often requires calibration and data processing, increasing the complexity of the testing process and resource consumption, which is detrimental to improving efficiency and stability in high-throughput testing scenarios. Summary of the Invention

[0003] In view of this, embodiments of this application provide a time interval measurement method, apparatus, semiconductor testing equipment, and storage medium, which can improve the accuracy and stability of time interval measurement and reduce the impact of nonlinear errors on test results without increasing the burden of complex calibration and data processing.

[0004] A first aspect of this application provides a time interval measurement method applied to a semiconductor testing device, wherein the semiconductor testing device includes at least a programmable logic unit, and the programmable logic unit is provided with a carry delay chain composed of multiple cascaded carry logic units; the method includes: Acquire the start and stop signals of the measured quantity; The number of clock cycles spanned between the start signal and the stop signal is counted using the system clock to obtain an integer time. The start signal is controlled to be transmitted via the carry delay chain. The output of the carry delay chain is latched on the trigger edge of the system clock, and the number of delay units at a preset level in the latch result is counted. Access the delay lookup table, find the corresponding path time based on the number of delay units and the delay lookup table, and obtain the decimal time. The delay lookup table is predetermined based on the timing analysis results of the carry delay chain and includes the mapping relationship between the number of delay units and the corresponding path time. The time interval measurement result between the start signal and the stop signal is determined based on the integer time and the fractional time.

[0005] In this embodiment, the start signal and stop signal to be measured are first acquired, and the number of clock cycles spanned between them is counted using the system clock to obtain an integer time. Therefore, the main part of the time interval can be obtained using the system clock cycle as the quantization unit, ensuring the measurement range. On this basis, the start signal is further controlled to be transmitted via a carry delay chain, and the output of the carry delay chain is latched at the trigger edge of the system clock. The number of delay units at a preset level in the latched result is counted, thereby converting the propagation position of the start signal within one clock cycle into a calculable subdivision. Subsequently, by accessing a delay lookup table predetermined based on the timing analysis result of the carry delay chain, the number of delay units is mapped to the corresponding path time to obtain a fractional time, so that the time part that is less than one clock cycle and cannot be quantized by the counter can be effectively characterized. Finally, the measurement result of the time interval between the start signal and the stop signal is determined based on the integer time and the fractional time. The above solution utilizes a carry delay chain in the programmable logic unit of a semiconductor test device, combined with a pre-defined delay lookup table, to achieve combined measurement of integer and fractional times. This can improve the accuracy and stability of time interval measurement without increasing the burden of complex calibration and data processing, and reduce the impact of nonlinear errors on test results.

[0006] In one possible implementation, the step of latching the output of the carry delay chain at the trigger edge of the system clock and counting the number of delay units at a preset level in the latch result includes: After the start signal enters the carry delay chain, the output of each tap of the carry delay chain is controlled to form a level state; At the trigger edge of the system clock, a flip-flop array is used to synchronously latch the output of each stage of the tap to obtain the latch code; The number of delay units is obtained by counting the bits in the latch code that are at a preset level.

[0007] In this embodiment, by synchronously latching and counting the preset level bits using a trigger array, the process of obtaining the number of delay units becomes clear and achievable, and the certainty of subdivision measurement is improved.

[0008] In one possible implementation, before the number of delay units at a preset level in the statistical latch result, the method further includes: Determine whether the latch code is a thermometer code with a bubbling function; When the latch code is a thermometer code with bubbling, the path times corresponding to each tap of the carry delay chain are sorted in ascending order to obtain the delay sorting result. The latch outputs of the trigger array are rearranged and mapped based on the delay sorting results; The number of delay units is obtained by counting the rearranged and mapped latch codes.

[0009] In this embodiment, by judging, sorting in ascending order and remapping the bubbling thermometer code, the impact of bubbling errors caused by non-monotonic delay on the number of delay units is reduced, thereby improving the reliability of fractional time calculation.

[0010] In one possible implementation, the access delay lookup table, which searches for the corresponding path time based on the number of delay units and the delay lookup table to obtain the decimal time, includes: Use the number of delay units as the index value; Read the path time corresponding to the index value from the delay lookup table; The path time read is output as the decimal time.

[0011] In this implementation, the method of "using the number of delay units as an index - looking up a table - outputting the path time" is adopted, which simplifies the logic of calculating decimal time and makes the delay conversion more direct.

[0012] In one possible implementation, the delay lookup table is predetermined based on the timing analysis results of the carry delay chain, including: Obtain data path information from the timing report of the programmable logic unit development tool; Extract the path delay from the start signal to each tap output and to the latch register; Perform differential operations on the path delays of adjacent taps to obtain the incremental delays at each stage; The incremental delays at each level are accumulated to generate a mapping relationship between the number of delay units and the path time, forming the delay lookup table.

[0013] In this embodiment, by extracting path delays from data path information and constructing a mapping relationship through differentiation and accumulation, the hierarchical delay of the carry delay chain can be refined to a smaller granularity, which is beneficial to improving the fractional time resolution capability.

[0014] In one possible implementation, the delay lookup table is predetermined based on the timing analysis results of the carry delay chain, including: Obtain the overall path delay of each carry logic unit in the carry delay chain; The overall path delay of each carry logic unit is taken as the delay amount of a delay unit, and a delay lookup table is constructed based on the delay amount, so that the delay lookup table includes the mapping relationship between the number of delay units and the corresponding path time.

[0015] In this implementation, a lookup table is constructed using the overall path delay of a single carry logic unit, providing an alternative with lower implementation complexity and facilitating rapid deployment in scenarios with lower accuracy requirements.

[0016] In one possible implementation, the step of counting the number of clock cycles spanned between the start signal and the stop signal using the system clock to obtain an integer time includes: Upon detection of the start signal, the counter is started and begins counting the system clock. The counter is stopped when the stop signal is detected. The integer time is obtained by multiplying the counter value by the system clock period.

[0017] In this implementation, a counting control method that uses start-triggered activation and stop-triggered deactivation avoids invalid counting and ensures that integer time counts are strictly aligned with start / stop events.

[0018] A second aspect of this application provides a time interval measurement device configured in a semiconductor testing apparatus, wherein the semiconductor testing apparatus includes at least a programmable logic unit, and the programmable logic unit is provided with a carry delay chain composed of multiple cascaded carry logic units; the device includes: The signal acquisition module is used to acquire the start and stop signals of the measured quantity. The integer time determination module is used to count the number of clock cycles spanned between the start signal and the stop signal using the system clock to obtain the integer time; The delay quantity determination module is used to control the transmission of the start signal through the carry delay chain, latch the output of the carry delay chain at the trigger edge of the system clock, and count the number of delay units at a preset level in the latch result. The fractional time determination module is used to access the delay lookup table, look up the corresponding path time according to the number of delay units and the delay lookup table, and obtain the fractional time. The delay lookup table is predetermined based on the timing analysis results of the carry delay chain and includes the mapping relationship between the number of delay units and the corresponding path time. The measurement result determination module is used to determine the measurement result of the time interval between the start signal and the stop signal based on the integer time and the fractional time.

[0019] A third aspect of the embodiments of this application provides a semiconductor testing device, including a memory, a processor, a programmable logic unit, and a computer program stored in the memory and executable on the programmable logic unit; The programmable logic unit is provided with a carry delay chain consisting of multiple cascaded carry logic units, and a delay lookup table is provided. The delay lookup table is predetermined based on the timing analysis results of the carry delay chain and includes a mapping relationship between the number of delay units and the corresponding path time. When the programmable logic unit executes the computer program, it is used to implement the method described in the first aspect above.

[0020] A fourth aspect of this application provides a computer-readable storage medium storing a computer program that, when executed by a processor, implements the method described in the first aspect above.

[0021] A fifth aspect of this application provides a computer program product that, when run on a semiconductor testing device, causes the semiconductor testing device to perform the method described in the first aspect.

[0022] For the beneficial effects of the second to fifth aspects mentioned above, please refer to the first aspect mentioned above, which will not be repeated here. Attached Figure Description

[0023] To more clearly illustrate the technical solutions in the embodiments of this application, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0024] Figure 1 This is a flowchart illustrating a time interval measurement method provided in an embodiment of this application; Figure 2 This is a schematic diagram illustrating the principle of the time interval measurement method provided in the embodiments of this application; Figure 3 This is a schematic diagram of the structure of a time interval measuring device provided in an embodiment of this application; Figure 4 This is a schematic diagram of the structure of a semiconductor testing device provided in an embodiment of this application. Detailed Implementation

[0025] In the following description, specific details such as particular system architectures and techniques are set forth for illustrative purposes and not for limitation, in order to provide a thorough understanding of the embodiments of this application. However, those skilled in the art will understand that this application may also be implemented in other embodiments without these specific details. In other instances, detailed descriptions of well-known systems, apparatuses, circuits, and methods have been omitted so as not to obscure the description of this application with unnecessary detail.

[0026] It should be understood that, when used in this application specification and the appended claims, the term "comprising" indicates the presence of the described features, integrals, steps, operations, elements and / or components, but does not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components and / or a collection thereof.

[0027] It should also be understood that the term “and / or” as used in this application specification and the appended claims means any combination of one or more of the associated listed items and all possible combinations, and includes such combinations.

[0028] As used in this application specification and the appended claims, the term "if" may be interpreted, depending on the context, as "when," "once," "in response to determination," or "in response to detection." Similarly, the phrase "if determined" or "if detected [the described condition or event]" may be interpreted, depending on the context, as meaning "once determined," "in response to determination," "once detected [the described condition or event]," or "in response to detection [the described condition or event]."

[0029] Furthermore, in the description of this application and the appended claims, the terms "first," "second," "third," etc., are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0030] It should be understood that the sequence number of each step in this embodiment does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of this application embodiment.

[0031] Semiconductor testing equipment often requires high-precision measurement of the time interval between the start and stop signals of the measured signal. Existing time-to-digital converters (TD-SCDMA) mostly employ a combination of system clock counting and microstepping delay interpolation, where the microstepping delay typically relies on the internal delay structure of the programmable logic device (PLD). Because the internal delay of the device is affected by process technology, temperature, voltage, and layout routing, the linearity and consistency of the microstepping delay are difficult to guarantee, leading to nonlinear errors in the measurement results. Furthermore, achieving high accuracy often requires calibration and data processing, increasing the complexity of the testing process and resource consumption, which is detrimental to improving efficiency and stability in high-throughput testing scenarios.

[0032] To address the aforementioned issues, this application provides a time interval measurement method, apparatus, semiconductor testing equipment, and storage medium. In this method, the start signal and stop signal to be measured are first acquired, and the number of clock cycles spanned between them is counted using the system clock to obtain an integer time. This allows the main portion of the time interval to be obtained using the system clock cycle as the quantization unit, ensuring the measurement range. Furthermore, the start signal is controlled to be transmitted via a carry-delay chain, and the output of the carry-delay chain is latched at the trigger edge of the system clock. The number of delay units at a preset level in the latched result is counted, thereby converting the propagation position of the start signal within one clock cycle into a calculable subdivision. Subsequently, by accessing a delay lookup table predetermined based on the timing analysis results of the carry-delay chain, the number of delay units is mapped to the corresponding path time to obtain a fractional time, enabling the portion of time less than one clock cycle that cannot be quantized by the counter to be effectively characterized. Finally, the time interval measurement result between the start signal and the stop signal is determined based on the integer time and the fractional time. The above solution utilizes a carry delay chain in the programmable logic unit of a semiconductor test device, combined with a pre-defined delay lookup table, to achieve combined measurement of integer and fractional times. This can improve the accuracy and stability of time interval measurement without increasing the burden of complex calibration and data processing, and reduce the impact of nonlinear errors on test results.

[0033] The time interval measurement method, apparatus, semiconductor testing equipment, storage medium, and computer program provided in the embodiments of this application will be described in detail below with reference to the accompanying drawings.

[0034] See Figure 1 The diagram shows a flowchart of a time interval measurement method provided in an embodiment of this application. The method is applied to a semiconductor testing device, which includes at least a programmable logic unit and a carry delay chain composed of multiple cascaded carry logic units.

[0035] like Figure 1 As shown, the method may include the following steps: Step 101: Obtain the start signal and stop signal of the measured signal.

[0036] It should be noted that the semiconductor test equipment in this application embodiment is a test platform used to perform functional and parameter tests on the semiconductor device under test. It typically has signal excitation, signal acquisition, and timing measurement capabilities, used to acquire the timing-related signals to be measured during the test and output the corresponding test results. The programmable logic unit (PLU) is a programmable hardware computing and timing processing unit (e.g., a Field-Programmable Gate Array (FPGA)) located in the semiconductor test equipment, used to perform timing control, edge capture, and subsequent time interval measurement processing on the signals acquired / generated during the test.

[0037] In this embodiment, the start signal is an event signal used to indicate the beginning of the measured time interval. It can be a trigger edge generated by a test stimulus, a target edge of the output signal of the device under test, or a signal corresponding to a start event defined in the test procedure. The start signal is used to identify the start time of the time interval measurement. The stop signal is an event signal used to indicate the end time of the measured time interval. It can be a response edge to the start event, another target edge of the output signal of the device under test, or a signal corresponding to a termination event defined in the test procedure. The stop signal is used to identify the end time of the time interval measurement.

[0038] In the specific execution of step 101, the semiconductor testing equipment can determine two event signals from the test channel to characterize the start and end points of the time interval according to the measurement object defined by the current test item, and input them as start and stop signals to the measurement interface of the programmable logic unit respectively. In one implementation, the programmable logic unit performs necessary level shaping and edge judgment on the input signals to ensure that the subsequent measurement process can stably identify the start and stop events, thereby completing the acquisition of the start and stop signals of the measured quantity.

[0039] Step 102: Count the number of clock cycles between the start signal and the stop signal using the system clock to obtain an integer time.

[0040] The system clock is a periodic clock signal used by semiconductor test equipment and its programmable logic unit to provide a unified time reference. Its period length can be used as the basic unit of time quantization to measure the order of events and the number of clock cycles spanned.

[0041] The number of clock cycles refers to the number of complete system clock cycles spanned from the start time indicated by the start signal to the end time indicated by the stop signal in a continuous cycle of the system clock. The number can be accumulated by a counter driven by the system clock.

[0042] In the specific execution of step 102 above, a counter is set in the programmable logic unit, and the system clock is used as the counting drive signal; when the start signal is detected, the counter is controlled to enter the counting state and start accumulating the system clock cycle from the preset initial value; during the counter is in the counting state, the counter value is updated once every system clock cycle; when the stop signal is detected, the counter is controlled to exit the counting state and latch the current count value to obtain the number of clock cycles spanned between the start signal and the stop signal; according to the correspondence between the latched number of clock cycles and the system clock cycle, the integer time is obtained.

[0043] In one possible implementation, the number of clock cycles spanned between the start signal and the stop signal is counted using the system clock to obtain an integer time, including: The counter is started and begins counting the system clock when the start signal is detected; The counter stops when a stop signal is detected. Multiply the counter value by the system clock cycle to obtain the integer time.

[0044] Specifically, when the target edge of the start signal is detected, the control logic sends a start command to the counter, causing the counter to be cleared or loaded with a preset initial value, and enters the counting state to accumulate the system clock pulses cycle by cycle. During the counting process, the counter updates its count value once every time the system clock reaches a trigger edge. When the target edge of the stop signal is detected, the control logic sends a stop command to the counter, causing the counter to exit the counting state and latch the current count value. Subsequently, the control logic reads the count value and multiplies the count value by the system clock cycle to obtain the integer time span between the start signal and the stop signal.

[0045] For example, if the system clock frequency is 200 MHz, then the system clock period is 5 nanoseconds. When a start signal is detected, the counter is started and begins counting the system clock. When a stop signal is detected, the counter is stopped and the count value is latched. If the latched count value is 40, then the integer time is 40 multiplied by 5 nanoseconds, which is 200 nanoseconds. This integer time is used as the integer part of the time interval measurement result in subsequent combination calculations.

[0046] Step 103: The control start signal is transmitted via the carry delay chain. The output of the carry delay chain is latched at the trigger edge of the system clock, and the number of delay units at the preset level in the latch result is counted.

[0047] In this embodiment, the carry delay chain is a delay structure set in a programmable logic unit. It is composed of multiple cascaded carry logic units and is used to make the input signal propagate along the chain step by step and form different propagation times at each level, thereby providing a multi-level delay state for subdividing time measurement.

[0048] The trigger edge of the system clock is the effective edge used by the system clock to trigger latching and counting, such as a rising edge or a falling edge. During the time interval measurement process, the trigger edge is used to determine the uniform time for sampling and latching the carry delay chain output.

[0049] Among them, the preset level is the target level state used for statistics. It can be either a high level or a low level. The semiconductor test equipment can preset the preset level according to the implementation requirements and count the number of delay units at that level in the latch result.

[0050] During the specific execution of step 103, when measuring the time interval, the programmable logic unit inputs the start signal to the input of the carry delay chain, causing the start signal to propagate step by step along the carry delay chain and form corresponding level states at the outputs of each stage of the carry delay chain. At the trigger edge of the system clock, the flip-flop array synchronously samples and latches the output levels of each stage of the carry delay chain to obtain a latched result reflecting the signal propagation state at the trigger edge. Subsequently, the statistics unit performs traversal or accumulation operations on the latched result to count the number of output bits at the preset level and obtain the number of delay units. This number of delay units is used in subsequent steps to obtain the fractional time in conjunction with the delay lookup table.

[0051] For example, after the start signal enters the carry delay chain, its level propagates along the chain step by step; when the system clock reaches the trigger edge, the flip-flop array latches the multi-level output of the carry delay chain, and the latching result may present a distribution pattern of "the first few bits are high level and the last few bits are low level"; when the statistical unit uses the high level as the preset level, it can count the number of high level bits in the latching result and output the number as the number of delay units to characterize the number of delay stages when the start signal arrives at the trigger edge.

[0052] In one possible implementation, the output of the carry delay chain is latched at the trigger edge of the system clock, and the number of delay units at a preset level in the latch result is counted, including: After the start signal enters the carry delay chain, the output of each tap of the carry delay chain is controlled to form a level state; At the trigger edge of the system clock, a flip-flop array is used to synchronously latch the output of each stage of the tap to obtain the latch code; The number of delay units is obtained by counting the bits in the latch code that are at a preset level.

[0053] Among them, each tap output refers to the output node led out at different cascade positions of the carry delay chain, which is used to reflect the level state at each node when the starting signal propagates step by step along the carry delay chain; different tap outputs correspond to different propagation delay positions, which can be used to form multi-level state information at the same sampling time.

[0054] Among them, the latch code is a multi-bit digital code latched by the trigger array at the trigger edge of the system clock. It is used to characterize the level distribution state of the output of each stage of the carry delay chain at the trigger moment. It can be represented as a thermometer code or a thermometer code with abnormal bits.

[0055] In this implementation, the programmable logic unit connects the start signal to the input of the carry delay chain, causing the start signal to propagate sequentially along the chain. As the start signal propagates, the outputs of each tap in the carry delay chain are driven to their corresponding levels. Subsequently, when the system clock reaches the trigger edge, the flip-flop array synchronously samples and latches the outputs of each tap at the same trigger moment to obtain the latch code. Finally, the statistics unit performs a counting operation on the latch code, counts the number of bits at the preset level, and outputs the counted number of bits as the number of delay units for use in the subsequent decimal time determination step.

[0056] For example, a carry delay chain has multiple tap outputs. When the initial signal enters the carry delay chain, its level propagates sequentially along the chain. At a certain system clock trigger edge, the flip-flop array simultaneously latches all tap outputs, and the resulting latch code may exhibit a distribution of "the first few bits are preset levels, and the last few bits are non-preset levels." Taking a high preset level as an example, if the number of high-level bits in the latch code is N, then the number of delay units output by the statistical unit is N, which is used to characterize the propagation level of the initial signal in the carry delay chain at that trigger moment.

[0057] In another possible implementation, before counting the number of delay units at a preset level in the latch result, the method further includes: Determine if the latch code is a thermometer code with a bubbling function; When the latch code is a thermometer code with bubbling, the path times corresponding to each tap of the carry delay chain are sorted in ascending order to obtain the delay sorting result. The latch outputs of the trigger array are rearranged and mapped based on the delay sorting results; The number of delay units is obtained by counting the latch codes after rearrangement and mapping.

[0058] The thermometer code is an ideal code type of multi-bit latch code. Its level distribution changes monotonically with the position of the signal propagation in the carry delay chain. It is usually expressed as "several consecutive bits before the preset level and several consecutive bits after the preset level", which is used to intuitively reflect the delay level of the signal propagation.

[0059] Bubbling thermometer code refers to non-ideal thermometer code where the actual delays corresponding to each tap of the carry delay chain do not meet the strict progressive relationship, resulting in partial reversals or breakpoints in the code pattern latched by the trigger array. For example, a code pattern with abnormal bits interspersed in a continuous segment, such as "000...01011111", appears. The abnormal bits can be regarded as "bubbling" and will interfere with the subsequent statistics of the delay level.

[0060] In this implementation, after the trigger array latches the outputs of each stage of the carry delay chain, a latch code is obtained. Then, the determination module detects the code pattern characteristics of the latch code to determine whether it is a bubbling thermometer code; for example, this can be done by detecting whether there are partial inversions, breaks, or discontinuities in the preset level segment of the latch code. When the determination result is a bubbling thermometer code, the sorting module sorts the path times of each tap in ascending order according to the path time corresponding to each tap of the carry delay chain, obtaining a delay sorting result. Based on this delay sorting result, the mapping module establishes a rearranged mapping relationship for the latch outputs of the trigger array, that is, rearranging the latch bits originally output according to the physical tap order according to the "path time from smallest to largest" order, or mapping the latch bits to the input of the statistics unit in this order. Finally, the statistics unit counts the bits at the preset level in the rearranged and mapped latch code to obtain the number of delay units, and uses this number of delay units for the subsequent decimal time lookup process.

[0061] For example, because the actual delay of each tap in the carry delay chain may not be strictly progressive, the latch code obtained after latching by the flip-flop array on a certain system clock trigger edge may be in the form of "000…01011111", that is, abnormal bits are mixed in the preset level segment that should be continuous, forming bubbles. In this case, the system first determines that the latch code is a thermometer code with bubbles; then it performs ascending sorting according to the path time of each tap to obtain the tap order consistent with the actual delay; then it rearranges and maps the latch outputs of the flip-flop array in this order, so that the mapped latch code is monotonically distributed according to the actual delay; finally, it counts the bits in the mapped latch code that are at the preset level to obtain the corresponding number of delay units, thereby reducing the impact of bubbles on the counting result.

[0062] Step 104: Access the delay lookup table, find the corresponding path time based on the number of delay units and the delay lookup table, and obtain the decimal time.

[0063] The delay lookup table is predetermined based on the timing analysis results of the carry delay chain and includes the mapping relationship between the number of delay units and the corresponding path time.

[0064] In this embodiment, the semiconductor testing equipment accesses a delay lookup table within a programmable logic unit, inputting the number of delay units as a lookup parameter into the lookup table unit. The lookup table unit locates the corresponding entry in the delay lookup table based on the number of delay units and reads the corresponding path time that matches the number of delay units. Subsequently, the read corresponding path time is output as a decimal time, which is used to perform subsequent combination calculations with an integer time to obtain the measurement result of the time interval between the start signal and the stop signal.

[0065] In one possible implementation, a delay lookup table is accessed, and the corresponding path time is looked up based on the number of delay units and the delay lookup table to obtain the decimal time, including: Use the number of delay units as the index value; Read the path time corresponding to the index value from the delayed lookup table; The path time read will be output as a decimal time.

[0066] Specifically, after obtaining the number of delay units, the lookup unit directly inputs the number of delay units as the index value and performs an index addressing operation in the delay lookup table; then, it reads the path time entry corresponding to the index value from the delay lookup table and outputs the read path time to the subsequent time calculation logic; finally, it outputs the path time as a decimal time so that it can be combined with the integer time to obtain the time interval measurement result.

[0067] In one possible implementation, the delay lookup table is predetermined based on the timing analysis results of the carry delay chain, including: Obtain data path information from the timing report of the programmable logic unit development tool; Extract the path delay from the start signal to each tap output and to the latch register; Perform differential operations on the path delays of adjacent taps to obtain the incremental delays at each stage; The incremental delays at each level are accumulated to generate a mapping relationship between the number of delay units and the path time, forming a delay lookup table.

[0068] In this embodiment, the timing report of the programmable logic unit development tool refers to the analysis result file generated by the development tool after the synthesis, placement and routing, and timing analysis of the target circuit of the programmable logic unit are completed, which is used to characterize the timing characteristics of the signal. The timing report includes at least data path information, which describes the logic units, interconnect resources and their corresponding path delays that the target signal passes through from the start point of the path to the end point of the path. It can also provide the propagation delay data of the target signal reaching the output of each tap and reaching the input of the latch register, thereby providing a basis for subsequently determining the path time and mapping relationship of the carry delay chain.

[0069] Among them, data path information refers to the signal propagation path and its corresponding delay information given by the programmable logic unit development tool in the timing report. It is used to characterize the actual propagation delay of the starting signal from the input end, through the taps of each stage of the carry delay chain, and to the latch register.

[0070] Path delay refers to the time consumed by the initial signal propagating along a specific path, including the propagation delay within the carry delay chain and the connection and latching path delay from the tap output to the latch register; path delay is used to subsequently calculate the incremental delay at each stage and determine the lookup table mapping relationship.

[0071] Incremental delay is the difference in path delay between two adjacent taps, used to characterize the time increment between adjacent delay stages in the carry delay chain; by accumulating the incremental delays of each stage, the path time corresponding to different numbers of delay units can be obtained.

[0072] Specifically, in this implementation, after the carry delay chain is built and synthesis and placement / routing are completed, the timing report output by the programmable logic unit development tool is obtained, and the data path information related to the start signal is read from it. Then, based on the data path information, the path delay from the start signal to the output of each tap of the carry delay chain, and the path delay from the output of each tap to the latch register are extracted. Next, the path delays corresponding to adjacent tap outputs are differentially calculated to obtain the incremental delays of each stage. Finally, the incremental delays of each stage are accumulated in order of delay stage to generate a mapping relationship between the number of delay units and the path time, and a delay lookup table is formed accordingly, which is used to convert the number of delay units into the corresponding path time during the measurement process.

[0073] For example, after using multiple carry logic units to form a carry delay chain, the timing report of the programmable logic unit development tool provides the delay information of the starting signal through each stage of the carry delay chain. Taking the first-stage tap output of the first carry logic unit as an example, the timing report can give the incremental delay from the starting signal to the tap output as 0.096ns, and the path delay from the tap output to the latch register as 0.054ns. Adding the two together gives the total path time from the starting signal to the latch register. Furthermore, since each carry logic unit has multiple stages of tap output (e.g., 8 stages), the above extraction, differential, and accumulation processes can be performed sequentially on each stage of the tap. When the carry delay chain is composed of multiple cascaded carry logic units (e.g., 64 cascaded carry logic units), the mapping relationship covering the number of multiple delay units can be statistically obtained, thereby forming a delay lookup table, which can be used to subsequently look up the corresponding path time by the number of delay units and output the decimal time.

[0074] In another possible implementation, the delay lookup table is predetermined based on the timing analysis results of the carry delay chain, including: Obtain the overall path delay of each carry logic unit in the carry delay chain; The overall path delay of each carry logic unit is taken as the delay amount of a delay unit, and a delay lookup table is constructed based on the delay amount, so that the delay lookup table includes the mapping relationship between the number of delay units and the corresponding path time.

[0075] For example, in one implementation, the carry delay chain is divided into multiple carry logic units, and the overall path delay of each carry logic unit is obtained through timing analysis. Assuming the overall path delay of a certain carry logic unit is T, T can be used as the delay amount of one delay unit. Further, when the number of delay units corresponding to the latched result is M, the path time TM corresponding to M can be read from the delay lookup table, and TM is output as a fractional time. Compared to establishing mapping relationships based on the taps of each level within the carry logic unit, this implementation uses the overall delay of the carry logic unit as the basic unit, which is convenient for estimation and implementation. However, its granularity is limited by the overall delay of the carry logic unit and cannot be further refined to the outputs of each level within the unit, resulting in relatively low time resolution.

[0076] Step 105: Determine the measurement result of the time interval between the start signal and the stop signal based on the integer time and the fractional time.

[0077] In this embodiment, after obtaining the integer time in step 102 and the fractional time in step 104, the time combination unit in the programmable logic unit reads the integer time and the fractional time, and performs a combination operation on them according to a preset time combination relationship to obtain the measurement result of the time interval between the start signal and the stop signal. In one implementation, the time combination unit merges the integer time and the fractional time to obtain a more refined time value, and outputs this time value as the measurement result of the time interval of this measurement to the result register of the semiconductor test equipment or the upper-level control module for subsequent test judgment, recording, or display.

[0078] Based on the above method embodiments, this application first acquires the start signal and stop signal to be measured, and counts the number of clock cycles spanned between them using the system clock to obtain an integer time. Therefore, the main part of the time interval can be obtained using the system clock cycle as the quantization unit, ensuring the measurement range. On this basis, the start signal is further controlled to be transmitted via a carry delay chain, and the output of the carry delay chain is latched at the trigger edge of the system clock. The number of delay units at a preset level in the latched result is counted, thereby converting the propagation position of the start signal within one clock cycle into a calculable subdivision quantity. Subsequently, by accessing a delay lookup table predetermined based on the timing analysis result of the carry delay chain, the number of delay units is mapped to the corresponding path time to obtain a fractional time, so that the time part that is less than one clock cycle and cannot be quantized by the counter can be effectively characterized. Finally, the measurement result of the time interval between the start signal and the stop signal is determined based on the integer time and the fractional time. The above solution utilizes a carry delay chain in the programmable logic unit of a semiconductor test device, combined with a pre-defined delay lookup table, to achieve combined measurement of integer and fractional times. This can improve the accuracy and stability of time interval measurement without increasing the burden of complex calibration and data processing, and reduce the impact of nonlinear errors on test results.

[0079] See Figure 2 The diagram illustrates the principle of the time interval measurement method provided in this application embodiment, which corresponds to... Figure 1 The flowchart shows the time interval measurement method.

[0080] Specifically, the method is applied to a semiconductor testing device, which includes at least a programmable logic unit. The programmable logic unit is configured with a computation time integer part unit for outputting the integer part time, a carry delay chain unit for subdividing the sub-cycle time, a counting unit for counting the latch code, a computation time fractional part unit for generating the fractional part time, and a time combination unit for synthesizing the final result.

[0081] Specifically, the measured start and stop signals are input into the integer part calculation unit. This unit counts the number of clock cycles spanned between the start and stop signals under the system clock reference, thereby obtaining the integer part of the time interval; the integer part of the time interval is calculated along... Figure 2 The path above is output to the time combination unit for subsequent combination.

[0082] Simultaneously, the initial signal is input to the carry-delay chain unit and propagates step-by-step along the carry-delay chain. The outputs of each tap of the carry-delay chain are latched at the trigger edge of the system clock, forming latched outputs representing the propagation position. This latched output serves as the input to the counting unit for the "output after the delay chain." The counting unit counts the delay units at a preset level in the latched result to obtain the "number of stages (number of delay units) the signal has passed through in the delay chain." Correspondingly, Figure 2 The following diagram also illustrates the source of the information "delay time of each stage in the delay chain": this information can be predetermined by the timing analysis results of the carry delay chain and form a delay lookup table, so that there is a mapping relationship between the number of delay units and the corresponding path time.

[0083] In the fractional part of the time interval, the "number of delay units" mentioned above is combined with the "delay time / delay lookup table for each stage of the delay chain" to find the path time corresponding to that number of delay units, thus obtaining the fractional part of the time interval; the fractional part of the time interval follows... Figure 2 The middle path output is sent to the time combination unit. Finally, the time combination unit performs a combination operation on the integer and fractional parts of the time, and outputs the final result. Figure 2 The “Final Timestamp” shown on the right is the time interval measurement result obtained in this application.

[0084] See Figure 3 The diagram shows a schematic of a time interval measuring device provided in an embodiment of this application. The device is configured in a semiconductor testing equipment, which includes at least a programmable logic unit. The programmable logic unit is provided with a carry delay chain composed of multiple cascaded carry logic units.

[0085] For ease of explanation, only the parts relevant to the embodiments of this application are shown.

[0086] The time interval measuring device 300 may specifically include: The signal acquisition module 301 is used to acquire the start signal and stop signal of the measured quantity; The integer time determination module 302 is used to count the number of clock cycles spanned between the start signal and the stop signal using the system clock to obtain the integer time; The delay quantity determination module 303 is used to control the transmission of the start signal through the carry delay chain, latch the output of the carry delay chain at the trigger edge of the system clock, and count the number of delay units at the preset level in the latch result. The fractional time determination module 304 is used to access the delay lookup table, look up the corresponding path time according to the number of delay units and the delay lookup table, and obtain the fractional time. The delay lookup table is predetermined based on the timing analysis results of the carry delay chain and includes the mapping relationship between the number of delay units and the corresponding path time. The measurement result determination module 305 is used to determine the measurement result of the time interval between the start signal and the stop signal based on the integer time and the fractional time.

[0087] In this embodiment of the application, the delay quantity determination module 303 may specifically include: The level output unit is used to control the output of each tap of the carry delay chain to form a level state after the start signal enters the carry delay chain; The latch unit is used to synchronously latch the output of each stage of the tap using a flip-flop array at the trigger edge of the system clock to obtain the latch code; The first counting unit is used to count the bits in the latch code that are at a preset level to obtain the number of delay units.

[0088] In this embodiment, the time interval measuring device 300 may further include: The determination unit is used to determine whether the latch code is a thermometer code with a bubbling function. The sorting unit is used to sort the path times corresponding to each tap of the carry delay chain in ascending order when the latch code is a thermometer code with bubbling, and to obtain the delay sorting result. The mapping unit is used to rearrange and map the latched outputs of the trigger array based on the delay sorting result; The second counting unit is used to count the rearranged and mapped latch codes to obtain the number of delay units.

[0089] In this embodiment of the application, the decimal time determination module 304 may specifically include: The index determines the unit, using the number of delay units as the index value; The read unit is used to read the path time corresponding to the index value from the delayed lookup table; The fractional time output unit is used to output the read path time as fractional time.

[0090] In this embodiment of the application, the decimal time determination module 304 may further include: The report acquisition unit is used to acquire data path information from the timing report of the programmable logic unit development tool; The delay extraction unit is used to extract the path delay from the start signal to the output of each tap and to the latch register; The differential operation unit is used to perform differential operations on the path delay output by adjacent taps to obtain the incremental delay at each stage; The delay accumulation unit is used to accumulate the incremental delays at each level, generate a mapping relationship between the number of delay units and the path time, and form a delay lookup table.

[0091] In this embodiment of the application, the decimal time determination module 304 may further include: The overall delay acquisition unit is used to acquire the overall path delay of each carry logic unit in the carry delay chain; The lookup table determination unit is used to treat the overall path delay of each carry logic unit as the delay amount of a delay unit, and to construct a delay lookup table based on the delay amount, so that the delay lookup table includes the mapping relationship between the number of delay units and the corresponding path time.

[0092] In this embodiment of the application, the integer time determination module 302 may specifically include: The clock counting unit is used to start the counter and begin counting the system clock when a start signal is detected; A counting stop unit is used to stop the counter when a stop signal is detected. The multiplication unit is used to multiply the counter value by the system clock cycle to obtain an integer time.

[0093] The time interval measuring device 300 provided in this application embodiment can be applied to the time interval measuring method provided in the foregoing embodiment. For details, please refer to the description of the time interval measuring method provided in the above embodiment, which will not be repeated here.

[0094] join Figure 4 This diagram illustrates the structure of a semiconductor testing device provided in an embodiment of this application. Figure 4 As shown, the semiconductor testing equipment 400 of this embodiment includes: at least one processor 410 ( Figure 4 (Only one is shown in the image), memory 420, programmable logic unit 430, and computer program 421 stored in the memory 420 and executable on the programmable logic unit 430, wherein the programmable logic unit 430 executes the computer program 421 to implement the above-mentioned time interval measurement method.

[0095] The semiconductor testing equipment 400 can be a server, physical server, or computing device, etc. This semiconductor testing equipment may include, but is not limited to, a processor 410, a memory 420, and a programmable logic unit 430. Those skilled in the art will understand that... Figure 4 This is merely an example of semiconductor test equipment 400 and does not constitute a limitation on semiconductor test equipment 400. It may include more or fewer components than shown, or combine certain components, or use different components.

[0096] The processor 410 can be a Central Processing Unit (CPU), but it can also be other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), discrete gate or transistor logic devices, discrete hardware components, etc. The general-purpose processor can be a microprocessor or any conventional processor.

[0097] In some embodiments, the memory 420 may be an internal storage unit of the semiconductor testing equipment 400, such as a hard disk or memory of the semiconductor testing equipment 400. In other embodiments, the memory 420 may be an external storage device of the semiconductor testing equipment 400, such as a plug-in hard disk, smart media card (SMC), secure digital (SD) card, flash card, etc., equipped on the semiconductor testing equipment 400. Furthermore, the memory 420 may include both internal and external storage units of the semiconductor testing equipment 400. The memory 420 is used to store operating systems, applications, bootloaders, data, and other programs, such as the program code of computer programs. The memory 420 can also be used to temporarily store data that has been output or will be output.

[0098] The programmable logic unit 430 can be an off-the-shelf field-programmable gate array (FPGA) or other programmable logic devices. The programmable logic unit is provided with a carry delay chain composed of multiple carry logic units cascaded together, and a delay lookup table is provided. The delay lookup table is predetermined based on the timing analysis results of the carry delay chain and includes the mapping relationship between the number of delay units and the corresponding path time.

[0099] In specific implementations, the processor 410, memory 420, programmable logic unit 430, and computer program 421 described in the embodiments of this application can execute the embodiments of the time interval measurement method of this application, which will not be repeated here.

[0100] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the above-described division of functional units and modules is merely an example. In practical applications, the above functions can be assigned to different functional units and modules as needed, that is, the internal structure of the device can be divided into different functional units or modules to complete all or part of the functions described above. The functional units and modules in the embodiments can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit. Furthermore, the specific names of the functional units and modules are only for easy differentiation and are not intended to limit the scope of protection of this application. The specific working process of the units and modules in the above system can be referred to the corresponding process in the foregoing method embodiments, and will not be repeated here.

[0101] In the above embodiments, the descriptions of each embodiment have different focuses. For parts that are not described in detail or recorded in a certain embodiment, please refer to the relevant descriptions of other embodiments.

[0102] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0103] In the embodiments provided in this application, it should be understood that the disclosed apparatus / semiconductor testing equipment and methods can be implemented in other ways. For example, the apparatus / semiconductor testing equipment embodiments described above are merely illustrative. For instance, the division of modules or units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the mutual coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between apparatuses or units may be electrical, mechanical, or other forms.

[0104] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0105] Furthermore, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0106] If the integrated module / unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, all or part of the processes in the methods of the above embodiments can also be implemented by a computer program instructing related hardware. The computer program can be stored in a computer-readable storage medium, and when executed by a processor, it can implement the steps of the various method embodiments described above. The computer program includes computer program code, which can be in the form of source code, object code, executable files, or certain intermediate forms. The computer-readable medium can include: any entity or device capable of carrying the computer program code, recording media, USB flash drives, portable hard drives, magnetic disks, optical disks, computer memory, read-only memory (ROM), random access memory (RAM), electrical carrier signals, telecommunication signals, and software distribution media, etc. It should be noted that the content included in the computer-readable medium can be appropriately added or removed according to the requirements of legislation and patent practice in the jurisdiction. For example, in some jurisdictions, according to legislation and patent practice, computer-readable media do not include electrical carrier signals and telecommunication signals.

[0107] The implementation of all or part of the processes in the methods of the above embodiments can also be accomplished by a computer program product. When the computer program product is run on a semiconductor testing device, the semiconductor testing device can implement the steps in the various method embodiments described above.

[0108] The embodiments described above are only used to illustrate the technical solutions of this application, and are not intended to limit it. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application, and should all be included within the protection scope of this application.

Claims

1. A method for measuring time intervals, characterized in that, The method is applied to semiconductor testing equipment, which includes at least a programmable logic unit, wherein the programmable logic unit is provided with a carry delay chain composed of multiple cascaded carry logic units; the method includes: Acquire the start and stop signals of the measured quantity; The number of clock cycles spanned between the start signal and the stop signal is counted using the system clock to obtain an integer time. The start signal is controlled to be transmitted via the carry delay chain. The output of the carry delay chain is latched on the trigger edge of the system clock, and the number of delay units at a preset level in the latch result is counted. Access the delay lookup table, find the corresponding path time based on the number of delay units and the delay lookup table, and obtain the decimal time. The delay lookup table is predetermined based on the timing analysis results of the carry delay chain and includes the mapping relationship between the number of delay units and the corresponding path time. The time interval measurement result between the start signal and the stop signal is determined based on the integer time and the fractional time.

2. The method as described in claim 1, characterized in that, The step of latching the output of the carry delay chain on the trigger edge of the system clock and counting the number of delay units at a preset level in the latch result includes: After the start signal enters the carry delay chain, the output of each tap of the carry delay chain is controlled to form a level state; At the trigger edge of the system clock, a flip-flop array is used to synchronously latch the output of each stage of the tap to obtain the latch code; The number of delay units is obtained by counting the bits in the latch code that are at a preset level.

3. The method as described in claim 2, characterized in that, Before the number of delay units at a preset level in the statistical latch result, the following is also included: Determine whether the latch code is a thermometer code with a bubbling function; When the latch code is a thermometer code with bubbling, the path times corresponding to each tap of the carry delay chain are sorted in ascending order to obtain the delay sorting result. The latch outputs of the trigger array are rearranged and mapped based on the delay sorting results; The number of delay units is obtained by counting the rearranged and mapped latch codes.

4. The method as described in claim 1, characterized in that, The access delay lookup table, based on the number of delay units and the corresponding path time in the lookup table, yields a decimal time, including: Use the number of delay units as the index value; Read the path time corresponding to the index value from the delay lookup table; The path time read is output as the decimal time.

5. The method as described in claim 1, characterized in that, The delay lookup table is predetermined based on the timing analysis results of the carry delay chain, including: Obtain data path information from the timing report of the programmable logic unit development tool; Extract the path delay from the start signal to each tap output and to the latch register; Perform differential operations on the path delays of adjacent taps to obtain the incremental delays at each stage; The incremental delays at each level are accumulated to generate a mapping relationship between the number of delay units and the path time, forming the delay lookup table.

6. The method as described in claim 1, characterized in that, The delay lookup table is predetermined based on the timing analysis results of the carry delay chain, including: Obtain the overall path delay of each carry logic unit in the carry delay chain; The overall path delay of each carry logic unit is taken as the delay amount of a delay unit, and a delay lookup table is constructed based on the delay amount, so that the delay lookup table includes the mapping relationship between the number of delay units and the corresponding path time.

7. The method according to any one of claims 1 to 6, characterized in that, The step of counting the number of clock cycles spanned between the start signal and the stop signal using the system clock to obtain an integer time includes: Upon detection of the start signal, the counter is started and begins counting the system clock. The counter is stopped when the stop signal is detected. The integer time is obtained by multiplying the counter value by the system clock period.

8. A time interval measuring device, characterized in that, The device is configured in a semiconductor testing equipment, the semiconductor testing equipment including at least a programmable logic unit, the programmable logic unit being provided with a carry delay chain composed of multiple cascaded carry logic units; the device includes: The signal acquisition module is used to acquire the start and stop signals of the measured quantity. The integer time determination module is used to count the number of clock cycles spanned between the start signal and the stop signal using the system clock to obtain the integer time; The delay quantity determination module is used to control the transmission of the start signal through the carry delay chain, latch the output of the carry delay chain at the trigger edge of the system clock, and count the number of delay units at a preset level in the latch result. The fractional time determination module is used to access the delay lookup table, look up the corresponding path time according to the number of delay units and the delay lookup table, and obtain the fractional time. The delay lookup table is predetermined based on the timing analysis results of the carry delay chain and includes the mapping relationship between the number of delay units and the corresponding path time. The measurement result determination module is used to determine the measurement result of the time interval between the start signal and the stop signal based on the integer time and the fractional time.

9. A semiconductor testing device, characterized in that, Includes a memory, a processor, a programmable logic unit, and a computer program stored in the memory and executable on the programmable logic unit; The programmable logic unit is provided with a carry delay chain consisting of multiple cascaded carry logic units, and a delay lookup table is provided. The delay lookup table is predetermined based on the timing analysis results of the carry delay chain and includes a mapping relationship between the number of delay units and the corresponding path time. When the programmable logic unit executes the computer program, it is used to implement the method as described in any one of claims 1 to 7.

10. A computer-readable storage medium storing a computer program, characterized in that, When the computer program is executed by a processor, it implements the method as described in any one of claims 1 to 7.

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