Rocket-borne comprehensive control system of reusable carrier rocket

Abstract

The invention belongs to the technical field of avionics control of carrier rockets, and particularly relates to a rocket-borne comprehensive control system of a reusable carrier rocket. The system comprises at least two rocket-borne equipment units with different control functions, each rocket-borne equipment unit comprises a plurality of functional modules with different numbers, and the number of each functional module is set according to the control functions and load paths of the rocket-borne equipment units; wherein the communication among the functional modules to which each type of rocket-borne equipment unit belongs is completed through the MLVDS backboard bus, and the rocket-borne equipment units with different control functions are communicated with external equipment through the Powerlink external bus. According to the invention, the problem of insufficient control technology of the existing carrier rocket avionics system is effectively solved.

Description

Technical Field

[0001] This invention belongs to the field of launch vehicle avionics control technology, and particularly relates to an onboard integrated control system for a reusable launch vehicle. Background Technology

[0002] Existing launch vehicle avionics systems mainly employ two architectures: traditional distributed architecture and hybrid architecture. Driven by mega-constellation projects such as "StarNet," high-density rocket launches have become an inevitable trend in the industry, placing stringent requirements on the avionics system to achieve synergistic optimization of high reliability, rapid turnaround, and low cost.

[0003] Traditional distributed architectures have the following drawbacks: • Numerous products: Each functional module is designed independently, resulting in a surge in the number of system components; • Complex cable layout: Discrete signal connection methods make the cable network large and chaotic; • Excessive system weight: Redundant connectors and cables significantly increase the load on the rocket body; • Difficulty in troubleshooting: Distributed fault points are difficult to locate and isolate quickly; • Low resource utilization: Computing power is scattered across various independent modules.

[0004] Hybrid architectures have the following drawbacks: • Difficult to upgrade and maintain: Any functional improvement requires the introduction of new hardware; • Extended R&D cycle: Hardware redesign led to a significant increase in development time; • Bus bandwidth bottleneck: The 1MHz bandwidth of the traditional 1553B bus is insufficient to meet the needs of large data transmission. • Cost control is difficult: hardware redundancy and dedicated designs lead to high manufacturing costs; • Limited scalability: Fixed architectures are difficult to adapt to future technological evolution and task changes.

[0005] In traditional distributed architectures, functional modules such as navigation, guidance and control, drive control, data management, telemetry, self-destruct safety, power supply and distribution, and timing and pyrotechnics management operate independently, interconnecting and communicating via discrete signals and analog buses (such as the 1553B). While this architecture achieves functional separation, it leads to a series of engineering problems, including a large number of products, complex cable layouts, excessive system weight, and difficulties in troubleshooting.

[0006] Through continuous optimization, some advanced avionics systems have shifted to a hybrid architecture, integrating guidance, data management, and some information acquisition functions around a core processor, while distributing remote interface units throughout the rocket body. However, the hybrid architecture still suffers from problems such as dispersed computing power, low system resource utilization, and difficulty in meeting the stringent data processing efficiency requirements of high-density launches.

[0007] System upgrade difficulties are a common pain point for existing avionics systems. Any functional improvement may require the introduction of new hardware, leading to extended development cycles and increased costs. In particular, the lack of a high-bandwidth system bus makes it difficult to cope with the surge in data volume from new rockets, limiting further improvements in system performance and hindering the support of advanced functions such as real-time image transmission and health status big data feedback. Summary of the Invention

[0008] The purpose of this invention is to provide a reusable launch vehicle integrated control system to solve the technical problems of various defects in the architecture of existing launch vehicle avionics systems.

[0009] This invention provides an onboard integrated control system for a reusable launch vehicle, comprising at least two onboard equipment units with different control functions. Each onboard equipment unit includes several functional modules of varying quantities, and the number of each functional module is set according to the control function and load path of the onboard equipment unit. The communication between the functional modules of each type of rocket-borne equipment unit is accomplished through the MLVDS backplane bus, and the rocket-borne equipment units with different control functions communicate with external devices through the Powerlink external bus. The aforementioned functional modules include a power supply module, a processor module, a timing module, a motor drive module, a converter acquisition and editing module, and a data integration module. The power module, the processor module, and the timing module all adopt a triple-redundancy architecture layout strategy. Both the motor drive module and the converter acquisition module adopt a dual-redundancy architecture layout strategy. The data integration module adopts a partially redundant architecture layout strategy.

[0010] In some embodiments, the power module constructs the triple redundancy architecture by connecting three independent and identically configured first welding circuits in parallel. The processor module constructs the triple redundancy architecture by connecting three independent and identically configured second welding circuits in parallel. The timing module constructs the triple redundancy architecture by connecting three independent and identically configured third welding circuits in parallel. The motor drive module constructs the dual redundancy architecture by hot-backup switching between two independent and identically configured fourth welding circuits. The converter acquisition module constructs the dual-redundancy architecture by connecting two independent and identical fifth welding circuits in parallel.

[0011] In some embodiments, communication between the functional modules to which each of the aforementioned onboard equipment units belongs is accomplished via the MLVDS backplane bus, including: The processor module is used as the main site; The power supply module, the timing module, the motor drive module, the converter acquisition and editing module, and the data integration module are used as slave stations; Communication between the master station and the slave station is achieved through three MLVDS backplane buses; wherein each MLVDS backplane bus independently serves each set of soldering circuits within the master station, and each set of soldering circuits corresponds to a redundancy.

[0012] In some embodiments, the processor module uses three sets of independent and identically configured second welding circuits to perform a two-out-of-three voting procedure to select output data or execute instructions. The timing module includes a control platform and a driver platform. The three redundancies constructed by the control platform correspond one-to-one with the three redundancies constructed by the processor module. After parsing the execution instructions of the processor module, the control platform controls the driver platform to implement a 2-out-of-5 MOSFET configuration and outputs five control signals to control the five MOSFETs. Specifically, the 2-out-of-5 MOSFET configuration includes five control signals or instructions for the five MOSFETs output by the control platform. The three redundancies constructed by the control platform are denoted as Redundancy 1, Redundancy 2, and Redundancy 3, where Redundancy 1 controls two MOSFETs, Redundancy 2 controls two MOSFETs, and Redundancy 3 controls one MOSFET. The two redundancies of the motor drive module interact with each other via the LVDS interface. Each redundancy acquires data or instructions from the three redundancies of the processor module and selects the acquired data or instructions by running a three-out-of-two voting procedure.

[0013] In some embodiments, the communication between the master station and the slave station via the three MLVDS backplane buses adopts the MLVDS bus instruction scheduling strategy.

[0014] In some embodiments, the instruction scheduling strategy of the MLVDS bus includes an initialization process and a self-test and identification process.

[0015] In some embodiments, the initialization process includes software reset after the MLVDS bus is powered on and MLVDS interface initialization; wherein, the MLVDS interface initialization includes register initialization and memory space clearing.

[0016] In some embodiments, the self-testing and identification process includes sending a self-testing instruction from the main site, identifying the site ID, performing a self-test on the site, and receiving the self-testing result instruction from the main site and then sending back the self-testing result.

[0017] In some embodiments, performing a self-test from the site includes: The power supply voltage is compared three times with the preset voltage value from the sampling backplane of the site. If the voltage exceeds the preset value, an error mark is made. The self-test interface status is obtained by comparing the initialization status of each interface read from the site with the preset values. The self-test results, including the error identifier and the self-test interface status, are fed back from the station to the master station via the MLVDS bus.

[0018] In some embodiments, the converter acquisition module includes an analog acquisition unit and a power conversion unit; the data integration module includes a bus unit and a digital serial interface unit.

[0019] This invention provides an integrated onboard control system for a reusable launch vehicle. Through modular design, the traditional "functional chimney" architecture is transformed into a "modular building block" structure, which reduces the number of system components, cables, and connectors. The MLVDS backplane bus bandwidth is 20 times higher than that of traditional buses, and the Powerlink external bus bandwidth is more than 100 times higher, meeting the requirements of high sampling rate telemetry and real-time image transmission. At the same time, the differentiated redundancy strategy achieves triple redundancy in the core functional domain, ensuring that the system can still operate stably under a first-degree failure, thus improving system reliability. Attached Figure Description

[0020] Figure 1 This is a schematic diagram of the onboard integrated control system of a reusable launch vehicle according to an embodiment of the present invention; Figure 2 This is an example diagram of the onboard integrated control system of a reusable launch vehicle according to an embodiment of the present invention; Figure 3 This is a connection diagram of the three redundancy modules in the triple redundancy architecture of this invention embodiment; Figure 4 This is a connection diagram of the two redundant modules in the dual-redundancy architecture of an embodiment of the present invention. Detailed Implementation

[0021] Various embodiments and features of this application are described herein with reference to the accompanying drawings.

[0022] It should be understood that various modifications can be made to the embodiments described herein. Therefore, the above description should not be considered as limiting, but merely as an example of embodiments. Other modifications within the scope and spirit of this application will be apparent to those skilled in the art.

[0023] The accompanying drawings, which are included in and form part of this specification, illustrate embodiments of the present application and, together with the general description of the present application given above and the detailed description of the embodiments given below, serve to explain the principles of the present application.

[0024] These and other features of this application will become apparent from the following description of preferred forms of embodiments given as non-limiting examples, with reference to the accompanying drawings.

[0025] It should also be understood that although this application has been described with reference to some specific examples, those skilled in the art can certainly implement many other equivalent forms of this application.

[0026] This invention aims to solve the following technical problems existing in the avionics systems of launch vehicles: 1. The reliability-cost balance problem: Traditional redundancy design often adopts a single redundancy strategy, which either leads to excessive redundancy and high costs, or insufficient redundancy and affects system reliability; 2. Low system integration: Dispersed functional modules result in a large number of products, complex cables, and heavy system weight; 3. Difficult to upgrade and maintain: The hardware platform is not unified, and functional improvements require redesigning the hardware, resulting in a long development cycle; 4. Data transmission bottleneck: Traditional bus bandwidth is limited, making it difficult to meet the needs of high-density large-volume data transmission. 5. Difficulty in rapid turnaround: The system deployment, testing, and maintenance processes are complex, making it difficult to achieve rapid launch and turnaround.

[0027] This invention provides an integrated onboard control system for a reusable launch vehicle, such as... Figure 1 As shown, the system includes at least two types of onboard equipment units with different control functions. Each type of onboard equipment unit includes several functional modules of different quantities. The number of each type of functional module is set according to the control function and load path of the onboard equipment unit. The communication between the functional modules of each type of rocket-borne equipment unit is accomplished through the MLVDS backplane bus, and the rocket-borne equipment units with different control functions communicate with external devices through the Powerlink external bus. Specifically, the system adopts a two-level high-speed bus architecture: Internal communication: Relying on the MLVDS high-speed backplane bus, the single channel rate is up to 200Mbps, and the single bus supports parallel communication of 32 nodes, which meets the low latency and high bandwidth data interaction between multiple modules. External Communication: Employing the Powerlink real-time industrial Ethernet bus, built on standard Ethernet hardware, it supports dual-rate adaptive speeds of 100Mbps / 1Gbps, offering over a hundred times the transmission capacity compared to the limited 1MHz bandwidth of the traditional 1553B bus. Powerlink's deterministic scheduling mechanism achieves microsecond-level time synchronization accuracy, ensuring flight control commands are delivered without jitter within strict time slots.

[0028] Crucially, this dual-level high-speed bus architecture is fully compatible with TSN (Time-Sensitive Networking) standards such as IEEE 802.1AS / 802.1Qbv at the physical layer, allowing for a smooth transition to TSN networks via firmware upgrades without the need for hardware replacement.

[0029] The aforementioned functional modules include a power supply module, a processor module, a timing module, a motor drive module, a converter acquisition and editing module, and a data integration module. The power module, the processor module, and the timing module all adopt a triple-redundancy architecture layout strategy. Both the motor drive module and the converter acquisition module adopt a dual-redundancy architecture layout strategy. The data integration module adopts a partially redundant architecture layout strategy.

[0030] It should be noted that the data integration module has a triple redundancy design in the power supply section, corresponds to the triple redundancy of the system in the bus interface section, and is a separate hardware platform in the data parsing and data caching sections.

[0031] In terms of hardware platform design, this architecture achieves a software-defined hardware model by unifying the hardware base and development ecosystem, as detailed below: Unified hardware platform: All functional modules are built on the same industrial-grade hardware platform and adopt a unified EDA toolchain and firmware development framework.

[0032] Processor compatibility: The standard computing platform uses the Xilinx Zynq-7000 series SoC, while the high-performance platform uses a combination of an independent high-performance ARM processor and a dedicated FPGA chip. The two processor modules are fully compatible in terms of physical interface, power timing, communication protocol and firmware API.

[0033] Zero-reconfiguration migration: Enables hardware-level interchange and zero-reconfiguration software migration, allowing performance upgrades to be completed without changing the backplane or firmware.

[0034] Compared with existing technologies, the technical solution of this invention transforms the traditional "functional chimney" architecture into a "modular building block" structure through modular design, reducing the number of system components, cables, and connectors. The MLVDS backplane bus bandwidth is 20 times higher than that of traditional buses, and the Powerlink external bus bandwidth is more than 100 times higher, meeting the requirements of high sampling rate telemetry and real-time image transmission. At the same time, the differentiated redundancy strategy achieves triple redundancy in the core functional domain, ensuring that the system can still operate stably under a first-degree failure, thus improving system reliability.

[0035] Specifically, such as Figure 1 and combined Figure 2 As shown, the core of this invention lies in constructing a modular system composed of six standardized functional modules: 1. Power supply module: It realizes the conversion from the primary power supply of 28V to the secondary power supply of +5V and ±15V, and adopts a triple redundancy independent design; 2. Processor Module: Employs Xilinx Zynq-7000 series SoC, integrating an ARM Cortex-A9 processing system and an Artix-7 FPGA logic unit, supporting a triple redundancy architecture; 3. Timing module: Designed with triple redundancy, implemented using the "FPGA minimum system + interface" approach, with the timing output interface employing a "five-transistor three-out-of-two" hardware voting circuit; 4. Motor drive module: Adopting a DSP and FPGA-based architecture, it supports dual-redundant winding control for permanent magnet synchronous motors and stepper motors; 5. Converter acquisition module: mainly includes analog signal acquisition and power conversion, and adopts a dual-redundancy design and heterogeneous calibration mechanism; 6. Data Integration Module: This module is responsible for integrating all types of data across the entire rocket. It uses an FPGA to acquire, store, and frame data from buses such as MLVDS, Powerlink, and RS422.

[0036] All functional modules adopt a standard 6U pluggable size and a unified backplane connector, enabling signal interconnection between modules through the backplane. The type and quantity of modules can be flexibly selected according to specific task requirements, achieving a flexible configuration of "one platform, multiple outputs".

[0037] It should be noted that this invention employs a design approach of "high reliability, high integration, and low cost" while maintaining system redundancy. For sequential modules, traditional solid-state relay (SSR) solutions are expensive and bulky. Now, a solid-state switch network is built using discrete MOSFETs and driver logic, which effectively reduces costs and facilitates high-density layout on printed circuit boards. A single 6U module can realize more sequential switches.

[0038] For the motor drive module, a single-chip integrated stepper motor driver is adopted. Each chip independently drives the A / B dual windings of one phase motor. It has built-in current sampling and closed-loop control, supports adaptive microstepping and dynamic current optimization, and has stall detection algorithm and multiple protection mechanisms for over-temperature, over-current and short circuit.

[0039] This solution reduces the number of components in traditional discrete drive circuits by 70%, compresses the PCB area by 50%, and achieves "drive as monitoring" through chip-level fault self-diagnosis, significantly reducing system complexity and maintenance costs.

[0040] like Figure 2 As shown, taking the first-stage flight control assembly and first-stage integrated controller of a reusable rocket as an example, the specific implementation of the present invention is illustrated. (Reference) Figure 1 It consists of six functional modules that can be freely combined to form a primary flight control assembly and a primary integrated controller.

[0041] The primary flight control system consists of the following modules: • 1 power supply module; • One processor module; • 2 timing modules; • One converter-based data acquisition module; • One data integration module; The primary integrated controller consists of the following modules: • 1 power supply module; • One processor module; • 3 timing modules; • 3 motor drive modules; • One converter-based data acquisition module; The number of functional modules can be expanded or reduced according to the overall function and load requirements, reflecting the flexibility of modular design.

[0042] visible Figure 2 As shown, through the flexible combination of modules, this invention forms two types of core integrated electronic single-unit devices: The first-level flight control unit integrates a power module, processor module, timing module, converter acquisition and editing module, and data integration module to realize core functions such as rocket guidance, attitude control, pyrotechnic timing control, telemetry data acquisition and integrated processing.

[0043] The primary integrated controller adds a motor drive module to the flight control assembly, providing thrust adjustment functionality for the rocket propulsion system and further improving the system's control accuracy and adaptability.

[0044] Both types of stand-alone units adopt a triple-redundant overall architecture. The power module contains three independent power supplies (5V1, 5V2, and 5V3), and the processor module has three computing platforms and external interfaces. The system communicates between internal modules through three MLVDS backplane buses and communicates with external devices (distributors, inertial navigation systems, servo controllers, etc.) through three Powerlink external buses.

[0045] Based on the above embodiments, the power module constructs the triple redundancy architecture by connecting three independent and identically configured first welding circuits in parallel; The processor module constructs the triple redundancy architecture by connecting three independent and identically configured second welding circuits in parallel. The timing module constructs the triple redundancy architecture by connecting three independent and identically configured third welding circuits in parallel. The motor drive module constructs the dual redundancy architecture by hot-backup switching between two independent and identically configured fourth welding circuits. The converter acquisition module constructs the dual-redundancy architecture by connecting two independent and identical fifth welding circuits in parallel.

[0046] This embodiment, based on the trade-offs of Functional Failure Mode and Effects Analysis (FMEA), adopts a differentiated redundancy architecture to achieve collaborative optimization of "high reliability, high integration, and low cost".

[0047] Specifically, the detailed design of each functional module is as follows: 1) The power module realizes the conversion from the primary power supply 28V to the secondary power supply +5V and ±15V. It realizes a triple redundant power supply on a 6U printed circuit board. The three power supplies are independent of each other and do not interfere with each other.

[0048] Circuit configuration: • Input protection: spike protection circuit, reverse connection protection circuit, surge voltage suppression circuit.

[0049] • Filtering circuit: EMI filtering circuit to suppress electromagnetic interference.

[0050] • Power conversion: DC / DC power conversion circuit, using domestic chip HDS150E24M05PNSG, input voltage range 18~40V, output 5V, 30A, output voltage adjustable, with undervoltage protection function.

[0051] • Status monitoring: Power failure indicator circuit monitors the power supply status in real time.

[0052] 2) The processor module adopts a triple-redundancy architecture, with three redundancies achieved by a single 6U board. It achieves core functions such as navigation, guidance, and control through internal and external bus communication. The core chip is the Xilinx automotive-grade ZYNQ7000 series chip, which integrates: Processing System (PS): 64-bit dual-core ARM Cortex-A9 processor, with a maximum clock speed of 1GHz; Programmable Logic (PL): Artix-7 FPGA logic units, the number of logic units is optional depending on the model; Internal bus: The PS and PL share the AXI bus, with a bandwidth of up to 1.2 GB / s; On-chip resources: on-chip memory, multi-port external memory interface, and rich peripheral interfaces.

[0053] Memory: External DDR3 memory for data caching.

[0054] Extended NOR FLASH for system boot and program storage.

[0055] MLVDS interface: Implemented by FPGA, using UART IP core, external MLVDS interface chip, supporting a rate of 200Mbps, and the communication protocol is software defined.

[0056] LVDS interface: It adopts a five-wire system and is implemented using the LVDS electrical interface provided by the processor PL and the internal serialization / deserialization IP core.

[0057] Powerlink bus: adopts a star redundant topology, implements the Ethernet protocol stack with open source IP cores, and connects to TI's DP83822 PHY chip and network transformer, with a transmission rate of 100 / 1000Mbps adaptive.

[0058] RS422 interface: 12 mutually isolated RS422 transceiver circuits, with the bus protocol implemented by PL, and the interface chip selected is TI's ADM2867 isolated RS422 transceiver.

[0059] CAN bus: One CAN bus serves as the ground communication interface, utilizing the interface resources built into the processor chip's PS side.

[0060] Debugging interface: Supports JTAG, serial port and network debugging development.

[0061] Synchronization mechanism: Implements hard synchronization between the three redundancies. Each of the three redundancies uses an independent clock and generates its own timer interrupt. The final synchronization interrupt signal is generated through a two-out-of-three voting method, achieving real-time synchronization between the three machines with a synchronization accuracy better than 1μs.

[0062] 3) The timing module is designed with triple redundancy, with each redundancy independent of the others. Each redundancy is implemented using the "FPGA minimum system + interface" approach. It receives timing instructions from the processor module via the MLVDS backplane bus and outputs them using a hardware 3-out-of-2 mode.

[0063] The timing module features a triple redundancy design, with one 6U board containing three FPGA chips, each operating independently.

[0064] Output interface: A "five-tube, three-out-of-two" hardware voting circuit is used to ensure output reliability.

[0065] Acquisition interface: Single-redundancy acquisition is adopted, and the acquired information is sent to the FPGA with three redundancies for processing.

[0066] Integration: A single 6U board enables 32-channel timing output and 32-channel timing feedback.

[0067] Drive capability: The timing output uses the BSZ096N10LS5 NMOS field-effect transistor, with an actual output capability of up to 62A. The 32-channel timing standard design meets the performance requirements of 24 channels with a normal output of 2A and a transient output of up to 10A@100ms, and 8 channels with a normal output of 4A and a transient output of up to 20A@100ms.

[0068] The 28V1 and 28V2 power supplies can be used separately or combined.

[0069] The timing outputs can be multiplexed to enhance drive capability.

[0070] The number of modules can be expanded according to task requirements.

[0071] 4) The motor drive module must have the control functions of both permanent magnet synchronous motor (hybrid ratio adjustment motor) and stepper motor (thrust adjustment motor). Both types of motors are designed with double redundant windings and operate in a cold backup mode.

[0072] Therefore, the entire board is designed with dual redundancy, corresponding to two sets of windings. Under normal circumstances, the second set of control is in a cold standby state, participating in instruction voting but not outputting anything.

[0073] After the processor decodes the instructions, it acquires the parameters of the synchronous motor, calculates the closed-loop control algorithm, and outputs a signal to control the synchronous motor's movement. The thrust adjustment module needs to implement functions such as instruction decoding, secondary power supply, feedback signal sampling, current and voltage signal sampling, resolver driving, telemetry uploading, control algorithm calculation, and motor driving. The stepper motor is controlled using TI's dedicated stepper motor driver ADN4680EBCPZ, which has integrated current detection, intelligent optimization technology, stall detection, and other functions, and the control strategy is easy to implement.

[0074] Combination Figure 2It is evident that the core flight control domain—including high-risk functional paths such as navigation, guidance, and attitude calculation—adopts a triple-redundancy architecture, encompassing power modules, processor modules, and timing modules, ensuring continuous and stable system operation even in the event of a single failure. The local execution and data acquisition domain—including control links such as motor drive and converter data acquisition—adopts a dual-redundancy architecture, significantly reducing hardware redundancy costs and system weight while ensuring functional availability.

[0075] Based on the above embodiments, communication between the functional modules of each type of onboard equipment unit is accomplished via the MLVDS backplane bus, including: The processor module is used as the main site; The power supply module, the timing module, the motor drive module, the converter acquisition and editing module, and the data integration module are used as slave stations; Communication between the master station and the slave station is achieved through three MLVDS backplane buses; wherein each MLVDS backplane bus independently serves each set of soldering circuits within the master station, and each set of soldering circuits corresponds to a redundancy.

[0076] As can be seen, the overall system of this invention adopts a triple-redundant overall architecture: 1. Power System: Each power module contains three completely independent power systems, labeled 5V1, 5V2, and 5V3 respectively. Each power system supplies power to the corresponding redundant functional modules.

[0077] 2. Processor System: Three computing platforms and external interfaces are distributed on a single processor module, located in redundancy 1, redundancy 2, and redundancy 3 respectively.

[0078] 3. Internal bus: Three MLVDS backplane buses serve as communication channels between various modules within the machine, with each bus independently serving a redundancy.

[0079] 4. External Bus: Three Powerlink external buses communicate with external devices (including power distributors, inertial measurement units, servo controllers, etc.), with one external bus corresponding to each redundancy.

[0080] In other words, the processor module acts as the protocol host, communicating with other modules via the MLVDS bus. The Powerlink bus interface is located on the processor module, corresponding to three redundancies, and can act as either a master (MN) or a slave (CN) depending on the system configuration. The backplane enables signal interconnection between the various functional modules, using a 200Mbps MLVDS high-speed backplane bus to achieve communication between the master node (processor module) and slave nodes (other functional modules), including command transmission and data exchange.

[0081] Bus configuration: The backplane provides three redundant MLVDS buses.

[0082] Connection method: Different connection methods are adopted for functional boards with different redundancy.

[0083] Based on the above embodiments, the processor module uses the three sets of independent and identically configured second welding circuits to construct three redundancies to run a two-out-of-three voting procedure to select output data or execute instructions; The timing module includes a control platform and a drive platform. The three redundancies constructed by the control platform correspond one-to-one with the three redundancies constructed by the processor module. After parsing the execution instructions of the processor module, the control platform controls the drive platform to implement a 2-out-of-5-transistor configuration and outputs five control signals to control the five MOS transistors. It should be noted that the timing module's driving platform is implemented using a hardware five-transistor, three-out-of-two configuration. The five control signals or instructions of the five transistors are output by the control platform. The three redundancies constructed by the control platform are denoted as Redundancy 1, Redundancy 2, and Redundancy 3, respectively. Redundancy 1 controls two MOS transistors, Redundancy 2 controls two MOS transistors, and Redundancy 3 controls one MOS transistor.

[0084] The two redundancies of the motor drive module interact with each other via the LVDS interface. Each redundancy acquires data or instructions from the three redundancies of the processor module and selects the acquired data or instructions by running a three-out-of-two voting procedure.

[0085] It should be noted that, as Figure 3 As shown, the triple-redundancy architecture uses functional boards (such as power modules, processor modules, and timing modules) with triple redundancy design, and the connection method is as follows: The three redundancies are connected to the three redundancies of the processor via the backplane bus. The three bus systems operate independently, with no interference between them in terms of redundancy. Each redundancy operates independently, and faults do not affect each other.

[0086] like Figure 4 As shown, the dual-redundancy architecture uses dual-redundant functional boards. Taking the motor drive module as an example, that is, assuming... Figure 4 The redundancy of the other boards shown is the redundancy of the motor drive module, and the connection method is as follows: The redundancy 1 of the motor drive module communicates with the redundancy 1 of the processor module; The motor drive module redundancy 2 simultaneously receives information from processor modules redundancy 2 and 3; The three redundancy information are exchanged via the internal LVDS bus; The software uses a two-out-of-three voting system to achieve fault tolerance.

[0087] In other words, for dual-redundant functional boards, such as motor drive modules, the second redundancy receives information from the second and third redundancy of the processor module simultaneously. Then, the three redundancy information are exchanged through the internal LVDS bus, and the software performs a two-out-of-three vote to achieve fault tolerance.

[0088] Based on the above embodiments, the communication between the master station and the slave station through the three MLVDS backplane buses adopts the instruction scheduling strategy of the MLVDS bus.

[0089] Based on the above embodiments, the instruction scheduling strategy of the MLVDS bus includes an initialization process and a self-test and identification process.

[0090] It should be noted that the instruction scheduling strategy of the MLVDS bus is based on the following communication method and working mode.

[0091] Communication method: The master station and the slave station use response-based communication.

[0092] Operating mode: Half-duplex mode, the bus can only transmit data in one direction at a time.

[0093] Based on the above embodiments, the initialization process includes software reset after the MLVDS bus is powered on and MLVDS interface initialization; wherein, the MLVDS interface initialization includes register initialization and memory space clearing.

[0094] Specifically, the initialization process includes: Power-on reset: The MLVDS bus is first reset via software after power-on. Register initialization: Initialize all relevant registers; Zero out storage space: Write 0x0000 to all storage spaces.

[0095] Based on the above embodiments, the self-test and identification process includes sending a self-test command from the main site, identifying the site ID, performing a self-test on the site, and receiving the self-test result command from the main site and then sending back the self-test result.

[0096] Specifically, the self-checking and identification process includes: Self-test command sending: Send a self-test command (including ID number) from the master station to the slave station. Slave identification: After receiving the data, the slave station identifies whether it is its own ID; Perform self-test: The slave station performs a self-test, which includes three power supply voltage tests on each board and the initialization status of each interface. Result feedback: After receiving the self-test result instruction from the main station, the self-test result shall be fed back within the specified time.

[0097] Through this implementation, the system can autonomously identify the types and quantities of functional boards, and determine whether they are working properly, achieving intelligent system management and fault diagnosis.

[0098] Based on the above embodiments, the self-check of the slave station includes: The slave station samples the three power supply voltages on the backplane and compares them with the preset voltage values. If the preset voltage values are exceeded, an error flag is marked. The slave station reads the initialization status of each interface and compares it with the preset value to obtain the self-check interface status. The slave station feeds back the self-check results including the error flag and the self-check interface status to the master station through the MLVDS bus.

[0099] That is to say, the slave station samples the three power supply voltages on the backplane, compares them with the preset theoretical values, determines an error if the theoretical value threshold is exceeded, gives an error flag, and reads the initial status of each bus interface and compares it with the theoretical value. Finally, the above self-check results are fed back to the master station through the backplane MLVDS bus.

[0100] Based on the above embodiments, the commutation and acquisition module includes an analog quantity acquisition unit and a power conversion unit; the data integration module includes a bus unit and a digital serial interface unit.

[0101] Specifically, the commutation and acquisition module mainly includes two parts: analog quantity acquisition and power conversion. The main functions of analog quantity acquisition are anti-aliasing filtering, dual-channel acquisition, digital filtering, etc. The main function of the commutation part is to convert the secondary power supply of the whole machine into a three-time analog power supply for external sensors and converters.

[0102] The analog quantity acquisition part is divided into two parts according to the signal frequency: low speed (signal frequency, Fsig≤100Hz) and high speed (100Hz<Fsig≤8000Hz). Among them, there are 120 low-speed channels and 30 high-speed channels.

[0103] The overall design is of dual redundancy. All signals are acquired in dual channels, and the commutation part also adopts a dual-power supply design. And heterologous calibration is used for ADC self-check and fault isolation. A high-precision voltage reference chip REF3325 is used and directly sent into the idle channels of each AD7616, and sampling is performed at the end of each sampling cycle. Once the heterologous calibration error range exceeds the limit, operations such as switching redundancy are immediately performed.

[0104] The data integration module mainly includes a bus unit and a digital serial interface unit. It consists of an FPGA circuit, a power conversion and monitoring circuit, an MLVDS circuit, an Ethernet physical layer circuit, an RS422 interface circuit, an EEPROM circuit, a clock circuit, a data storage Flash, and a RAM.

[0105] The basic functions of the data synthesis module are all implemented by FPGA. The FPGA chip selected is the Xilinx XC7A200T-1FBG484I from the XC7A series. The XC7A series FPGA has abundant resources and is the core data processing chip of the data synthesis module, mainly performing the following functions: Protocol processing, data parsing, and data caching of the flight control unit's internal bus MLVDS interface; The Powerlink bus (star topology) CN link and application layer implementation listens to Powerlink bus data and caches the data; The Powerlink bus (ring topology) MN link and application layer implementation sends control commands (synchronization commands, forwarding internal bus-related commands) to other devices on the bus, receives data from other devices on the bus, and buffers the data; Implement synchronous and asynchronous RS-422 interface protocols, receive data from connected devices, and cache the data; The control power monitoring circuit monitors the voltage and current of the motherboard power supply and the converted power supply, and acquires voltage and current data. The frame format, bit rate, parallel delay and other parameters are received through the Powerlink bus interface and stored in the EEPROM. The parameters are read from the EEPROM each time the power is turned on, which serves as the basis for the operation of the data synthesis module. Perform parallel delay on specified data based on parallel delay parameters; Based on the frame format parameters, the data of each interface and the parallel acceptance data are comprehensively framed, and the telemetry PCM code stream is output to the transmitter and memory through the RS-422 interface. Control the Flash memory to erase and write data, and write telemetry data into the Flash memory for storage according to internal bus instructions.

[0106] Compared with existing technologies, the technical solution of this invention transforms the traditional "functional silo" architecture into a "modular building block" structure through modular design. This reduces the number of system components, cables, and connectors significantly. Simultaneously, a differentiated redundancy strategy achieves triple redundancy in the core functional domain, ensuring stable system operation even under a single fault, thus improving system reliability. In this application's technical solution, the 200Mbps bandwidth of the MLVDS backplane bus is 20 times higher than that of traditional buses, and the bandwidth of the Powerlink external bus is over 100 times higher than that of the 1553B, meeting the requirements of high sampling rate telemetry and real-time image transmission. Furthermore, the Powerlink deterministic scheduling mechanism achieves microsecond-level time synchronization accuracy, reducing control command transmission latency by 80%.

[0107] To facilitate understanding, the beneficial effects of the technical solution of this invention will be explained in further detail below.

[0108] Compared with the control technology of existing launch vehicle avionics systems, the present invention has the following advantages: 1. Technical effects: (1) Significantly improved reliability: The differentiated redundancy strategy achieves triple redundancy in the core functional domain, ensuring that the system can still operate stably under a first-degree failure, thus improving the system reliability.

[0109] (2) Enhanced data processing capabilities: The MLVDS backplane bus has a bandwidth of 200Mbps, which is 20 times higher than that of the traditional bus, and the Powerlink external bus has a bandwidth of more than 100 times higher than that of the 1553B, meeting the needs of high sampling rate telemetry and real-time image transmission.

[0110] (3) Improved system integration: Modular design transforms the traditional “functional chimney” architecture into a “modular building block” construction, reducing the number of system components, cables, and connectors.

[0111] (4) Real-time optimization: Powerlink deterministic scheduling mechanism achieves microsecond-level time synchronization accuracy, reducing control command transmission latency by 80%.

[0112] 2. Economic effects: (1) Reduced manufacturing costs: The unified hardware platform and highly integrated design reduce the manufacturing cost of a single machine by 35%.

[0113] (2) Reduced maintenance costs: Modular design and software-defined hardware reduce maintenance costs by 50% and spare parts inventory requirements by 70%.

[0114] (3) Shortened R&D cycle: The unified development framework and hardware compatibility shorten the R&D cycle of new products by 40%.

[0115] (4) Upgrade cost savings: The ability to migrate software with zero refactoring reduces system upgrade costs by 60%.

[0116] 3. Engineering applications: (1) Simplified testing process: Standardized interfaces and unified protocols simplify the testing process by 50%.

[0117] (2) Accelerated fault recovery: Modular replacement reduces the average fault recovery time from several hours to tens of minutes.

[0118] (3) Flexible system expansion: The modular architecture supports flexible expansion of functions to adapt to future task changes.

[0119] Those skilled in the art will understand that all or part of the steps of the methods described above can be implemented by a program instructing related hardware. The program can be stored in a readable storage medium, and when executed, the program includes one or a combination of the steps of the method implementation.

[0120] In the various embodiments of this application, the functional units can be integrated into a single processing module, or each unit can exist physically separately, or two or more units can be integrated into a single module. The integrated module can be implemented in hardware or as a software functional module. If the integrated module is implemented as a software functional module and sold or used as an independent product, it can also be stored in a readable storage medium. The storage medium can be a read-only memory, a disk, or an optical disk, etc.

[0121] In the description of this specification, the references to terms such as "one embodiment / mode," "some embodiments / modes," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment / mode or example is included in at least one embodiment / mode or example of this application. Furthermore, the described specific features, structures, materials, or characteristics may be combined in any suitable manner in one or more embodiments / modes or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments / modes or examples described in this specification, as well as the features of different embodiments / modes or examples.

[0122] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this application, "multiple" means at least two, such as two, three, etc., unless otherwise explicitly specified.

[0123] Those skilled in the art should understand that the above embodiments are merely for illustrative purposes and are not intended to limit the scope of this application. Those skilled in the art can make other changes or modifications based on the above disclosure, and these changes or modifications still fall within the scope of this application.

Claims

1. A reusable launch vehicle's integrated onboard control system, characterized in that, The system includes at least two different control functions of the onboard equipment unit. Each of the onboard equipment units includes several functional modules of different quantities. The number of each functional module is set according to the control function and load path of the onboard equipment unit. The communication between the functional modules of each type of rocket-borne equipment unit is accomplished through the MLVDS backplane bus, and the rocket-borne equipment units with different control functions communicate with external devices through the Powerlink external bus. The aforementioned functional modules include a power supply module, a processor module, a timing module, a motor drive module, a converter acquisition and editing module, and a data integration module. The power module, the processor module, and the timing module all adopt a triple-redundancy architecture layout strategy. Both the motor drive module and the converter acquisition module adopt a dual-redundancy architecture layout strategy. The data integration module adopts a partially redundant architecture layout strategy.

2. The system according to claim 1, characterized in that, The power module constructs the triple redundancy architecture by connecting three independent and identically configured first welding circuits in parallel. The processor module constructs the triple redundancy architecture by connecting three independent and identically configured second welding circuits in parallel. The timing module constructs the triple redundancy architecture by connecting three independent and identically configured third welding circuits in parallel. The motor drive module constructs the dual redundancy architecture by hot-backup switching between two independent and identically configured fourth welding circuits. The converter acquisition module constructs the dual-redundancy architecture by connecting two independent and identical fifth welding circuits in parallel.

3. The system according to claim 1, characterized in that, Communication between the functional modules of each type of onboard equipment unit is accomplished via the MLVDS backplane bus, including: The processor module is used as the main site; The power supply module, the timing module, the motor drive module, the converter acquisition and editing module, and the data integration module are used as slave stations; Communication between the master station and the slave station is achieved through three MLVDS backplane buses; wherein each MLVDS backplane bus independently serves each set of soldering circuits within the master station, and each set of soldering circuits corresponds to a redundancy.

4. The system according to claim 2, characterized in that, The processor module uses a two-out-of-three voting procedure built by the three independent and identically configured second welding circuits to select output data or execute instructions. The timing module includes a control platform and a driver platform. The three redundancies constructed by the control platform correspond one-to-one with the three redundancies constructed by the processor module. After parsing the execution instructions of the processor module, the control platform controls the driver platform to implement a 2-out-of-5 MOSFET configuration and outputs five control signals to control the five MOSFETs. Specifically, the 2-out-of-5 MOSFET configuration includes five control signals or instructions for the five MOSFETs output by the control platform. The three redundancies constructed by the control platform are denoted as Redundancy 1, Redundancy 2, and Redundancy 3, where Redundancy 1 controls two MOSFETs, Redundancy 2 controls two MOSFETs, and Redundancy 3 controls one MOSFET. The two redundancies of the motor drive module interact with each other via the LVDS interface. Each redundancy acquires data or instructions from the three redundancies of the processor module and selects the acquired data or instructions by running a three-out-of-two voting procedure.

5. The system according to claim 3, characterized in that, The communication between the master station and the slave station is achieved through the three MLVDS backplane buses, which adopt the instruction scheduling strategy of the MLVDS bus.

6. The system according to claim 5, characterized in that, The instruction scheduling strategy of the MLVDS bus includes an initialization process and a self-test and identification process.

7. The system according to claim 6, characterized in that, The initialization process includes software reset after the MLVDS bus is powered on and MLVDS interface initialization; wherein, the MLVDS interface initialization includes register initialization and memory space clearing.

8. The system according to claim 6, characterized in that, The self-test and identification process includes sending a self-test command from the main site, identifying the site ID, performing a self-test on the site, and receiving the self-test result command from the main site and then sending back the self-test result.

9. The system according to claim 8, characterized in that, The self-test performed from the site includes: The power supply voltage is compared three times with the preset voltage value from the sampling backplane of the site. If the voltage exceeds the preset value, an error mark is made. The self-test interface status is obtained by comparing the initialization status of each interface read from the site with the preset values. The self-test results, including the error identifier and the self-test interface status, are fed back from the station to the master station via the MLVDS bus.

10. The system according to claim 2, characterized in that, The converter acquisition module includes an analog signal acquisition unit and a power conversion unit; the data integration module includes a bus unit and a digital serial interface unit.

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