MIPI DSI host controller with advanced DPI

Abstract

The invention belongs to the technical field of display system interfaces, and particularly relates to an MIPI DSI host controller with an advanced DPI. The controller comprises an application layer, a protocol layer and a physical layer, an aDPI interface of the controller is compatible with a video mode and an adaptive command mode, and supports an AMBA APB bus to carry out internal register configuration and transmit a general command; the video mode and the self-adaptive command mode can work cooperatively or can be switched according to display requirements; the application layer receives pixel data from a processor from an aDPI interface and processes the pixel data, interface adaptation and clock domain isolation of a display data link before transmission are completed, and the processed pixel data are sent to the protocol layer; the protocol layer realizes data transmission with the physical layer through cooperative work of internal modules of the protocol layer; unification of high-performance full-screen refreshing and ultra-low power consumption local updating is achieved on a single framework, and an excellent power consumption and performance balancing scheme is provided for an embedded display system with specific requirements.

Description

Technical Field

[0001] This invention belongs to the field of display system interface technology, and specifically relates to a MIPI DSI host controller with advanced DPI. Background Technology

[0002] While existing MIPI DSI (Display Serial Interface) controllers are compatible with both MIPI DPI video mode and MIPI DSI (MIPI Display Bus Interface) command mode, and support configuration of their internal registers via the AMBA APB bus, they have several drawbacks, as follows:

[0003] 1. Its DSI architecture is limited by the mutual exclusion of the DPI and DBI interfaces, which means that the two modes cannot work at the same time.

[0004] 2. In DPI video mode, the DSI controller needs to continuously refresh the entire screen at a fixed frame rate. This mechanism has an inherent flaw: when the displayed content is only partially updated, the system still needs to perform a full-screen refresh, resulting in unnecessary power consumption and bandwidth waste.

[0005] 3. In DBI command mode, although the DSI controller can transmit a small amount of pixel data through the MIPI DCS (MIPI Display Command Set) command set, its transmission bandwidth is limited by the low clock rate of the DBI interface (the DPI clock can reach up to 250MHz, while the DBI clock is generally 41MHz).

[0006] In summary, there is an urgent need for a new MIPI DSI host controller that can address the inherent shortcomings of traditional MIPI DSI controllers in terms of mode mutual exclusion, partial refresh power consumption, and command mode bandwidth, thereby achieving a balance between high-performance full-screen refresh and ultra-low-power partial updates. This would provide an excellent power consumption and performance balance solution for embedded display systems with specific requirements. Summary of the Invention

[0007] To address the shortcomings of existing technologies, this invention proposes an advanced MIPI DSI host controller, comprising: an application layer, a protocol layer, and a physical layer; the controller's aDPI interface is compatible with both video mode and adaptive command mode, and supports internal register configuration and general command transmission via the AMBA APB bus; the video mode and adaptive command mode can be switched according to display requirements.

[0008] The application layer receives pixel data from the processor via the aDPI interface and processes it, completing the interface adaptation and clock domain isolation of the display data link before transmission, and then sends the processed pixel data to the protocol layer. The application layer includes an aDPI interface, an aDPI video signal format interface module, two asynchronous FIFO control modules, and an APB bus interface module. The two asynchronous FIFO control modules are the aDPI payload FIFO and the aDPI command FIFO, respectively.

[0009] The protocol layer receives pixel data sent by the application layer and realizes data transmission with the physical layer through the coordinated work of its internal modules. The protocol layer includes an error handling module, an ECC generation module, a CRC generation module, a data packet generation module, an ECC verification module, a CRC verification module, and a data packet decoding module.

[0010] The physical layer includes a physical layer interface controller finite state machine, data channel allocation control logic, a channel management module, a high-speed transmission channel module, and a low-speed transmission / reception channel module.

[0011] Preferably, in the application layer, the APB bus interface module serves as a configuration channel, receiving and temporarily storing pixel data parameters and display device configuration information from the processor via the APB bus;

[0012] The aDPI video signal format interface module serves as a data and control signal channel, receiving pixel data streams and their control signals generated by the image processing unit or other upstream modules; and is used for pixel format conversion and protocol mapping.

[0013] Two asynchronous FIFO control modules are used for cross-clock domain processing of pixel data and control signals, respectively.

[0014] Preferably, in the protocol layer, the data packet generation module receives pixel data from the application layer and encapsulates it into long packets or short packets conforming to the DSI standard;

[0015] The ECC generation unit generates ECC checksums for the packet header;

[0016] The CRC generation unit generates CRC checksums for the payload of long packets and places them into the end of the data packets.

[0017] The error handling module continuously monitors the status of the asynchronous FIFO control module and each module in the protocol layer. When an error is detected, the error handling module receives the abnormal information, raises the global error flag, and uses register toggling. It then reports the error flag signal to the upper-layer system, driving it to perform a retransmission operation.

[0018] The ECC verification module is used to verify the header of the DSI data packet read back from the display device. It has a 1-bit error correction function. If a single bit or multiple bit error occurs in the ECC, it will be reported to the error handling module for further processing.

[0019] The CRC check module is used to check the payload of the DSI data packets read from the display device. If there is an error, it will report an error to the error handling module.

[0020] The data packet decoding module is used to parse and process the DSI data packets read back from the display device.

[0021] Furthermore, when the error handling module continuously monitors the status of the FIFO control module, if it detects that the FIFO control module is about to be full, the error handling module sends a full signal to the upper-level system and suspends data input to the upper-level system.

[0022] Preferably, the ports of the aDPI interface include:

[0023] Timing and control signals: pixel clock adpiclk, vertical synchronization adpivsync, horizontal synchronization adpihsync, data enable adpidataen, disable adpishutdn, and color mode adpicolorm.

[0024] Data signal: Pixel data input adpipixdata;

[0025] Command mode signals: tearing effect feedback adpi_te and transmission enable adpi_dcs;

[0026] Other control signals: tearing effect enable adpi_tearon and register configuration data for regbank configuration via APB.

[0027] Preferably, the pixel data transmission process of the aDPI interface in video mode includes:

[0028] The upper-level system configures the controller to operate in video mode: internal register parameters are configured via the AMBA APB bus;

[0029] The display device is woken up by the APB bus interface module, and the physical layer is kept in a state where it can enter high-speed transmission at any time.

[0030] The upper-layer system sends pixel data streams and corresponding control signals to the aDPI interface;

[0031] The aDPI video signal format interface module standardizes pixel data and control signals, and the standardized pixel data and control signals are cached in the aDPI payload FIFO and the aDPI command FIFO, respectively.

[0032] The protocol layer packages the pixel data into DSI data packets according to the configured format and sends them to the physical layer;

[0033] The physical layer transmits DSI data packets in parallel to the physical layer receiver at the display device through multiple configured differential data channels.

[0034] Preferably, the pixel data transmission process of the aDPI interface in the self-adaptive command mode includes:

[0035] The upper-layer system configures the controller to operate in adaptive command mode;

[0036] The rising edge of the control signal adpi_dcs triggers the signal, indicating that the signal is valid; pixel data transmission begins.

[0037] The pixel counter inside the aDPI video signal format interface module begins counting valid pixels;

[0038] When the counter reaches the set value of adpi_cmd_size, the packet full flag is pulled high and passed to the protocol layer, and the counter is cleared.

[0039] The protocol layer generates a DSI command data packet after detecting the full packet flag.

[0040] The DSI command data packet is transmitted to the display device via the DSI link;

[0041] At the end of the transmission, if there are still pixels remaining in the counter, the remaining pixels are used to generate the last DSI command data packet, which is then transmitted to the display device via the DSI link.

[0042] Furthermore, the process by which the system configuration controller operates in adaptive command mode includes:

[0043] Configure internal register parameters via the AMBA APB bus, including operating mode, DSI packet payload size adpi_cmd_size, and pixel format;

[0044] The upper-layer system sends a pulse on the adpi_tearon port of the aDPI interface;

[0045] After the application layer detects the rising edge of adpi_tearon, the protocol layer generates the corresponding tearcmd data packet and sends it to the display device;

[0046] The display device activates the tearing effect and waits for the upper-level system to send pixel data.

[0047] The beneficial effects of this invention are as follows:

[0048] Unified Mode Architecture: This invention innovatively designs the aDPI interface, which no longer treats video mode (DPI) and command mode (DBI) as mutually exclusive options, unlike the traditional DSI architecture. aDPI is compatible with standard video modes and introduces a self-adaptive command mode, enabling both modes to meet the functions of full-screen refresh and partial refresh without hardware switching on a single architecture as needed;

[0049] High-bandwidth partial refresh mechanism: Addressing the low bandwidth issue of traditional DBI command mode, this invention designs an adaptive command mode that uses specific high-bandwidth DCS command data packets (such as Memory Write Start and Memory Write Continue) to send pixel data as a command stream using the aDPI high-speed clock, significantly improving the transmission efficiency of partial pixel data updates. Simultaneously, the refresh timing is coordinated through the adpi_tearon port signal, effectively avoiding screen tearing issues that may result from partial refresh and asynchronous refresh.

[0050] Closed-loop fault-tolerant system: The protocol layer is designed with a distributed monitoring and centralized error handling module, which can detect abnormal system status in real time and drive the retransmission mechanism, greatly enhancing the reliability of data transmission.

[0051] Simplified architecture and improved integration: A unified aDPI interface replaces some functions of the original discrete or mutually exclusive DPI and DBI interfaces, simplifying system design and improving the integration of the controller.

[0052] This invention, by introducing the aDPI interface, successfully solves the inherent defects of traditional MIPI DSI controllers in terms of mode mutual exclusion, partial refresh power consumption, and command mode bandwidth. It achieves the unification of high-performance full-screen refresh and ultra-low-power partial update on a single architecture, providing an excellent power consumption and performance balance solution for embedded display systems with specific requirements. Attached Figure Description

[0053] Figure 1 This is a schematic diagram of the MIPI DSI host controller structure in this invention;

[0054] Figure 2 This is a schematic diagram of the aDPI interface in this invention;

[0055] Figure 3 This is a diagram illustrating the FIFO overflow prevention detection method in this invention.

[0056] Figure 4 This is a flowchart of the MIPI DSI controller initialization configuration and TE signal configuration in this invention;

[0057] Figure 5This is a flowchart of the self-adaptive command mode data transmission process in this invention. Detailed Implementation

[0058] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0059] This invention proposes a MIPI DSI host controller with advanced DPI (aDPI), such as... Figure 1 As shown, the controller includes an application layer, a protocol layer, and a physical layer.

[0060] The controller designed in this invention features an aDPI (Advanced Display Pixel Interface) interface that is compatible with both video mode and adaptive command mode, and supports internal register configuration and general command transmission via the AMBA / APB bus. The video mode and adaptive command mode can be switched according to display requirements.

[0061] Application layer:

[0062] The core function of the application layer is to complete the interface adaptation and clock domain isolation of the display data link before transmission. Its specific structure includes: an aDPI interface, an aDPI video signal format interface module, two asynchronous FIFO control modules, and an APB bus interface module.

[0063] The APB bus interface module serves as a configuration channel, receiving and temporarily storing pixel data parameters (such as resolution, timing, DCS command parameters) and display device configuration information from the processor via the APB bus.

[0064] The aDPI video signal format interface module serves as a data and control signal channel, receiving pixel data streams and their control signals generated by the upper-layer system (image processing unit or other upstream modules). The core function of this module is to perform pixel format conversion, mapping various input RGB formats (RGB565, RGB666, RGB888) to a unified byte stream format according to the aDPI protocol standard. Specifically, RGB565, RGB666, and RGB888 correspond to three, two, and one specific byte stream mapping methods, respectively, and the byte stream is sent to the protocol layer according to the video signal sequence.

[0065] The two asynchronous FIFO control modules are aDPI payload FIFO and aDPI cmd FIFO, respectively. These two asynchronous FIFO control modules are used for cross-clock domain processing of pixel data and control signals, effectively solving the timing matching problem between the upstream system clock domain and the downstream DSI link layer byte clock domain. This ensures the integrity and reliability of data transmission between asynchronous clock domains, thus providing the necessary buffering and synchronization mechanism for stable transmission of the DSI link.

[0066] Protocol layer:

[0067] The protocol layer achieves efficient and reliable data transmission through the coordinated work of its internal modules. The protocol layer includes an error handling module, an ECC generation module, a CRC generation module, a data packet generation module, an ECC verification module, a CRC verification module, and a data packet decoding module.

[0068] On the data transmission path:

[0069] The data packet generation module receives pixel data from the application layer and encapsulates it into long or short packets conforming to the DSI standard. At the same time, the ECC generation unit generates an ECC checksum for the data packet header, and the CRC generation unit generates a CRC checksum for the payload of the long packet, and places them into the packet tail respectively.

[0070] At the system monitoring level:

[0071] The error handling module continuously monitors the status of the FIFO control module and other modules at the protocol layer (implementing distributed monitoring and centralized processing). When a module detects an error (such as a verification failure), the error handling module receives the exception information and immediately raises the global error flag. This signal is reported to the upper-layer system, driving it to perform a retransmission operation, thus forming a complete closed-loop fault-tolerant control process.

[0072] In some preferred embodiments of the present invention, such as Figure 3 As shown, when the error handling module continuously monitors the status of the FIFO control module, if it detects that the FIFO control module is about to be full, the error handling module sends a full signal to the upper-level system and suspends data input to the upper-level system.

[0073] On the data receiving path:

[0074] The ECC verification module is used to verify the header of the DSI data packet read from the display device. It has a 1-bit error correction function. If a single bit or multiple bit error occurs in the ECC, it will be reported to the error handling module for further processing. The CRC verification module is used to verify the payload of the DSI data packet read from the display device. Then it is compared with the CRC value of the original data packet. If they are different, an error is reported to the error handling module for further processing.

[0075] The packet decoding module is used to analyze the DSI packets read back from the display device, including parsing packet information such as packet type and pixel format.

[0076] Physical layer:

[0077] The physical layer is an implementation based on the D-PHY (physical layer) protocol, integrating the channel management layer within the digital logic of the PHY. This physical layer includes a physical layer interface controller finite state machine, data channel allocation control logic, a channel management module, a high-speed transmit channel module, and a low-speed transmit / receive channel module, and supports one pair of clock channels and one to four pairs of configurable data channels.

[0078] The physical layer interface controller module finite state machine refers to the state machine circuit used to manage and control the physical layer (PHY) communication interface.

[0079] The data channel allocation control logic refers to the distribution of protocol layer data packets to data channels for data transmission in 32-bit widths. The number of data channels can be configured through APB. Among them, datalane0 can switch between low-power and high-speed transmission modes, and the low-power mode has two modes: receive and transmit. The other three datalanes 1-3 only have high-speed transmission mode.

[0080] The channel management module manages all channels in the physical layer, including the clock lane and 1-4 data lanes.

[0081] The high-speed transmit channel module and the low-speed transmit / receive channel module are both mode switching modules for data lane 0; other data lanes are directly output from the data channel allocation control logic.

[0082] Regarding the initialization process: First, the master D-PHY must complete its own initialization via the PPI interface, ensuring that no stop state lasting TINIT (≥100μs) occurs on the channel during this process. Then, when the master drive line enters a stop state and remains there for more than TINIT, the initialization cycle of the display device is triggered. The channel management module is responsible for ensuring strict synchronization of the initialization actions of all channels in a multi-channel configuration. The display device's D-PHY is configured to complete startup within the initialization cycle, ignoring all line states prior to the start of this cycle.

[0083] In some preferred embodiments of the present invention, such as Figure 2 As shown, the core ports of the aDPI interface mainly consist of the following types of signals:

[0084] Timing and control signals: pixel clock adpiclk, vertical synchronization adpivsync, horizontal synchronization adpihsync, data enable adpidataen, disable adpishutdn, and color mode adpicolorm.

[0085] Data signal: Pixel data input adpipixdata;

[0086] Command mode signals: tear effect feedback adpi_te and transmission enable adpi_dcs.

[0087] Other control signals: tearing effect enable adpi_tearon and register configuration data for regbank configuration via APB.

[0088] The aDPI interface of this invention is compatible with both video mode and adaptive command mode. When updating image data with complete frame pixel data, video mode is selected. The pixel data transmission process of the aDPI interface in video mode includes:

[0089] Step 1: Configure the upper-layer system controller to work in video mode: Configure the internal registers of the aDPI interface through the AMBA APB bus. The registers in the internal regbank of the APB configuration include some registers of the physical layer. The physical layer's self-initialization is completed through configuration.

[0090] The system configures the internal registers of the aDPI interface via the APB bus. Parameters include the number of pixels per row in a frame, the payload size of the DSI data packet, and the pixel format (e.g., RGB888). Key parameters are configured externally via the APB bus, for example:

[0091] h_active_pixels (horizontal active pixels): Set to 480;

[0092] v_active_lines (vertical active lines): Set to 800;

[0093] pixel_format: Configured to RGB888;

[0094] The payload size of the DSI data packet is set to 5, meaning that each command data packet carries 5 pixels of data.

[0095] The main processor completes its own initialization of the D-PHY physical layer via the PPI interface. Subsequently, the main-side D-PHY driver enters a stopped state and remains in this state for more than TINIT (≥100μs) to trigger the display device's D-PHY initialization cycle. The channel management module ensures that the initialization actions of all data channels are strictly synchronized.

[0096] Step 2: After configuration, wake up the display device via APB and keep the D-PHY physical layer in a state where it can enter high-speed transmission at any time.

[0097] Step 3: The upper-layer system (such as the image processing unit) sends the pixel data stream and corresponding control signals to the aDPI interface. For example:

[0098] Pixel data enters the aDPI video signal format interface module and is converted from RGB888 format to a unified 24-bit byte stream;

[0099] Data streams and control signals are isolated and synchronously buffered from the graphics processing unit clock domain to the DSI byte clock domain through two asynchronous FIFO control modules.

[0100] The control signals strictly follow the definition of MIPI DPI-2 protocol architecture 4, including the following five categories:

[0101] adpivsync (vertical synchronization signal, Vsync), adpihsync (horizontal synchronization signal, Hsync), adpidataen (data enable signal, DE), adpishutdn (power off signal, SD), adpicolorm (color mode signal, CM).

[0102] Step 4: The aDPI video signal format interface module standardizes the pixel data and control signals. The standardized pixel data and control signals are then buffered into the aDPI payload FIFO and the aDPI command FIFO, respectively.

[0103] Step 5: After completing the handshake with the protocol layer, the data is sent to the protocol layer packetization module. The protocol layer packages the pixel data into DSI data packets according to the configured format (e.g., long packets for pixel data and short packets for control commands). The ECC / CRC generation unit adds check codes to the packet header and payload respectively. The packaged data stream is finally sent to the physical layer (D-PHY).

[0104] Step 6: The DSI data packets are transmitted in parallel through multiple configured differential data channels, thereby utilizing multi-channel technology to improve the overall bandwidth and efficiently and reliably transmit image data to the D-PHY receiver at the slave end.

[0105] When only a local area of ​​the display device needs to be updated, the system switches to a low-power state, i.e., the aDPI interface operates in adaptive command mode. The aDPI interface's adaptive command mode is a high-bandwidth solution designed for efficient transmission of small amounts of display data. This mode does not rely on traditional video timing but instead sends pixel data to the display device's frame buffer as a command stream via specific DCS command packets—Memory Write Start (WMS) and Memory Write Continue (WMC). Its core advantage lies in significantly improving the bandwidth of pixel data transmission when transmitting local pixel data. To address tearing issues that may occur with partial and asynchronous refreshes, once the adaptive command mode is configured, the upper-layer system sends a pulse on the adpi_tearon port. After the aDPI application layer detects the rising edge of adpi_tearon, the protocol layer generates a corresponding tearcmd packet to enable tearing on the slave side. After configuration, pixel data transmission in this mode is triggered by the rising edge of the control signal adpi_dcs. When this signal is valid, it works in conjunction with the adpidataen control signal to complete the pixel data bus transmission. During the configuration phase, a key parameter, `adpi_cmd_size`, is configured via APB. This parameter defines the number of pixels a single data packet can hold. The aDPI video signal format interface module internally has a pixel counter that counts the valid input pixels. When the counter reaches the set value of `adpi_cmd_size`, a full flag is raised and passed to the protocol layer, and the counter is reset. Upon detecting this flag, the protocol layer generates DSI command data packets in its packetization module. The first packet is a WMS command packet, followed by WMC command packets, and the corresponding number of pixel data packets are packaged and prepared for transmission via the DSI link. This process repeats until the `dpivsync_adpiwms` signal becomes invalid. At the end of transmission, if there are still pixels remaining in the counter, the system automatically sends the last WMC data packet (the counter does not need to reach `adpi_cmd_size`) to ensure data transmission integrity.

[0106] In some preferred embodiments of the present invention, the pixel data transmission process of the aDPI interface in the self-adaptive command mode includes:

[0107] Step 1: Configure the upper-layer system controller to operate in adaptive command mode, such as... Figure 4 As shown, specifically:

[0108] The AMBA APB bus configures internal register parameters, including key parameters such as operating mode, DSI packet payload size (adpi_cmd_size), and pixel format. The APB configuration's internal regbank registers include some physical layer registers, enabling the physical layer's self-initialization. This ensures the physical layer is in a defined low-power state and the channel is in a stopped transmission state.

[0109] Key parameters, such as h_active_pixels (horizontal effective pixels), should be set to 480.

[0110] v_active_lines (vertical active lines): Set to 800;

[0111] pixel_format: Configured to RGB888;

[0112] adpi_cmd_size (adaptive command mode packet size): Set to 5, meaning each command packet carries 5 pixels of data.

[0113] To prevent screen tearing caused by switching and partial updates, the upper-layer system sends a pulse on the adpi_tearon port of the aDPI interface;

[0114] After the application layer detects the rising edge of adpi_tearon, the protocol layer generates the corresponding tearcmd data packet and sends it to the display device;

[0115] Step 2: As Figure 5 As shown, the rising edge of the control signal adpi_dcs triggers, indicating that the signal is valid; pixel data transmission begins.

[0116] When adpi_dcs is active, it works in conjunction with the original DPI interface control signal DE to transmit local pixel data under the self-adaptive command, and then starts transmitting pixel data after sending the device local update address general command in conjunction with the APB interface.

[0117] Step 3: Pixel data enters the aDPI video signal format interface module, and the pixel counter inside the aDPI video signal format interface module begins counting valid pixels.

[0118] Step 4: When the counter reaches the set value of adpi_cmd_size, pull the packet full flag high and pass it to the protocol layer, then clear the counter.

[0119] Step 5: After detecting the full packet flag, the protocol layer will generate a DSI command data packet.

[0120] After detecting the full packet flag, the packetization module of the protocol layer generates a Memory Write Continue (WMC) command packet (the first one is Memory Write Start (WMS)) and sends the data of these 5 pixels as the payload to the display.

[0121] Steps 3-5 are repeated, automatically dividing and packaging local update data of any size into a series of efficient DSI command packets for transmission.

[0122] Step 6: At the end of the transmission, if there are still pixels remaining in the counter, generate the last DSI command data packet from the remaining pixels and transmit it to the display device through the DSI link.

[0123] After the adpi_dcs signal fails, the remaining valid payload counted in the counter will be put into the WMC for transmission, completing the entire data transmission.

[0124] Throughout the process, the error handling module continuously monitors the FIFO status. If upstream data flows too quickly, causing the FIFO to fill up rapidly, the module will send a signal to pause data input from the upper-layer system modules to prevent data loss and ensure transmission reliability.

[0125] The self-adaptive command mode achieves a "self-adaptive" capability by automatically segmenting a pixel stream of arbitrary length into a series of compliant data packets. To ensure data transmission reliability, this mode integrates a handshake mechanism. When the internal FIFO is about to be full, a write-full signal is fed back to pause upstream data input and prevent data overflow. In addition, the aDPI interface needs to work in conjunction with the AMBA APB bus, which is responsible for transmitting non-pixel data such as display configuration and read-back commands, thus forming a complete and efficient display command transmission system.

[0126] In summary, by introducing the aDPI interface, this invention successfully solves the inherent defects of traditional MIPI DSI controllers in terms of mode mutual exclusion, partial refresh power consumption, and command mode bandwidth. It achieves a unified high-performance full-screen refresh and ultra-low power partial update on a single architecture, providing an excellent power consumption and performance balance solution for embedded display systems with specific requirements, and has good application prospects.

[0127] The above-described embodiments further illustrate the purpose, technical solution, and advantages of the present invention. It should be understood that the above-described embodiments are merely preferred embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made to the present invention within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A MIPI DSI host controller with advanced DPI, characterized in that, It includes the application layer, protocol layer, and physical layer; the controller's aDPI interface is compatible with video mode and adaptive command mode, and supports AMBA APB bus for internal register configuration and transmission of general commands; video mode and adaptive command mode can be switched according to display requirements. The application layer receives pixel data from the processor and processes it, completing interface adaptation and clock domain isolation of the display data link before transmission, and then sends the processed pixel data to the protocol layer. The application layer includes an aDPI interface, an aDPI video signal format interface module, two asynchronous FIFO control modules, and an APB bus interface module. The two asynchronous FIFO control modules are the aDPI payload FIFO and the aDPI cmd FIFO, respectively. The protocol layer receives pixel data sent by the application layer and realizes data transmission with the physical layer through the coordinated work of its internal modules. The protocol layer includes an error handling module, an ECC generation module, a CRC generation module, a data packet generation module, an ECC verification module, a CRC verification module, and a data packet decoding module. The physical layer includes a physical layer interface controller finite state machine, data channel allocation control logic, a channel management module, a high-speed transmission channel module, and a low-speed transmission / reception channel module.

2. A MIPI DSI host controller with advanced DPI according to claim 1, characterized in that, In the application layer, the APB bus interface module serves as a configuration channel, receiving and temporarily storing pixel data parameters and display device configuration information from the processor via the APB bus. The aDPI video signal format interface module serves as a data and control signal channel, receiving pixel data streams and their control signals generated by the image processing unit or other upstream modules; and is used for pixel format conversion and protocol mapping. Two asynchronous FIFO control modules are used for cross-clock domain processing of pixel data and control signals, respectively.

3. A MIPI DSI host controller with advanced DPI according to claim 1, characterized in that, In the protocol layer, the packet generation module receives pixel data from the application layer and encapsulates it into long or short packets conforming to the DSI standard. The ECC generation unit generates ECC checksums for the packet header; The CRC generation unit generates CRC checksums for the payload of long packets and places them into the end of the data packets. The error handling module continuously monitors the status of the asynchronous FIFO control module and each module in the protocol layer. When an error is detected, the error handling module receives the abnormal information, raises the global error flag, and uses register toggling. It then reports the error flag signal to the upper-layer system, driving it to perform a retransmission operation. The ECC verification module is used to verify the header of the DSI data packet read back from the display device. It has a 1-bit error correction function. If a single bit or multiple bit error occurs in the ECC, it will be reported to the error handling module for further processing. The CRC check module is used to check the payload of the DSI data packets read from the display device. If there is an error, it will report an error to the error handling module. The data packet decoding module is used to parse and process the DSI data packets read back from the display device.

4. A MIPI DSI host controller with advanced DPI according to claim 3, characterized in that, When the error handling module continuously monitors the status of the FIFO control module, if it detects that the FIFO control module is about to be full, the error handling module sends a full signal to the upper-level system and suspends data input to the upper-level system.

5. A MIPI DSI host controller with advanced DPI according to claim 1, characterized in that, The ports of the aDPI interface include: Timing and control signals: pixel clock adpiclk, vertical synchronization adpivsync, horizontal synchronization adpihsync, data enable adpidataen, disable adpishutdn, and color mode adpicolorm. Data signal: Pixel data input adpipixdata; Command mode signals: tearing effect feedback adpi_te and transmission enable adpi_dcs; Other control signals: tearing effect enable adpi_tearon and register configuration data for regbank configuration via APB.

6. A MIPI DSI host controller with advanced DPI according to claim 1, characterized in that, The pixel data transmission process of the aDPI interface in video mode includes: The upper-level system configures the controller to operate in video mode: internal register parameters are configured via the AMBA APB bus; The display device is woken up by the APB bus interface module, and the physical layer is kept in a state where it can enter high-speed transmission at any time. The upper-layer system sends pixel data streams and corresponding control signals to the aDPI interface; The aDPI video signal format interface module standardizes pixel data and control signals, and the standardized pixel data and control signals are cached in the aDPI payload FIFO and the aDPI command FIFO, respectively. The protocol layer packages the pixel data into DSI data packets according to the configured format and sends them to the physical layer; The physical layer transmits DSI data packets in parallel to the physical layer receiver at the display device through multiple configured differential data channels.

7. A MIPI DSI host controller with advanced DPI according to claim 1, characterized in that, The pixel data transmission process of the aDPI interface in adaptive command mode includes: The upper-layer system configures the controller to operate in adaptive command mode; The rising edge of the control signal adpi_dcs triggers the signal, indicating that the signal is valid; pixel data transmission begins. The pixel counter inside the aDPI video signal format interface module begins counting valid pixels; When the counter reaches the set value of adpi_cmd_size, the packet full flag is pulled high and passed to the protocol layer, and the counter is cleared. The protocol layer generates a DSI command data packet after detecting the full packet flag. The DSI command data packet is transmitted to the display device via the DSI link; At the end of the transmission, if there are still pixels remaining in the counter, the remaining pixels are used to generate the last DSI command data packet, which is then transmitted to the display device via the DSI link.

8. A MIPI DSI host controller with advanced DPI according to claim 7, characterized in that, The process of configuring the system controller to operate in adaptive command mode includes: Configure internal register parameters via the AMBA APB bus, including operating mode, DSI packet payload size adpi_cmd_size, and pixel format; The upper-layer system sends a pulse on the adpi_tearon port of the aDPI interface; After the application layer detects the rising edge of adpi_tearon, the protocol layer generates the corresponding tearcmd data packet and sends it to the display device; The display device activates the tearing effect and waits for the upper-level system to send pixel data.

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