Defect detection method and device and storage medium

Abstract

The embodiment of the invention provides a defect detection method and device and a storage medium. The method comprises the following steps: acquiring a test image of a to-be-detected part of a wafer and a reference image of a reference part corresponding to the to-be-detected part in the wafer; respectively generating corresponding multi-scale feature representations of the test image and the reference image in a defect detection model based on the test image and the reference image; using the defect detection model to generate difference features based on the corresponding multi-scale feature representation, the difference features representing the difference between the to-be-detected part and the reference part; and generating a defect detection result for the to-be-detected part based on the difference characteristics. In this way, the accuracy and applicability of defect detection can be improved.

Description

Technical Field

[0001] The embodiments of this disclosure are primarily related to the field of integrated circuit technology, and more specifically, to methods, apparatus and storage media for defect detection. Background Technology

[0002] With the continuous development of integrated circuit manufacturing processes and packaging technologies, chip systems are evolving towards higher integration, more complex structures, and finer manufacturing scales. In this process, the structural consistency and manufacturing reliability within or between chips have a significant impact on the performance and yield of the final product. Especially in wafer-level manufacturing and advanced packaging scenarios, multiple structurally identical or similar chip units are often manufactured and combined simultaneously, and their manufacturing process is inevitably affected by various factors such as process fluctuations, material differences, and environmental factors.

[0003] Therefore, how to effectively analyze the structural differences between chip units in complex manufacturing environments, and how to ensure detection accuracy while taking into account detection efficiency and adaptability, has become an urgent issue in the field of integrated circuit manufacturing and quality control. Summary of the Invention

[0004] In a first aspect of this disclosure, a method for defect detection is provided. The method includes: acquiring a test image of a portion of a wafer to be inspected and a reference image of a reference portion of the wafer corresponding to the portion to be inspected; generating corresponding multi-scale feature representations of the test image and the reference image using a defect detection model, based on the test image and the reference image; generating difference features based on the corresponding multi-scale feature representations using the defect detection model, the difference features representing the difference between the portion to be inspected and the reference portion; and generating a defect detection result for the portion to be inspected based on the difference features.

[0005] In a second aspect of this disclosure, a method for training a defect detection model is provided. The method includes: constructing a plurality of training samples, wherein the training samples include a predetermined test image, a predetermined reference image, and labeled images for one or more defect regions in the predetermined test image; and inputting the predetermined test image and the predetermined reference image as paired inputs into the defect detection model to generate defect detection results for the predetermined test image; and updating the defect detection model based on the defect detection results and the labeled images using a composite loss function, the composite loss function including a first loss term for measuring classification accuracy and a second loss term for improving the ability to distinguish one or more defect regions in cases of imbalanced sample class distributions.

[0006] In a third aspect of this disclosure, an electronic device is provided. The electronic device includes a processor and a memory coupled to the processor. The memory has instructions stored therein, which, when executed by the processor, cause the electronic device to perform a method according to a first or second aspect of this disclosure.

[0007] In a fourth aspect of this disclosure, a computer-readable storage medium is provided. A computer program is stored on the computer-readable storage medium. When executed by a processor, the computer program implements the method according to a first or second aspect of this disclosure.

[0008] As will be understood from the following description, according to embodiments of this disclosure, firstly, a test image of the portion of the wafer to be inspected and a reference image of a reference portion of the wafer corresponding to the portion to be inspected are obtained. Further, based on the test image and the reference image, a defect detection model is used to generate corresponding multi-scale feature representations for the test image and the reference image, respectively. Further still, using the defect detection model, based on the corresponding multi-scale feature representations, difference features are generated, representing the differences between the portion to be inspected and the reference portion. Based on the difference features, a defect detection result for the portion to be inspected is generated.

[0009] It should be understood that the content described in this summary section is not intended to limit the key or essential features of the embodiments of this disclosure, nor is it intended to restrict the scope of this disclosure. Other features of this disclosure will become readily apparent from the following description. Attached Figure Description

[0010] The above and other features, advantages, and aspects of the embodiments of this disclosure will become more apparent from the accompanying drawings and the following detailed description. In the drawings, the same or similar reference numerals denote the same or similar elements, wherein: Figure 1 A schematic diagram of an example environment in which the various embodiments of this disclosure can be implemented is shown; Figure 2A Schematic diagrams of test images and reference images according to some embodiments of the present disclosure are shown; Figure 2B Schematic diagrams of registered test and reference images according to some embodiments of the present disclosure are shown; Figure 2C A schematic diagram illustrating a defect detection process according to some embodiments of the present disclosure is shown; Figure 2D A schematic diagram illustrating the process of determining the corresponding processed multi-scale feature representation according to some embodiments of the present disclosure is shown; Figure 2E A schematic diagram illustrating the process of constructing training samples according to some embodiments of the present disclosure is shown; Figure 3 A flowchart of a process for defect detection according to some embodiments of the present disclosure is shown; Figure 4 A flowchart illustrating the process of training a defect detection model according to some embodiments of the present disclosure is shown; and Figure 5 A block diagram of an electronic device in which one or more embodiments of the present disclosure may be implemented is shown. Detailed Implementation

[0011] Embodiments of this disclosure will now be described in more detail with reference to the accompanying drawings. While some embodiments of this disclosure are shown in the drawings, it should be understood that this disclosure can be implemented in various forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided to provide a more thorough and complete understanding of this disclosure. It should be understood that the accompanying drawings and embodiments of this disclosure are for illustrative purposes only and are not intended to limit the scope of protection of this disclosure.

[0012] In the description of embodiments of this disclosure, the term "comprising" and similar terms should be understood as open-ended inclusion, i.e., "including but not limited to". The term "based on" should be understood as "at least partially based on". The term "one embodiment" or "the embodiment" should be understood as "at least one embodiment". The terms "first", "second", etc., may refer to different or the same objects. Other explicit and implicit definitions may also be included below.

[0013] The following will describe in detail various example implementations of this scheme with reference to the accompanying drawings.

[0014] First see Figure 1 It illustrates a schematic diagram of an example environment 100 in which the various embodiments of this disclosure can be implemented. For example... Figure 1 As shown, the example environment 100 may generally include electronic device 110.

[0015] In some embodiments, the electronic device 110 can interact with other devices (not shown). For example, the electronic device 110 can receive input information from other devices and output feedback information to other devices. In some embodiments, the input message from other devices can be one or more images 120 of the chip unit to be detected. The electronic device 110 can perform corresponding analysis and detection on these images and output the corresponding detection results 130 to other devices.

[0016] In example environment 100, electronic device 110 can be any type of computing-capable device, including terminal devices or server devices. Terminal devices can be any type of mobile terminal, fixed terminal, or portable terminal, including mobile phones, desktop computers, laptop computers, notebook computers, netbook computers, tablet computers, media computers, multimedia tablets, personal communication system (PCS) devices, personal navigation devices, personal digital assistants (PDAs), audio / video players, digital cameras / camcorders, positioning devices, television receivers, radio receivers, e-book devices, gaming devices, or any combination of the foregoing, including accessories and peripherals of these devices or any combination thereof. Server devices can include, for example, computing systems / servers, such as mainframes, edge computing nodes, computing devices in cloud environments, and so on.

[0017] It should be understood that the structure and function of environment 100 are described for illustrative purposes only and do not imply any limitation on the scope of this disclosure. Exemplary embodiments according to this disclosure will now be described in detail with reference to the accompanying drawings.

[0018] As briefly mentioned above, with the development of integrated circuit manufacturing processes towards higher integration levels and more complex structures, advanced packaging technology has gradually become an important means to improve system performance and functional density. For example, in chiplet and 2.5D / 3D integrated packaging, different chip units are interconnected through interconnect structures such as microbumps, hybrid bonding, and silicon bridges to achieve high-density connections. The manufacturing quality of the structures between these chip units directly affects signal integrity, electrical performance, and the long-term reliability of the packaging system. Therefore, it is of great significance to inspect the relevant structures during the manufacturing and packaging process.

[0019] In actual production environments, to assess the quality of the aforementioned structures, images of the structures are typically acquired, and corresponding areas between chip units are analyzed to identify potential structural anomalies or manufacturing defects. These defects may include, but are not limited to, missing interconnect structures, abnormal connections, localized voids, and positional misalignments. These defects are often small in size, discretely distributed, and visually similar to normal process variations. Therefore, high precision and robustness are required for the detection methods.

[0020] A typical solution involves image pixel comparison strategies between chip units, determining the presence of anomalies by performing pixel-level difference calculations on the images. However, on the one hand, there are normal differences within the allowable range of process conditions (e.g., differences in surface roughness, material reflectivity, minor fluctuations in linewidth, etc.). These normal differences often resemble the behavior of real defects. Detection processes that rely on fixed thresholds for binarization may struggle to adaptively distinguish between normal fluctuations and abnormal defects in different scenarios, easily leading to a trade-off between false positive and false negative rates.

[0021] On the other hand, the interconnect structure of chip cells typically possesses well-defined structural prior characteristics, such as regular arrays and continuous traces. These characteristics are of significant reference value in defect identification. However, in detection processes based on pixel numerical changes, the semantic information at the structural level is often difficult to fully utilize. Especially when the defect amplitude is small or the background is complex, abnormal areas are easily submerged in the overall structural changes, leading to insufficient detection sensitivity.

[0022] Building upon this, another typical solution involves introducing deep learning models for defect detection. These methods extract and analyze features from input images to identify anomalous regions. However, in chip manufacturing, chip cells often possess highly similar but not identical structural features. Relying solely on a single image or simple differencing methods is insufficient to fully characterize the subtle differences between the "desired structure" and the "actual structure." Furthermore, the manufacturing process involves registration differences and numerous legitimate process variations (e.g., uneven illumination, surface reflections, material textures, and other process noise). If the model does not adequately cover these normal variations, it may misclassify them as anomalies, thus affecting the reliability of the detection results.

[0023] On the other hand, most deep learning models used for defect detection are designed to extract features from the image to be detected, or simply stitch the image to be detected with a reference image before inputting it into the model. In this case, the model struggles to explicitly model the correspondence between the two images and fails to fully utilize the structural alignment information after registration. This is especially true in scenarios where the defect amplitude is small or local changes are subtle, further limiting the model's detection capabilities.

[0024] Furthermore, detection methods based on image reconstruction errors typically assume that the model can reconstruct normal samples with relatively high accuracy and identify abnormal regions through reconstruction errors. However, in actual manufacturing processes, there are numerous legitimate and continuously varying forms of process fluctuations, such as linewidth tolerances or alignment offset tolerances. If the training data fails to adequately cover these normal variations, the model may misclassify them as abnormal regions, leading to an increased false alarm rate and affecting the reliability of the detection results.

[0025] Furthermore, in some deep learning detection processes, the model output still needs to be combined with manually set area thresholds, connected component analysis, or morphological processing rules to filter noise or merge scattered prediction results. This approach not only increases the complexity of the detection system but also makes the detection process dependent on human experience and parameter configuration to a certain extent, making it difficult to achieve stable and efficient end-to-end automated detection.

[0026] Furthermore, if the manufacturing process changes or new structural types are introduced, both pixel-based and model-based detection methods may require parameter readjustment or re-adaptation. This increases the complexity of system maintenance and deployment, and also limits the versatility of the detection solution across multiple scenarios and process conditions.

[0027] Therefore, embodiments of this disclosure propose a scheme for defect detection. According to embodiments of this disclosure, firstly, a test image of the portion of a wafer to be inspected and a reference image of a reference portion of the wafer corresponding to the portion to be inspected are acquired. Further, based on the test image and the reference image, a defect detection model is used to generate corresponding multi-scale feature representations for the test image and the reference image, respectively. Further still, using the defect detection model, based on the corresponding multi-scale feature representations, difference features are generated, representing the differences between the portion to be inspected and the reference portion. Based on the difference features, a defect detection result for the portion to be inspected is generated.

[0028] In the embodiments of this disclosure, by acquiring the image to be detected and a reference image, and using a defect detection model to extract features at multiple scales and generate difference features, the structural differences between the part to be detected and the reference part can be characterized in a multi-scale feature space, thereby achieving deep modeling of the semantic information of the chip interconnect structure. In this way, the defect detection results no longer rely on isolated local grayscale changes, but are based on a comprehensive characterization of structural consistency and anomalies at the feature level, thus significantly improving the ability to distinguish between normal process fluctuations and real minute defects under complex process conditions.

[0029] The following describes various example implementations of this scheme in further detail with reference to the accompanying drawings. In some embodiments, the process of determining the mask pattern described above can be performed by, for example... Figure 1 The electronic device 110 shown is performing this action.

[0030] In some embodiments, the electronic device 110 can acquire a test image of a portion of the wafer to be inspected and a reference image of a reference portion of the wafer corresponding to the portion to be inspected. In some examples, a wafer refers to a substrate carrier used to manufacture integrated circuits or package structures, on which multiple dies, also called chip cells, and corresponding circuit structures and interconnect structures are formed. A wafer may include, but is not limited to, semiconductor wafers, such as silicon wafers, compound semiconductor wafers, or wafer-level structures on which redistribution layers, interconnect layers, bonding structures, etc., are formed.

[0031] In some embodiments, after the front-end or mid-end processes are completed, multiple chip cells with identical or similar layout structures can be formed on the surface of the wafer. Each chip cell corresponds to a functional entity in the integrated circuit design. These chip cells can be formed into independent chips or multi-chip package structures through methods such as dicing, bonding, or stacking during subsequent manufacturing or packaging processes.

[0032] In some embodiments, the portion to be inspected can be a region within a chip cell on a wafer that requires defect detection, such as an interconnect structure region, a functional structure region, or a sub-region thereof located within that chip cell. The reference portion can be a region on the wafer that structurally corresponds to the portion to be inspected. This reference portion can be located in another chip cell, and that chip cell is considered to have not exhibited defects or is in an expected normal state during manufacturing or inspection.

[0033] Different chip units on a wafer can maintain structural design consistency, making corresponding regions in different chip units comparable in terms of geometric layout and functional structure. Based on this consistency, a target region in one chip unit on the wafer can be selected as the part to be inspected, while a corresponding region in another chip unit can be selected as a reference part, thereby supporting defect detection analysis based on the differences between paired regions.

[0034] As an example, Figure 2A Schematic diagrams of test image 211 and reference image 212 according to some embodiments of the present disclosure are shown. Figure 2A As shown, test image 211 can be an image acquired by an automated optical inspection device during wafer inspection of the portion to be inspected, for example, a defect image acquired by an imaging system for a potential anomaly location. Correspondingly, reference image 212 can be an image acquired from another chip cell on the wafer marked as "good," thus serving as a reference for defect detection. Reference image 212 and test image 211 can correspond in spatial location, structural layout, or functional area to support subsequent difference analysis.

[0035] In some embodiments, before feature processing of the test image and the reference image, the electronic device 110 may register the test image and the reference image so that the corresponding structures of the part to be detected and the reference part are matched in the same pixel coordinate system.

[0036] In some examples, registration processing may include performing high-precision registration between the test image and the reference image to achieve accurate spatial alignment between the two. For example, subpixel-level registration (registration with alignment accuracy of less than 0.1 pixel resolution) maps the same physical location to consistent or nearly consistent pixel coordinates in both images, thus providing a reliable basis for subsequent pixel-level or feature-level difference analysis.

[0037] In some embodiments, the electronic device 110 may perform global registration based on the displacement and rotation relationship between the test image and the reference image. For example, at least one of the images may be subjected to phase-correlation-based global rigid registration by analyzing the overall translation and rotation angle between the two images to eliminate overall alignment errors introduced by imaging position offset or imaging angle changes.

[0038] Alternatively or additionally, in some embodiments, the electronic device 110 may perform local registration based on local geometric deformations between the test image and the reference image. For example, a non-rigid registration algorithm based on B-spline transform may be used to non-rigidly adjust local regions of the image. In this way, local deformations caused by manufacturing processes, environmental changes, or material properties can be compensated for, thereby further improving the structural consistency between images.

[0039] As an example, Figure 2B Schematic diagrams of a registered test image 221 and a reference image 222 according to some embodiments of the present disclosure are shown. Figure 2B As shown, after registration, the test image 221 and the reference image 222 are strictly aligned in space. The corresponding physical locations of the test image 221 and the reference image 222 have consistent pixel coordinate relationships in the two images, thus providing accurate input conditions for subsequent feature extraction and differential feature generation.

[0040] In some embodiments, the electronic device 110 may utilize a defect detection model to perform defect detection on the part to be detected. As an example, Figure 2C A schematic diagram of a defect detection process 230 according to some embodiments of the present disclosure is shown. Figure 2C As shown, the process of defect detection using a defect detection model can include a feature extraction (downsampling) path and a feature processing (upsampling) path, which work together to detect the differences between the test image and the reference image.

[0041] In some embodiments, the electronic device 110 can generate corresponding multi-scale feature representations of the test image and the reference image respectively, using the feature extraction module in the defect detection model. Unlike methods that extract features from only a single image, this feature extraction module can simultaneously receive image information from both the part to be detected and the reference part, thereby establishing a correspondence between them at the feature level. Through this feature extraction process, the input image can be transformed from a pixel-level representation into a feature representation containing structural and contextual information, thus providing a foundation for the subsequent generation of differential features.

[0042] like Figure 2C As shown, the downward-extending path on the left can constitute a downsampling path for progressively extracting multi-scale feature representations from test image 231-1 and reference image 231-2. In some examples, the feature extraction module in the defect detection model may include a multi-level encoder (e.g., encoder 232). The multi-level encoder can process test image 231-1 and reference image 231-2 separately through multi-level feature extraction operations to extract corresponding multi-scale feature representations.

[0043] During feature extraction, encoder 232 can reduce the spatial resolution of the feature map layer by layer while increasing the dimensionality of the features. In this way, as the layers deepen, the features gradually transition from reflecting local details to abstract representations reflecting the overall structure and semantic information. This allows feature information from both the test and reference images to be acquired at multiple scales, thus forming a multi-scale feature representation.

[0044] In some embodiments, the feature extraction module includes two feature extraction branches with shared weights. The electronic device 110 can input a test image and a reference image into the two feature extraction branches respectively. For example, the feature extraction module may include two branch structures for image feature extraction, and the two feature extraction branches maintain consistent parameter configurations. The electronic device 110 can input the test image into one feature extraction branch and the reference image into the other feature extraction branch, so that both images are processed using the same feature extraction method.

[0045] In some embodiments, in the two feature extraction branches, the electronic device 110 can extract corresponding multi-scale feature representations of the test image and the reference image at multiple scales based on shared weights. For example, during the feature extraction process, low-level features reflecting local detail information and high-level features reflecting overall structural information can be extracted by progressively changing the feature resolution, thereby forming multi-scale feature representations.

[0046] By employing a parallel feature extraction branch with shared parameters, the test and reference images are mapped to a consistent feature representation space across multiple scales. In this way, the same structures in the test and reference images exhibit consistent feature representation across different images, while structural variations caused by real defects are amplified at the feature level. This approach allows subsequent feature-based processing to more consistently address structural inconsistencies, avoiding over-responsiveness to pixel-level noise or process-permissible fluctuations.

[0047] In some embodiments, the electronic device 110 can utilize the feature processing module in the defect detection model to generate difference features based on corresponding multi-scale feature representations. These difference features represent the differences between the part to be detected and a reference part. For example, difference features can be used to reflect structural and morphological inconsistencies between the part to be detected and the reference part, thereby providing a basis for generating defect detection results.

[0048] In some embodiments, the feature processing module includes an attention module. The electronic device 110 may utilize the attention module to process the corresponding multi-scale feature representations of the test image and the reference image, such that the target region has a greater influence on the processed corresponding multi-scale feature representation than other regions besides the target region. The target region is the region of difference between the test image and the reference image.

[0049] Through the above processing method, regions related to the differences between the test image and the reference image have a higher influence in feature processing, while background regions or repetitive structures unrelated to the differences are relatively suppressed. Therefore, the model can focus more on regions that may correspond to defects at the feature level, rather than assigning equal importance to all locations in the entire image. Especially when the structures to be detected are regularly arranged or the background is complex, this processing method helps to reduce the interference of large-area uniform structures on the detection results, making small but structurally significant anomalies more prominent in feature representation.

[0050] In some embodiments, to preserve detailed information from the feature extraction stage during feature upsampling, multi-scale feature representations can be directly passed from the downsampling path to the corresponding layers in the upsampling path via skip connections. For example, features generated in the encoder can be passed as skip features 233 to the corresponding upsampling layer and fused with features 234 generated during the upsampling process. Skip connections allow for the introduction of high-resolution detailed features while restoring spatial resolution, thereby improving the ability to perceive local structural changes.

[0051] In some embodiments, features in the upsampling path can be processed by attention module 235 before or during fusion with skip features. Attention module 235 can weight features from different scales or sources, giving higher weight to regions related to the differences between the test and reference images, while relatively suppressing background regions unrelated to the differences. In this way, the model can pay more attention to regions with potential defects during the feature reconstruction stage.

[0052] As an example, Figure 2D A schematic diagram of a process 240 for determining the processed corresponding multi-scale feature representation according to some embodiments of the present disclosure is shown. Figure 2D As shown, the input to the attention module 235 can include skip features 241 obtained from downsampled "skip connections" and upsampled features 242 from the output of the previous layer decoder. Skip features 241 typically have high spatial resolution and are used to reflect local structural details. Upsampled features 242 can contain semantic information from deeper network layers and are used to reflect larger-scale structural and contextual relationships.

[0053] In some embodiments, the electronic device 110 may perform feature transformation operations on the skip feature 241 and the upsampled feature 242, respectively. For example, as Figure 2D As shown, skip features 241 can be channel-mapped via the first convolutional layer 243-1, and upsampled features 242 can be channel-mapped via the second convolutional layer 243-2. ​​Through the above processing, features from different paths can be mapped to a unified feature space for subsequent joint modeling.

[0054] Furthermore, the electronic device 110 can perform an addition operation 244 on the channel-mapped skip features 241 and upsampled features 242 to fuse feature information from different paths. This addition operation can be used to aggregate multi-scale contextual information at the feature level, enabling the attention module to simultaneously perceive local detail features and high-level semantic features.

[0055] In some embodiments, the fused features obtained by addition can be input to the nonlinear transformation module 245 (e.g., a linear rectified function) to enhance the nonlinear expressive power of the features. Furthermore, the electronic device 110 can further process the fused features through another convolutional layer 243-3 to generate intermediate feature representations characterizing the importance of each spatial location.

[0056] Furthermore, the intermediate feature representations can be input into activation function module 246 (e.g., the sigmoid function) to generate attention weights with a limited range of values. These attention weights can reflect the importance of different locations or different feature channels in the spatial and / or channel dimensions.

[0057] In some embodiments, the electronic device 110 may perform a multiplication operation 247 on the generated attention weights with the original upsampled features or fused features, thereby weighting the features. Through this multiplication operation, regions related to the differences between the test image and the reference image receive higher weights in the features, while background regions or repetitive structures unrelated to the differences are relatively suppressed. Thus, a weighted feature representation 248 is obtained, which is the corresponding processed multi-scale feature representation.

[0058] Through the aforementioned attention processing, the attention module can adaptively adjust the influence of different spatial locations and feature channels on differential features during the multi-scale feature fusion stage. In this way, the model can focus more on regions that may correspond to real defects during subsequent differential feature generation and defect detection, while reducing sensitivity to registration residuals, process variations, or structurally repetitive regions.

[0059] In some embodiments, the electronic device 110 generates difference features based on the processed corresponding multi-scale feature representations. The difference features can comprehensively reflect the structural differences between the test image and the reference image at different scales, and serve as input for subsequently generating defect detection results.

[0060] As an example, such as Figure 2C As shown, in the upsampling path, based on the features processed by the attention module and the multi-scale features from the skip connections, difference features can be generated to characterize the differences between the test image and the reference image. These difference features can reflect the structural and morphological inconsistencies between the two images at multiple spatial locations and serve as the basis for subsequent defect identification.

[0061] In some embodiments, the difference features may include a difference feature map. For example, a difference feature map may be used to represent the distribution of differences between a test image and a reference image in spatial location, wherein the feature values ​​corresponding to different locations reflect the degree of structural difference at that location.

[0062] In some embodiments, the electronic device 110 may generate a difference feature map through a feature difference fusion module. The feature difference fusion module may model the difference between the test image and the reference image based on the processed multi-scale feature representations at corresponding pixel locations, thereby obtaining a feature map for characterizing the difference information.

[0063] In some embodiments, for pixels in the test image and the reference image, the electronic device 110 can calculate the difference between the processed multi-scale feature representations at that pixel to generate a difference feature map. For example, the electronic device 110 can calculate the difference between the processed multi-scale feature representations of the test image and the reference image at the corresponding pixel location on a pixel-by-pixel basis, and use this difference as the feature value of the difference feature map at that pixel location. In this way, the difference feature map can directly reflect the degree of feature difference between the test image and the reference image at corresponding locations.

[0064] In some embodiments, the electronic device 110 can stitch together the processed multi-scale feature representations at the pixel location to generate a difference feature map. For example, the electronic device 110 can stitch together the processed multi-scale feature representations of the test image and the reference image at the corresponding pixel location to form a joint feature representation, and generate a difference feature map based on the joint feature representation. By stitching together the feature representations, feature information from both the test image and the reference image can be retained in the difference feature map, thereby providing richer contextual information for subsequent difference discrimination.

[0065] In some embodiments, the electronic device 110 may perform weighted fusion of the processed multi-scale feature representations at that pixel location to generate a difference feature map. For example, the electronic device 110 may perform weighted fusion of the processed multi-scale feature representations of the test image and the reference image at that pixel location to generate a difference feature map. By assigning different weights to features from different sources or at different scales, feature components related to difference can be enhanced, while feature components that contribute less to difference discrimination can be weakened.

[0066] The difference feature map generated in the above manner can comprehensively reflect the difference information between the test image and the reference image at multiple scales and multiple spatial locations, providing a stable and discriminative feature basis for the subsequent generation of defect detection results.

[0067] In some embodiments, the electronic device 110 can generate defect detection results for the part to be inspected based on differential features. The defect detection results are used to characterize whether there are structural anomalies in the part to be inspected and can reflect the spatial distribution of the anomalies, thereby supporting subsequent quality assessment, defect localization, or process analysis.

[0068] For example, continue to refer to Figure 2C The decoder 236 can further process the difference information based on the aforementioned difference feature map and generate a defect detection result 237. In this way, the defect detection model can output pixel-level defect detection results while maintaining spatial correspondence.

[0069] In some embodiments, the defect detection results may include defect information related to the part to be detected, such as the location of the detected defect, the defect distribution area, and confidence information related to the defect. In this way, the defect detection results can not only indicate whether a defect exists, but also provide spatial reference information related to the defect location, making it easier to correlate the detection results with the actual structural location.

[0070] In some embodiments, the defect detection result includes a defect probability map. For example, the defect detection result includes a defect probability map P∈[0,1]H×W, where H and W represent the height and width of the image, respectively. Each pixel value in the defect probability map represents the confidence that the corresponding location of the detected part has a defect. For example, the defect probability map can maintain a spatial resolution correspondence with the test image, where each pixel location corresponds to a probability value. This probability value represents the confidence that the detected part has a defect at that pixel location. By expressing the detection result in probabilistic form, the instability caused by simple binary judgment can be avoided, and a more flexible basis can be provided for subsequent processing or decision-making.

[0071] In some embodiments, the aforementioned process of generating defect detection results for the part to be detected based on the test image and the reference image is executed based on the network architecture of the defect detection model. This process can be executed during the inference phase of the defect detection model or during the training phase of the defect detection model. Some embodiments are described below regarding the training of the defect detection model.

[0072] In some embodiments, the defect detection model can determine the relevant parameters through a pre-training process, enabling the model to distinguish structural differences between a test image and a reference image in the feature space. To this end, the electronic device 110 can construct multiple training samples for training the defect detection model. The training samples may include a predetermined test image, a predetermined reference image, and labeled images of one or more defect regions in the predetermined test image.

[0073] As an example, Figure 2E A schematic diagram of a process 250 for constructing training samples according to some embodiments of the present disclosure is shown. Figure 2E As shown, the electronic device 110 can acquire labeled images 251 for one or more defect regions (e.g., region 252) in a predetermined test image. In this way, each training sample can contain a pair of images and corresponding defect labeling information to guide the model in learning how to identify structural differences at the feature level.

[0074] Alternatively or additionally, the labeled images in the training samples can be in the form of masks. For example, in the coordinate system of the registered defect image, engineers or automatic annotation tools perform pixel-level annotations on various defects (e.g., missing micro-bumps, bridging, voids, offsets, etc.) to obtain a mask image 253. In the mask image 253, the pixel value of the area labeled as a defect is 1, and the pixel value of the background area is 0. The electronic device 110 can combine the registered predetermined test image, predetermined reference image, and corresponding mask image into a training sample, and repeat this process for multiple chip units and multiple interconnect layers to construct training samples in a uniform format.

[0075] Furthermore, the electronic device 110 can input a predetermined test image and a predetermined reference image as paired inputs to the defect detection model to generate defect detection results for the predetermined test image. In this way, the defect detection model can be trained end-to-end, enabling the model to directly learn feature representations and decision rules for defect discrimination from the input test image and reference image.

[0076] For example, electronic device 110 can input a predetermined test image and a predetermined reference image as paired inputs into a defect detection model to generate defect detection results for the predetermined test image. Unlike training methods that only use a single test image as input, by inputting the predetermined test image and the corresponding predetermined reference image into the model in a paired manner, the defect detection model can simultaneously perceive the "current structure to be detected" and the "normal reference structure" during the training phase, thereby explicitly establishing the correspondence between the two at the feature level.

[0077] In some embodiments, during the training of the defect detection model, features can be extracted from the predetermined test image and the predetermined reference image using the aforementioned feature extraction module. For example, the feature extraction module may include two feature extraction branches with shared weights, used to process the predetermined test image and the predetermined reference image respectively.

[0078] In some embodiments, the two feature extraction branches can form a symmetrical bi-branch coding structure, extracting corresponding multi-scale feature representations of the predetermined test image and the predetermined reference image at multiple scales. By sharing weights, the comparability of the representations of the two images in the feature space can be ensured, which is beneficial for the model to learn a stable difference discrimination ability during training.

[0079] In some embodiments, the multi-scale feature representations can be processed by the aforementioned feature processing module during the training of the defect detection model. For example, the feature processing module may include an attention module for weighting the corresponding multi-scale feature representations of a predetermined test image and a predetermined reference image, so that the target region has a greater influence on the processed corresponding multi-scale feature representation than other regions, where the target region is the difference region between the predetermined test image and the predetermined reference image.

[0080] Furthermore, based on the processed multi-scale feature representations, difference features can be generated to characterize the differences between the predetermined test image and the predetermined reference image. By introducing an attention mechanism during training, the model can be guided to pay more attention to defect-related regional features when updating parameters, thereby improving the model's ability to discriminate defect regions.

[0081] In some embodiments, the attention module is positioned on the skip connection path between the feature extraction module and the decoding module, enabling features from different scales to be dynamically weighted according to the significance of differences during the fusion process, thereby enhancing the model's ability to model multi-scale differential features during the training phase.

[0082] Furthermore, the electronic device 110 can update the defect detection model based on the defect detection results and labeled images using a composite loss function. In this way, the model can improve its ability to identify defect regions even when the sample class distribution is imbalanced, while optimizing classification accuracy.

[0083] In some embodiments, the composite loss function may include a first loss term for measuring classification accuracy and a second loss term for improving the ability to distinguish one or more defective regions in the case of imbalanced sample class distribution.

[0084] As an example, electronic device 110 can construct a composite loss function using the following formula: L=λ1 L BCE +λ2 L Focal Among them, L BCE L represents the cross-entropy loss used for pixel-level binary classification tasks, which guides the model to learn the overall classification boundary. Focal This represents the loss term used to reinforce the contribution of hard-to-classify samples. By assigning higher weights to low-confidence samples, the impact of differences in the number of positive and negative samples can be mitigated. λ1 and λ2 are weighting coefficients used to balance the contributions of different loss terms. In different embodiments, the values ​​of λ1 and λ2 can be set according to the specific application scenario; for example, λ1=0.5, λ2=0.5.

[0085] In some embodiments, after generating the defect probability map, the electronic device 110 can perform post-processing on the defect probability map to generate the final defect detection result and determine the spatial location information of the defect. For example, the electronic device 110 can perform defect confidence processing on the defect probability map corresponding to each pixel position, and convert the defect probability map into a binary defect map by threshold segmentation, thereby distinguishing defect areas from non-defect areas.

[0086] In some examples, an adaptive threshold τ can be set to binarize the defect probability map. For instance, if the defect confidence level corresponding to a pixel location is greater than or equal to the threshold τ (e.g., 0.5), the pixel is identified as a defect pixel. Otherwise, if the defect confidence level is less than the threshold τ, the pixel is identified as a non-defect pixel. This threshold can be set or dynamically adjusted according to the specific application scenario to achieve a balance between detection sensitivity and false detection rate.

[0087] In some embodiments, the electronic device 110 may perform morphological processing operations on the binary defect map to improve the coherence and stability of the defect region. For example, by removing isolated noise points, filling voids inside the defect region, or connecting adjacent defect segments in space, the defect region becomes more complete and continuous in spatial distribution, thereby reducing misjudgments caused by noise or local interference.

[0088] In some embodiments, the electronic device 110 can perform connected component analysis based on a post-processed binary defect graph to identify one or more independent defect regions. For each defect region, the electronic device 110 can further calculate the geometric properties of the defect region, such as region area, center location, or minimum circumscribed boundary, thereby characterizing the spatial location and extent of the defect region. Based on the above analysis results, corresponding visual detection results can be generated to intuitively display the distribution of defects in the part to be detected.

[0089] In some embodiments, since the test image is processed in a uniform coordinate system throughout the defect detection process, the electronic device 110 can directly map the detected defect location information to the physical coordinate space corresponding to the original test image. In this way, a list of defect location coordinates consistent with the production line coordinate system can be generated. This defect location information can then be further used for subsequent process rule checks, defect verification, or root cause analysis.

[0090] It should be noted that the above application scenario of defect detection in the micro-bump interconnect region in 2.5D advanced packaging is only used to illustrate the working principle and technical effect of this disclosure, and does not constitute a limitation on the scope of application of this disclosure. In other embodiments, this disclosure is also applicable to defect detection in other regions or structures such as redistribution layers, through-hole interconnect structures, and hybrid bonding structures.

[0091] In summary, the defect detection scheme of the embodiments of this disclosure introduces a defect detection mechanism with test images and reference images as dual inputs. It generates differential features and outputs detection results based on a unified feature extraction and processing flow, eliminating the need to design dedicated detection rules or adjust fixed thresholds for different interconnect layer structures or different defect types. On the one hand, since the detection logic is automatically learned by the model from the structural differences between the test and reference images, when introducing new products or processes, only a small number of samples are needed to complete model training or adaptation, thereby significantly reducing the cost of manual intervention and shortening the traditional detection process that relies on manual rule configuration from a long cycle to a shorter deployment time.

[0092] On the other hand, by performing multi-scale feature modeling on the test image and the reference image, and representing the differences between them in a unified feature space, the defect detection model can learn the structural semantic differences between the "current state to be detected" and the "corresponding reference state". Therefore, the embodiments of this disclosure can be applied to various interconnect structure levels and different wafer or chip types, without depending on the geometry of a specific interconnect layer or the specific defect type.

[0093] Furthermore, by training the defect detection model in an end-to-end manner, the detection process is automated, driven by data, to complete feature extraction, difference modeling, and result generation, thereby reducing the intervention of subjective human factors. This approach maintains consistency in detection standards across different application scenarios, improving the stability and repeatability of defect detection results.

[0094] In summary, the embodiments of this disclosure achieve a defect detection process that does not rely on manual rules and fixed thresholds by explicitly modeling the difference relationship between the test image and the reference image at the feature level. In this way, pixel-level defect detection results can be stably output under complex backgrounds and diverse structural conditions, while balancing detection accuracy, robustness, and versatility.

[0095] Figure 3 A flowchart of a process 300 for defect detection according to some embodiments of the present disclosure is shown. In some embodiments, process 300 may be performed by, for example... Figure 1 The illustrated electronic device 110 performs this operation. It should be understood that process 300 may also include additional boxes not shown and / or some (or more) of the boxes shown may be omitted; the scope of this disclosure is not limited in this respect. The following is in conjunction with... Figure 1 The process 300 is described in detail.

[0096] like Figure 3 As shown in block 310, electronic device 110 can acquire a test image of the portion of the wafer to be inspected and a reference image of a reference portion of the wafer corresponding to the portion to be inspected.

[0097] In box 320, electronic device 110 can generate corresponding multi-scale feature representations of the test image and the reference image respectively using a defect detection model based on the test image and the reference image.

[0098] In box 330, electronic device 110 can utilize the defect detection model to generate differential features based on the corresponding multi-scale feature representation.

[0099] In box 340, electronic device 110 can generate defect detection results for the part to be detected based on the difference features.

[0100] In some embodiments, generating corresponding multi-scale feature representations of the test image and the reference image includes: inputting the test image and the reference image into the defect detection model respectively; and using the defect detection model, based on shared weights, extracting corresponding multi-scale feature representations of the test image and the reference image at multiple scales respectively.

[0101] In some embodiments, generating difference features includes: processing the corresponding multi-scale feature representations of the test image and the reference image using a defect detection model, such that the target region has a greater influence on the processed corresponding multi-scale feature representation than other regions, where the target region is the difference region between the test image and the reference image; and generating difference features based on the processed corresponding multi-scale feature representations.

[0102] In some embodiments, the difference features include a difference feature map, and generating the difference features based on the processed corresponding multi-scale feature representations includes performing at least one of the following for pixels in the test image and the reference image: calculating the difference between the processed multi-scale feature representations at the pixel to generate a difference feature map; concatenating the processed corresponding multi-scale feature representations at the pixel to generate a difference feature map; or performing a weighted fusion of the processed corresponding multi-scale feature representations at the pixel to generate a difference feature map.

[0103] In some embodiments, the defect detection result includes a defect probability map, where each pixel value in the defect probability map represents the confidence level that the corresponding location of the part to be detected has a defect.

[0104] In some embodiments, before generating corresponding multi-scale feature representations of the test image and the reference image, process 300 further includes: registering the test image and the reference image so that the corresponding structures of the part to be detected and the reference part match in the same pixel coordinate system.

[0105] In some embodiments, registering the test image and the reference image includes at least one of the following: global registration based on the displacement and rotation relationship between the test image and the reference image, or local registration based on the local geometric deformation between the test image and the reference image.

[0106] Figure 4 A flowchart of a process 400 for training a defect detection model according to some embodiments of the present disclosure is shown. In some embodiments, process 400 may be performed by, for example... Figure 1 The illustrated electronic device 110 performs this operation. It should be understood that process 400 may also include additional boxes not shown and / or one (or some) of the boxes shown may be omitted; the scope of this disclosure is not limited in this respect. The following is in conjunction with… Figure 1 The process 400 is described in detail.

[0107] like Figure 4 As shown in box 410, the electronic device 110 can construct multiple training samples, the training samples of which include a predetermined test image, a predetermined reference image, and a labeled image for one or more defect regions in the predetermined test image.

[0108] In box 420, electronic device 110 can input a predetermined test image and a predetermined reference image as a pair of inputs into a defect detection model to generate defect detection results for the predetermined test image.

[0109] In box 430, electronic device 110 can update the defect detection model based on the defect detection results and labeled images using a composite loss function. The composite loss function includes a first loss term to measure classification accuracy and a second loss term to improve the ability to distinguish one or more defect regions in the case of imbalanced sample class distribution.

[0110] In some embodiments, generating a defect detection result for a predetermined test image includes: using a feature extraction module in the defect detection model to generate corresponding multi-scale feature representations of the predetermined test image and a predetermined reference image, respectively; using a feature processing module in the defect detection model to generate difference features based on the corresponding multi-scale feature representations, wherein the difference features represent the difference between the part to be detected in the predetermined test image and the reference part in the predetermined reference image; and using a decoding module in the defect detection model to generate a defect detection result for the predetermined test image based on the difference features.

[0111] In some embodiments, the feature extraction module includes two feature extraction branches with shared weights, and generating corresponding multi-scale feature representations of a predetermined test image and a predetermined reference image includes: inputting the predetermined test image and the predetermined reference image into the two feature extraction branches respectively; and in the two feature extraction branches, extracting corresponding multi-scale feature representations of the predetermined test image and the predetermined reference image at multiple scales based on the shared weights respectively.

[0112] In some embodiments, the two feature extraction branches are symmetric dual-branch coding structures.

[0113] In some embodiments, the feature processing module includes an attention module, and generating difference features includes: using the attention module to process the corresponding multi-scale feature representations of a predetermined test image and a predetermined reference image such that the target region has a greater influence on the processed corresponding multi-scale feature representation than other regions except the target region, the target region being the difference region between the predetermined test image and the predetermined reference image; and generating difference features based on the processed corresponding multi-scale feature representations.

[0114] In some embodiments, the attention module is positioned on the skip connection path between the feature extraction module and the decoding module.

[0115] Figure 5 A block diagram is shown of an electronic device 500 in which one or more embodiments of the present disclosure may be implemented. The electronic device 500 may, for example, be used to implement... Figure 1 The electronic device 110 shown. It should be understood that, Figure 5 The electronic device 500 shown is merely exemplary and should not be construed as limiting the functionality and scope of the embodiments described herein.

[0116] like Figure 5 As shown, electronic device 500 is in the form of a general-purpose electronic device. Components of electronic device 500 may include, but are not limited to, one or more processors 510 or processing units, memory 520, storage device 530, one or more communication units 540, one or more input devices 550, and one or more output devices 560. The processing unit may be a physical or virtual processor and is capable of performing various processes according to programs stored in memory 520. In a multiprocessor system, multiple processing units execute computer-executable instructions in parallel to improve the parallel processing capability of electronic device 500.

[0117] Electronic device 500 typically includes multiple computer storage media. Such media can be any available media accessible to electronic device 500, including but not limited to volatile and non-volatile media, removable and non-removable media. Memory 520 can be volatile memory (e.g., registers, cache, random access memory (RAM)), non-volatile memory (e.g., read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory), or some combination thereof. Storage device 530 can be a removable or non-removable medium and can include machine-readable media, such as flash drives, disks, or any other media that can be used to store information and / or data (e.g., training data for training) and can be accessed within electronic device 500.

[0118] Electronic device 500 may further include additional removable / non-removable, volatile / non-volatile storage media. Although not explicitly stated... Figure 5 As shown, disk drives for reading from or writing to removable, non-volatile disks (e.g., "floppy disks") and optical disk drives for reading from or writing to removable, non-volatile optical disks can be provided. In these cases, each drive can be connected to a bus (not shown) via one or more data media interfaces. Memory 520 may include computer program product 525 having one or more program modules configured to perform various methods or actions of various embodiments of this disclosure.

[0119] Communication unit 540 enables communication with other electronic devices via a communication medium. Additionally, the functionality of components of electronic device 500 can be implemented using a single computing cluster or multiple computing machines capable of communicating via communication connections. Therefore, electronic device 500 can operate in a networked environment using logical connections to one or more other servers, network personal computers (PCs), or another network node.

[0120] Input device 550 can be one or more input devices, such as a mouse, keyboard, trackball, etc. Output device 560 can be one or more output devices, such as a monitor, speaker, printer, etc. Electronic device 500 can also communicate with one or more external devices (not shown) via communication unit 540 as needed. These external devices include storage devices, display devices, etc., and can communicate with one or more devices that enable user interaction with electronic device 500, or with any device that enables electronic device 500 to communicate with one or more other electronic devices (e.g., network card, modem, etc.). Such communication can be performed via input / output (I / O) interface (not shown).

[0121] According to an exemplary implementation of this disclosure, a computer-readable storage medium is provided that stores one or more computer instructions, wherein one or more computer instructions are executed by a processor to implement the methods described above.

[0122] Various aspects of this disclosure are described herein with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products implemented according to this disclosure. It should be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer-readable program instructions.

[0123] These computer-readable program instructions can be provided to a processing unit of a general-purpose computer, a special-purpose computer, or other programmable data processing apparatus to produce a machine such that, when executed by the processing unit of the computer or other programmable data processing apparatus, they create means for implementing the functions / actions specified in one or more blocks of the flowchart and / or block diagram. These computer-readable program instructions can also be stored in a computer-readable storage medium that causes a computer, programmable data processing apparatus, and / or other device to operate in a particular manner. Thus, the computer-readable medium storing the instructions comprises an article of manufacture that includes instructions for implementing aspects of the functions / actions specified in one or more blocks of the flowchart and / or block diagram.

[0124] Computer-readable program instructions may also be loaded onto a computer, other programmable data processing apparatus, or other device to cause a series of operational steps to be performed on the computer, other programmable data processing apparatus, or other device to produce a computer-implemented process, thereby causing the instructions that execute on the computer, other programmable data processing apparatus, or other device to perform the functions / actions specified in one or more boxes of a flowchart and / or block diagram.

[0125] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of this disclosure. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of an instruction, which contains one or more executable instructions for implementing the specified logical function. In some alternative implementations, the functions indicated in the blocks may occur in a different order than those indicated in the drawings. For example, two consecutive blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, may be implemented using a dedicated hardware-based system that performs the specified function or action, or using a combination of dedicated hardware and computer instructions.

[0126] Various implementations of this disclosure have been described above. The foregoing description is exemplary and not exhaustive, nor is it limited to the disclosed implementations. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described implementations. The terminology used herein is chosen to best explain the principles, practical applications, or improvements to technology in the market, or to enable others skilled in the art to understand the implementations disclosed herein.

Claims

1. A method for defect detection, characterized in that, include: Acquire a test image of the portion of the wafer to be inspected and a reference image of a reference portion of the wafer corresponding to the portion to be inspected; Based on the test image and the reference image, a defect detection model is used to generate corresponding multi-scale feature representations of the test image and the reference image, respectively. The feature processing module of the defect detection model performs weighted processing on the corresponding multi-scale feature representations; based on the processed corresponding multi-scale feature representations, the difference features are generated; and Based on the aforementioned differences, defect detection results are generated for the part to be detected.

2. The method for defect detection according to claim 1, characterized in that, Generating the corresponding multi-scale feature representations of the test image and the reference image includes: The test image and the reference image are respectively input into the defect detection model; and Using the defect detection model, corresponding multi-scale feature representations of the test image and the reference image are extracted at multiple scales.

3. The method for defect detection according to claim 1, characterized in that, The weighting process for the corresponding multi-scale feature representations includes: Using the feature processing module, the corresponding multi-scale feature representations of the test image and the reference image are weighted so that the target region has a greater influence on the processed corresponding multi-scale feature representation than other regions except the target region. The target region is the difference region between the test image and the reference image.

4. The method for defect detection according to claim 1, characterized in that, The difference features include a difference feature map, and generating difference features based on the processed corresponding multi-scale feature representations includes performing at least one of the following on pixels in the test image and the reference image: The difference between the processed multi-scale feature representations at the pixel is calculated to generate the difference feature map; At this pixel, the processed corresponding multi-scale feature representation is stitched together to generate the difference feature map; or At that pixel, the processed corresponding multi-scale feature representations are weighted and fused to generate the difference feature map.

5. The method for defect detection according to claim 1, characterized in that, The defect detection result includes a defect probability map, where each pixel value in the defect probability map represents the confidence level that the corresponding position of the part to be detected has a defect.

6. The method for defect detection according to claim 1, characterized in that, Before generating the corresponding multi-scale feature representations of the test image and the reference image, the method further includes: The test image and the reference image are registered so that the corresponding structures of the part to be detected and the reference part are matched in the same pixel coordinate system.

7. The method for defect detection according to claim 6, characterized in that, Registering the test image with the reference image includes at least one of the following: Overall registration is performed based on the displacement and rotation relationship between the test image and the reference image, or Local registration is performed based on the local geometric deformation between the test image and the reference image.

8. A method for training a defect detection model, characterized in that, include: Multiple training samples are constructed, wherein the training samples include a predetermined test image, a predetermined reference image, and an annotated image for one or more defect regions in the predetermined test image; as well as The predetermined test image and the predetermined reference image are used as paired inputs to the defect detection model to generate defect detection results for the predetermined test image. Based on the defect detection results and the labeled image, the defect detection model is updated using a composite loss function. The composite loss function includes a first loss term for measuring classification accuracy and a second loss term for improving the ability to distinguish one or more defect regions when the sample class distribution is imbalanced.

9. The method for training a defect detection model according to claim 8, characterized in that, Generating defect detection results for the predetermined test image includes: Using the feature extraction module in the defect detection model, corresponding multi-scale feature representations of the predetermined test image and the predetermined reference image are generated respectively. Using the feature processing module in the defect detection model, based on the corresponding multi-scale feature representation, difference features are generated. These difference features represent the difference between the part to be detected in the predetermined test image and the reference part in the predetermined reference image; and Using the decoding module in the defect detection model, defect detection results are generated for the predetermined test image based on the difference features.

10. The method for training a defect detection model according to claim 9, characterized in that, The feature extraction module includes two feature extraction branches with shared weights, and generates corresponding multi-scale feature representations for the predetermined test image and the predetermined reference image, including: The predetermined test image and the predetermined reference image are respectively input into the two feature extraction branches; and In the two feature extraction branches, based on the shared weights, corresponding multi-scale feature representations of the predetermined test image and the predetermined reference image are extracted at multiple scales respectively.

11. The method for training a defect detection model according to claim 10, characterized in that, The two feature extraction branches are symmetrical dual-branch coding structures.

12. The method for training a defect detection model according to claim 9, characterized in that, The feature processing module includes an attention module, and generating the differential features includes: The attention module is used to process the corresponding multi-scale feature representations of the predetermined test image and the predetermined reference image, such that the target region has a greater influence on the processed corresponding multi-scale feature representations than other regions, where the target region is the difference region between the predetermined test image and the predetermined reference image; and The difference features are generated based on the processed corresponding multi-scale feature representations.

13. The method for training a defect detection model according to claim 12, characterized in that, The attention module is positioned on the skip connection path between the feature extraction module and the decoding module.

14. An electronic device, characterized in that, include: At least one processing unit; as well as At least one memory coupled to the at least one processing unit and storing instructions for execution by the at least one processing unit, the instructions causing the electronic device to perform the method according to any one of claims 1 to 7 or 8 to 13 when executed by the at least one processing unit.

15. A computer-readable storage medium, characterized in that, It stores a computer program thereon, characterized in that the computer program can be executed by a processor to implement the method according to any one of claims 1 to 7 or 8 to 13.

Images