Fractional frequency division phase-locked loop for FMCW radar

Abstract

The invention relates to a fractional frequency division phase-locked loop for an FMCW radar. The fractional frequency division phase-locked loop comprises a phase frequency detector, a charge pump, a low-pass filter, a voltage-controlled oscillator, a multimode frequency divider, a delta-sigma modulator, a chirp signal generation module and a linearity calibration module, when the fractional frequency division phase-locked loop is in a closed-loop acquisition mode, the chirp signal generation module acquires control voltage time sequence data of the voltage-controlled oscillator in a complete chirp period; and when the fractional frequency division phase-locked loop is in an open-loop driving mode, the chirp signal generation module generates an analog voltage signal according to the control voltage time sequence data, and drives the voltage-controlled oscillator to output a chirp signal. The problems of poor VCO tuning linearity, performance drift at extreme temperature, quantization noise leakage, insufficient multi-target interference adaptation, slow frequency modulation response speed and the like in the prior art are solved, the distance measurement precision of the FMCW radar is improved, and particularly the close-range distance measurement performance and the high-speed target detection capability are improved.

Description

Technical Field

[0001] This invention relates to the field of radio frequency integrated circuit design technology, and in particular to a fractional frequency division phase-locked loop for FMCW radar. Background Technology

[0002] FMCW radar, with its advantages of simple structure, high ranging accuracy, and strong anti-interference capability, is widely used in vehicle ranging, industrial inspection, security monitoring, and other fields. In an FMCW radar system, the quality of the linear frequency modulated signal output by the local oscillator module directly determines the ranging accuracy of the radar. The greater the linearity error of the frequency modulated signal, the more severe the distortion of the difference frequency signal between the radar echo and the local oscillator signal, which in turn leads to an increase in ranging error, especially in close-range ranging scenarios where this problem is more prominent.

[0003] Fractional-frequency divider PLLs have become the core choice for FMCW radar local oscillator modules due to their high frequency resolution and wide output frequency band. However, existing fractional-frequency divider PLLs have the following technical drawbacks: 1. Insufficient tuning linearity of voltage-controlled oscillator (VCO): Most existing VCOs adopt a single-stage or two-stage capacitor tuning structure. Near the first and second frequencies, the non-linear characteristics of the capacitance-voltage (CV) of the varactor tube can easily lead to a large tuning linearity error, which cannot meet the requirements of high-precision short-range ranging. 2. Poor adaptability to extreme environments: In a wide operating temperature range of -40℃ to 125℃, the capacitance of the low-pass filter (LPF) and the output current of the charge pump (CP) will drift with temperature, resulting in a decrease in the stability of the PLL loop and further deterioration of the VCO frequency modulation linearity. 3. Insufficient quantization noise suppression: Quantization noise generated by the Δ-Σ modulator is prone to leakage in the 80~100MHz frequency band and cannot be completely suppressed by the traditional LPF, resulting in increased spurious signals in the PLL output signal and affecting the radar's anti-interference capability; 4. Slow frequency modulation response speed: Traditional fractional frequency divider PLLs use a closed-loop adjustment mechanism, and the lock-in delay is usually several microseconds, which limits the frequency modulation slope and cannot meet the requirements of high-speed target detection for fast chirped signals; Therefore, developing a fractional-division PLL that combines high linearity, wide temperature stability, low noise characteristics, and fast frequency modulation capability, and is suitable for the multi-scenario requirements of FMCW radar, has become an urgent need in the field of radio frequency integrated circuit design. Summary of the Invention

[0004] The purpose of this invention is to overcome the shortcomings of existing fractional frequency division phase-locked loops (FCLs) in FMCW radar applications, and to provide a FCL that can generate fast, high-linearity chirped signals. This invention solves problems such as poor VCO tuning linearity, performance drift under extreme temperatures, quantization noise leakage, insufficient multi-target interference adaptation, and slow frequency modulation response in existing technologies. At the same time, it improves the ranging accuracy of FMCW radar (especially improving short-range ranging performance) and high-speed target detection capability.

[0005] The technical solution of the present invention is as follows: a fractional-frequency phase-locked loop for FMCW radar, comprising: a frequency and phase detector, a charge pump, a low-pass filter, a voltage-controlled oscillator, a multi-mode frequency divider and a Δ-Σ modulator, a chirp signal generation module, and a linearity calibration module; The output of the frequency and phase detector is connected to the input of the charge pump. The output of the charge pump is connected to the input of the low-pass filter. The output of the low-pass filter is connected to the input of the chirp signal generation module. The output of the chirp signal generation module is connected to the input of the voltage-controlled oscillator. The output of the voltage-controlled oscillator is connected to one input of the linearity calibration module and the multi-mode frequency divider. The other input of the multi-mode frequency divider is connected to the Δ-Σ modulator. The output of the multi-mode frequency divider is connected to the input of the frequency and phase detector. When the fractional-frequency phase-locked loop is in closed-loop acquisition mode, the chirp signal generation module acquires the control voltage timing data of the voltage-controlled oscillator within the complete chirp cycle; When the fractional-frequency phase-locked loop is in open-loop drive mode, the chirp signal generation module generates an analog voltage signal based on the control voltage timing data, driving the voltage-controlled oscillator to output a chirp signal.

[0006] Furthermore, the chirp signal generation module includes a mode switching unit, an analog-to-digital conversion unit, a storage unit, and a digital-to-analog conversion unit. The mode switching unit is connected to the output of the low-pass filter, the input of the analog-to-digital conversion unit, and the output of the digital-to-analog conversion unit. The output of the analog-to-digital conversion unit is connected to the input of the storage unit, and the output of the storage unit is connected to the input of the digital-to-analog conversion unit.

[0007] Furthermore, when the fractional-frequency phase-locked loop is in closed-loop acquisition mode, the mode switching unit can connect the output of the low-pass filter to the input of the voltage-controlled oscillator and the input of the analog-to-digital converter. When the fractional-frequency phase-locked loop is in open-loop drive mode, the output of the low-pass filter can be connected to the input of the voltage-controlled oscillator and the output of the digital-to-analog converter.

[0008] Furthermore, the linearity calibration module includes: a linearity detection module, a calibration voltage generation module, and a feedback control module. The input terminal of the linearity detection module is connected to a voltage-controlled oscillator, the output terminal of the linearity detection module is connected to the input terminal of the calibration voltage generation module, the output terminal of the calibration voltage generation module is connected to the input terminal of the feedback control module, and the output terminal of the feedback control module is connected to the voltage-controlled oscillator. The linearity detection module converts the frequency modulation signal output by the voltage-controlled oscillator into a corresponding voltage signal, compares the voltage signal with a preset ideal linear voltage reference curve, and outputs a linearity error signal. The calibration voltage generation module converts the linearity error signal into an analog calibration voltage. The feedback control module is used to compensate the analog calibration voltage when the voltage-controlled oscillator is at a preset temperature.

[0009] Furthermore, the charge pump adopts a current-directing charge pump topology.

[0010] Furthermore, the low-pass filter adopts a passive third-order RC topology.

[0011] Furthermore, the voltage-controlled oscillator includes: a current source I1, a MOSFET group, a resistor R1, a capacitor C1, an inductor L1, a first MOSFET M1, a second MOSFET M2, a third MOSFET M3, a coarse adjustment capacitor group, a fine adjustment capacitor group, and an ultra-fine adjustment capacitor group. The positive terminal of the current source I1 is connected to the operating voltage VDD, and the negative terminal of the current source I1 is connected to one end of the MOSFET group. The other end of the MOSFET group is grounded. The gate of the MOSFET group is connected to one end of the resistor R1. The other end of the resistor R1 is connected to one end of the capacitor C1 and the gate of the first MOSFET M1. The other end of the capacitor C1 is grounded. The source of the first MOSFET M1 is grounded. The drain of the first MOSFET M1 is connected to the source of the second MOSFET M2 and the source of the third MOSFET M3. The gate of the second MOSFET M2 is connected to the drain of the third MOSFET M3, one end of the coarse adjustment capacitor group, one end of the fine adjustment capacitor group, one end of the ultra-fine adjustment capacitor group, and one end of the inductor L1. The gate of the third MOSFET M3 is connected to the drain of the second MOSFET M2, which is connected to the other end of the coarse adjustment capacitor group, the other end of the fine adjustment capacitor group, the other end of the ultra-fine adjustment capacitor group, and the other end of the inductor L1.

[0012] Furthermore, the coarse adjustment capacitor bank includes two sets of parallel MOS varactor transistors with slightly larger capacitance values; The fine-tuning capacitor bank consists of three groups of MOS varactors with medium capacitance values, used to finely calibrate the operating frequency band to the target frequency band. The ultra-fine adjustable capacitor bank uses low-noise MOS varactor transistors.

[0013] Furthermore, the multi-mode frequency divider adopts a synchronous frequency division architecture, supporting 2 N ~2 N+1 Integer division ratio switching within the range of -1.

[0014] Furthermore, the Δ-Σ modulator adopts a 3rd-order sp-mash111 topology.

[0015] The beneficial effects of this invention are: 1. Significantly improved tuning linearity: Through the coordinated design of the three-stage tuning array of the voltage-controlled oscillator (VCO) and the linearity calibration circuit, the tuning linearity error of the VCO in the entire target frequency band is controlled to ≤2%, especially solving the nonlinearity problem at the frequency band edge, reducing the ranging error of FMCW radar at close range, and meeting the requirements of high-precision ranging. 2. Strong wide temperature adaptability: Through the self-bias temperature compensation of the charge pump CP, the temperature-sensitive capacitor compensation of the LPF PTC, and the temperature compensation of the linearity calibration circuit, the PLL can operate stably in a wide temperature range of -40℃ to 125℃, reducing loop bandwidth fluctuations and VCO frequency drift, making it suitable for extreme environment applications such as automotive and industrial applications. 3. Excellent noise suppression capability: The 3rd order sp-mash111 topology and noise shaping technology of the Δ-Σ modulator, combined with the high-frequency noise suppression function of the low-pass filter LPF, makes the in-band quantization noise power density ≤-100dBc / Hz and the phase noise at a 1MHz offset frequency ≤-115dBc / Hz, thus improving the radar's anti-interference capability. 4. Balance between power consumption and integration: Based on 55nm RF CMOS process, it integrates functions such as linearity calibration and temperature compensation, without the need for additional external circuits, and is suitable for the miniaturization and low power consumption design requirements of FMCW radar. 5. Good radar adaptability: Through the fast frequency division ratio switching and adjustable frequency modulation slope design of the multi-mode frequency divider (MMD), it can adapt to the target detection requirements of different distances and speeds, and can be widely used in various FMCW radar systems; 6. Excellent frequency modulation response speed: By adopting the newly added "closed-loop acquisition-open-loop drive" fast chirp signal generation structure, the locking delay of the traditional closed-loop PLL is avoided. The frequency modulation slope of the chirp signal in open-loop mode can be greatly improved, resulting in a significant improvement in response speed compared to the traditional closed-loop mode. At the same time, through the linearity calibration voltage superposition mechanism, the frequency modulation linearity error is guaranteed during open-loop drive, which can accurately adapt to high-speed target detection scenarios. Attached Figure Description

[0016] Figure 1 This is a structural block diagram of the present invention.

[0017] Figure 2 This is a circuit diagram of the charge pump of the present invention.

[0018] Figure 3 This is a circuit diagram of the voltage-controlled oscillator of the present invention.

[0019] Figure 4 This is a schematic diagram of the linearity calibration module in this invention. Detailed Implementation

[0020] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments. The described embodiments are merely some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0021] In the technical solution of the present invention, Figure 1 This is a structural block diagram provided according to a specific structure of a fractional frequency division phase-locked loop for FMCW radar according to the present invention. Figure 1 As shown, the present invention includes: A fractional-frequency phase-locked loop for FMCW radar includes: a frequency and phase detector 1, a charge pump 2, a low-pass filter 3, a voltage-controlled oscillator 4, a multi-mode frequency divider 5, a Δ-Σ modulator 6, a chirp signal generation module 7, and a linearity calibration module 8.

[0022] The output terminal of the frequency and phase detector 1 is connected to the input terminal of the charge pump 2. The output terminal of the charge pump 2 is connected to the input terminal of the low-pass filter 3. The output terminal of the low-pass filter 3 is connected to the input terminal of the chirp signal generation module 7. The output terminal of the chirp signal generation module 7 is connected to the input terminal of the voltage-controlled oscillator 4. The output terminal of the voltage-controlled oscillator 4 is connected to one input terminal of the linearity calibration module 8 and the multi-mode frequency divider 5. The other input terminal of the multi-mode frequency divider 5 is connected to the Δ-Σ modulator 6. The output terminal of the multi-mode frequency divider 5 is connected to the input terminal of the frequency and phase detector 1. When the fractional-frequency phase-locked loop is in closed-loop acquisition mode, the chirp signal generation module 7 acquires the control voltage timing data of the voltage-controlled oscillator 4 within the complete chirp cycle; When the fractional frequency division phase-locked loop is in open-loop drive mode, the chirp signal generation module 7 generates an analog voltage signal based on the control voltage timing data, driving the voltage-controlled oscillator 4 to output a chirp signal.

[0023] In embodiments of the present invention, such as Figure 1As shown, the chirp signal generation module 7 includes a mode switching unit 71, an analog-to-digital converter 72, a storage unit 73, and a digital-to-analog converter 74. The mode switching unit 71 is connected to the output of the low-pass filter 3, the input of the analog-to-digital converter 72, and the output of the digital-to-analog converter 74. The output of the analog-to-digital converter 72 is connected to the input of the storage unit 73, and the output of the storage unit 73 is connected to the input of the digital-to-analog converter 74.

[0024] The mode switching unit 71 can connect the output of the low-pass filter 3 to the input of the voltage-controlled oscillator 4 and the input of the analog-to-digital converter 72 when the fractional-frequency-locked loop is in closed-loop acquisition mode. It can also connect the output of the low-pass filter 3 to the input of the voltage-controlled oscillator 4 and the output of the digital-to-analog converter 74 when the fractional-frequency-locked loop is in open-loop drive mode. The mode switching unit 71 includes multiple switches and a controller; path switching is achieved by the controller controlling the switches.

[0025] The chirp signal generation structure includes an analog-to-digital converter (ADC), a high-speed memory, a digital-to-analog converter (DAC), and a mode switching unit 71. The mode switching unit 71 is connected to the LPF output, ADC input, DAC output, and VCO control terminal, respectively, and is used to switch the PLL between "closed-loop acquisition mode" and "open-loop drive mode". The ADC input is coupled to the VCO control terminal through the mode switching unit 71, and its output is connected to the high-speed memory, and is used to acquire VCO control voltage timing data within a complete chirp cycle in the closed-loop acquisition mode. The high-speed memory output is connected to the DAC input and is used to buffer the control voltage timing data. The DAC output is coupled to the VCO control terminal through the mode switching unit 71 and is used to restore the buffered control voltage timing data to an analog voltage signal in the open-loop drive mode, driving the VCO to output a fast chirp signal. Furthermore, the calibration voltage of the linearity calibration circuit can be superimposed on the DAC output to ensure the frequency modulation linearity of the open-loop drive.

[0026] In embodiments of the present invention, such as Figure 4 As shown, the linearity calibration module 8 includes: a linearity detection module 81, a calibration voltage generation module 82, and a feedback control module 83. The input terminal of the linearity detection module 81 is connected to the voltage-controlled oscillator 4, the output terminal of the linearity detection module 81 is connected to the input terminal of the calibration voltage generation module 82, the output terminal of the calibration voltage generation module 82 is connected to the input terminal of the feedback control module 83, and the output terminal of the feedback control module 83 is connected to the voltage-controlled oscillator 4.

[0027] The linearity detection module 81 converts the frequency modulation signal output by the voltage-controlled oscillator 4 into a corresponding voltage signal, compares the voltage signal with a preset ideal linear voltage reference curve, and outputs a linearity error signal.

[0028] The calibration voltage generation module 82 converts the linearity error signal into an analog calibration voltage.

[0029] The feedback control module 83 is used to compensate the analog calibration voltage when the voltage-controlled oscillator 4 is at a preset temperature.

[0030] Linearity detection module 81: It adopts a high-precision frequency-to-voltage (FV) converter to convert the frequency modulation signal output by the VCO into a corresponding voltage signal, compares it with the preset ideal linear voltage reference curve through a comparator, and outputs a linearity error signal. Calibration voltage generation module 82: Uses a digital-to-analog converter (DAC) to convert the linearity error signal into an analog calibration voltage, and ensures calibration accuracy through a high-resolution DAC; Feedback control module 83: Built-in temperature sensor to collect the operating temperature of the VCO in real time. When the temperature changes within the range of -40℃ to 125℃, temperature compensation is performed on the calibration voltage to suppress the influence of temperature drift on the tuning linearity.

[0031] The signal input terminal of the linearity calibration circuit is coupled to the output terminal of the VCO, and the signal output terminal is connected to the control terminal of the three-stage capacitor tuning array. The linearity calibration circuit is used to detect the linearity deviation of the VCO output frequency modulation signal in real time, generate a dynamic calibration voltage and apply it to the ultra-fine tuning capacitor group, dynamically correct the capacitance-voltage (CV) nonlinearity characteristics of the varactor tube, and ensure that the tuning linearity error of the VCO in the entire target frequency band meets the requirements.

[0032] In an embodiment of the present invention, the charge pump employs a current-directing charge pump topology.

[0033] In an embodiment of the present invention, the low-pass filter 3 adopts a passive third-order RC topology.

[0034] In an embodiment of the present invention, the voltage-controlled oscillator 4 includes: a current source I1, a MOSFET group, a resistor R1, a capacitor C1, an inductor L1, a first MOSFET M1, a second MOSFET M2, a third MOSFET M3, a coarse adjustment capacitor group, a fine adjustment capacitor group, and an ultra-fine adjustment capacitor group. The positive terminal of the current source I1 is connected to the operating voltage VDD, and the negative terminal of the current source I1 is connected to one end of the MOSFET group. The other end of the MOSFET group is grounded. The gate of the MOSFET group is connected to one end of the resistor R1. The other end of the resistor R1 is connected to one end of the capacitor C1 and the gate of the first MOSFET M1. The other end of the capacitor C1 is grounded. The source of the first MOSFET M1 is grounded. The drain of the first MOSFET M1 is connected to the source of the second MOSFET M2 and the source of the third MOSFET M3. The gate of the second MOSFET M2 is connected to the drain of the third MOSFET M3, one end of the coarse adjustment capacitor group, one end of the fine adjustment capacitor group, one end of the ultra-fine adjustment capacitor group, and one end of the inductor L1. The gate of the third MOSFET M3 is connected to the drain of the second MOSFET M2, which is connected to the other end of the coarse adjustment capacitor group, the other end of the fine adjustment capacitor group, the other end of the ultra-fine adjustment capacitor group, and the other end of the inductor L1.

[0035] In an embodiment of the present invention, the coarse adjustment capacitor group includes two groups of parallel MOS varactors with slightly larger capacitance values; The fine-tuning capacitor bank consists of three groups of MOS varactors with medium capacitance values, used to finely calibrate the operating frequency band to the target frequency band. The ultra-fine adjustable capacitor bank uses low-noise MOS varactor transistors.

[0036] In an embodiment of the present invention, the multi-mode frequency divider adopts a synchronous frequency division architecture and supports 2 N ~2 N+1 Integer division ratio switching within the range of -1.

[0037] In an embodiment of the present invention, the Δ-Σ modulator adopts a 3rd order sp-mash111 topology.

[0038] This invention is based on a 55nm RF CMOS process.

[0039] In this invention: 1. Frequency and Phase Detector (PFD): It adopts an edge-triggered architecture based on RS flip-flops, integrates a precharge unit and a high-speed inverter chain, and is used to receive the reference clock signal and the frequency division signal fed back by MMD to achieve accurate detection of the phase difference between the two. Its response time is ≤5ns, dead time is ≤1ns, and phase detection error is ≤0.1rad.

[0040] The PFD adopts an edge-triggered structure based on TSPC (True Single Phase Clock) RS flip-flops. The pre-charge circuit uses a current source load composed of PMOS transistors, and the high-speed inverter chain consists of 5 CMOS inverters. The power supply voltage is 1.2V. Simulation tests show that the PFD has a response time of 4.8ns, a dead time of 0.8ns, and a phase detection error of 0.08rad, which meets the high-frequency phase detection requirements of the 5.8GHz band.

[0041] 2. Charge Pump (CP): Employs a current-directing charge pump topology, such as... Figure 2 As shown, this structure is an improvement on the drain-switched charge pump, incorporating a set of inverted UP and DOWN signal control switches and a unity-gain buffer, while integrating a self-biased temperature compensation circuit. This circuit converts the phase difference signal output by the PFD into a corresponding charge signal, improving its static current matching and current fluctuation within the operating temperature range of -40℃ to 125℃. In this structure, the output of the unity-gain buffer maintains a tracking potential with the output of the charge pump. Regardless of whether the switch is on or off, the drains of the two current-source MOSFETs always maintain electrical connection to the charge pump output through their corresponding switch branches or unity-gain buffers. Therefore, the drain voltage can be kept consistent with the charge pump output voltage, effectively avoiding the capacitance charging and discharging phenomenon between the source and substrate of the switching MOSFET, thus eliminating the charge shunting problem. Since the current source can continuously maintain the current path through its corresponding switch branch, the current source can always remain on, significantly improving the switching response speed of the charge pump. Based on the above design, the response speed of the charge pump structure described in this application is superior to existing charge pump structures. In this structure, the current flowing into the power supply terminal and the ground terminal can remain constant, effectively reducing the crosstalk effect on the power supply.

[0042] It adopts a current-directing charge pump topology, and the operational amplifier is a rail-to-rail input operational amplifier. The switches for UP and DOWN signals are equipped with dummy transistors. The self-biased temperature compensation circuit consists of an NTC thermistor and an operational amplifier.

[0043] 3. Low-pass filter (LPF): It adopts a passive third-order RC topology. The LPF integrates a PTC temperature-sensitive capacitor to compensate for capacitance drift caused by temperature changes, reduce loop bandwidth fluctuations, and stabilize the damping coefficient in the range of 0.7~0.9.

[0044] The passive 3rd order RC topology uses high-precision resistors, MIM capacitors for the base capacitors, and ceramic capacitors for the PTC temperature-sensitive capacitors. Within the temperature range of -40℃ to 125℃, the loop bandwidth fluctuates by 6%, and the damping coefficient remains stable in the range of 0.75 to 0.85.

[0045] 4. Voltage-controlled oscillator (VCO): such as Figure 4 As shown, a high-linearity three-stage tuning architecture is adopted, consisting of a resonant cavity and a three-stage capacitor tuning array coupled to the resonant cavity; the resonant cavity is composed of a high-Q spiral inductor and a basic varactor diode, used to achieve wide-band frequency resonance; the three-stage capacitor tuning array includes: Coarse adjustment capacitor bank: It consists of two sets of MOS varactors with slightly larger capacitance values ​​connected in parallel. It achieves step-by-step coarse adjustment of the frequency band through digital control signals, covering a wide frequency band. Fine-tuning capacitor bank: Consists of 3 groups of medium-capacitance MOS varactors, used to finely calibrate the operating frequency band to the target frequency band; Ultra-fine tuning capacitor bank: It adopts low-noise MOS varactors with the smallest capacitance adjustment range, which is specifically used to compensate for the nonlinear distortion of varactors at the edge of the frequency band.

[0046] The resonant cavity uses an octagonal topology for its spiral inductor; the coarse tuning capacitor group of the three-stage capacitor tuning array uses two sets of MOS varactors in parallel, the fine tuning capacitor group uses three sets of MOS varactors, and the ultra-fine tuning capacitor group uses low-noise MOS varactors; simulation tests show that the VCO's tuning range is 5.6~6.0GHz, and the tuning linearity error in the target frequency band of 5.725~5.875GHz is 1.5%.

[0047] 5. Linearity calibration circuit: Integrated inside the PLL, its signal input terminal is coupled to the output terminal of the VCO, and its signal output terminal is connected to the control terminal of the three-stage capacitor tuning array; the linearity calibration circuit includes a linearity detection module 81, a calibration voltage generation module 82, and a feedback control module 83. The ideal linear voltage reference curve is generated by calibration data stored in ROM; the calibration voltage generation module 82 uses a 12-bit DAC; the feedback control module 83 includes a temperature sensor with a temperature acquisition accuracy of 0.1℃; simulation test shows that the calibration circuit can correct the linearity error of VCO in the low frequency band of 5.725~5.75GHz from 4.1% to 1.9%, and the linearity fluctuation after temperature compensation is ≤0.2%.

[0048] 6. Multimode divider (MMD): Employs a synchronous frequency division architecture and supports 2 N ~2 N+1 The MMD allows for integer division ratio switching within a range of -1; its clock tree employs a symmetrical layout design to reduce signal transmission delay and avoid frequency glitches during frequency division switching; the input terminals of the MMD are connected to the output terminals of the VCO and the Δ-Σ modulator, respectively, and the output terminal is connected to the PFD. The symmetrical layout design of the MMD's clock tree reduces signal transmission delay, avoids frequency glitches during frequency division switching, and ensures the spectral purity of the PLL output signal.

[0049] It adopts a cascaded architecture of two / three frequency division units, and the frequency division ratio is switched by modifying the control word. The clock tree adopts a symmetrical H-tree layout; there are no frequency glitches during the switching process.

[0050] 7. Δ-Σ modulator: It adopts a 3rd order sp-mash111 topology and uses noise shaping technology to push quantization noise to the high frequency band. In conjunction with the LPF, it effectively suppresses quantization noise, making the in-band quantization noise power density ≤-100dBc / Hz, and ensuring the frequency stability of the PLL output signal. The output terminal of the Δ-Σ modulator is connected to the control terminal of the MMD and is used to dynamically adjust the division ratio of the MMD to realize the fractional division function.

[0051] The sp-mash111 structure is generated using digital Verilog code. Simulation tests show that the in-band quantization noise power density is <-103dBc / Hz, and the quantization noise power density in the high-frequency range can be effectively suppressed by the LPF.

[0052] 8. Chirped signal generation structure: including an analog-to-digital converter (ADC), a non-volatile memory, a digital-to-analog converter (DAC), and a mode switching unit 71. The connections and functions of each module are as follows: Mode switching unit 71: connected to the PLL loop (LPF output), ADC input, DAC output and VCO control terminal respectively, used to switch the PLL's "closed-loop acquisition mode" and "open-loop drive mode"; ADC: A high-speed ADC is adopted. The input terminal is coupled to the control voltage terminal of the VCO through the mode switching unit 71. It is used to acquire the control voltage timing data of the VCO within a complete chirp signal cycle in closed-loop acquisition mode. High-speed memory: SRAM memory is used and connected to the ADC output to buffer the timing data of VCO control voltage acquired by the ADC, ensuring that the data read / write rate matches the ADC sampling rate.

[0053] DAC: A high-speed DAC is adopted. The input terminal is connected to the output terminal of the memory, and the output terminal is coupled to the VCO control terminal through the mode switching unit 71. It is used to restore the control voltage timing data cached in the memory into an analog voltage signal in open-loop drive mode, and drive the VCO to output a fast chirp signal. The workflow of the fast chirp signal generation structure is as follows: When the first chirp signal is generated, the mode switching unit 71 switches to the closed-loop acquisition mode, the PLL operates in the conventional closed-loop mode, and the ADC synchronously acquires the real-time control voltage timing data of the VCO within the chirp cycle and stores it in the high-speed memory; when the subsequent chirp signal is generated, the mode switching unit 71 switches to the open-loop drive mode, disconnects the conventional closed-loop circuit of the PLL, and the high-speed memory restores the cached control voltage timing data into an analog voltage signal through the DAC and outputs it to the VCO control terminal, driving the VCO to output the fast chirp signal according to the preset timing; at the same time, the calibration voltage of the linearity calibration circuit can be superimposed on the DAC output terminal in real time to ensure the frequency modulation linearity in the open-loop drive mode.

[0054] The fractional-order frequency-locked loop (FLL) of the high-linearity chirped signal in this invention can be applied to an FMCW radar system using a PLL. The PLL serves as the local oscillator module of the radar and supports selective switching between closed-loop high-precision mode and open-loop fast mode. In closed-loop high-precision mode, it outputs a high-quality linear frequency-modulated signal; in open-loop fast mode, it outputs a fast chirped signal with an adjustable frequency modulation slope. The radar system also includes a transmitting antenna, a receiving antenna, a mixer, and a signal processing unit. The frequency-modulated signal output by the local oscillator module is divided into two paths: one path is radiated out through the transmitting antenna, and the other path is input to the mixer as a local oscillator reference signal. The echo signal reflected by the target is input to the mixer through the receiving antenna, mixed with the local oscillator reference signal, and output as a difference frequency signal. The difference frequency signal is processed by the signal processing unit to obtain the target distance, velocity, and angle information.

[0055] To further achieve fast frequency modulation and adapt to the requirements of high-speed target detection, this embodiment integrates a fast chirped signal generation structure on the basis of the aforementioned basic PLL architecture. Both are monolithically integrated using a 55nm RF CMOS process. The workflow of this fast chirped signal generation structure is as follows: (1) Closed-loop acquisition stage: The mode is switched to the closed-loop acquisition mode. The PLL works in closed loop and outputs a complete chirp signal. The ADC synchronously acquires the control voltage timing data of the VCO in this cycle and stores it in SRAM. (2) Open-loop drive stage: The mode is switched to open-loop drive mode, the PLL conventional closed-loop circuit is disconnected, the SRAM reads the cached data, restores it to the analog voltage signal through the DAC and outputs it to the VCO control terminal; the calibration voltage of the linearity calibration circuit is superimposed to the DAC output terminal through the adder to dynamically correct the linearity deviation of the open-loop drive. According to Cadence Virtuoso simulation verification, after integrating the fast chirp signal generation structure, the PLL in this embodiment has dual-mode operation capability and excellent overall performance: in closed-loop high-precision mode, it outputs a high-precision linear frequency modulated signal; in open-loop fast mode, the frequency modulation slope of the chirp signal can be stably and significantly improved.

[0056] In summary, the chirped signal generated by this invention has the characteristics of high precision, speed and high linearity. Its overall performance can meet many demanding application requirements and can significantly improve the performance of radar systems.

[0057] Finally, it should be noted that the above specific embodiments are only used to illustrate the technical solutions of the present invention and not to limit it. Although the present invention has been described in detail with reference to examples, those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical solutions of the present invention without departing from the spirit and scope of the technical solutions of the present invention, and all such modifications or substitutions should be covered within the scope of the claims of the present invention.

Claims

1. A fractional-frequency division multiplexing phase-locked loop for FMCW radar, characterized in that, include: Frequency and phase detector (1), charge pump (2), low-pass filter (3), voltage-controlled oscillator (4), multi-mode frequency divider (5) and Δ-Σ modulator (6), chirp signal generation module (7), linearity calibration module (8); The output of the frequency and phase detector (1) is connected to the input of the charge pump (2), the output of the charge pump (2) is connected to the input of the low-pass filter (3), the output of the low-pass filter (3) is connected to the input of the chirp signal generation module (7), the output of the chirp signal generation module (7) is connected to the input of the voltage-controlled oscillator (4), the output of the voltage-controlled oscillator (4) is connected to one input of the linearity calibration module (8) and the multi-mode frequency divider (5), the other input of the multi-mode frequency divider (5) is connected to the Δ-Σ modulator (6), and the output of the multi-mode frequency divider (5) is connected to the input of the frequency and phase detector (1). When the fractional frequency-locked loop is in closed-loop acquisition mode, the chirp signal generation module (7) acquires the control voltage timing data of the voltage-controlled oscillator (4) within the complete chirp cycle; When the fractional frequency-locked loop is in open-loop drive mode, the chirp signal generation module (7) generates an analog voltage signal based on the control voltage timing data, and drives the voltage-controlled oscillator (4) to output a chirp signal.

2. The fractional-frequency division multiplexing phase-locked loop for FMCW radar as described in claim 1, characterized in that, The chirp signal generation module (7) includes a mode switching unit (71), an analog-to-digital converter (72), a storage unit (73), and a digital-to-analog converter (74). The mode switching unit (71) is connected to the output of the low-pass filter (3), the input of the analog-to-digital converter (72), and the output of the digital-to-analog converter (74). The output of the analog-to-digital converter (72) is connected to the input of the storage unit (73), and the output of the storage unit (73) is connected to the input of the digital-to-analog converter (74).

3. The fractional-frequency division multiplexing phase-locked loop for FMCW radar as described in claim 2, characterized in that, The mode switching unit (71) can connect the output of the low-pass filter (3) to the input of the voltage-controlled oscillator (4) and the input of the analog-to-digital converter (72) when the fractional frequency division phase-locked loop is in closed-loop acquisition mode. When the fractional frequency division phase-locked loop is in open-loop drive mode, the output terminal of the low-pass filter (3) can be connected to the input terminal of the voltage-controlled oscillator (4) and the output terminal of the digital-to-analog converter (74).

4. The fractional-frequency division multiplexing phase-locked loop for FMCW radar as described in claim 1, characterized in that, The linearity calibration module (8) includes: a linearity detection module (81), a calibration voltage generation module (82), and a feedback control module (83). The input terminal of the linearity detection module (81) is connected to the voltage-controlled oscillator (4), the output terminal of the linearity detection module (81) is connected to the input terminal of the calibration voltage generation module (82), the output terminal of the calibration voltage generation module (82) is connected to the input terminal of the feedback control module (83), and the output terminal of the feedback control module (83) is connected to the voltage-controlled oscillator (4). The linearity detection module (81) converts the frequency modulation signal output by the voltage-controlled oscillator (4) into a corresponding voltage signal, compares the voltage signal with the preset ideal linear voltage reference curve, and outputs a linearity error signal. The calibration voltage generation module (82) converts the linearity error signal into an analog calibration voltage; The feedback control module (83) is used to compensate the analog calibration voltage when the voltage-controlled oscillator (4) is at a preset temperature.

5. The fractional-frequency division multiplexing phase-locked loop for FMCW radar as described in claim 1, characterized in that, The charge pump adopts a current-directing charge pump topology.

6. The fractional-frequency division multiplexing phase-locked loop for FMCW radar as described in claim 1, characterized in that, The low-pass filter (3) adopts a passive third-order RC topology.

7. The fractional-frequency division multiplexing phase-locked loop for FMCW radar as described in claim 1, characterized in that, The voltage-controlled oscillator (4) includes: current source I1, MOS transistor group, resistor R1, capacitor C1, inductor L1, first MOS transistor M1, second MOS transistor M2, third MOS transistor M3, coarse adjustment capacitor group, fine adjustment capacitor group, and ultra-fine adjustment capacitor group. The positive terminal of the current source I1 is connected to the operating voltage VDD, and the negative terminal of the current source I1 is connected to one end of the MOSFET group. The other end of the MOSFET group is grounded. The gate of the MOSFET group is connected to one end of the resistor R1. The other end of the resistor R1 is connected to one end of the capacitor C1 and the gate of the first MOSFET M1. The other end of the capacitor C1 is grounded. The source of the first MOSFET M1 is grounded. The drain of the first MOSFET M1 is connected to the source of the second MOSFET M2 and the source of the third MOSFET M3. The gate of the second MOSFET M2 is connected to the drain of the third MOSFET M3, one end of the coarse adjustment capacitor group, one end of the fine adjustment capacitor group, one end of the ultra-fine adjustment capacitor group, and one end of the inductor L1. The gate of the third MOSFET M3 is connected to the drain of the second MOSFET M2, which is connected to the other end of the coarse adjustment capacitor group, the other end of the fine adjustment capacitor group, the other end of the ultra-fine adjustment capacitor group, and the other end of the inductor L1.

8. The fractional-frequency division multiplexing phase-locked loop for FMCW radar as described in claim 7, characterized in that, The coarse adjustment capacitor bank includes two sets of parallel-connected MOS varactor transistors with slightly larger capacitance values. The fine-tuning capacitor bank consists of three groups of MOS varactors with medium capacitance values, used to finely calibrate the operating frequency band to the target frequency band. The ultra-fine adjustable capacitor bank uses low-noise MOS varactor transistors.

9. The fractional-frequency division multiplexing phase-locked loop for FMCW radar as described in claim 1, characterized in that, The multi-mode frequency divider adopts a synchronous frequency division architecture and supports 2 N ~2 N+1 Integer division ratio switching within the range of -1.

10. The fractional-frequency division multiplexing phase-locked loop for FMCW radar as described in claim 1, characterized in that, The Δ-Σ modulator adopts a 3rd order sp-mash111 topology.

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