Method for forming isolation structure of image sensor and image sensor

Abstract

The invention discloses a forming method of an image sensor isolation structure and an image sensor, and the method comprises the steps: S1, providing a substrate, and forming a blanket type N well layer in the substrate; s2, a pixel area, a protection ring area and a peripheral area are arranged on the blanket type N well layer along the same plane, the protection ring area is arranged outside the pixel area in a surrounding mode, and the peripheral area is arranged outside the protection ring area in a surrounding mode; s3, etching between the peripheral region and the protection ring region and / or between the protection ring region and the pixel region to form a silicon through hole isolation structure; and the silicon through hole isolation structure penetrates through the blanket type N well layer and extends to the upper surface of the substrate. According to the through silicon via isolation structure, the blanket type N well layer is isolated into two or more sub-wells, a transverse leakage path of electrons migrating between different functional areas through the blanket type N well layer is fundamentally cut off, and electrical isolation or optical isolation between the different functional areas is achieved while high full well capacity is guaranteed.

Description

Technical Field

[0001] This invention relates to the field of image sensor technology, and in particular to a method for forming an image sensor isolation structure and an image sensor. Background Technology

[0002] In the design and manufacturing of small-pixel image sensors, the full-well capacity of a pixel directly determines the dynamic range and image acquisition quality of the sensor. Improving the full-well capacity is one of the core requirements for optimizing device performance. To enhance the full-well capacity, the industry commonly introduces a blanket N-well layer within the semiconductor substrate. This layer is typically fabricated using mature processes such as high-energy ion implantation or epitaxial growth, covering functional areas such as the pixel region, guard ring region, and peripheral region. The blanket N-well layer expands the charge storage region from a localized, shallow N-type region to a global, deep N-type layer, significantly increasing the physical volume of charge storage. Furthermore, the uniform doping concentration of the blanket N-well layer forms a broad and gentle potential well, allowing for uniform charge distribution and greatly improving the utilization efficiency of the storage space.

[0003] While blanket N-well layers can improve full-well capacity, they still have drawbacks. Specifically, the blanket N-well layer causes all similar N-type doped regions within its coverage area (such as the N-type regions of photodiodes, guard rings, and peripheral transistors in pixel units) to form electrical shorts, directly disrupting the necessary electrical isolation between the pixel region, guard ring region, and peripheral region, introducing various performance risks to the device. For example, the blanket N-well layer provides multiple paths for current leakage, severely affecting the performance stability and reliability of the image sensor. One leakage path involves electrons migrating from the heavily doped N-type region in the peripheral region through the blanket N-well layer to the PN junction in the guard ring region, and then flowing into the P-type region and then to the heavily doped P-type region. This process significantly increases the standby power consumption of the image sensor and reduces device energy efficiency. Another leakage path involves electrons leaking directly from the blanket N-well layer to the semiconductor substrate. This process increases substrate noise, leading to aggravated fixed-mode noise and increased dark current levels in the image sensor, resulting in noise and image quality degradation during image acquisition.

[0004] To address the aforementioned shortcomings, traditional methods often employ deep trench isolation (DTI) structures to improve their structure. However, DTI structures are limited by their etching depth. When the depth of the blanket N-well layer exceeds the etching depth of DTI, or when the semiconductor substrate itself is N-type, DTI still cannot achieve effective electrical isolation.

[0005] The statements herein provide only background information in relation to this invention and do not necessarily constitute prior art. Summary of the Invention

[0006] The purpose of this invention is to isolate the blanket N-well layer into two or more sub-wells by introducing a silicon via isolation structure that penetrates the blanket N-well layer. This fundamentally cuts off the lateral leakage path for electrons to migrate between different functional regions of the blanket N-well layer, thereby achieving truly effective electrical or optical isolation between different functional regions while ensuring high full-well capacity, thus optimizing the performance of the image sensor.

[0007] To achieve the above objectives, the present invention provides a method for forming an image sensor isolation structure, comprising at least the following steps: Step S1: Provide a substrate and form a blanket N-well layer in the substrate; Step S2: A pixel region, a guard ring region, and a peripheral region are arranged along the same plane on the blanket N-well layer. The guard ring region is arranged around the pixel region, and the peripheral region is arranged around the guard ring region. Step S3: A through-silicon via (TSV) isolation structure is etched between the peripheral region and the guard ring region and / or between the guard ring region and the pixel region; the TSV isolation structure penetrates the blanket N-well layer and extends to the upper surface of the substrate.

[0008] Optionally, in step S1, the method for forming the blanket N-well layer is either ion implantation or epitaxial growth.

[0009] Optionally, the upper surface of the substrate may further form a shallow trench isolation structure, an interlayer dielectric layer, and a metal interconnect layer. The through-silicon via isolation structure penetrates the blanket N-well layer and extends to the shallow trench isolation structure, or extends to the interlayer dielectric layer, or extends to the metal interconnect layer.

[0010] Optionally, the depth of the through-silicon via isolation structure is greater than or equal to the depth of the substrate, or greater than or equal to the difference between the depth of the substrate and the depth of the shallow trench isolation structure.

[0011] Optionally, an insulating material layer is deposited on the sidewall surface of the through-silicon via isolation structure to achieve isolation from the substrate.

[0012] Optionally, the internal filling layer of the through-silicon via isolation structure is used to achieve metal interconnection, enhanced optical isolation, or thermal isolation.

[0013] Optionally, the metal filler layer is selected from any one of tungsten, titanium, copper, and aluminum.

[0014] Optionally, the interior of the through-silicon via (TSV) isolation structure is a cavity or filled with insulating material to enhance optical or thermal isolation.

[0015] Optionally, the depth of the blanket-type N-well layer is 0.5 μm to 6 μm.

[0016] The present invention also provides an image sensor formed using the method described above.

[0017] Compared with the prior art, the technical solution of the present invention has at least the following beneficial effects: 1) This invention forms a silicon via isolation structure that penetrates the blanket N-well layer by etching between different functional regions (between the peripheral region and the guard ring region and / or between the guard ring region and the pixel region). This physically divides the continuous blanket N-well layer into two or more sub-wells, fundamentally cutting off the lateral leakage path of electrons migrating between different functional regions through the blanket N-well layer. While ensuring high full-well capacity, it achieves truly effective and deep electrical or optical isolation between different functional regions, significantly improving the dynamic range, reliability and overall imaging performance of the image sensor.

[0018] 2) Furthermore, the through-silicon via (TSV) isolation structure is used to isolate different functional areas, and the deep trench isolation structure is used to isolate adjacent photodiodes in the pixel area. The two isolation structures work together to optimize the performance between different functional areas of the image sensor and within the pixel. Attached Figure Description

[0019] Figure 1 This is a flowchart illustrating the method for forming the image sensor isolation structure of the present invention.

[0020] Figure 2 This is a schematic diagram of the through-silicon via isolation structure formed between different functional regions according to the present invention.

[0021] Attached image labels: Substrate 10, Blanket N-well layer 20, Pixel region 30, Photodiode 31, Guard ring region 40, Peripheral region 50, Deep trench isolation structure 60, Through silicon via isolation structure 70, Shallow trench isolation structure 80, Interlayer dielectric layer 90, Metal interconnect layer 100, Insulating material layer 110, Metal filler layer 120. Detailed Implementation

[0022] The following detailed description, in conjunction with the accompanying drawings and specific embodiments, provides a method for forming an image sensor isolation structure and an image sensor according to the present invention. The advantages and features of the present invention will become clearer from the following description. It should be noted that the accompanying drawings are in a very simplified form and use non-precise proportions, used only to facilitate and clearly illustrate the embodiments of the present invention. Please refer to the accompanying drawings to make the objectives, features, and advantages of the present invention more apparent and understandable. It should be understood that the structures, proportions, sizes, etc., depicted in the accompanying drawings are only for illustrative purposes to aid those skilled in the art and are not intended to limit the implementation conditions of the present invention. Therefore, they have no substantial technical significance. Any modifications to the structure, changes in proportions, or adjustments to the size, without affecting the effects and objectives achieved by the present invention, should still fall within the scope of the technical content disclosed in the present invention.

[0023] In the manufacturing of image sensors, although introducing a blanket N-well layer into the substrate can increase the full-well capacity of the pixels, the blanket N-well layer will cause all the N-type doped regions of the same type in the area it covers to form an electrical short circuit, providing multiple paths for current leakage, destroying the necessary electrical isolation between different functional areas (peripheral area, guard ring area, pixel area), and seriously affecting the performance stability and reliability of the image sensor.

[0024] Traditional methods often employ deep trench isolation structures to isolate adjacent photodiodes in the pixel region to prevent crosstalk. For example, deep trench isolation structures can be applied to the isolation periphery and guard ring regions, or the guard ring region and the pixel region. However, the etching depth of the deep trench isolation structure in the periphery and guard ring regions is limited. When the depth of the blanket N-well layer in the periphery and guard ring regions (from the back side BS to the front side FS) exceeds the etching depth of the deep trench isolation structure, or when the semiconductor substrate itself is N-type, the deep trench isolation structure still cannot achieve effective electrical isolation.

[0025] To address the current leakage problem caused by the potential connection between different functional regions in a blanket N-well layer, this invention forms a through-silicon via (TSV) isolation structure that penetrates the blanket N-well layer by etching between the peripheral region and the guard ring region, and / or between the guard ring region and the pixel region. This physically divides the continuous blanket N-well layer into two or more sub-wells, fundamentally cutting off the lateral leakage path for electrons migrating between different functional regions through the blanket N-well layer. While ensuring high full-well capacity, this achieves truly effective electrical or optical isolation between different functional regions, significantly improving the performance of the image sensor. The following details the method for forming the image sensor isolation structure and the image sensor itself.

[0026] like Figure 1 As shown, the present invention provides a method for forming an image sensor isolation structure, comprising at least the following steps: Step S1: Provide a substrate and form a blanket N-well layer within the substrate.

[0027] Figure 2 In this design, the substrate 10 can be a P-type substrate, which, together with the internally formed blanket N-well layer 20, forms a vertical PN junction. The built-in electric field of this PN junction is the driving force for separating and collecting photogenerated electrons. The driving force of the built-in electric field pushes the photogenerated electrons toward the blanket N-well layer 20, which provides a larger and deeper potential well (i.e., a storage region) for the photogenerated electrons, thereby significantly increasing the total charge that a single pixel can hold and improving the full-well capacity. In some embodiments, the depth of the blanket N-well layer 20 is 0.5 μm to 6 μm.

[0028] In some embodiments, the method for forming the blanket N-well layer 20 is either ion implantation or epitaxial growth. If ion implantation is used, phosphorus or arsenic can be used as dopants, and a higher implantation energy is required to ensure a sufficiently deep well layer. If epitaxial growth is used, an N-type single-crystal silicon layer can be directly epitaxially grown on the upper surface (front FS) of the substrate 10, and epitaxial growth can achieve better crystal quality. This invention does not limit this, as long as a blanket N-well layer 20 that meets the performance requirements can be obtained.

[0029] Step S2: A pixel area, a guard ring area, and a peripheral area are arranged along the same plane on the blanket N-well layer. The guard ring area is arranged around the pixel area, and the peripheral area is arranged around the guard ring area.

[0030] After forming the blanket N-well layer 20, at least three functional regions are arranged on it along the same plane: pixel region 30, guard ring region 40, and peripheral region 50 (see [link]). Figure 2 In this design, pixel region 30 is located internally and serves as the photosensitive area. A guard ring region 40 surrounds pixel region 30 to prevent stray charges from the peripheral region 50 from flowing into pixel region 30. It also collects stray charges at the edges of pixel region 30 to prevent outward diffusion. The peripheral region 50 surrounds the guard ring region 40 and includes logic circuits such as row / column drivers and readout circuits. However, since these three functional regions are all located above the blanket N-well layer 20, all N-type doped regions of the same type form an electrical short circuit, which may lead to current leakage problems.

[0031] Therefore, after the three functional regions are formed, some embodiments further include etching a deep trench isolation structure 60 from the lower surface (back side BS) of the substrate 10. The deep trench isolation structure 60 penetrates the blanket N-well layer 20 and extends upward to the photodiode 31, isolating adjacent photodiodes 31.

[0032] Step S3: A through-silicon via (TSV) isolation structure is etched between the peripheral region and the guard ring region and / or between the guard ring region and the pixel region; the TSV isolation structure penetrates the blanket N-well layer and extends to the upper surface of the substrate.

[0033] Etching is performed on the lower surface (back side BS) of substrate 10 to form a through-silicon via (TSV) isolation structure 70. The TSV isolation structure 70 penetrates the blanket N-well layer 20 and extends to the upper surface (front side FS) of substrate 10. The depth of the TSV isolation structure 70 must be greater than or equal to the depth of substrate 10 to ensure complete penetration. In some embodiments, the TSV isolation structure 70 is formed between the peripheral region 50 and the guard ring region 40 to completely isolate the peripheral region 50 and the guard ring region 40. In other embodiments, the TSV isolation structure 70 is formed between the guard ring region 40 and the pixel region 30 to completely isolate the guard ring region 40 and the pixel region 30. In still other embodiments, the TSV isolation structure 70 is formed between the peripheral region 50 and the guard ring region 40 to completely isolate the peripheral region 50 and the guard ring region 40, and also between the guard ring region 40 and the pixel region 30 to completely isolate the guard ring region 40 and the pixel region 30. This invention does not limit the number of through-silicon via (TSV) isolation structures 70, as long as the TSV isolation structures 70 can isolate different functional areas.

[0034] In some embodiments, the upper surface (front side FS) of the substrate 10 is further formed with a shallow trench isolation structure 80, an interlayer dielectric layer 90, and a metal interconnect layer 100 to meet relevant performance requirements. The shallow trench isolation structure 80 effectively isolates adjacent transistors or active regions, preventing electrical crosstalk between circuits; the interlayer dielectric layer 90 provides electrical isolation with the metal interconnect layer 100 on its upper surface and provides a planarized surface. The main function of the metal interconnect layer 100 is to provide a foundation for subsequent metal interconnects and through-silicon vias (TSVs). In this example, the interlayer dielectric layer 90 is selected from silicon oxide, silicon nitride, and silicon oxynitride, and the method for depositing the interlayer dielectric layer 90 and the metal interconnect layer 100 is any one of chemical vapor deposition (CVD), physical vapor deposition (PVD), and atomic layer deposition (ALD), which is not limited in this invention.

[0035] When a shallow trench isolation structure 80, an interlayer dielectric layer 90, and a metal interconnect layer 100 are formed on the upper surface (front side FS) of the substrate 10, a through-silicon via (TSV) isolation structure 70 penetrates the blanket N-well layer 20 and extends to the shallow trench isolation structure 80, the interlayer dielectric layer 90, or the metal interconnect layer 100 to isolate different functional regions. When the TSV isolation structure 70 extends to the shallow trench isolation structure 80, the depth of the TSV isolation structure 70 must be greater than or equal to the difference between the depth of the substrate 10 and the depth of the shallow trench isolation structure 80 to ensure complete penetration of the blanket N-well layer 20.

[0036] Understandably, regardless of whether the through-silicon via (TSV) isolation structure 70 penetrates the blanket N-well layer 20 and extends to any of the following structures: the shallow trench isolation structure 80, the interlayer dielectric layer 90, or the metal interconnect layer 100, the TSV isolation structure 70 can divide the continuous blanket N-well layer 20 into two or more sub-wells (such as peripheral region sub-wells, pixel guard ring region sub-wells, etc.). This blocks the lateral leakage path of electrons migrating between different functional regions (peripheral region 50, guard ring region 40, pixel region 30) of the blanket N-well layer 20. While ensuring high full-well capacity, it achieves truly effective electrical or optical isolation between different functional regions, significantly reducing dark current, fixed-mode noise, and standby power consumption of the image, and improving the signal-to-noise ratio and reliability of the image sensor.

[0037] In some embodiments, an insulating material layer 110 is deposited on the sidewall surface of the through-silicon via (TSV) isolation structure 70. The insulating material layer 110 may be silicon oxide, used to achieve isolation from the substrate 10.

[0038] In some embodiments, the interior of the through-silicon via (TSV) isolation structure 70 may be filled with a metal filler layer 120 for metal interconnection. Specifically, the metal filler layer 120 forms an electrical connection with the metal interconnect layer 100, establishing a vertical electrical path from the front side (FS) to the back side (BS). The metal filler layer 120 also enhances optical or thermal isolation. The metal filler layer 120 is selected from any one of tungsten, titanium, copper, and aluminum.

[0039] In some embodiments, the interior of the through-silicon via (TSV) isolation structure 70 can be a cavity or filled with insulating material to enhance optical or thermal isolation.

[0040] In this example, the width of the through-silicon via (TSV) isolation structure 70 can also be appropriately controlled. If the width is too small, the high aspect ratio effect will cause uneven coverage depth of the insulating material layer 110 on the sidewalls, or even uncovered areas, resulting in incomplete electrical isolation; if the width is too large, it will introduce greater mechanical stress, thereby causing defects in the silicon lattice and impairing image quality.

[0041] The present invention also provides an image sensor formed by the above method, the image sensor including a through-silicon via (TSV) isolation structure 70. The TSV isolation structure 70 is formed between the peripheral region 50 and the guard ring region 40 and / or between the guard ring region 40 and the pixel region 30; the TSV isolation structure 70 penetrates the blanket N-well layer 20 and extends to the upper surface (front side FS) of the substrate 10, or extends to the shallow trench isolation structure 80, or extends to the interlayer dielectric layer 90, or extends to the metal interconnect layer 100. An insulating material layer 110 is deposited on the sidewall surface of the TSV isolation structure 70, the interior of which may be filled with a metal filler layer 120 or an insulating material, and the interior may also be a cavity.

[0042] In summary, this invention forms a through-silicon via (TSV) isolation structure that penetrates the blanket N-well layer by etching between the peripheral region and the guard ring region and / or between the guard ring region and the pixel region. This physically divides the continuous blanket N-well layer into two or more sub-wells, fundamentally cutting off the lateral leakage path for electrons to migrate between different functional regions (peripheral region, guard ring region, pixel region) through the blanket N-well layer. While ensuring high full-well capacity, it achieves truly effective and deep electrical or optical isolation between different functional regions, significantly improving the dynamic range, reliability, and overall imaging performance of the image sensor.

[0043] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0044] In the description of this invention, it should be understood that the terms "center," "height," "depth," "upper," "lower," "vertical," "horizontal," "top," "bottom," "inner," "outer," "axial," "radial," and "circumferential," etc., indicating orientation or positional relationships, are based on the orientation or positional relationships shown in the accompanying drawings and are only for the convenience of describing the invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of the invention. In the description of this invention, unless otherwise stated, "a plurality of" means two or more.

[0045] In this invention, unless otherwise explicitly specified and limited, "above" or "below" the second feature can include direct contact between the first and second features, or contact between the first and second features through another feature between them. Furthermore, "above," "over," and "on top" of the second feature includes the first feature directly above or diagonally above the second feature, or simply indicates that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature includes the first feature directly below or diagonally below the second feature, or simply indicates that the first feature is at a lower horizontal level than the second feature.

[0046] Although the present invention has been described in detail through the preferred embodiments above, it should be understood that the above description should not be considered as a limitation of the present invention. Various modifications and substitutions to the present invention will be apparent to those skilled in the art after reading the above description. Therefore, the scope of protection of the present invention should be defined by the appended claims.

Claims

1. A method for forming an isolation structure for an image sensor, characterized in that, Include at least the following steps: Step S1: Provide a substrate and form a blanket N-well layer in the substrate; Step S2: A pixel region, a guard ring region, and a peripheral region are arranged along the same plane on the blanket N-well layer. The guard ring region is arranged around the pixel region, and the peripheral region is arranged around the guard ring region. Step S3: A through-silicon via (TSV) isolation structure is etched between the peripheral region and the guard ring region and / or between the guard ring region and the pixel region; the TSV isolation structure penetrates the blanket N-well layer and extends to the upper surface of the substrate.

2. The method as described in claim 1, characterized in that, In step S1, the method for forming the blanket N-well layer is either ion implantation or epitaxial growth.

3. The method as described in claim 1, characterized in that, The upper surface of the substrate is further formed with a shallow trench isolation structure, an interlayer dielectric layer, and a metal interconnect layer. The through-silicon via isolation structure penetrates the blanket N-well layer and extends to the shallow trench isolation structure, or to the interlayer dielectric layer, or to the metal interconnect layer.

4. The method as described in claim 3, characterized in that, The depth of the through-silicon via isolation structure is greater than or equal to the depth of the substrate, or greater than or equal to the difference between the depth of the substrate and the depth of the shallow trench isolation structure.

5. The method as described in claim 1, characterized in that, An insulating material layer is deposited on the sidewall surface of the through-silicon via isolation structure to achieve isolation from the substrate.

6. The method as described in claim 5, characterized in that, The internal filling metal layer of the through-silicon via (TSV) isolation structure is used to achieve metal interconnection, enhanced optical isolation, or thermal isolation.

7. The method as described in claim 6, characterized in that, The metal filler layer is selected from any one of tungsten, titanium, copper, and aluminum.

8. The method as described in claim 5, characterized in that, The interior of the through-silicon via (TSV) isolation structure is either hollow or filled with insulating material to enhance optical or thermal isolation.

9. The method as described in claim 1, characterized in that, The depth of the blanket-type N-well layer is 0.5 μm to 6 μm.

10. An image sensor, characterized in that, It is formed using the method described in any one of claims 1-9.

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