Strong-surge-resistant protection circuit for multi-stage energy transfer

Abstract

The invention discloses a multi-stage energy transfer strong-surge-resistant protection circuit, which comprises a TVS (Transient Voltage Suppressor) tube network, a first-stage thyristor network and a second-stage thyristor network which are arranged in sequence, and is characterized in that the first-stage thyristor network is used for discharging surge exceeding first-stage peak voltage and current, and the second-stage thyristor network is used for discharging surge exceeding second-stage peak voltage and current; the second-stage thyristor network is used for discharging surge exceeding second-stage peak voltage and current, the second-stage peak voltage and current are larger than the first-stage peak voltage and current, and the TVS network is used for discharging residual surge peak energy. According to the strong-surge-resistant protection circuit with the multi-stage energy transfer function, the TVS network is used for preventing surge impact from a power grid; the two-stage thyristor network is used for realizing clamping protection at peak values of voltage and current; an auxiliary diode is additionally arranged in a feedback protection loop, so that overvoltage protection caused by surge impact is realized. The protection circuit solves the problem that inductive load equipment suffers from surge impact of a power grid during starting and stopping, and is simple in circuit structure, low in cost and high in universality.

Description

Technical Field

[0001] This invention relates to a multi-stage energy transfer surge protection circuit, belonging to the field of switching power supply technology. Background Technology

[0002] In electrical equipment with numerous inductive coils, such as welding machines, electric motors, and compressors (air conditioners, refrigerators), the current flowing through the coils creates a magnetic field during steady-state operation. However, during the transient process of starting and stopping, to maintain the original current, according to Lenz's law, suddenly connecting or disconnecting the circuit causes a drastic change in the magnetic field. This results in an extremely high back electromotive force (EMF) being generated in the inductor coil within a very short time (typically on the order of microseconds to milliseconds). Theoretically, the peak voltage of this back EMF can reach over 3kV, i.e., a surge voltage.

[0003] Assuming a clamping voltage of 1kV, a peak current of 5kA, and a duration of 50μs, the energy E ≈ 1kV * 5kA * 50e-6s = 250J. In reality, the energy is affected by the overall circuit impedance. Due to factors such as line distributed parameters, switching speed, and arc reignition, even higher surge voltages may occur. For a single high-power welding machine, the surge energy generated by a single switching action is typically between tens and hundreds of joules. If multiple welding machines operate simultaneously or frequently at the same node in the power grid, the accumulated energy will be enormous. Furthermore, high surge voltages are accompanied by huge surge currents. In the main circuit or related auxiliary circuits of equipment, the breakdown or energy release process caused by turn-off overvoltage may be accompanied by surge currents with peak values ​​between 3kA and 10kA. This current pulse has extremely high instantaneous power, with a very short rise time, typically within 0.1μs to 10μs, while the duration of the entire pulse (often measured in half-width time) ranges from 20μs to 200μs. This means that within a timescale of microseconds to hundreds of microseconds, the system needs to withstand a combined high-voltage, high-current surge with extremely high power density, representing a typical high-frequency, high-energy short-pulse event. The rapid influx of this instantaneous surge energy can cause bulging and even tube failure in internal electrolytic capacitors or common-mode inductors, such as... Figure 1 As shown, this directly leads to frequent machine failures; on the other hand, it can also inject into the power grid in reverse, affecting other equipment on the same line, ultimately severely reducing operating efficiency and safety. Therefore, in the design practice of protection circuits, engineers often need to consider a higher safety margin, designing the ability to withstand transient voltages to 6kV or even higher levels to ensure that the system maintains high reliability under extreme or unpredictable operating conditions. Figure 2The surge protection circuit shown uses a varistor connected in parallel across the input line of the device. When the line voltage is within the normal range, it presents a large impedance. When a surge voltage enters the device and exceeds the tolerance, the impedance of the varistor drops rapidly, absorbing the surge current to prevent the line voltage from becoming too high. However, the varistor has a slow response speed and cannot quickly suppress the voltage. Figure 3 As shown, the commonly used surge protection circuit solution in the industry is a varistor + TVS diode (transient voltage suppressor diode). Its advantages include extremely fast response speed (typically in the nanosecond range), precise clamping, and no aging issues, but its protection effect is limited and its cost is relatively high. Furthermore, in fields such as electricity metering, this type of electrical equipment, in addition to AC mains input, also features both AC and DC output functionality. In DC output applications, surge energy can also generate pulses and spikes in the output voltage, jeopardizing the reliable operation of downstream load equipment. Therefore, feedback protection considering surge energy is also of great significance.

[0004] In surge testing, 8 / 20μs current waveforms and 1.2 / 50μs voltage waveforms are commonly used to simulate such transient pulses. Specifically, "8 / 20μs" describes the waveform characteristics of the current pulse: the wavefront time (the time required for the current value to rise from 10% peak value to 90% peak value, or approximately to 80% peak value) is 8μs, and the half-peak width (the pulse duration, the time it takes for the peak value to drop to 50% peak value) is 20μs. This waveform can effectively simulate surge current impacts caused by indirect lightning strikes or the switching of large-capacity inductive loads on power or signal lines. The "1.2 / 50μs" voltage waveform simulates similar transient overvoltage events. In summary, the transient overvoltage and surge current phenomena caused by inductive devices during start-up and shutdown transitions constitute a complex process involving the rapid conversion and release of electromagnetic energy. Its high frequency (rapid rise), high amplitude (kV-level voltage, kA-level current), and high energy (although short in duration, extremely high instantaneous power) characteristics make effective suppression and protection against it a continuous technical challenge in the field of power electronics and electrical engineering. To overcome these challenges, this invention proposes a surge protection circuit scheme with multi-stage energy transfer, providing a new technological path to ensure the long-term operational safety and reliability of inductive devices. Summary of the Invention

[0005] The purpose of this invention is to provide a multi-stage energy transfer surge protection circuit.

[0006] The objective of this invention is achieved through the following technical solution: A multi-stage energy transfer surge protection circuit includes: a TVS diode network, a first-stage thyristor network, and a second-stage thyristor network arranged sequentially, wherein: The first-stage thyristor network is used to discharge surges exceeding the peak voltage and peak current corresponding to the first-stage protection. The second-stage thyristor network is used to discharge surges exceeding the peak voltage and peak current corresponding to the second-stage protection, and the peak voltage and peak current of the second-stage protection are both greater than those of the first-stage protection. The TVS tube network is used to discharge the remaining surge spike energy.

[0007] Preferably, the first-stage thyristor network includes voltage divider resistors R11 and R12, dead load R13, thyristor DIAC1, bidirectional thyristor VT1, and a high-frequency filter capacitor. R11 and R12 are connected in series between the L line and the N line, the filter capacitor is connected in parallel across R12, R13 is connected in series with the bidirectional thyristor VT1 between the L line and the N line, the control terminal of the bidirectional thyristor VT1 is connected to the anode of thyristor DIAC1, and the cathode of thyristor DIAC1 is connected between resistors R11 and R12.

[0008] Preferably, the first-stage thyristor network is configured to break down DIAC1 and turn on VT1 at 280Vac and a peak current of 100A.

[0009] Preferably, the second-stage thyristor network includes voltage divider resistors R21 and R22, dead load R23, thyristor DIAC2, bidirectional thyristor VT2, and a high-frequency filter capacitor. R21 and R22 are connected in series between the L line and the N line, the filter capacitor is connected in parallel across R22, R23 and bidirectional thyristor VT2 are connected in series between the L line and the N line, the control terminal of bidirectional thyristor VT2 is connected to the anode of thyristor DIAC2, and the cathode of thyristor DIAC2 is connected between resistors R21 and R22.

[0010] Preferably, the second-stage thyristor network is configured to break down DIAC2 and turn on VT2 at 300Vac and a peak current of 1kA.

[0011] Preferably, the TVS tube network includes: a varistor MOV1 and a TVS tube 1 connected in series between the L line and the N line; a varistor MOV2 and a TVS tube 2 connected in series between the L line and the ground line; and a varistor MOV3 and a TVS tube 3 connected in series between the N line and the ground line. The rated current capacity and maximum continuous operating voltage of the varistor MOV1, MOV2, and MOV3 are all greater than the peak voltage and peak current corresponding to the second level of protection.

[0012] Preferably, it also includes an auxiliary diode network, which is located in the feedback protection loop and includes a bootstrap diode D1, an auxiliary clamping diode D2, detection branch resistors R1, R2, R3 and a filter capacitor; Among them, D1 is used to provide bootstrap power to the control chip, D2 is used to clamp the Vaux terminal voltage of the control chip to prevent the control chip from being over-voltaged and broken down due to surge impact; R1 / R2 / R3 are used for voltage sampling and surge status detection; and the filter capacitor is used to provide a stable DC power supply.

[0013] Preferably, in the auxiliary diode network, the negative terminal of diode D1 is connected to the VCC interface of the control chip, the positive terminal of diode D1 is connected to the positive terminal of diode D2, the negative terminal of diode D1 is connected to the GND interface of the control chip in series with resistors R2 and R3, the VS interface of the control chip is connected between R2 and R3, resistor R1 is connected in parallel with diode D2, and two filter capacitors are connected in parallel between the VCC interface and the GND interface of the control chip.

[0014] The beneficial effects of this invention are as follows: This invention presents a multi-stage energy transfer surge protection circuit, consisting of a TVS diode network, a two-stage thyristor network, and an auxiliary diode network. The TVS network protects against surges from the power grid; the two-stage thyristor network provides clamping protection during peak voltage and current conditions; and an auxiliary diode added to the feedback protection loop provides overvoltage protection against surges by shunting current. This protection circuit solves the problem of inductive loads being subjected to power grid surges during start-up and shutdown. It features a simple structure, low cost, and high versatility. Attached Figure Description

[0015] Figure 1 The photo shows the bulging of electrolytic capacitors and the breakdown of common-mode inductors caused by surge energy impact.

[0016] Figure 2 This is a circuit diagram for surge protection in existing technology.

[0017] Figure 3 This is another surge protection circuit diagram from the existing technology.

[0018] Figure 4 This is a circuit diagram for the multi-stage energy transfer surge protection of the present invention.

[0019] Figure 5 This is a circuit diagram for surge protection against multi-stage energy transfer in Example 1.

[0020] Figure 6 This is a schematic diagram of surge impact and the multi-stage key timing of the present invention, where t0 corresponds to the first stage thyristor network in operation; t1 corresponds to the second stage thyristor network in operation; and t2 corresponds to the TVS tube network. Detailed Implementation

[0021] The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of them. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0022] The terminology used in the embodiments of this invention is for the purpose of describing specific embodiments only and is not intended to limit the invention. It should be noted that directional terms such as "upper," "lower," "left," and "right" described in the embodiments of this invention are used to describe the angles shown in the accompanying drawings and should not be construed as limiting the embodiments of this invention. Furthermore, in the context, it should be understood that when referring to an element being formed "on" or "below" another element, it can be formed not only directly on or below the other element, but also indirectly on or below it through intermediate elements. The terms "first," "second," etc., are used for descriptive purposes only and do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Those skilled in the art can understand the specific meaning of the above terms in this invention based on the specific circumstances.

[0023] The term "comprising" and its variations as used in this invention are open-ended, meaning "including but not limited to". The term "based on" means "at least partially based on". The term "one embodiment" means "at least one embodiment".

[0024] It should be noted that the concepts of "first" and "second" mentioned in this invention are only used to distinguish the corresponding contents and are not used to limit the order or interdependence.

[0025] It should be noted that the terms "a" and "a plurality of" used in this invention are illustrative rather than restrictive. Those skilled in the art should understand that, unless otherwise expressly indicated in the context, they should be understood as "one or more".

[0026] Example 1 like Figure 4-5 As shown, this multi-stage energy transfer surge protection circuit includes: a TVS diode network, a first-stage thyristor network, and a second-stage thyristor network arranged sequentially. The TVS diode network includes: a varistor MOV1 and a TVS diode 1 connected in series between the L and N lines; a varistor MOV2 and a TVS diode 2 connected in series between the L and ground lines; and a varistor MOV3 and a TVS diode 3 connected in series between the N and ground lines. Its function is to rapidly discharge most of the energy when the surge voltage exceeds the varistor threshold. When the rapid spike energy cannot be absorbed by the MOV in time, the TVS diodes achieve rapid and precise clamping. The first-stage thyristor network includes voltage divider resistors R11 and R12, dead load R13, thyristor DIAC1, bidirectional thyristor VT1, and a high-frequency filter capacitor. R11 and R12 are connected in series between the L line and the N line, and the filter capacitor is connected in parallel across R12. R13 is connected in series with the bidirectional thyristor VT1 between the L line and the N line. The control terminal of the bidirectional thyristor VT1 is connected to the anode of thyristor DIAC1, and the cathode of thyristor DIAC1 is connected between resistors R11 and R12. The first-stage thyristor network is configured to break down thyristor DIAC1 and turn on bidirectional thyristor VT1 at 280Vac and a peak current of 100A, thereby dissipating surge energy through the dead load R13. The second-stage thyristor network includes voltage divider resistors R21 and R22, dead load R23, thyristor DIAC2, bidirectional thyristor VT2, and a high-frequency filter capacitor. R21 and R22 are connected in series between the L and N lines, and the filter capacitor is connected in parallel across R22. R23 and bidirectional thyristor VT2 are connected in series between the L and N lines. The control terminal of bidirectional thyristor VT2 is connected to the anode of thyristor DIAC2, and the cathode of thyristor DIAC2 is connected between resistors R21 and R22. The second-stage thyristor network is configured to break down thyristor DIAC2 and turn on bidirectional thyristor VT2 at 300Vac and peak current of 1kA, thereby dissipating surge energy through dead load R23. The surge protection circuit also includes an auxiliary diode network located in the feedback protection loop. This network includes a bootstrap diode D1, an auxiliary clamping diode D2, detection branch resistors R1, R2, and R3, and a filter capacitor. The cathode of diode D1 is connected to the VCC interface of the control chip, and the anode of diode D1 is connected to the anode of diode D2. The cathode of diode D1 is connected in series with resistors R2 and R3 and then to the GND interface of the control chip. The VS interface of the control chip is connected between R2 and R3. Resistor R1 is connected in parallel with diode D2. Two filter capacitors are connected in parallel between the VCC and GND interfaces of the control chip. Their function is to provide stable voltage clamping when the diodes are conducting, preventing the control chip from malfunctioning and forcing abnormal output protection when the input is subjected to surge energy. This also avoids overvoltage damage to the control chip's power supply.

[0027] For this circuit, considering a time interval of 20μs, the two-stage thyristor network is first configured. R11 = R12, R21 = R22.

[0028] For the front-end thyristor network, the surge voltage overvoltage threshold is set to 280Vac and the surge current overcurrent threshold is set to 100A through the voltage divider parameter design of R11 and R12. When the surge energy exceeds the voltage and current thresholds, i.e. Figure 6 At time t0 in the time series, Figure 5 When DIAC1 is broken down, the bidirectional thyristor VT1 turns on and absorbs energy through the dead load of R13 (e.g., 2.8Ω) to avoid affecting the subsequent circuits, thus achieving the first stage of surge protection. Similarly, for the subsequent thyristor network, the surge voltage overvoltage threshold is set to 300Vac and the surge current overcurrent threshold is set to 1kA through the voltage divider parameter design of R21 and R22. When the surge energy exceeds the voltage and current thresholds, i.e. Figure 6 At time t1 in the time series, Figure 5 When DIAC2 is broken down, the bidirectional thyristor VT2 turns on and absorbs energy through the dead load of R23 (e.g., 0.3Ω), thus achieving the second stage of surge protection. The traditional surge suppression scheme using varistors and TVS diodes is improved by adding independent and complete varistor + TVS diode branches between the L and N lines, between the L and ground lines, and between the N and ground lines. This complete TVS diode protection network ensures that both differential-mode and common-mode surges have corresponding, low-impedance paths to dissipate their energy, thereby enhancing the synergistic protection against differential-mode and common-mode surges and extending the lifespan of all protective devices. The TVS network branches between the L and N lines are used to suppress differential-mode surge energy, while the networks between the L and ground lines, and between the N and ground lines, are used to suppress common-mode surge energy. In fact, a lack of or inadequate absorption of common-mode surge energy will force it to attempt to find a discharge path through internal circuitry (transformer parasitic capacitance, Y capacitors, etc.), easily leading to insulation breakdown and ultimately electrical equipment failure.

[0029] The third-level surge protection is constructed by using a varistor of approximately 400V / 4kA and a low-voltage TVS diode of approximately 40V. Figure 6At time t2 in the timing sequence, when the surge energy exceeds the voltage and current thresholds (400V / 4kA), the impedance of the varistor MOV begins to drop sharply and conducts first, dissipating most of the surge energy. However, when the extremely fast peak energy cannot be absorbed by the MOV in time, the TVS diode with a nanosecond-level response speed precisely "harvests" the "leaked" energy. The breakdown voltage of the TVS is usually much lower than the varistor voltage of the MOV. However, before the MOV activates, because the MOV is in a high-resistance state, the voltage across the TVS is insufficient to break it down.

[0030] Additionally, the power supply for the flyback converter's closed-loop control chip is typically drawn from the auxiliary winding on the primary side of the transformer. When the AC input is subjected to surge energy, the control chip's power supply inevitably surges in with the energy, potentially causing chip breakdown. The auxiliary diode network, added to the existing bootstrap power supply, serves both detection and protection functions, assisting the control chip's Vs pin in more accurate detection. When power-on, Vaux rises slowly. At this time, the current to the Vs detection branch (auxiliary diode network branch) is small, and D2 is not conducting. R1, R2, and R3 form the detection output voltage. When the voltage reaches a certain value or reaches steady state, D2 conducts, and the current in the VS detection branch becomes (Vaux - 0.3V) / (R107 + R108). At this point, the voltage across VS is higher than without D2. Furthermore, VS also provides overvoltage protection. During startup (when VS voltage is high at power-on) or when a light load suddenly increases to a heavy load, the duty cycle suddenly increases, potentially triggering overvoltage protection.

[0031] The above embodiments are preferred embodiments of the present invention, but the embodiments of the present invention are not limited to the above embodiments. Any changes, modifications, substitutions, combinations, or simplifications made without departing from the spirit and principle of the present invention shall be considered equivalent substitutions and shall be included within the protection scope of the present invention.

Claims

1. A multi-stage energy transfer surge protection circuit, characterized in that, include: The TVS diode network, the first-stage thyristor network, and the second-stage thyristor network are configured sequentially, wherein: The first-stage thyristor network is used to discharge surges exceeding the peak voltage and peak current corresponding to the first-stage protection. The second-stage thyristor network is used to discharge surges exceeding the peak voltage and peak current corresponding to the second-stage protection, and the peak voltage and peak current of the second-stage protection are both greater than those of the first-stage protection. The TVS tube network is used to discharge the remaining surge spike energy.

2. The surge protection circuit according to claim 1, characterized in that, The first-stage thyristor network includes voltage divider resistors R11 and R12, dead load R13, thyristor DIAC1, bidirectional thyristor VT1, and a high-frequency filter capacitor. R11 and R12 are connected in series between the L line and the N line, the filter capacitor is connected in parallel across R12, R13 is connected in series with the bidirectional thyristor VT1 between the L line and the N line, the control terminal of the bidirectional thyristor VT1 is connected to the anode of thyristor DIAC1, and the cathode of thyristor DIAC1 is connected between resistors R11 and R12.

3. The surge protection circuit according to claim 2, characterized in that, The first-stage thyristor network is configured to break down DIAC1 and turn on VT1 at 280Vac and a peak current of 100A.

4. The surge protection circuit according to claim 2, characterized in that, The second-stage thyristor network includes voltage divider resistors R21 and R22, dead load R23, thyristor DIAC2, bidirectional thyristor VT2, and a high-frequency filter capacitor. R21 and R22 are connected in series between the L line and the N line, and the filter capacitor is connected in parallel across R22. R23 and bidirectional thyristor VT2 are connected in series between the L line and the N line. The control terminal of bidirectional thyristor VT2 is connected to the anode of thyristor DIAC2, and the cathode of thyristor DIAC2 is connected between resistors R21 and R22.

5. The surge protection circuit according to claim 4, characterized in that, The second-stage thyristor network is configured to break down DIAC2 and turn on VT2 at 300Vac and a peak current of 1kA.

6. The surge protection circuit according to claim 4, characterized in that, The TVS tube network includes: a varistor MOV1 and a TVS tube 1 connected in series between the L line and the N line; a varistor MOV2 and a TVS tube 2 connected in series between the L line and the ground line; and a varistor MOV3 and a TVS tube 3 connected in series between the N line and the ground line. The rated current capacity and maximum continuous operating voltage of the varistor MOV1, MOV2, and MOV3 are all greater than the peak voltage and peak current corresponding to the second level of protection.

7. The surge protection circuit according to any one of claims 1-6, characterized in that, It also includes an auxiliary diode network, which is located in the feedback protection loop and includes a bootstrap diode D1, an auxiliary clamping diode D2, detection branch resistors R1, R2, R3 and a filter capacitor; Among them, D1 is used to provide bootstrap power to the control chip, D2 is used to clamp the Vaux terminal voltage of the control chip to prevent the control chip from being over-voltaged and broken down due to surge impact; R1 / R2 / R3 are used for voltage sampling and surge status detection; and the filter capacitor is used to provide a stable DC power supply.

8. The surge protection circuit according to claim 7, characterized in that, In the auxiliary diode network, the negative terminal of diode D1 is connected to the VCC interface of the control chip, the positive terminal of diode D1 is connected to the positive terminal of diode D2, the negative terminal of diode D1 is connected in series with resistors R2 and R3 and then connected to the GND interface of the control chip, the VS interface of the control chip is connected between R2 and R3, resistor R1 is connected in parallel with diode D2, and two filter capacitors are connected in parallel between the VCC interface and the GND interface of the control chip.

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