Display panel and display device

Abstract

The invention relates to a display panel and a display device.In the display panel, a first light-emitting unit and a second light-emitting unit share one second electrode, a first sub-electrode and a second sub-electrode are both connected with an array substrate, and the first light-emitting unit and the second light-emitting unit are connected with the same array substrate. The arrangement of the array substrate is reduced, and the overall thickness of the display panel is reduced. In addition, the orthographic projection of the first light-emitting unit and the orthographic projection of the second light-emitting unit in the first direction are overlapped, so that the integration level of the display panel is also improved. Besides, the same array substrate can respectively control the first light-emitting unit and the second light-emitting unit, the first light-emitting unit and the second light-emitting unit can respectively display independent pictures during double-sided display, the mirror image problem is avoided, and the display picture of double-sided display is optimized.

Description

Technical Field

[0001] This application relates to the field of display technology, and in particular to a display panel and display device. Background Technology

[0002] Currently, the demand for display products in various display formats is increasing. Among them, double-sided displays, with their ability to provide richer and more interactive information display, are attracting more attention.

[0003] Existing double-sided displays use a single transmissive light-emitting unit, resulting in consistent light emission from both sides of the display panel and thus producing a mirror-like image. Currently, the industry typically addresses this issue by using two display panels bonded back-to-back; however, this leads to thicker display devices and excessively high manufacturing costs. Summary of the Invention

[0004] Therefore, it is necessary to provide a display panel and display device that do not produce mirrored images and are thinner, in order to address the problems of double-sided displays.

[0005] This application provides a display panel, including:

[0006] Array substrate;

[0007] The first electrode is located on one side of the array substrate and includes a first sub-electrode and a second sub-electrode arranged sequentially along a first direction, the first direction being perpendicular to the array substrate.

[0008] A light-emitting unit is located between the first sub-electrode and the second sub-electrode, and the light-emitting unit includes a first light-emitting unit and a second light-emitting unit arranged sequentially along the first direction;

[0009] The second electrode is located between the first light-emitting unit and the second light-emitting unit;

[0010] Both the first sub-electrode and the second sub-electrode are connected to the array substrate.

[0011] In one embodiment, the first electrode further includes:

[0012] An auxiliary electrode is located on the same layer as the first sub-electrode and is spaced apart from the first sub-electrode. The second sub-electrode is connected to the array substrate through the auxiliary electrode.

[0013] In one embodiment, the display panel further includes:

[0014] A connection structure is located on the side of the first electrode away from the array substrate, and the connection structure connects the second sub-electrode and the auxiliary electrode.

[0015] In one embodiment, the orthographic projection of the connection structure on the array substrate does not overlap with the orthographic projection of the light emission port of the second light-emitting unit on the array substrate.

[0016] In one embodiment, the display panel further includes:

[0017] An encapsulation layer is located on the side of the second sub-electrode away from the array substrate;

[0018] The encapsulation layer includes a first through-hole and a second through-hole, the first through-hole exposing the auxiliary electrode and the second through-hole exposing the second sub-electrode;

[0019] Optionally, the connection structure includes:

[0020] A first connecting portion is located inside the first through hole, and the first connecting portion is in contact with the auxiliary electrode;

[0021] The second connecting part is located inside the second through hole, and the second connecting part is in contact with the second sub-electrode;

[0022] The third connection portion is located on the side of the encapsulation layer opposite to the array substrate, and the first connection portion and the second connection portion are connected through the third connection portion;

[0023] Optionally, the display panel further includes:

[0024] The encapsulation module is located on the side of the encapsulation layer opposite to the array substrate and covers the encapsulation layer and the connection structure.

[0025] In one embodiment, the display panel further includes:

[0026] A pixel definition layer, located on the side of the first sub-electrode facing away from the array substrate, includes a first opening and a second opening spaced apart.

[0027] The first opening exposes the first sub-electrode, and the second opening exposes the auxiliary electrode;

[0028] Optionally, the display panel further includes:

[0029] A planarization layer covers the array substrate and the first sub-electrode. The pixel definition layer covers the first sub-electrode, the auxiliary electrode, and the planarization layer. The planarization layer includes a third via, through which the first electrode is connected to the array substrate.

[0030] In one embodiment, the second electrode at least covers the first light-emitting unit, and the orthographic projection of the second electrode on the array substrate does not overlap with the orthographic projection of the auxiliary electrode on the array substrate;

[0031] Optionally, the second electrode of each of the light-emitting units is an integral structure, and the second electrode has a fourth through hole that exposes the auxiliary electrode.

[0032] In one embodiment, the array substrate includes:

[0033] The driving circuit drives the first light-emitting unit and the second light-emitting unit in a time-division manner.

[0034] In one embodiment, the array substrate further includes:

[0035] A first light-emitting region is provided at an interval from the driving circuit;

[0036] The orthographic projection of the first sub-electrode onto the array substrate at least partially overlaps with the first light-emitting region;

[0037] Optionally, the orthographic projection of the first sub-electrode on the array substrate overlaps with the first light-emitting region.

[0038] On the other hand, a display device is also provided, including a display panel as described in any of the above.

[0039] In the aforementioned display panel and display device, a first sub-electrode, a first light-emitting unit, a second electrode, a second light-emitting unit, and a second sub-electrode are sequentially stacked in a first direction. The first light-emitting unit and the second light-emitting unit share a second electrode, and both the first sub-electrode and the second sub-electrode are connected to an array substrate. Since the first light-emitting unit and the second light-emitting unit are connected to the same array substrate, compared to existing double-sided display structures, the number of array substrates is reduced, thus thinning the overall thickness of the display panel. Furthermore, because the orthographic projections of the first light-emitting unit and the second light-emitting unit overlap in the first direction, the integration density of the display panel is also improved.

[0040] In some embodiments, both the first sub-electrode and the second sub-electrode are connected to the array substrate. The same array substrate can control the first light-emitting unit and the second light-emitting unit respectively. In the case of double-sided display, the first light-emitting unit and the second light-emitting unit can be displayed as separate images, without mirroring problems, thus optimizing the display screen of double-sided display. Attached Figure Description

[0041] To more clearly illustrate the technical solutions in the embodiments of this application or the conventional technology, the drawings used in the description of the embodiments or the conventional technology will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0042] Figure 1 This is a partial cross-sectional structural diagram of a display panel provided in an embodiment of this application;

[0043] Figure 2 A schematic diagram of the circuit structure of a driving circuit provided in an embodiment of this application;

[0044] Figure 3 A timing diagram illustrating a time-sharing drive provided in an embodiment of this application;

[0045] Figure 4 This is a timing diagram illustrating the emission of another light-emitting unit provided in an embodiment of this application.

[0046] Explanation of reference numerals in the attached figures: 01-Array substrate; 021-First sub-electrode; 022-Second sub-electrode; 023-Auxiliary electrode; 031-First light-emitting unit; 032-Second light-emitting unit; 04-Second electrode; 05-Connection structure; 06-Encapsulation layer; 07-Encapsulation module; 08-Pixel definition layer; 09-Planarization layer. Detailed Implementation

[0047] To facilitate understanding of the present invention, a more complete description will be given below with reference to the accompanying drawings. Preferred embodiments of the invention are shown in the drawings. However, the invention can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a thorough and complete understanding of the disclosure of the invention.

[0048] It should be noted that when a component is said to be "fixed to" another component, it can be directly attached to the other component or there may be an intervening component. When a component is said to be "connected to" another component, it can be directly connected to the other component or there may be an intervening component. The terms "vertical," "horizontal," "left," "right," and similar expressions used in this document are for illustrative purposes only.

[0049] In this document, spatial terms such as “upper” and “lower” are defined with reference to the accompanying drawings. Therefore, it will be understood that “upper” and “lower” are used interchangeably. It will be understood that when a layer is referred to as being “on” another layer, it can be formed directly on that other layer, or there may be intermediate layers. Therefore, it will be understood that when a layer is referred to as being “directly” on another layer, no intermediate layer is inserted in between.

[0050] In the accompanying drawings, the dimensions of layers and regions may be exaggerated for clarity. It is understood that when a layer or element is referred to as "on" another layer or substrate, the layer or element may be directly on said other layer or substrate, or there may be intermediate layers. Furthermore, it is understood that when a layer is referred to as "between" two layers, the layer may be the only layer between said two layers, or there may be one or more intermediate layers. Additionally, the same reference numerals always denote the same elements.

[0051] In the following text, although terms such as “first” and “second” may be used to describe various components, these components are not necessarily limited to the terms above. The terms above are used only to distinguish one component from another. It will also be understood that expressions used in the singular form include plural expressions unless the singular form has a distinct meaning in the context. Furthermore, in the embodiments below, it will also be understood that the terms “comprising” and / or “having” as used herein indicate the presence of the stated feature or component, but do not exclude the presence or addition of one or more other features or components.

[0052] In the following embodiments, when a layer, region, or element is “connected,” it can be interpreted as the layer, region, or element being connected not only directly but also through other constituent elements placed therebetween. For example, when a layer, region, element, etc., is described as being connected or electrically connected, the layer, region, element, etc., can not only be directly connected or directly electrically connected, but can also be connected or electrically connected through another layer, region, element, etc., placed therebetween.

[0053] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used herein in the specification of the application is for the purpose of describing particular embodiments only and is not intended to limit the scope of the application. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0054] It should also be understood that the terms “including / comprise” or “have” specify the presence of the stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not preclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof.

[0055] Please refer to Figure 1 , Figure 1 This application provides a partial cross-sectional structural diagram of a display panel according to an embodiment of the present application; the display panel includes:

[0056] Array substrate 01.

[0057] The first electrode is located on one side of the array substrate 01 and includes a first sub-electrode 021 and a second sub-electrode 022 arranged sequentially along the first direction X, which is perpendicular to the array substrate 01.

[0058] The light-emitting unit is located between the first sub-electrode 021 and the second sub-electrode 022. The light-emitting unit includes a first light-emitting unit 031 and a second light-emitting unit 032 arranged sequentially along the first direction X.

[0059] The second electrode 04 is located between the first light-emitting unit 031 and the second light-emitting unit 032.

[0060] Both the first sub-electrode 021 and the second sub-electrode 022 are connected to the array substrate 01.

[0061] Specifically, the array substrate 01 can be a thin-film transistor array. The material of the array substrate 01 can be a transparent CPI material. The first electrode can be either an anode or a cathode, and the second electrode 04 can also be either an anode or a cathode; the first electrode and the second electrode 04 are different. In this embodiment, the example of the first electrode being the anode and the second electrode 04 being the cathode will be used for illustration.

[0062] The first electrode includes a first sub-electrode 021 and a second sub-electrode 022, wherein the first sub-electrode 021 can serve as the anode of the first light-emitting unit 031, and the second sub-electrode 022 can serve as the anode of the second light-emitting unit 032. Both the first sub-electrode 021 and the second sub-electrode 022 are connected to the array substrate 01, that is, one array substrate 01 can control two different light-emitting units stacked in the first direction X.

[0063] The first light-emitting unit 031 and the second light-emitting unit 032 also include a second electrode 04. The second electrode 04 can be used as the cathode of the first light-emitting unit 031 or the cathode of the second light-emitting unit 032. In other words, the second electrode 04 is a shared cathode of the first light-emitting unit 031 and the second light-emitting unit 032.

[0064] like Figure 1 As shown, the light-emitting sides of the first light-emitting unit 031 and the second light-emitting unit 032 are opposite. Therefore, the second light-emitting unit 032 can be formed with an inverted structure. For example, when fabricating the first light-emitting unit 031, a first hole transport layer, a first light-emitting layer, and a first electron transport layer are formed sequentially on the upper side of the first sub-electrode 021; while when forming the second light-emitting unit 032, a second electron transport layer, a second light-emitting layer, and a second hole transport layer are formed sequentially on the side of the second electrode 04 opposite to the first electron transport unit. This makes the light-emitting sides of the first light-emitting unit 031 and the second light-emitting unit 032 opposite. Both the first light-emitting unit 031 and the second light-emitting unit 032 can be AMOLEDs, and conventional AMOLED processes can be used during fabrication. For example, the light-emitting unit can be fabricated using a vapor deposition process, where the transport layer and injection layer are fabricated using a common metal mask (CMM), and the light-emitting layer and compensation layer are fabricated using a fine metal mask (FMM), which helps to improve display quality.

[0065] To achieve double-sided display, the material of the first electrode can be a transparent or semi-transparent conductive material, such as a thin layer of Ag material or ITO material. Setting the first sub-electrode 021 to a transparent or semi-transparent conductive material ensures that the emitted light from the first light-emitting unit 031 is emitted from the bottom array substrate 01 side. Setting the second sub-electrode 022 to a transparent or semi-transparent conductive material ensures that the emitted light from the second light-emitting unit 032 is emitted from the top. To ensure that the first light-emitting unit 031 and the second light-emitting unit 032 do not interfere with each other's light emission effect, the material of the second electrode 04 can be an opaque conductive material or a totally reflective conductive material, such as an Ag electrode.

[0066] It should be noted that the first electrode can be fabricated using patterning processes, such as patterning of CPM material or laser ablation. This fabrication method is well known to those skilled in the art and is not the focus of this application; therefore, its specific method will not be described in detail here.

[0067] In this embodiment, the first sub-electrode 021, the first light-emitting unit 031, the second electrode 04, the second light-emitting unit 032, and the second sub-electrode 022 are sequentially stacked in the first direction X. The first light-emitting unit 031 and the second light-emitting unit 032 share a second electrode 04, and both the first sub-electrode 021 and the second sub-electrode 022 are connected to the array substrate 01. Since the first light-emitting unit 031 and the second light-emitting unit 032 are connected to the same array substrate 01, compared to the existing double-sided display structure, the number of array substrates 01 is reduced, thus thinning the overall thickness of the display panel. Furthermore, since the orthographic projections of the first light-emitting unit 031 and the second light-emitting unit 032 overlap in the first direction X, the integration of the display panel is also improved.

[0068] In another embodiment of this application, such as Figure 1 As shown, the array substrate 01 includes:

[0069] The driving circuit is the same circuit that drives the first light-emitting unit 031 and the second light-emitting unit 032 in a time-division manner.

[0070] Specifically, the array substrate 01 may be provided with multiple driving circuits. The driving circuits are respectively connected to the first sub-electrode 021 of the first light-emitting unit 031 and the second sub-electrode 022 of the second light-emitting unit 032, and then drive the first light-emitting unit 031 and the second light-emitting unit 032 in a time-division manner.

[0071] In this embodiment, a single driving circuit drives the first light-emitting unit 031 and the second light-emitting unit 032 in a time-division manner, reducing the number of driving circuits and saving the area of ​​the array substrate 01, thus freeing up space for the light-emitting port on one side of the array substrate 01. Furthermore, using a single driving circuit to drive the first light-emitting unit 031 and the second light-emitting unit 032 also reduces the number of array substrates 01, thereby reducing the thickness of the display panel.

[0072] It should be noted that the first light-emitting unit 031 and the second light-emitting unit 032 can also be driven by their respective driving circuits, and no specific limitation is made in this regard.

[0073] In another embodiment of this application, such as Figure 1 As shown, the array substrate 01 also includes:

[0074] The first light-emitting area 011 is spaced apart from the driving circuit.

[0075] The orthographic projection of the first sub-electrode 021 on the array substrate 01 at least partially overlaps with the first light-emitting region 011.

[0076] Optionally, the orthographic projection of the first sub-electrode 021 onto the array substrate 01 overlaps with the first light-emitting region 011.

[0077] Specifically, the first light-emitting region 011 is a transparent region. This display panel is a double-sided display; the light-emitting side of the first light-emitting unit 031 is the side of the first light-emitting unit 031 furthest from the second electrode 04. In other words, the array substrate 01 needs to maintain transparency. Therefore, the metal wiring, gate, and capacitor plate in the array substrate 01 need to be designed to improve light transmittance. The first light-emitting region 011 is provided on the array substrate 01, and this first light-emitting region 011 is spaced apart from the driving electrode to ensure that the first light-emitting unit 031 in each light-emitting unit corresponds to the first light-emitting region 011. The orthographic projection of the first sub-electrode 021 onto the array substrate 01 at least partially overlaps with the first light-emitting region 011, ensuring that the light emitted by the first light-emitting unit 031 is emitted from the first light-emitting region 011.

[0078] When the orthogonal projection of the first sub-electrode 021 on the array substrate 01 overlaps with the first light-emitting region 011, the light-emitting effect of the first light-emitting unit 031 can be improved.

[0079] In this embodiment, the first light-emitting region 011 is set as a transparent region, serving as the light-emitting port of the first light-emitting unit 031, thus ensuring the light-emitting effect of the first light-emitting unit 031. Furthermore, since a driving circuit drives the first light-emitting unit 031 and the second light-emitting unit 032, space is left for designing the first light-emitting region 011 on the array substrate 01, ensuring the effect of double-sided display.

[0080] In another embodiment of this application, reference is made to Figure 1 The first electrode also includes:

[0081] The auxiliary electrode 023 is located on the same layer as the first sub-electrode 021 and is spaced apart from the first sub-electrode 021. The second sub-electrode 022 is connected to the array substrate 01 through the auxiliary electrode 023.

[0082] Specifically, the material of the auxiliary electrode 023 may include, but is not limited to, transparent or semi-transparent conductive materials, opaque conductive materials, etc. The auxiliary electrode 023 and the first sub-electrode 021 are located in the same layer, and the first sub-electrode 021 and the auxiliary electrode 023 can be fabricated simultaneously during fabrication.

[0083] In this embodiment, the second sub-electrode 022 is connected to the auxiliary electrode 023, and the auxiliary electrode 023 is connected to the array substrate 01. Without affecting the pixels, the metal wiring connecting the second sub-electrode 022 can be reduced, the integration of the display panel can be improved, and the cost can be reduced.

[0084] In another embodiment of this application, reference is made to Figure 1 The display panel also includes:

[0085] The connection structure 05 is located on the side of the first electrode away from the array substrate 01, and the connection structure 05 connects the second sub-electrode 022 and the auxiliary electrode 023.

[0086] Specifically, the material of the connection structure 05 can be metal. The connection structure 05 connects the second sub-electrode 022 and the auxiliary electrode 023. Compared with using metal wiring to connect the second sub-electrode 022 and the auxiliary electrode 023, the connection structure 05 directly connects the auxiliary electrode 023 and the second sub-electrode 022 on the upper side, which saves the area of ​​metal wiring and shortens the signal path.

[0087] It should be noted that the connection structure 05 can be fabricated using physical vapor deposition (PVD) and the auxiliary electrode 023 can be connected to the second sub-electrode 022 by etching patterning.

[0088] In this embodiment, the connection structure 05 is set up, which improves the integration of the display panel, shortens the signal path due to the shorter connection distance, and also optimizes the display screen of the double-sided display.

[0089] In another embodiment of this application, the orthographic projection of the connection structure 05 on the array substrate 01 does not overlap with the orthographic projection of the light emission port of the second light-emitting unit 032 on the array substrate 01.

[0090] Specifically, the light-emitting side of the second light-emitting unit 032 is the upper side away from the array substrate 01. In order to ensure the light-emitting effect of the second light-emitting unit 032, the connecting structure 05 cannot block the second light-emitting unit 032 when connecting the auxiliary electrode 023 and the second sub-electrode 022. Therefore, the orthographic projection of the connecting structure 05 on the array substrate 01 and the orthographic projection of the light-emitting port of the second light-emitting unit 032 on the array substrate 01 cannot overlap.

[0091] In this embodiment, the orthographic projection of the connection structure 05 on the array substrate 01 does not overlap with the light emission port of the second light-emitting unit 032, which can ensure the display effect of the display panel.

[0092] In another embodiment of this application, reference is made to Figure 1 The display panel also includes:

[0093] The encapsulation layer 06 is located on the side of the second sub-electrode 022 away from the array substrate 01.

[0094] The encapsulation layer 06 includes a first through-hole and a second through-hole (not shown in the figure). The first through-hole exposes the auxiliary electrode 023, and the second through-hole exposes the second sub-electrode 022.

[0095] Specifically, the encapsulation layer 06 is a CVD encapsulation layer 06. The encapsulation layer 06 includes a first through-hole and a second through-hole, and the second sub-electrode 022 is connected to the auxiliary electrode 023 through the second through-hole and the first through-hole.

[0096] It should be noted that the orthographic projection of the second via on the array substrate 01 does not overlap with the light emission port of the second light-emitting unit 032, in order to ensure the light-emitting effect of the second light-emitting unit 032. The second via can be fabricated using processes such as etching.

[0097] Optionally, the connection structure 05 includes:

[0098] The first connecting part is located inside the first through hole and is in contact with the auxiliary electrode 023.

[0099] The second connecting part is located inside the second through hole and is in contact with the second sub-electrode 022.

[0100] The third connection part is located on the side of the encapsulation layer 06 away from the array substrate 01, and the first connection part and the second connection part are connected through the third connection part.

[0101] The first connecting part, the second connecting part, and the third connecting part (not shown in the figure) are an integral structure, and are only explained here for clarity. The first connecting part is in contact with the auxiliary electrode 023, the second connecting part is in contact with the second sub-electrode 022, and the third connecting part connects the first connecting part and the second connecting part to form a connecting structure 05, which leads the signal on the auxiliary electrode 023 to the second sub-electrode 022 to ensure the light emission of the second light-emitting unit 032.

[0102] It should be noted that by setting the first connecting part in the first through hole and the second connecting part in the second through hole, the connection distance between the auxiliary electrode 023 and the second sub-electrode 022 can be shortened, the signal transmission distance can be shortened, and the display effect of the double-sided display can be optimized.

[0103] Optionally, refer to Figure 1 The display panel also includes:

[0104] The packaging module 07 is located on the side of the packaging layer 06 away from the array substrate 01, and covers the packaging layer 06 and the connection structure 05.

[0105] Specifically, an encapsulation module 07 is also provided on the upper side of the encapsulation layer 06, including a thin-film encapsulation layer, a touch screen, etc. The encapsulation module 07 can protect the display panel and improve the heat dissipation performance of the display panel.

[0106] It should be noted that the packaging module 07 can be manufactured using conventional methods. The packaging module 07 is well known to those skilled in the art and is not the focus of this application. Therefore, its specific structure and principle will not be described in detail here.

[0107] In this embodiment, the encapsulation layer 06 and the encapsulation module 07 can further improve the integration of the display panel, protect the display panel, and provide the reliability of the display panel.

[0108] In another embodiment of this application, reference is made to Figure 1 The display panel also includes:

[0109] The pixel definition layer 08 is located on the side of the first sub-electrode 021 facing away from the array substrate 01, and includes a first opening and a second opening (not shown in the figure) arranged at intervals.

[0110] The first opening exposes the first sub-electrode 021, and the second opening exposes the auxiliary electrode 023.

[0111] Specifically, pixel definition layer 08 is used to isolate adjacent light-emitting units to prevent them from interfering with each other and thus affecting the light-emitting effect.

[0112] In the pixel definition layer 08, a first opening exposes a first sub-electrode 021. Within the first opening, a first light-emitting unit 031, a second electrode 04, a second light-emitting unit 032, and a second sub-electrode 022 are sequentially disposed on the first sub-electrode 021. A second opening exposes an auxiliary electrode 023 to facilitate connection between the second sub-electrode 022 and the auxiliary electrode 023.

[0113] It should be noted that the second opening is small enough compared to the first opening to have a negligible impact on the display panel, but it greatly improves the integration of the display panel.

[0114] Optionally, refer to Figure 1 The display panel also includes:

[0115] A planarization layer 09 covers the array substrate 01 and the first sub-electrode 021. A pixel definition layer 08 covers the first sub-electrode 021, the auxiliary electrode 023, and the planarization layer 09. The planarization layer 09 includes a third via (not shown in the figure), through which the first electrode is connected to the array substrate 01.

[0116] The planarization layer 09 can be made of transparent CPR material, which can ensure that the first light-emitting unit 031 can emit light from the bottom.

[0117] The planarization layer 09 is provided with a third through hole, and the first sub-electrode 021 and the auxiliary electrode 023 are both filled with the third through hole, thereby connecting with the array substrate 01.

[0118] In this embodiment, a pixel definition layer 08 defines a first opening and a second opening spaced apart, which can prevent short circuits between the first sub-electrode 021 and the auxiliary electrode 023. Furthermore, it can limit the size of the light emission ports of the first light-emitting unit 031 and the second light-emitting unit 032, and also ensure isolation between adjacent light-emitting units to prevent crosstalk. The planarization layer 09 can improve the flatness of the display panel surface, increase the yield of subsequent processes, and also protect the array substrate 01 from contamination, ensuring the reliability of the display panel.

[0119] In another embodiment of this application, the second electrode 04 at least covers the first light-emitting unit 031, and the orthographic projection of the second electrode on the array substrate 01 does not overlap with the orthographic projection of the auxiliary electrode 023 on the array substrate 01.

[0120] Specifically, the second electrode 04 is located on the side of the first light-emitting unit 031 facing away from the array substrate 01, and each light-emitting unit is provided with a shared second electrode 04. The second electrode 04 at least covers the first light-emitting unit 031, and may also extend to both sides to the edge of the first opening and cover part of the pixel definition layer 08. It should be noted that the various second electrodes 04 are arranged at intervals, that is, the shared cathode of each light-emitting unit is set separately.

[0121] Optionally, the second electrode 04 of each light-emitting unit is an integral structure, and the second electrode 04 has a fourth through hole, which exposes the auxiliary electrode 023.

[0122] Alternatively, the second electrode 04 of each light-emitting unit can also be a single integrated structure. That is, the second electrode 04 only has a fourth through hole on the upper side of the auxiliary electrode 023, exposing the auxiliary electrode 023 so that the auxiliary electrode 023 can be connected to the second sub-electrode 022 on the upper side. In this case, the second electrode 04 on the display panel is a single integrated structure, and the signals received by the second electrode 04 of each light-emitting unit are the same.

[0123] It should be noted that, as mentioned above, the second electrode 04 is a patterned second electrode 04, which can be fabricated using a patterning process. For example, the patterned second electrode 04 can be achieved using CPM material patterning or laser ablation. When the second electrode 04 is set separately, an electrode layer can be formed first, and then the electrode layer except for the upper side of the first light-emitting unit 031 can be removed, leaving the remaining electrode layer as the second electrode 04. When the second electrode 04 is an integral structure, an electrode layer can be formed first, and then the electrode layer above the auxiliary electrode 023 can be removed, leaving the remaining electrode layer as the second electrode 04.

[0124] In this embodiment, the second electrode 04 can be configured as an independent structure, allowing for individual control of the power supply to the second electrode 04 of each light-emitting unit, thus facilitating the maintenance of the display panel. Alternatively, the second electrode 04 can be integrated into a single unit. Since the second electrode 04 is a shared electrode, its potential is constantly supplied, powering both the first sub-electrode 021 and the second sub-electrode 022. This allows for distributed driving of the first light-emitting unit 031 and the second light-emitting unit 032 within a single light-emitting unit.

[0125] This application also provides a circuit structure for a driving circuit and a driving method; see reference. Figure 2 , Figure 2 A schematic diagram of the circuit structure of a driving circuit provided in an embodiment of this application; see reference. Figure 3 , Figure 3 This is a timing diagram illustrating a time-sharing drive provided in an embodiment of this application. Details are as follows:

[0126] The driving circuit can be, for example, Figure 2 The 9T1C circuit shown includes a first transistor M1, a second transistor M2, a third transistor M3, a fourth transistor M4, a fifth transistor M5, a sixth transistor M6, a seventh transistor M7, an eighth transistor M8, a ninth transistor M9, and a capacitor C1. All these transistors can be P-type transistors. The third transistor M3 and the fourth transistor M4 can be dual-gate transistors to reduce leakage current. The driving circuit is not specifically limited and can use other time-division multiplexing driving circuit structures. The driving timing can be controlled.

[0127] like Figure 2 As shown, the second end of the first light-emitting unit OLED1 and the second light-emitting unit OLED2 can both be electrically connected to the second power supply terminal VSS of the driving circuit. The first power supply terminal VDD transmits the first power signal, and the second power supply terminal VSS transmits the second power signal. The first power signal and the second power signal have different high and low levels. The first power signal can be high level and the second power signal can be low level, without any specific limitation.

[0128] The first transistor M1 is a driving transistor, including a gate G, a source S, and a drain D.

[0129] The first terminal of the second transistor M2 is used to write data, the second terminal of the second transistor M2 is connected to the source S of the first transistor M1, and the control terminal of the second transistor M2 is used to input the second scan signal S2.

[0130] The control terminal of the third transistor M3 is connected to the control terminal of the second transistor M2. The first terminal of the third transistor M3 is connected to the gate G of the first transistor M1 and the first terminal of the fourth transistor M4. The second terminal of the third transistor M3 is connected to the first terminal of the sixth transistor M6 and the first terminal of the ninth transistor M9.

[0131] The control terminal of the fourth transistor M4 is used to input the first scan signal S1. The second terminal of the fourth transistor M4 is connected to the first terminal of the seventh transistor M7 and the input reset signal Vref. The first terminal of the fourth transistor M4 is connected to the gate G of the first transistor M1 and the first terminal of the capacitor C1.

[0132] The first terminal of the fifth transistor M5 is connected to the first power supply terminal VDD, and the second terminal of the fifth transistor M5 is connected to the source S of the first transistor M1 and the first terminal of the eighth transistor M8.

[0133] The second terminal of the sixth transistor M6 is connected to the second terminal of the first light-emitting unit OLED1 and the seventh transistor M7. The control terminal of the sixth transistor M6 is connected to the control terminal of the fifth transistor M5 and is used to output the first enable signal EM1.

[0134] The control terminal of the seventh transistor M7 is used to input the third scan signal S3. When the seventh transistor M7 is turned on, the third scan signal S3 is input to the positive terminals of the first light-emitting unit OLED1 and the second light-emitting unit OLED2, eliminating the previous frame signal and resetting the first light-emitting unit OLED1 and the second light-emitting unit OLED2.

[0135] The first terminal of the eighth transistor M8 is connected to the first power supply terminal VDD, the second terminal of the eighth transistor M8 is connected to the second terminal of the capacitor C1, and the control terminal of the eighth transistor M8 is connected to the control terminal of the ninth transistor M9 to output the second enable signal EM2.

[0136] The second terminal of the ninth transistor M9 is connected to the second light-emitting unit OLED2 and the second terminal of the seventh transistor M7.

[0137] The driving method of the driving circuit can be as follows: Figure 3 The timing sequence shown includes:

[0138] Within one frame, the first light-emitting unit OLED1 and the second light-emitting unit OLED2 are driven in a time-division manner. During a first time period, the first light-emitting unit OLED1 is driven. During a second time period, the second light-emitting unit OLED2 is driven.

[0139] The first time period includes the first initialization phase T1, the first data writing phase T2, and the first light emission phase T3.

[0140] During the first initialization phase T1, the input terminal of the first scan signal S1 is at a low level, while the input terminals of the second scan signal S2, the first enable signal EM1, and the second enable signal EM2 are at a high level. At this time, the seventh transistor M7 is turned on, and the initialization signal initializes the control terminal of the first transistor M1 and the first terminal of the first light-emitting unit OLED1.

[0141] During the first data writing stage T2, the second scan signal input terminal S2 is at a low level, while the first scan signal input terminal S1, the first enable signal input terminal EM1, and the second enable signal input terminal EM2 are all at a high level. The second transistor M2 is turned on, and simultaneously the first transistor M1 and the third transistor M3 are turned on. The first data voltage is written to the control terminal of the first transistor M1 after passing through the second transistor M2, the first transistor M1, and the third transistor M3.

[0142] During the first light-emitting stage T3, the input terminal of the first enable signal EM1 is at a low level, and the input terminal of the second enable signal EM2 is at a high level, thereby controlling the fifth transistor M5 and the sixth transistor M6 to be turned on, providing a current path for the first light-emitting unit OLED1 and controlling the first light-emitting unit OLED1 to emit light; at this time, the eighth transistor M8 and the ninth transistor M9 are turned off, and the second light-emitting unit OLED2 does not emit light.

[0143] The second time period includes the second initialization phase t1, the second data writing phase t2, and the second light emission phase t3.

[0144] During the second initialization phase t1, the input terminal of the first scan signal S1 is at a low level, while the input terminals of the second scan signal S2, the first enable signal EM1, and the second enable signal EM2 are at a high level. At this time, the seventh transistor M7 is turned on, and the initialization signal initializes the control terminal of the first transistor M1 and the first terminal of the second light-emitting unit OLED2.

[0145] During the second data writing stage t2, the second scan signal input terminal S2 is at a low level, while the first scan signal input terminal S1, the first enable signal input terminal EM1, and the second enable signal input terminal EM2 are all at a high level. The second transistor M2 is turned on, and simultaneously the first transistor M1 and the third transistor M3 are turned on. The first data voltage is written to the control terminal of the first transistor M1 after passing through the second transistor M2, the first transistor M1, and the third transistor M3.

[0146] During the second light-emitting stage t3, the input terminal of the first enable signal EM1 is at a low level, and the input terminal of the second enable signal EM2 is at a high level, thereby controlling the eighth transistor M8 and the ninth transistor M9 to be turned on, providing a current path for the second light-emitting unit OLED2 and controlling the second light-emitting unit OLED2 to emit light; at this time, the fifth transistor M5 and the sixth transistor M6 are turned off, and the first light-emitting unit OLED1 does not emit light.

[0147] This enables time-division driving of the first light-emitting unit OLED1 and the second light-emitting unit OLED2, achieving high PPI display on the double-sided display panel.

[0148] refer to Figure 4 , Figure 4 This is a timing diagram illustrating another light-emitting unit's emission according to an embodiment of this application. The first enable signal EM1 and the second enable signal EM2 respectively turn on their corresponding transistors within a frame. The first light-emitting unit OLED1 and the second light-emitting unit OLED2 share the emission time within a frame, changing the duty cycle of an existing OLED from the conventional >90% to 40-50% for each OLED. With a high refresh rate, the human eye cannot perceive the decrease in duty cycle, and the visual effect is that the first light-emitting unit OLED1 and the second light-emitting unit OLED2 are lit simultaneously.

[0149] Based on the same inventive concept, this application also provides a display device (not shown), which includes the display panel in the above embodiments.

[0150] It is understood that the display device in the embodiments of this application can be any product or component with display function, such as OLED display device, QLED display device, electronic paper, mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, navigator, wearable device, Internet of Things device, etc., and the embodiments disclosed in this application do not limit this.

[0151] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0152] The embodiments described above are merely illustrative of several implementations of the present invention, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these all fall within the protection scope of the present invention. Therefore, the protection scope of this invention patent should be determined by the appended claims.

Claims

1. A display panel, characterized in that, include: Array substrate; The first electrode is located on one side of the array substrate and includes a first sub-electrode and a second sub-electrode arranged sequentially along a first direction, the first direction being perpendicular to the array substrate. A light-emitting unit is located between the first sub-electrode and the second sub-electrode, and the light-emitting unit includes a first light-emitting unit and a second light-emitting unit arranged sequentially along the first direction; The second electrode is located between the first light-emitting unit and the second light-emitting unit; Both the first sub-electrode and the second sub-electrode are connected to the array substrate.

2. The display panel according to claim 1, characterized in that, The first electrode further includes: An auxiliary electrode is located on the same layer as the first sub-electrode and is spaced apart from the first sub-electrode. The second sub-electrode is connected to the array substrate through the auxiliary electrode.

3. The display panel according to claim 2, characterized in that, The display panel also includes: A connection structure is located on the side of the first electrode away from the array substrate, and the connection structure connects the second sub-electrode and the auxiliary electrode.

4. The display panel according to claim 3, characterized in that, The orthographic projection of the connection structure on the array substrate does not overlap with the orthographic projection of the light emission port of the second light-emitting unit on the array substrate.

5. The display panel according to claim 3, characterized in that, The display panel also includes: An encapsulation layer is located on the side of the second sub-electrode away from the array substrate; The encapsulation layer includes a first through-hole and a second through-hole, the first through-hole exposing the auxiliary electrode and the second through-hole exposing the second sub-electrode; Optionally, the connection structure includes: A first connecting portion is located inside the first through hole, and the first connecting portion is in contact with the auxiliary electrode; The second connecting part is located inside the second through hole, and the second connecting part is in contact with the second sub-electrode; The third connection portion is located on the side of the encapsulation layer opposite to the array substrate, and the first connection portion and the second connection portion are connected through the third connection portion; Optionally, the display panel further includes: The encapsulation module is located on the side of the encapsulation layer opposite to the array substrate and covers the encapsulation layer and the connection structure.

6. The display panel according to claim 2, characterized in that, The display panel also includes: A pixel definition layer, located on the side of the first sub-electrode facing away from the array substrate, includes a first opening and a second opening spaced apart. The first opening exposes the first sub-electrode, and the second opening exposes the auxiliary electrode; Optionally, the display panel further includes: A planarization layer covers the array substrate and the first sub-electrode. The pixel definition layer covers the first sub-electrode, the auxiliary electrode, and the planarization layer. The planarization layer includes a third via, through which the first electrode is connected to the array substrate.

7. The display panel according to claim 2, characterized in that, The second electrode at least covers the first light-emitting unit, and the orthographic projection of the second electrode on the array substrate does not overlap with the orthographic projection of the auxiliary electrode on the array substrate; Optionally, the second electrode of each of the light-emitting units is an integral structure, and the second electrode has a fourth through hole that exposes the auxiliary electrode.

8. The display panel according to claim 1, characterized in that, The array substrate includes: The driving circuit drives the first light-emitting unit and the second light-emitting unit in a time-division manner.

9. The display panel according to claim 8, characterized in that, The array substrate further includes: A first light-emitting region is provided at an interval from the driving circuit; The orthographic projection of the first sub-electrode onto the array substrate at least partially overlaps with the first light-emitting region; Optionally, the orthographic projection of the first sub-electrode on the array substrate overlaps with the first light-emitting region.

10. A display device, characterized in that, Includes the display panel as described in any one of claims 1-9.

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