Semiconductor device and preparation method thereof

Abstract

The invention discloses a semiconductor device and a preparation method thereof, and relates to the technical field of semiconductors, and the preparation method comprises the steps: providing a semiconductor substrate; sequentially forming a first barrier layer, a first sacrificial layer and a second barrier layer on the semiconductor substrate; a first supporting part and at least two first conductive parts are formed, the first supporting part penetrates through the second barrier layer and the first sacrificial layer, and the first conductive parts penetrate through the second barrier layer, the first sacrificial layer and the first barrier layer and are electrically connected with the semiconductor substrate; and removing the first sacrificial layer to form a first cavity. The dielectric constant of the air is relatively low, so that the parasitic capacitance between the two first conductive parts can be effectively reduced, and the performance of the semiconductor device is further improved.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a semiconductor device and its fabrication method. Background Technology

[0002] With the continuous advancement of semiconductor manufacturing processes, the structure of metal interconnect layers in semiconductor devices has become increasingly complex in order to adapt to higher density integration. Multilayer metal wiring technology has been widely used to achieve high-density signal transmission and interconnection.

[0003] However, as the physical spacing between metal interconnects continues to shrink, the parasitic capacitance per unit length also increases significantly, leading to an increase in RC delay time. Compared to the ever-increasing switching speed of transistors, the RC delay on metal interconnects accounts for a larger and larger proportion of the total delay, becoming a key bottleneck restricting further improvements in the overall operating frequency and signal transmission speed of semiconductor devices. Summary of the Invention

[0004] The main objective of this invention is to propose a semiconductor device and its fabrication method, aiming to solve the problem of large parasitic capacitance between metal interconnects in existing semiconductor devices.

[0005] To achieve the above objectives, the present invention proposes a method for fabricating a semiconductor device, the method comprising the following steps:

[0006] A semiconductor substrate is provided, and a first barrier layer, a first sacrificial layer and a second barrier layer are sequentially formed on the semiconductor substrate; A first support portion and at least two first conductive portions are formed. The first support portion penetrates the second barrier layer and the first sacrificial layer. The first conductive portions penetrate the second barrier layer, the first sacrificial layer and the first barrier layer, and are electrically connected to the semiconductor substrate. The first sacrificial layer is removed to form the first cavity.

[0007] In one embodiment of the present invention, the step of forming the first support portion and at least two first conductive portions includes: Multiple first deposition trenches are formed that penetrate the second barrier layer and the first sacrificial layer; A first support material layer is formed inside the first deposition tank and on the second barrier layer; At least two second deposition trenches are formed that penetrate the first support material layer, the second barrier layer, the first sacrificial layer, and the first barrier layer; A conductive material layer is formed inside the second deposition tank and on the first support material layer; Remove the first support material layer and the conductive material layer located above the second barrier layer to form the first support portion located in the first deposition tank and the first conductive portion located in the second deposition tank.

[0008] In one embodiment of the present invention, the material of the first sacrificial layer is amorphous carbon, and the step of removing the first sacrificial layer to form the first cavity includes: The second barrier layer is etched to form a first opening that exposes the first sacrificial layer; The first sacrificial layer is removed by oxidation to form the first cavity.

[0009] In one embodiment of the present invention, after the step of forming the first support portion and at least two first conductive portions, and before the step of forming the first cavity, the method further includes: The second barrier layer is etched to form a second opening that exposes the first sacrificial layer.

[0010] In one embodiment of the present invention, the step of forming the first cavity is followed by: A second support material layer is deposited on the surface of the second barrier layer and inside the first cavity to form a second support material layer; Remove the second support material layer located on the second barrier layer to form a second support portion extending from the first barrier layer toward the second opening.

[0011] In one embodiment of the present invention, the step of forming the first cavity is followed by: A third barrier layer, a second sacrificial layer, and a fourth barrier layer are sequentially formed on the second barrier layer; A third support portion and at least two second conductive portions are formed, wherein the third support portion penetrates the fourth barrier layer and the second sacrificial layer, and the second conductive portions penetrate the fourth barrier layer, the second sacrificial layer and the third barrier layer; The second sacrificial layer is removed to form a second cavity.

[0012] In one embodiment of the present invention, the step of forming the second cavity includes: A window is formed in the fourth barrier layer to expose the second sacrificial layer; Remove the second sacrificial layer to form the second cavity; A fourth support portion is formed extending from the third barrier layer toward the window.

[0013] In one embodiment of the present invention, the step of forming the second cavity is followed by: A fifth barrier layer, a third sacrificial layer, and a sixth barrier layer are sequentially formed on the fourth barrier layer; A fifth support portion and at least two third conductive portions are formed, wherein the fifth support portion penetrates the sixth barrier layer and the third sacrificial layer, and the third conductive portions penetrate the sixth barrier layer, the third sacrificial layer and the fifth barrier layer; The third sacrificial layer is removed to form a third cavity.

[0014] In one embodiment of the present invention, after the step of forming the first support portion and at least two first conductive portions, and before the step of removing the first sacrificial layer and forming the first cavity, the method further includes: A third barrier layer, a second sacrificial layer, and a fourth barrier layer are sequentially formed on the second barrier layer; A third support portion and at least two second conductive portions are formed, wherein the third support portion penetrates the fourth barrier layer and the second sacrificial layer, and the second conductive portions penetrate the fourth barrier layer, the second sacrificial layer and the third barrier layer; A fifth barrier layer, a third sacrificial layer, and a sixth barrier layer are sequentially formed on the fourth barrier layer; A fifth support portion and at least two third conductive portions are formed, wherein the fifth support portion penetrates the sixth barrier layer and the third barrier layer, and the third conductive portions penetrate the sixth barrier layer, the third sacrificial layer and the fifth barrier layer.

[0015] In one embodiment of the present invention, the step of forming the first cavity includes: A third opening is formed to expose the first sacrificial layer, the second sacrificial layer, and the third sacrificial layer; The first sacrificial layer, the second sacrificial layer, and the third sacrificial layer are removed to form the first cavity, the second cavity, and the third cavity.

[0016] In one embodiment of the present invention, after the step of forming the first cavity, the second cavity, and the third cavity, the method further includes: A fourth opening is made, exposing the first barrier layer to the fourth opening; A third support material layer is deposited and formed on the surface of the sixth barrier layer, the surface of the first barrier layer, and inside the first cavity, the second cavity, and the third cavity; Remove the third support material layer located on the sixth barrier layer to form a sixth support portion extending from the first barrier layer toward the fourth opening.

[0017] The present invention also proposes a semiconductor device, the semiconductor device comprising: Semiconductor substrate; A metal interconnect layer disposed on the semiconductor substrate, the metal interconnect layer including a first barrier layer, a second barrier layer, a first support portion and at least two first conductive portions; The first barrier layer is disposed on the semiconductor substrate, and the second barrier layer is disposed at a distance from the first barrier layer on the side of the semiconductor substrate away from the semiconductor substrate. The two ends of the first support portion are respectively connected to the first barrier layer and the second barrier layer. A first cavity is formed between the first barrier layer and the second barrier layer. At least two first conductive portions are disposed in the first cavity and are spaced apart along a direction parallel to the semiconductor substrate. One end of the first conductive portion is connected to the semiconductor substrate, and the other end is exposed on the side of the second barrier layer away from the semiconductor substrate.

[0018] In one embodiment of the present invention, the metal interconnect layer further includes a second support portion, the two ends of which are respectively connected to the first barrier layer and the second barrier layer, and the cross-sectional area of ​​the first support portion is smaller than the cross-sectional area of ​​the second support portion.

[0019] In one embodiment of the present invention, the semiconductor device includes multiple layers of the metal interconnect layers, which are stacked sequentially on the semiconductor substrate.

[0020] In one embodiment of the present invention, the semiconductor device includes two metal interconnect layers. The metal interconnect layer disposed on the semiconductor substrate includes a first barrier layer, a second barrier layer, a first support portion, and at least two first conductive portions. The metal interconnect layer away from the semiconductor substrate includes a third barrier layer, a fourth barrier layer, a third support portion, and at least two second conductive portions. A second cavity is formed between the third barrier layer and the fourth barrier layer. The third support portion and at least two second conductive portions are disposed in the second cavity. The two ends of the third support portion are respectively connected to the third barrier layer and the fourth barrier layer.

[0021] In one embodiment of the present invention, the semiconductor device further includes a seventh support portion, which penetrates the fourth barrier layer, the third barrier layer and the second barrier layer in a direction perpendicular to the semiconductor substrate, and the two ends of the seventh support portion are respectively connected to the first barrier layer and the fourth barrier layer; The cross-sectional dimension of the seventh support portion along the direction parallel to the semiconductor substrate is larger than the cross-sectional dimensions of the first support portion and the third support portion.

[0022] In one embodiment of the present invention, the semiconductor device further includes a second support portion and a fourth support portion; the second support portion is located in the first cavity, and the two ends of the first cavity are respectively connected to the first barrier layer and the second barrier layer; the fourth support portion is located in the second cavity, and the two ends of the fourth support portion are respectively connected to the third barrier layer and the fourth barrier layer; the cross-sectional area of ​​the second support portion is larger than the cross-sectional area of ​​the first support portion, and the cross-sectional area of ​​the fourth support portion is larger than the cross-sectional area of ​​the third support portion.

[0023] The method for fabricating a semiconductor device provided by this invention involves firstly fabricating a first barrier layer, a first sacrificial layer, and a second barrier layer sequentially on a semiconductor substrate to form a first support portion and at least two first conductive portions. The first support portion penetrates the second barrier layer and the first sacrificial layer, and its two ends are respectively connected to the first barrier layer and the second barrier layer. The first conductive portions penetrate the second barrier layer, the first sacrificial layer, and the first barrier layer, with one end connected to the semiconductor substrate and the other end exposed on the side of the second barrier layer away from the semiconductor substrate. Finally, the first sacrificial layer is removed to form a first cavity. Because air has a low dielectric constant, the parasitic capacitance between the two first conductive portions can be effectively reduced, thereby improving the performance of the semiconductor device. Furthermore, by providing the first support portion and connecting it to the first and second barrier layers in a direction perpendicular to the semiconductor substrate, the first support portion can provide support to maintain the stability of the internal structure of the semiconductor device. Attached Figure Description

[0024] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on the structures shown in these drawings without creative effort.

[0025] Figure 1 This is a schematic diagram of the formation of a first stacked structure on a semiconductor substrate in the semiconductor device fabrication method of the present invention; Figure 2 In order to be in Figure 1 A schematic diagram showing the formation of the first sedimentation tank based on this. Figure 3 In order to be in Figure 2 A schematic diagram of the formation of the first supporting material layer based on the above; Figure 4 In order to be in Figure 3 A schematic diagram showing the formation of a second sedimentation tank based on the above. Figure 5 In order to be in Figure 4 A schematic diagram of a conductive material layer formed on the basis of the above. Figure 6 In order to be in Figure 5 A schematic diagram showing the formation of the first support part and the first conductive part based on the above. Figure 7 for Figure 6 Top view; Figure 8 In order to be in Figure 6 Based on this, a schematic diagram of the first opening is formed; Figure 9 for Figure 8 Top view; Figure 10 In order to be in Figure 8 A schematic diagram showing the formation of the first cavity based on this; Figure 11 In order to be in Figure 10 A schematic diagram showing the formation of the third barrier layer, the second sacrificial layer, and the fourth barrier layer based on this; Figure 12 In order to be in Figure 11 A schematic diagram of a stacked metal interconnect layer formed on the basis of the above. Figure 13 In order to be in Figure 8 A schematic diagram showing the formation of the second opening based on this; Figure 14 In order to be in Figure 13 A schematic diagram showing the formation of the first cavity based on this; Figure 15 for Figure 14 Top view; Figure 16 In order to be in Figure 14 A schematic diagram showing the formation of a second supporting material layer based on the existing structure; Figure 17 In order to be in Figure 16 A schematic diagram of the second support section formed based on the above; Figure 18 In order to be in Figure 17 A schematic diagram showing the formation of the third barrier layer, the second sacrificial layer, and the fourth barrier layer based on this; Figure 19 In order to be in Figure 18 A schematic diagram of a stacked metal interconnect layer formed on the basis of the above. Figure 20 In order to be in Figure 6 A schematic diagram of the first, second, and third stacked structures formed on the basis of the above. Figure 21 In order to be in Figure 20 A schematic diagram of the third opening is formed based on this; Figure 22 In order to be in Figure 21 A schematic diagram of a multilayer metal interconnect layer stacked on the basis of the above. Figure 23 In order to be in Figure 22 A schematic diagram of the fourth opening is formed based on this; Figure 24 In order to be in Figure 23 A schematic diagram of the formation of the third supporting material layer based on the above; Figure 25 In order to be in Figure 24 A schematic diagram of a multi-layered metal interconnect layer based on the above. Figure 26 This is a flowchart of one embodiment of the semiconductor device fabrication method of the present invention; Figure 27 for Figure 26 A flowchart of the steps in which the first support portion and the first conductive portion are formed; Figure 28 for Figure 26 Flowchart of the step in forming the first cavity; Figure 29 for Figure 28 Flowchart before the formation of the first cavity; Figure 30 for Figure 28 Flowchart following the step of forming the first cavity; Figure 31 for Figure 26 Flowchart following the step of forming the first cavity; Figure 32 for Figure 26 A flowchart showing the process after the steps of forming the first support portion and the first conductive portion and before the step of forming the first cavity; Figure 33 for Figure 32 A flowchart illustrating the steps involved in forming the first cavity; Figure 34 for Figure 33 The flowchart following the step of forming the first cavity.

[0026] Explanation of icon numbers: 10. Semiconductor substrate; 20. Metal interconnect layer; 21. First stacked structure; 211. First barrier layer; 212. First sacrificial layer; 213. Second barrier layer; 214. First cavity; 215. First deposition tank; 216. Second deposition tank; 217. First opening; 218. Second opening; 22. Second stacked structure; 221. Third barrier layer; 222. Second sacrificial layer; 223. Fourth barrier layer; 224. Second cavity; 225. Third opening; 226. Fourth opening; 23. Three-layer structure; 231, third cavity; 232, fifth barrier layer; 233, third sacrificial layer; 234, sixth barrier layer; 24, first support material layer; 25, conductive material layer; 26, second support material layer; 27, third support material layer; 201, first support part; 202, first conductive part; 203, second support part; 204, third support part; 205, fourth support part; 206, second conductive part; 207, fifth support part; 208, third conductive part; 209, sixth support part.

[0027] The realization of the objective, functional features and advantages of the present invention will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation

[0028] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of the present invention.

[0029] It should be noted that if the embodiments of the present invention involve directional indicators (such as up, down, left, right, front, back, etc.), the directional indicators are only used to explain the relative positional relationship and movement of the components in a specific posture. If the specific posture changes, the directional indicators will also change accordingly.

[0030] Furthermore, if the embodiments of this invention involve descriptions such as "first" or "second," these descriptions are for descriptive purposes only and should not be construed as indicating or implying their relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined with "first" or "second" may explicitly or implicitly include at least one of those features. Additionally, the use of "and / or" or "and / or" throughout the text includes three parallel solutions. For example, "A and / or B" includes solution A, solution B, or a solution where both A and B are satisfied simultaneously. Furthermore, the technical solutions of the various embodiments can be combined with each other, but this must be based on the ability of those skilled in the art to implement them. When the combination of technical solutions is contradictory or impossible to implement, it should be considered that such a combination of technical solutions does not exist and is not within the scope of protection claimed by this invention.

[0031] This invention proposes a method for fabricating a semiconductor device.

[0032] Combination Figure 1 , Figure 6 , Figure 10 as well as Figure 26 As shown, in one embodiment of the present invention, the preparation method includes the following steps: S1: Provide a semiconductor substrate 10; sequentially form a first barrier layer 211, a first sacrificial layer 212 and a second barrier layer 213 on the semiconductor substrate 10; Specifically, the semiconductor substrate 10 includes a substrate and a transistor formed on the substrate, wherein the substrate may be a single-crystal silicon substrate, a silicon-on-insulator (SOI) substrate, or other substrate materials suitable for semiconductor manufacturing.

[0033] like Figure 1 As shown, a first barrier layer 211, a first sacrificial layer 212, and a second barrier layer 213 are sequentially formed on a semiconductor substrate 10, and the first barrier layer 211, the first sacrificial layer 212, and the second barrier layer 213 form a first stacked structure 21.

[0034] Specifically, firstly, a first barrier layer 211 is formed on the surface of the semiconductor substrate 10. The first barrier layer 211 can be made of materials such as silicon carbonitride, silicon nitride, silicon oxynitride, silicon oxide, and silicon carbon oxynitride through a deposition process.

[0035] Then, an amorphous carbon layer or spin-coated carbon layer is formed on the first barrier layer 211 by deposition or spin coating as the first sacrificial layer 212. The thickness of the first sacrificial layer 212 can be 100-500nm.

[0036] Finally, a second barrier layer 213 is formed on the first sacrificial layer 212. The second barrier layer 213 serves as a hard mask layer and can be made of materials such as silicon nitride and silicon oxynitride through a deposition process.

[0037] S2: A first support portion 201 and at least two first conductive portions 202 are formed. The first support portion 201 penetrates the second barrier layer 213 and the first sacrificial layer 212. The first conductive portions 202 penetrate the second barrier layer 213, the first sacrificial layer 212 and the first barrier layer 211, and are electrically connected to the semiconductor substrate 10. Specifically, such as Figure 6 As shown, a first support portion 201 and at least two first conductive portions 202 are formed through photolithography, etching, and deposition processes. The first support portion 201 penetrates the second barrier layer 213 and the first sacrificial layer 212, and its two ends are respectively connected to the first barrier layer 211 and the second barrier layer 213. The end of the first support portion 201 facing the first barrier layer 211 can be flush with the surface of the first barrier layer 211 facing away from the semiconductor substrate 10, or it can be partially embedded within the first barrier layer 211. The first conductive portions 202 penetrate the second barrier layer 213, the first sacrificial layer 212, and the first barrier layer 211. One end of the first conductive portion 202 is electrically connected to the semiconductor substrate 10, and the other end is exposed on the side of the second barrier layer 213 facing away from the semiconductor substrate 10, serving as a signal transmission line. At least two first conductive portions 202 are spaced apart along a direction parallel to the semiconductor substrate 10.

[0038] Understandable, such as Figure 12 , Figure 19 , Figure 22 as well as Figure 25 As shown, the first stacked structure 21, together with the first support portion 201 and the first conductive portion 202 disposed therein, constitutes a metal interconnect layer 20. When the metal interconnect layer 20 has multiple layers, as mentioned in subsequent embodiments, a second stacked structure 22 is disposed on the first stacked structure 21, and a third support portion 204 and a second conductive portion 206 are disposed inside the second stacked structure 22. The second stacked structure 22, the third support portion 204, and the second conductive portion 206 constitute another metal interconnect layer 20. Similarly, a third stacked structure 23 is disposed on the second stacked structure 22, and a fifth support portion 207 and a third conductive portion 208 are disposed inside the third stacked structure 23. The third stacked structure 23, the fifth support portion 207, and the third conductive portion 208 constitute another metal interconnect layer 20.

[0039] S3: Remove the first sacrificial layer 212 to form the first cavity 214.

[0040] Specifically, such as Figure 10As shown, the first sacrificial layer 212 is removed by oxidation or etching. Since the first sacrificial layer 212 is removed, a first cavity 214 is formed in the area that was originally filled with the first sacrificial layer 212; therefore, there is an air gap between adjacent first conductive parts 202.

[0041] Since the dielectric constant of air (approximately 1) is much lower than that of commonly used interlayer dielectric materials (such as silicon oxide, which has a dielectric constant of approximately 4), an air gap exists between adjacent first conductive portions 202 after the formation of the first cavity 214. This reduces the parasitic capacitance between adjacent first conductive portions 202, thereby improving the performance of the semiconductor device. Simultaneously, since the first support portion 201 connects between the first barrier layer 211 and the second barrier layer 213, the first support portion 201 provides support for the first stacked structure 21, mitigating the problem of the second barrier layer 213 collapsing or deforming after losing the support of the first sacrificial layer 212. This improves the stability of the semiconductor device structure and the yield of the manufacturing process.

[0042] Combination Figures 2 to 6 as well as Figure 27 As shown, in one embodiment of the present invention, the step of forming the first support portion 201 and at least two first conductive portions 202 includes: S21: Form multiple first deposition trenches 215 that penetrate the second barrier layer 213 and the first sacrificial layer 212; Specifically, after forming the first stacked structure 21, multiple first deposition trenches 215 penetrating the second barrier layer 213 and the first sacrificial layer 212 are formed on the first stacked structure 21 through photolithography and etching processes. For example, a photoresist layer is coated on the second barrier layer 213, and then etching windows are opened on the photoresist layer through photolithography so that the second barrier layer 213 is exposed at the etching windows, and the shape and position of the etching windows correspond to the first deposition trenches 215. Then, the second barrier layer 213 and the first sacrificial layer 212 exposed at the etching windows are removed sequentially through etching processes, stopping at the first barrier layer 211. Since the materials of the second barrier layer 213 and the first sacrificial layer 212 are different and their etching selectivity is different, the second barrier layer 213 and the first sacrificial layer 212 exposed at the etching windows can be removed sequentially through step-by-step etching, or by using different etching processes, or etching gases or etching solvents, to form the first deposition trenches 215.

[0043] Additionally, in other embodiments, such as Figure 2As shown, when etching to form the first deposition tank 215, a portion of the first barrier layer 211 exposed to the etching window can be removed. That is, the bottom wall of the formed first deposition tank 215 is located inside the first barrier layer 211, so that the bottom of the first support portion 201 formed in the first deposition tank 215 can be embedded into the first barrier layer 211, thereby improving the connection strength between the first support portion 201 and the first barrier layer 211, and further improving the support stability of the first support portion 201 on the first stacked structure 21.

[0044] S22: A first support material layer 24 is formed in the first deposition tank 215 and on the second barrier layer 213; Specifically, such as Figure 3 As shown, in the first stacked structure 21, including the interior of the first deposition tank 215 and the surface of the second barrier layer 213, a first support material layer 24 is formed by processes such as flowable chemical vapor deposition (CVD) or atomic layer deposition (ALD). The material of the first support material layer 24 can be silicon nitride.

[0045] S23: Form at least two second deposition trenches 216 that penetrate the first support material layer 24, the second barrier layer 213, the first sacrificial layer 212, and the first barrier layer 211; Specifically, such as Figure 4 As shown, a second photolithography and etching process is performed to form a second deposition tank 216 that penetrates the first support material layer 24, the second barrier layer 213, the first sacrificial layer 212, and the first barrier layer 211. The second deposition tank 216 can be fabricated using similar process steps to form the first deposition tank 215 as described above.

[0046] In one embodiment, forming the second deposition tank 216 includes the following steps: S231: Form a through hole that penetrates the first support material layer 24, the second barrier layer 213, the first sacrificial layer 212 and the first barrier layer 211.

[0047] Specifically, a first layer of photoresist is coated on the surface of the first support material layer 24, and the location where the first conductive part 202 needs to be formed is defined by photolithography. Using the patterned photoresist as a mask, the first support material layer 24, the second barrier layer 213, the first sacrificial layer 212, and the first barrier layer 211 are etched sequentially, finally stopping at the surface of the semiconductor substrate 10 or inside the semiconductor substrate 10 to form a through hole and expose the semiconductor substrate 10. Then the first layer of photoresist is removed.

[0048] S232: A protective layer is formed inside the through hole.

[0049] A filling material is deposited on the surface of the first support material layer 24 and inside the through hole. The filling material fills the through hole to protect the bottom and sidewalls of the through hole from damage or etching in subsequent processes.

[0050] Then, excess filler material on the surface of the first support material layer 24 is removed by grinding or etching, leaving only the filler material inside the through hole to form a protective layer inside the through hole.

[0051] S233: Etch the first support material layer 24, the second barrier layer 213, and part of the first sacrificial layer 212 to form a trench communicating with the through hole.

[0052] Photoresist is applied again to the surface of the first support material layer 24. Through photolithography, a window is defined to form the first conductive part 202. The width of the window is greater than the diameter of the through hole.

[0053] Using the patterned photoresist as a mask, an etching process is performed again to remove the first support material layer 24, the second barrier layer 213, and part of the first sacrificial layer 212 that are not protected by the photoresist, forming a trench.

[0054] S234: Remove the protective layer, and connect the trench and the through hole to form a second deposition tank 216.

[0055] After removing the photoresist and the protective layer inside the via, the trench and via are connected to form a second deposition trench 216.

[0056] S24: A conductive material layer 25 is formed inside the second deposition tank 216 and on the first support material layer 24; Specifically, such as Figure 5 As shown, a conductive material layer 25, such as copper, tungsten or aluminum, is deposited inside the second deposition tank 216 and on the surface of the first support material layer 24 by means of physical vapor deposition (PVD), atomic layer deposition (ALD) or electroplating.

[0057] S25: Remove the first support material layer 24 and conductive material layer 25 located above the second barrier layer 213 to form a first support portion 201 located in the first deposition tank 215 and a first conductive portion 202 located in the second deposition tank 216.

[0058] As can be seen from the foregoing embodiments, the process of etching to form the second deposition tank 216 will simultaneously remove the first support material layer 24 corresponding to the region of the second deposition tank 216, but the first support material layer 24 located in other regions of the surface of the second barrier layer 213 is retained due to the protection of the photoresist.

[0059] Therefore, as Figure 6As shown, after the conductive material layer 25 and the first support material layer 24 are fabricated, the first support material layer 24 and the conductive material layer 25 located above the second barrier layer 213 are removed by a grinding process to expose the upper surface of the second barrier layer 213, thereby forming the first support portion 201 and the first conductive portion 202.

[0060] like Figure 7 As shown, the first support portion 201 is columnar, and its cross-sectional shape parallel to the semiconductor substrate 10 can be a regular shape such as a circle, a square, or a strip, or other irregular shapes.

[0061] Combination Figures 8 to 10 as well as Figure 28 As shown, in one embodiment of the present invention, the material of the first sacrificial layer 212 is amorphous carbon. Amorphous carbon not only has good filling and planarization properties, but can also be converted into gaseous carbon dioxide by oxygen ion oxidation, so as to achieve the purpose of removing the first sacrificial layer 212 while retaining the first barrier layer 211, the second barrier layer 213, the first support portion 201 and the first conductive portion 202.

[0062] The step of removing the first sacrificial layer 212 to form the first cavity 214 includes: S31: Etch the second barrier layer 213 to form a first opening 217 that exposes the first sacrificial layer 212; like Figure 8 As shown, firstly, photoresist is coated on the second barrier layer 213, and the opening region exposing the first sacrificial layer 212 is defined by photolithography. Then, the second barrier layer 213 is etched by etching to form a first opening 217 exposing the first sacrificial layer 212 beneath the second barrier layer 213. Figure 9 As shown, the first opening 217 can be a narrow groove or multiple small holes, and its function is to expose the first sacrificial layer 212 so that the first sacrificial layer 212 can be removed in subsequent processes.

[0063] S32: Oxidation removes the first sacrificial layer 212, forming the first cavity 214.

[0064] Specifically, utilizing the properties of amorphous carbon, an oxygen ion oxidation process is employed to oxidize the first sacrificial layer 212, generating carbon dioxide gas which is then discharged through the first opening 217. Since oxygen ions have an extremely low etching rate on silicon nitride, silicon oxide, silicon carbonitride, and metals, this oxygen ion oxidation process can selectively remove the first sacrificial layer 212 without damaging the first conductive portion 202 (metal), the second barrier layer 213 (such as silicon nitride), the first support portion 201 (such as silicon oxide), or the first barrier layer 211 (such as silicon carbonitride).

[0065] like Figure 10As shown, after removing the first sacrificial layer 212, a first cavity 214 is formed in the space originally occupied by the first sacrificial layer 212. Therefore, there is an air gap between two adjacent first conductive parts 202.

[0066] Combination Figure 13 as well as Figure 29 As shown, in one embodiment of the present invention, after the step of forming the first support portion 201 and the first conductive portion 202, and before the step of forming the first cavity 214, the following steps are further included: S33: Etch the second barrier layer 213 to form a second opening 218 that exposes the first sacrificial layer 212; like Figure 13 and Figure 14 As shown, firstly, photoresist is coated on the surface of the second barrier layer 213, and then an etching process is used again to etch the second barrier layer 213 to form a second opening 218 that exposes the underlying first sacrificial layer 212. The second opening 218 is located in a region with a large distance between two adjacent first conductive parts 202, or at a critical stress point in the device structure.

[0067] like Figure 13 and Figure 15 As shown, a second opening 218 can be formed at the same time as the first opening 217 is formed. The size of the second opening 218 is larger than the size of the first opening 217, and the shape of the second opening 218 can be circular, polygonal, or other shapes.

[0068] Combination Figure 14 , Figure 15 As shown, in one embodiment of the present invention, the step of forming the first cavity includes: S34: Remove the first sacrificial layer 212 to form the first cavity 214.

[0069] like Figure 14 and Figure 15 As shown, specifically, the amorphous carbon of the first sacrificial layer 212 is oxidized to generate carbon dioxide gas through an oxygen ion oxidation process, and then discharged through the first opening 217 and the second opening 218. By forming a larger second opening 218, the exposed area of ​​the first sacrificial layer 212 is increased, which also facilitates the removal of the first sacrificial layer 212 in the oxygen ion oxidation process.

[0070] Combination Figure 16 , Figure 17 as well as Figure 30 As shown, in one embodiment of the present invention, after the step of removing the first sacrificial layer 212 to form the first cavity 214, the method further includes: S35: A second support material layer 26 is deposited on the surface of the second barrier layer 213 and inside the first cavity 214; Specifically, such as Figure 16 As shown, the material of the second support material layer 26 can be the same as that of the first support material layer 24, such as silicon oxide, or it can be a different insulating material with good support properties than the first support material layer 24. During the deposition process, the deposited material begins to accumulate from the surface of the first barrier layer 211 exposed at the second opening 218, and extends in a direction perpendicular to the first barrier layer 211 and toward the second opening 218; at the same time, support material is also deposited on the surface of the second barrier layer 213, finally forming a second support material layer 26 covering the surface of the second barrier layer 213 and extending from the first barrier layer 211 to the second opening 218.

[0071] S36: Remove the second support material layer 26 located on the second barrier layer 213 to form the second support portion 203.

[0072] like Figure 17 As shown, the second support material layer 26 located on the surface of the second barrier layer 213 is removed through planarization processes such as grinding or etching, while the second support material layer 26 located in the first cavity 214 and on the inner sidewall of the second opening 218 is retained, forming a second support portion 203 extending from the first barrier layer 211 toward the second opening 218. The second support portion 203 connects the second barrier layer 213 and the first barrier layer 211, serving to support the first barrier layer 211 and the second barrier layer 213 and improve the stability of the metal interconnect layer 20. The cross-sectional dimension of the second support portion 203 is larger than that of the first support portion 201, and the second support portion 203 has greater support strength.

[0073] In the metal interconnect layer 20, where the metal interconnect lines (first conductive parts 202) are relatively dense, only the first support parts 201 with a small cross-sectional size can be made to maintain a large gap between adjacent first conductive parts 202, thereby reducing parasitic capacitance; where the metal interconnect lines are relatively sparse, the second support parts 203 can be made to improve the support performance of the metal interconnect layer 20 and ensure the yield of the process.

[0074] Combination Figure 11 , Figure 12 , Figure 18 as well as Figure 31 As shown, in one embodiment of the present invention, after the step of forming the first cavity 214, the method further includes: S41: A third barrier layer 221, a second sacrificial layer 222, and a fourth barrier layer 223 are sequentially formed on the second barrier layer 213; Specifically, such as Figure 11 and Figure 18As shown, a third barrier layer 221 is disposed on the surface of the second barrier layer 213. The material of the third barrier layer 221 can be the same as that of the first barrier layer 211, or it can be made of a different insulating material. The material of the second sacrificial layer 222 can be the same as that of the first sacrificial layer 212, or it can be made of a material that has a greater etching selectivity than the first barrier layer 211 and the second barrier layer 213, or it can be made of a material that is easy to remove. The material of the fourth barrier layer 223 can be the same as that of the second barrier layer 213, or it can be made of a different hard mask material. The third barrier layer 221, the second sacrificial layer 222, and the fourth barrier layer 223 form a second stacked structure 22.

[0075] The third barrier layer 221 serves to protect the underlying metal interconnect structure, particularly preventing the material of the subsequent second sacrificial layer 222 from filling the lower first cavity 214. It also acts as a bottom etching stop layer for the second stacked structure 22. The fabrication processes for the third barrier layer 221, the second sacrificial layer 222, and the fourth barrier layer 223 can be found in the aforementioned description of the first barrier layer 211, the first sacrificial layer 212, and the second barrier layer 213 in the first stacked structure 21, and will not be elaborated further here.

[0076] S42: A third support portion 204 and at least two second conductive portions 206 are formed. The third support portion 204 penetrates the fourth barrier layer 223 and the second sacrificial layer 222. The second conductive portions 206 penetrate the fourth barrier layer 223, the second sacrificial layer 222 and the third barrier layer 221. Specifically, through photolithography and etching processes, a third deposition tank (not shown) is first formed, penetrating the fourth barrier layer 223 and the second sacrificial layer 222. Then, a support material layer is formed within the third deposition tank and on the surface of the fourth barrier layer 223. Next, a fourth deposition tank (not shown) is formed, penetrating the support material layer, the fourth barrier layer 223, the second sacrificial layer 222, and the third barrier layer 221. A conductive material layer is formed within the fourth deposition tank and on the surface of the support material layer. Finally, the support material layer and the conductive material layer above the fourth barrier layer 223 are removed to form a third support portion 204 within the third deposition tank and a second conductive portion 206 within the fourth deposition tank. The steps for fabricating the third support portion 204 and the second conductive portion 206 are similar to those for the first conductive portion 202 and the first support portion 201; therefore, specific details can be found in the description of the foregoing embodiments and will not be elaborated further here.

[0077] Understandably, when forming the fourth deposition tank, the formation position of the fourth deposition tank is controlled to correspond to the second deposition tank 216, that is, the projections of the fourth deposition tank and the second deposition tank 216 onto the semiconductor substrate 10 at least partially overlap, so that the second conductive portion 206 is electrically connected to the first conductive portion 202, thereby realizing the signal connection of adjacent metal interconnect layers 20. Of course, in some embodiments, the second conductive portion 206 may not be electrically connected to the first conductive portion 202.

[0078] S43: Remove the second sacrificial layer 222 to form a second cavity 224.

[0079] Specifically, an opening is first formed on the fourth barrier layer 223 using photolithography and etching processes to expose the second sacrificial layer 222. Then, the second sacrificial layer 222 is removed using processes such as etching or oxygen ion oxidation. For example, when the second sacrificial layer 222 is amorphous carbon, it is oxidized to gaseous carbon dioxide using oxygen ion oxidation to remove the second sacrificial layer 222, thus creating the second cavity 224; therefore, an air gap exists between two adjacent first conductive portions 202. Figure 12 As shown, a double-layer metal interconnect layer 20 is formed in a direction perpendicular to the semiconductor substrate 10, and both metal interconnect layers 20 have air gaps.

[0080] The metal interconnects (i.e., the first conductive portion 202 and the second conductive portion 206) within each metal interconnect layer 20 are isolated by air with a low dielectric constant, thereby reducing parasitic capacitance and improving the performance of the semiconductor device.

[0081] Furthermore, such as Figure 19 As shown, the step of forming the second cavity 224 also includes: S431: A window exposing the second sacrificial layer 222 is formed on the fourth barrier layer 223. The size of the window is larger than the size of the opening formed on the fourth barrier layer 223. Specifically, the window can be formed on the fourth barrier layer 223 by photolithography and etching processes. The shape of the window can be circular, polygonal, or other shapes.

[0082] S432: Remove the second sacrificial layer 222 to form the second cavity 224; Specifically, through the oxygen ion oxidation process, the amorphous carbon of the second sacrificial layer 222 is oxidized to carbon dioxide gas and discharged through the window and the opening formed on the fourth barrier layer 223 in the above embodiment, thereby forming the second cavity 224. By setting a larger window, the exposed area of ​​the second sacrificial layer 222 is increased, which facilitates the removal of the second sacrificial layer 222 in the oxygen ion oxidation process.

[0083] S433: Form the fourth support section 205.

[0084] Specifically, through a deposition process, support material is sequentially deposited on the surface of the third barrier layer 221 exposed at the window, ultimately forming a fourth support portion 205 extending from the third barrier layer 221 toward the window. Specific steps can be referred to the aforementioned description of the second support portion 203, and will not be elaborated further here.

[0085] Understandable, such as Figure 22 As shown, a third stacked structure 23 can be further provided on the second stacked structure 22, and a support portion and a conductive portion can be made in the third stacked structure 23 to form another metal interconnect layer 20 with a third cavity 231. That is, a multi-layer stacked metal interconnect layer 20 is formed in the direction perpendicular to the semiconductor substrate 10, and a cavity structure is provided between two adjacent conductive portions in each metal interconnect layer 20.

[0086] In one embodiment of the present invention, after forming the second cavity 224, the method further includes the following steps: S51: A fifth barrier layer 232, a third sacrificial layer 233 and a sixth barrier layer 234 are sequentially formed on the fourth barrier layer 223; Specifically, the fifth barrier layer 232 is disposed on the surface of the fourth barrier layer 223. The material of the fifth barrier layer 232 can be the same as that of the first barrier layer 211 and the third barrier layer 221, or it can be made of a different insulating material. The material of the third sacrificial layer 233 can be the same as that of the first sacrificial layer 212 and the second sacrificial layer 222, or it can be made of other materials that offer greater etching selectivity or are easier to remove than the fifth barrier layer 232 and the sixth barrier layer 234. The material of the sixth barrier layer 234 can be the same as that of the fourth barrier layer 223 and the second barrier layer 213, or it can be made of a different hard mask material. The fabrication processes of the fifth barrier layer 232, the third sacrificial layer 233, and the sixth barrier layer 234 can be referred to the aforementioned description of the first stacked structure 21 or the second stacked structure 22, and will not be elaborated further here. The fifth barrier layer 232, the third sacrificial layer 233, and the sixth barrier layer 234 form the third stacked structure 23.

[0087] S52: A fifth support portion 207 and at least two third conductive portions 208 are formed. The fifth support portion 207 penetrates the sixth barrier layer 234 and the third sacrificial layer 233. The third conductive portions 208 penetrate the sixth barrier layer 234, the third sacrificial layer 233 and the fifth barrier layer 232. Specifically, a fifth deposition tank (not shown) penetrating the sixth barrier layer 234 and the third sacrificial layer 233 is formed through photolithography and etching processes. A support material layer is then formed within the fifth deposition tank and on the surface of the sixth barrier layer 234. Next, a sixth deposition tank (not shown) penetrating the support material layer, the sixth barrier layer 234, the third sacrificial layer 233, and the fifth barrier layer 232 is formed. A conductive material layer is formed within the sixth deposition tank and on the surface of the support material layer. Finally, the support material layer and the conductive material layer above the sixth barrier layer 234 are removed to form a fifth support portion 207 within the fifth deposition tank and a third conductive portion 208 within the sixth deposition tank. The third stacked structure 23 and the formed fifth support portion 207 and third conductive portion 208 constitute the metal interconnect layer 20.

[0088] The steps for manufacturing the fifth support portion 207 and the third conductive portion 208 are similar to those for the first conductive portion 202 and the first support portion 201. Therefore, for specific details, please refer to the description of the foregoing embodiments, and no further details will be provided here.

[0089] It should be noted that when forming the sixth deposition tank, the position and depth of the sixth deposition tank are controlled so that the second conductive portion 206 is exposed in the sixth deposition tank. Therefore, after the third conductive portion 208 is formed, the third conductive portion 208 is electrically connected to the second conductive portion 206, realizing the signal connection between adjacent metal interconnect layers 20. Of course, in some embodiments, the second conductive portion 206 may not be electrically connected to the first conductive portion 202.

[0090] S53: Remove the third sacrificial layer 233 to form the third cavity 231.

[0091] Specifically, an opening is first formed on the sixth barrier layer 234 using photolithography and etching processes to expose the third sacrificial layer 233. Then, the third sacrificial layer 233 is removed using etching or oxygen ion oxidation processes. For example, when the third sacrificial layer 233 is amorphous carbon, it is oxidized to gaseous carbon dioxide using oxygen ion oxidation to remove the third sacrificial layer 233, thereby forming the third cavity 231. Therefore, as... Figure 22 As shown, a stacked three-layer metal interconnect layer 20 is formed in a direction perpendicular to the semiconductor substrate 10, and air gaps exist between adjacent conductive structures of the three-layer metal interconnect layer 20.

[0092] Furthermore, a fourth stacked structure can be provided on the sixth barrier layer 234, and a support portion and a conductive portion can be provided within the fourth stacked structure. At the same time, a fourth cavity is formed on both sides of the conductive portion, thus ultimately forming a four-layer stacked metal interconnect layer. In other embodiments, five, six, or more layers of metal interconnect layers can also be provided.

[0093] The metal interconnects within each metal interconnect layer 20 (i.e., the first conductive part 202, the second conductive part 206, the third conductive part 208, etc.) are isolated from each other by air with a low dielectric constant, thereby reducing parasitic capacitance and improving the performance of the semiconductor device.

[0094] Combination Figure 20 and Figure 32 As shown, in one embodiment of the present invention, after the step of forming the first support portion 201 and at least two first conductive portions 202, and before the step of removing the first sacrificial layer 212 and forming the first cavity 214, the following steps are further included: S26: A third barrier layer 221, a second sacrificial layer 222, and a fourth barrier layer 223 are sequentially formed on the second barrier layer 213; After the fabrication of the first support portion 201 and the first conductive portion 202 is completed, a third barrier layer 221, a second sacrificial layer 222, and a fourth barrier layer 223 are sequentially formed on the surface of the second barrier layer 213. The third barrier layer 221, the second sacrificial layer 222, and the fourth barrier layer 223 form a second stacked structure 22, that is, the second stacked structure 22 is stacked on the first stacked structure 21. The materials and manufacturing processes of the third barrier layer 221, the second sacrificial layer 222, and the fourth barrier layer 223 are as described above.

[0095] S27: A third support portion 204 and at least two second conductive portions 206 are formed. The third support portion 204 penetrates the fourth barrier layer 223 and the second sacrificial layer 222. The second conductive portions 206 penetrate the fourth barrier layer 223, the second sacrificial layer 222 and the third barrier layer 221.

[0096] Specifically, a third deposition tank and a fourth deposition tank are formed on the second stacked structure 22 using photolithography and etching processes. A third support portion 204 is then formed in the third deposition tank, and a second conductive portion 206 is formed in the fourth deposition tank. The second conductive portion 206 is electrically connected to the first conductive portion 202. The second stacked structure 22, together with the second conductive portion 206 and the third support portion 204 disposed therein, forms a metal interconnect layer 20, thereby fabricating a two-layer stacked metal interconnect layer 20.

[0097] S28: A fifth barrier layer 232, a third sacrificial layer 233 and a sixth barrier layer 234 are sequentially formed on the fourth barrier layer 223; like Figure 20As shown, a fifth barrier layer 232, a third sacrificial layer 233, and a sixth barrier layer 234 are sequentially formed on the fourth barrier layer 223. The fifth barrier layer 232, the third sacrificial layer 233, and the sixth barrier layer 234 form a third stacked structure 23, which is stacked on top of the second stacked structure 22. The materials and manufacturing processes of the fifth barrier layer 232, the third sacrificial layer 233, and the sixth barrier layer 234 are as described above.

[0098] S29: A fifth support portion 207 and at least two third conductive portions 208 are formed. The fifth support portion 207 penetrates the sixth barrier layer 234 and the third barrier layer 221. The third conductive portions 208 penetrate the sixth barrier layer 234, the third sacrificial layer 233 and the fifth barrier layer 232. A fifth support portion 207 and a third conductive portion 208 are fabricated inside the third stacked structure 23. Specifically, a fifth deposition tank and a sixth deposition tank are formed in the third stacked structure 23 through photolithography and etching processes. Then, the fifth support portion 207 is formed in the fifth deposition tank, and the third conductive portion 208 is formed in the sixth deposition tank. The third conductive portion 208 is electrically connected to the second conductive portion 206. The third stacked structure 23, the fifth support portion 207, and the third conductive portion 208 form another metal interconnect layer 20. In other embodiments, the number of metal interconnect layers 20 can be four, five, or more.

[0099] In this embodiment, when fabricating the second stacked structure 22, the third support portion 204, and the second conductive portion 206, the underlying first sacrificial layer 212 has not yet been removed. The first sacrificial layer 212 serves to support the upper second stacked structure 22. Therefore, during subsequent etching or deposition, the underlying first stacked structure 21 has good mechanical support, is not easily deformed or damaged, and has a larger process window. Similarly, when fabricating the third stacked structure 23, the fifth support portion 207, and the third conductive portion 208, the underlying second sacrificial layer 222 and the first sacrificial layer 212 have not yet been removed. Therefore, the first sacrificial layer 212 and the second sacrificial layer 222 serve to support the upper third stacked structure 23.

[0100] Combination Figure 21 , Figure 22 as well as Figure 33 As shown, in one embodiment of the present invention, the step of forming the first cavity 214 includes: S301: Form a third opening 225 to expose the first sacrificial layer 212, the second sacrificial layer 222 and the third sacrificial layer 233; Specifically, such as Figure 21As shown, a photoresist layer is first coated on the uppermost third stacked structure 23, and then the photoresist layer is patterned to form an etching window exposing the third stacked structure 23. Then, an etching process is used to sequentially remove the third stacked structure 23, the second stacked structure 22, and the second barrier layer 213 exposed to the etching window to form a third opening 225. The third sacrificial layer 233, the second sacrificial layer 222, and the first sacrificial layer 212 are all exposed to the third opening 225. Alternatively, during the formation of the third opening 225, a portion of the first sacrificial layer 212 exposed to the etching window can also be etched away; that is, the etching of the third opening 225 stops within the first sacrificial layer 212.

[0101] S302: Remove the first sacrificial layer 212, the second sacrificial layer 222 and the third sacrificial layer 233 to form the first cavity 214, the second cavity 224 and the third cavity 231.

[0102] Specifically, such as Figure 22 As shown, using oxygen ion oxidation or etching processes, the first sacrificial layer 212, the second sacrificial layer 222, and the third sacrificial layer 233 are simultaneously removed through the third opening 225. For example, the materials of the first sacrificial layer 212, the second sacrificial layer 222, and the third sacrificial layer 233 are all amorphous carbon. Through the oxygen ion oxidation process, the amorphous carbon of the first sacrificial layer 212, the second sacrificial layer 222, and the third sacrificial layer 233 can be oxidized simultaneously to generate carbon dioxide gas, which is then discharged from the third opening 225. With the removal of the first sacrificial layer 212, the second sacrificial layer 222, and the third sacrificial layer 233, the space originally occupied by these materials simultaneously forms a first cavity 214 in the first stacked structure 21, a second cavity 224 in the second stacked structure 22, and a third cavity 231 in the third stacked structure 23.

[0103] The fabrication method of this embodiment enables the one-time molding of the cavity of the multilayer metal interconnect layer 20, which simplifies the process flow, improves the problem of needing to introduce additional photolithography and cleaning steps due to the layered fabrication of the cavity, and improves production efficiency.

[0104] Combination Figures 23 to 25 as well as Figure 34 As shown, in one embodiment of the present invention, after the step of forming the first cavity 214, the method further includes: S303: A fourth opening 226 is opened, and the first barrier layer 211 is exposed to the fourth opening 226; First, a photoresist layer is coated on top of the third stacked structure 23, and then etching windows are created on the photoresist layer using a photolithography process. For example... Figure 23As shown, the third stacked structure 23, the second stacked structure 22, and the first stacked structure 21 are then etched sequentially to form a fourth opening 226. This fourth opening 226 can be a rectangular or circular through-hole, with a cross-sectional dimension larger than that of the first deposition tank 215, the third deposition tank, and the fifth deposition tank, so that the size of the subsequently formed sixth support portion 209 is larger than that of the first support portion 201, the third support portion 204, and the fifth support portion 207.

[0105] The fourth opening 226 penetrates the third stacked structure 23, the second stacked structure 22 and the second barrier layer 213, and finally stops on or inside the first barrier layer 211.

[0106] S304: A third support material layer 27 is deposited on the surface of the sixth barrier layer 234, the surface of the first barrier layer 211, and inside the first cavity 214, the second cavity 224, and the third cavity 231; Specifically, such as Figure 24 As shown, a deposition process is used to deposit support material on the surface of the first barrier layer 211 exposed at the fourth opening 226 to form a third support material layer 27 covering the surface of the third stacked structure 23 and extending in a direction perpendicular to the semiconductor substrate 10 and toward the fourth opening 226.

[0107] S305: Remove the third support material layer 27 located on the sixth barrier layer 234 to form a sixth support portion 209 extending from the first barrier layer 211 toward the fourth opening 226.

[0108] Specifically, such as Figure 25 As shown, by planarization processes such as grinding or etching, the third support material layer 27 located on the third stacked structure 23 is removed, while the third support material layer 27 located inside the first stacked structure 21, the second stacked structure 22 and the third stacked structure 23 is retained, forming a sixth support portion 209 extending from the first barrier layer 211 toward the fourth opening 226.

[0109] The sixth support 209 connects the sixth barrier layer and the first barrier layer 211, and together with the fifth support 207, the third support 204 and the first support 201, it supports the multilayer stacked structure, thereby improving the mechanical reliability and long-term stability of the multilayer metal interconnect layer 20.

[0110] The present invention also proposes a semiconductor device.

[0111] Combination Figure 10As shown, the semiconductor device includes a semiconductor substrate 10 and a metal interconnect layer 20. The metal interconnect layer 20 is disposed on the semiconductor substrate 10 and includes a first barrier layer 211, a second barrier layer 213, a first support portion 201, and at least two first conductive portions 202. The first barrier layer 211 is disposed on the semiconductor substrate 10, and the second barrier layer 213 is disposed at a distance from the side of the first barrier layer 211 away from the semiconductor substrate 10. The two ends of the first support portion 201 are respectively connected to the first barrier layer 211 and the second barrier layer 213. A first cavity 214 is formed between the first barrier layer 211 and the second barrier layer 213. At least two first conductive portions 202 are disposed in the first cavity 214 and are spaced apart along a direction parallel to the semiconductor substrate 10. One end of the first conductive portion 202 is connected to the semiconductor substrate 10, and the other end is exposed on the side of the second barrier layer 213 away from the semiconductor substrate 10.

[0112] In this embodiment, the semiconductor substrate 10 may include a substrate and active devices disposed on the substrate. The substrate may be a single-crystal silicon substrate, a silicon-on-insulator (SOI) substrate, or other substrate materials suitable for semiconductor manufacturing. The active devices may include transistors, capacitors, etc. A metal interconnect layer 20, serving as a signal transmission channel, is disposed above these active devices to achieve electrical connections.

[0113] Specifically, the metal interconnect layer 20 includes a first barrier layer 211, a second barrier layer 213, a first support portion 201, and at least two first conductive portions 202. The first barrier layer 211 is disposed on the semiconductor substrate 10, and its material can be silicon carbonitride, silicon nitride, or silicon oxide, etc. The first barrier layer 211 serves as a stop layer for subsequent etching processes and also protects the underlying active devices. The second barrier layer 213 is disposed at a distance from the first barrier layer 211 on the side facing away from the semiconductor substrate 10. The second barrier layer 213 serves as a hard mask layer, and its material can be a hard mask material such as silicon nitride, used to protect the underlying materials in subsequent processes.

[0114] The first support portion 201 is connected to the first barrier layer 211 and the second barrier layer 213 at both ends. Specifically, the end of the first support portion 201 that connects to the first barrier layer 211 can be flush with the surface of the first barrier layer 211 or located inside the first barrier layer 211. The first support portion 201 can be cylindrical, polygonal, or other irregularly shaped, and its material can be a dielectric material with high mechanical strength such as silicon nitride or silicon oxide. The main function of the first support portion 201 is to act as a vertical "pillar" to provide stable mechanical support for the second barrier layer 213 and prevent the structure from collapsing during subsequent processes or use.

[0115] The number of first conductive portions 202 can be set according to the electrical connection points of the semiconductor substrate 10, and no further restrictions are imposed here. At least two first conductive portions 202 are arranged at intervals along a direction parallel to the semiconductor substrate 10. One end of the first conductive portion 202 penetrates the first barrier layer 211 and is connected to the semiconductor substrate 10, thereby realizing electrical connection with the active device of the semiconductor substrate 10; the other end is exposed on the side of the second barrier layer 213 away from the semiconductor substrate 10, so as to connect to the upper metal interconnect layer 20 or external circuit. The material of the first conductive portion 202 can be a low resistivity metal such as copper, tungsten, or aluminum.

[0116] Air replaces dielectric materials such as silicon dioxide between adjacent first conductive portions 202. Since the dielectric constant of air (approximately 1.0) is much lower than that of silicon dioxide (approximately 4), the parasitic capacitance between adjacent first conductive portions 202 can be reduced, thereby reducing RC delay in signal transmission and improving the performance of the semiconductor device. Simultaneously, by providing the first support portion 201, the problem of deteriorated structural stability caused by the cavity is solved or improved.

[0117] Combination Figure 10 As shown, in one embodiment of the present invention, the metal interconnect layer 20 includes a plurality of first support portions 201, which are spaced apart along a direction parallel to the semiconductor substrate 10.

[0118] In this embodiment, one first support portion 201 can be provided in the gap between every two adjacent first conductive portions 202, or two or more. By providing multiple spaced first support portions 201, a structure that provides multi-point support for the first barrier layer 211 and the second barrier layer 213 can be formed, which can more effectively disperse and bear the pressure from the second barrier layer 213 and other film layers above it, further improving the reliability and yield of the semiconductor device.

[0119] Combination Figure 17 As shown, in one embodiment of the present invention, the metal interconnect layer 20 further includes a second support portion 203, the two ends of which are respectively connected to the first barrier layer 211 and the second barrier layer 213, and the cross-sectional area of ​​the first support portion 201 is smaller than the cross-sectional area of ​​the second support portion 203.

[0120] In this embodiment, the cross-sectional area of ​​the first support portion 201 is smaller than that of the second support portion 203. Therefore, the second support portion 203 can provide stronger main support, ensuring the overall rigidity of the structure. The first support portion 201 occupies less space, thus reducing the parasitic capacitance between adjacent first conductive portions 202. For example, in areas where the first conductive portions 202 are densely packed, only the first support portion 201 can be fabricated to maintain a larger gap between adjacent first conductive portions 202, thereby reducing parasitic capacitance; in areas where the first conductive portions 202 are sparsely packed, the second support portion 203 can be fabricated to improve the support performance of the metal interconnect layer 20.

[0121] Combination Figure 19 , Figure 22 as well as Figure 25 As shown, in one embodiment of the present invention, the semiconductor device includes a multilayer metal interconnect layer 20, which is stacked sequentially on the semiconductor substrate 10.

[0122] In this embodiment, multiple metal interconnect layers 20 are sequentially stacked on the semiconductor substrate 10. Each metal interconnect layer 20 has a cavity structure, and the conductive portions in each metal interconnect layer 20 are disposed within the cavity structure, so that there is an air gap between adjacent conductive portions, thereby resulting in low parasitic capacitance between the conductive portions of each metal interconnect layer 20. Each metal interconnect layer 20 has a support portion to improve the stability of the cavity structure.

[0123] In some embodiments, adjacent metal interconnect layers 20 are electrically connected, and signals can be freely transmitted in a direction perpendicular to the semiconductor substrate 10 to electrically connect active devices in different regions of the semiconductor substrate 10, thereby forming complex logic or storage circuits.

[0124] Combination Figure 22 As shown, in one embodiment of the present invention, the semiconductor device includes three metal interconnect layers 20. The metal interconnect layers 20 disposed on the semiconductor substrate 10 include a first barrier layer 211, a second barrier layer 213, a first support portion 201, and at least two first conductive portions 202. The metal interconnect layers 20 in the middle layer include a third barrier layer 221, a fourth barrier layer 223, a third support portion 204, and at least two second conductive portions 206. The metal interconnect layers 20 away from the semiconductor substrate 10 include a fifth barrier layer 232, a sixth barrier layer 234, a fifth support portion 207, and at least two third conductive portions 208. A second cavity 224 is formed between the third barrier layer 221 and the fourth barrier layer 223. A third support portion 204 and at least two second conductive portions 206 are spaced apart in the second cavity 224. The two ends of the third support portion 204 are respectively connected to the third barrier layer 221 and the fourth barrier layer 223. A third cavity 231 is formed between the fifth barrier layer 232 and the sixth barrier layer 234. A fifth support portion 207 and at least two third conductive portions 208 are spaced apart in the third cavity 231. The two ends of the fifth support portion 207 are respectively connected to the fifth barrier layer 232 and the sixth barrier layer 234.

[0125] In this embodiment, three metal interconnect layers 20 are sequentially stacked on the surface of the semiconductor substrate 10. The first conductive portions 202 are spaced apart in the first cavity 214, the second conductive portions 206 are spaced apart in the second cavity 224, and the third conductive portions 208 are spaced apart in the third cavity 231. Therefore, there are air gaps between adjacent first conductive portions 202, adjacent second conductive portions 206, and adjacent third conductive portions 208, which reduces parasitic capacitance and improves the performance of the semiconductor device.

[0126] In some embodiments, the first conductive part 202, the second conductive part 206, and the third conductive part 208 are electrically connected to realize the interconnection and signal transmission of active devices inside the semiconductor substrate 10 in three-dimensional space. Of course, in other embodiments, the first conductive part 202, the second conductive part 206, and the third conductive part 208 may also be configured to be mutually insulated or electrically connected with a layer in between, that is, the first conductive part 202 is electrically connected to the third conductive part 208, but not electrically connected to the second conductive part 206.

[0127] Meanwhile, each metal interconnect layer 20 is provided with a support portion. The first support portion 201, the second support portion 203 and the third support portion 204 all play a supporting role for each film layer structure above it, thereby improving the structural stability of the semiconductor device.

[0128] Combination Figure 25 As shown, in one embodiment of the present invention, the semiconductor device further includes a sixth support portion 209, which penetrates the sixth barrier layer 234, the fifth barrier layer 232, the fourth barrier layer 223, the third barrier layer 221, and the second barrier layer 213. The two ends of the sixth support portion 209 are respectively connected to the first barrier layer 211 and the sixth barrier layer 234. The cross-sectional area of ​​the sixth support portion 209 along the direction parallel to the semiconductor substrate 10 is greater than the cross-sectional areas of the first support portion 201, the third support portion 204, and the fifth support portion 207.

[0129] In this embodiment, the sixth support portion 209 sequentially penetrates the sixth barrier layer 234, the fifth barrier layer 232, the fourth barrier layer 223, the third barrier layer 221, and the second barrier layer 213 along a direction perpendicular to the semiconductor substrate 10, thereby simultaneously connecting the sixth barrier layer 234, the fifth barrier layer 232, the fourth barrier layer 223, the third barrier layer 221, the second barrier layer 213, and the first barrier layer 211 to support the three-layer metal interconnect layer 20 structure. Furthermore, since the cross-sectional area of ​​the sixth support portion 209 is larger than that of the first support portion 201, the third support portion 204, and the fifth support portion 207, the sixth support portion 209 can provide a stronger support effect. Because of the larger cross-sectional area of ​​the sixth support portion 209, it can be placed in a relatively sparse area of ​​the conductive portions (e.g., the first conductive portion 202, the second conductive portion 206, and the third conductive portion 208) to reduce the impact on parasitic capacitance. The shape of the sixth support 209 can be cylindrical, polygonal, or other regular or irregular shapes.

[0130] Combination Figure 12 and Figure 19 As shown, in one embodiment of the present invention, the semiconductor device includes two metal interconnect layers 20, wherein the metal interconnect layer 20 disposed on the semiconductor substrate 10 includes a first barrier layer 211, a second barrier layer 213, a first support portion 201, and at least two first conductive portions 202; the metal interconnect layer 20 away from the semiconductor substrate 10 includes a third barrier layer 221, a fourth barrier layer 223, a third support portion 204, and at least two second conductive portions 206; the third barrier layer 221 and the fourth barrier layer 223 enclose a second cavity 224, the third support portion 204 and at least two second conductive portions 206 are all disposed in the second cavity 224, and the two ends of the third support portion 204 are respectively connected to the third barrier layer 221 and the fourth barrier layer 223.

[0131] Furthermore, in combination Figure 19 As shown, the semiconductor device further includes a second support portion 203 and a fourth support portion 205. The second support portion 203 is located in the first cavity 214 and is connected to the first barrier layer 211 and the second barrier layer 213 at its two ends, respectively. The fourth support portion 205 is located in the second cavity 224 and is connected to the third barrier layer 221 and the fourth barrier layer 223 at its two ends, respectively. The cross-sectional area of ​​the second support portion 203 along the direction parallel to the semiconductor substrate 10 is greater than the cross-sectional area of ​​the first support portion 201, and the cross-sectional area of ​​the fourth support portion 205 along the direction parallel to the semiconductor substrate 10 is greater than the cross-sectional area of ​​the third support portion 204.

[0132] The end of the second support portion 203 that connects to the first barrier layer 211 can be flush with the first barrier layer 211 or embedded within the first barrier layer 211. The shape of the second support portion 203 can be cylindrical, polygonal, or other regular or irregular shapes. The cross-sectional area of ​​the second support portion 203 is larger than that of the first support portion 201, thus providing a stronger support effect and improving the structural stability of the metal interconnect layer 20.

[0133] Similarly, the end of the fourth support portion 205 that connects to the third barrier layer 221 can be flush with the third barrier layer 221 or embedded within the third barrier layer 221. The shape of the fourth support portion 205 can be cylindrical, polygonal, or other regular or irregular shapes. The cross-sectional area of ​​the fourth support portion 205 is larger than that of the third support portion 204, thus providing a stronger support effect and improving the structural stability of the metal interconnect layer 20. In one embodiment of the present invention, the semiconductor device further includes a seventh support portion (not shown), which penetrates the fourth barrier layer 223, the third barrier layer 221, and the second barrier layer 213. The two ends of the seventh support portion are respectively connected to the first barrier layer 211 and the fourth barrier layer 223, wherein the cross-sectional area of ​​the sixth support portion 209 along the direction parallel to the semiconductor substrate 10 is larger than the cross-sectional areas of the first support portion 201 and the third support portion 204.

[0134] In this embodiment, the seventh support portion sequentially penetrates the fourth barrier layer 223, the third barrier layer 221, and the second barrier layer 213 along a direction perpendicular to the semiconductor substrate 10, thereby simultaneously connecting the fourth barrier layer 223, the third barrier layer 221, the second barrier layer 213, and the first barrier layer 211 to support the structure of the two metal interconnect layers 20. Since the cross-sectional area of ​​the seventh support portion is larger than that of the first support portion 201 and the third support portion 204, the seventh support portion can provide a stronger support effect. Due to the larger cross-sectional area of ​​the seventh support portion, it can be placed in a relatively sparse area of ​​the conductive portions (e.g., the first conductive portion 202 and the second conductive portion 206) to reduce the impact on parasitic capacitance. The shape of the seventh support portion can be cylindrical, polygonal, or other regular or irregular shapes. The above description is merely an exemplary embodiment of the present invention and does not limit the patent scope of the present invention. Any equivalent structural transformations made using the description and drawings of the present invention under the technical concept of the present invention, or direct / indirect applications in other related technical fields, are included within the patent protection scope of the present invention.

Claims

1. A method for fabricating a semiconductor device, characterized in that, The preparation method includes the following steps: A semiconductor substrate is provided, and a first barrier layer, a first sacrificial layer and a second barrier layer are sequentially formed on the semiconductor substrate; A first support portion and at least two first conductive portions are formed. The first support portion penetrates the second barrier layer and the first sacrificial layer. The first conductive portions penetrate the second barrier layer, the first sacrificial layer and the first barrier layer, and are electrically connected to the semiconductor substrate. The first sacrificial layer is removed to form the first cavity.

2. The preparation method according to claim 1, characterized in that, The step of forming the first support portion and at least two first conductive portions includes: Multiple first deposition trenches are formed that penetrate the second barrier layer and the first sacrificial layer; A first support material layer is formed inside the first deposition tank and on the second barrier layer; At least two second deposition trenches are formed that penetrate the first support material layer, the second barrier layer, the first sacrificial layer, and the first barrier layer; A conductive material layer is formed inside the second deposition tank and on the first support material layer; Remove the first support material layer and the conductive material layer located above the second barrier layer to form the first support portion located in the first deposition tank and the first conductive portion located in the second deposition tank.

3. The preparation method according to claim 1, characterized in that, The first sacrificial layer is made of amorphous carbon, and the step of removing the first sacrificial layer to form the first cavity includes: The second barrier layer is etched to form a first opening that exposes the first sacrificial layer; The first sacrificial layer is removed by oxidation to form the first cavity.

4. The preparation method according to claim 3, characterized in that, After the step of forming the first support portion and at least two first conductive portions, and before the step of forming the first cavity, the method further includes: The second barrier layer is etched to form a second opening that exposes the first sacrificial layer.

5. The preparation method according to claim 4, characterized in that, Following the step of forming the first cavity, the following is also included: A second support material layer is deposited on the surface of the second barrier layer and inside the first cavity to form a second support material layer; Remove the second support material layer located on the second barrier layer to form a second support portion extending from the first barrier layer toward the second opening.

6. The preparation method according to any one of claims 1 to 5, characterized in that, Following the step of forming the first cavity, the method further includes: A third barrier layer, a second sacrificial layer, and a fourth barrier layer are sequentially formed on the second barrier layer; A third support portion and at least two second conductive portions are formed, wherein the third support portion penetrates the fourth barrier layer and the second sacrificial layer, and the second conductive portions penetrate the fourth barrier layer, the second sacrificial layer and the third barrier layer; The second sacrificial layer is removed to form a second cavity.

7. The preparation method according to claim 6, characterized in that, The step of forming the second cavity includes: A window is formed in the fourth barrier layer to expose the second sacrificial layer; Remove the second sacrificial layer to form the second cavity; A fourth support portion is formed extending from the third blocking layer toward the window.

8. The preparation method according to claim 6, characterized in that, The step of forming the second cavity is followed by: A fifth barrier layer, a third sacrificial layer, and a sixth barrier layer are sequentially formed on the fourth barrier layer; A fifth support portion and at least two third conductive portions are formed, wherein the fifth support portion penetrates the sixth barrier layer and the third sacrificial layer, and the third conductive portions penetrate the sixth barrier layer, the third sacrificial layer and the fifth barrier layer; The third sacrificial layer is removed to form a third cavity.

9. The preparation method according to claim 1, characterized in that, After the step of forming the first support portion and at least two first conductive portions, and before the step of removing the first sacrificial layer and forming the first cavity, the method further includes: A third barrier layer, a second sacrificial layer, and a fourth barrier layer are sequentially formed on the second barrier layer; A third support portion and at least two second conductive portions are formed, wherein the third support portion penetrates the fourth barrier layer and the second sacrificial layer, and the second conductive portions penetrate the fourth barrier layer, the second sacrificial layer and the third barrier layer; A fifth barrier layer, a third sacrificial layer, and a sixth barrier layer are sequentially formed on the fourth barrier layer; A fifth support portion and at least two third conductive portions are formed, wherein the fifth support portion penetrates the sixth barrier layer and the third barrier layer, and the third conductive portions penetrate the sixth barrier layer, the third sacrificial layer and the fifth barrier layer.

10. The preparation method according to claim 9, characterized in that, The step of forming the first cavity includes: A third opening is formed to expose the first sacrificial layer, the second sacrificial layer, and the third sacrificial layer; The first sacrificial layer, the second sacrificial layer, and the third sacrificial layer are removed to form the first cavity, the second cavity, and the third cavity.

11. The preparation method according to claim 10, characterized in that, The step of forming the first cavity, the second cavity, and the third cavity is followed by: A fourth opening is made, exposing the first barrier layer to the fourth opening; A third support material layer is deposited and formed on the surface of the sixth barrier layer, the surface of the first barrier layer, and inside the first cavity, the second cavity, and the third cavity; Remove the third support material layer located on the sixth barrier layer to form a sixth support portion extending from the first barrier layer toward the fourth opening.

12. A semiconductor device, characterized in that, The semiconductor device includes: Semiconductor substrate; A metal interconnect layer disposed on the semiconductor substrate, the metal interconnect layer including a first barrier layer, a second barrier layer, a first support portion and at least two first conductive portions; The first barrier layer is disposed on the semiconductor substrate, and the second barrier layer is disposed at a distance from the first barrier layer on the side of the semiconductor substrate away from the semiconductor substrate. The two ends of the first support portion are respectively connected to the first barrier layer and the second barrier layer. A first cavity is formed between the first barrier layer and the second barrier layer. At least two first conductive portions are disposed in the first cavity and are spaced apart along a direction parallel to the semiconductor substrate. One end of the first conductive portion is connected to the semiconductor substrate, and the other end is exposed on the side of the second barrier layer away from the semiconductor substrate.

13. The semiconductor device as claimed in claim 12, characterized in that, The metal interconnect layer further includes a second support portion, the two ends of which are respectively connected to the first barrier layer and the second barrier layer, and the cross-sectional area of ​​the first support portion is smaller than the cross-sectional area of ​​the second support portion.

14. The semiconductor device as claimed in claim 12 or 13, characterized in that, The semiconductor device includes multiple metal interconnect layers, which are stacked sequentially on the semiconductor substrate.

15. The semiconductor device as claimed in claim 12, characterized in that, The semiconductor device includes two metal interconnect layers. The metal interconnect layer disposed on the semiconductor substrate includes a first barrier layer, a second barrier layer, a first support portion, and at least two first conductive portions. The metal interconnect layer away from the semiconductor substrate includes a third barrier layer, a fourth barrier layer, a third support portion, and at least two second conductive portions. A second cavity is formed between the third barrier layer and the fourth barrier layer. The third support portion and at least two second conductive portions are disposed in the second cavity. The two ends of the third support portion are respectively connected to the third barrier layer and the fourth barrier layer.

16. The semiconductor device as claimed in claim 15, characterized in that, The semiconductor device further includes a seventh support portion, which penetrates the fourth barrier layer, the third barrier layer, and the second barrier layer in a direction perpendicular to the semiconductor substrate, and the two ends of the seventh support portion are respectively connected to the first barrier layer and the fourth barrier layer; The cross-sectional dimension of the seventh support portion along the direction parallel to the semiconductor substrate is larger than the cross-sectional dimensions of the first support portion and the third support portion.

17. The semiconductor device as claimed in claim 15, characterized in that, The semiconductor device further includes a second support portion and a fourth support portion; the second support portion is located in the first cavity, and the two ends of the first cavity are respectively connected to the first barrier layer and the second barrier layer; the fourth support portion is located in the second cavity, and the two ends of the fourth support portion are respectively connected to the third barrier layer and the fourth barrier layer; the cross-sectional area of ​​the second support portion is larger than the cross-sectional area of ​​the first support portion, and the cross-sectional area of ​​the fourth support portion is larger than the cross-sectional area of ​​the third support portion.

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