Die backside profile of semiconductor device

Abstract

Embodiments of the present disclosure include apparatus and methods of forming a backside profile in a semiconductor element that includes die-to-wafer bonding. The method generally includes: removing a portion of a substrate layer included in a plurality of dies arranged on and bonding an insulating layer included in a support structure, where the plurality of dies define a plurality of channels between adjacent dies; and forming corner features on a plurality of corners of the substrate layer adjacent the plurality of channels. The use of backside profiles as described herein can mitigate downstream process risks associated with residues captured in the channels and provide stress relief for the semiconductor elements.

Description

Technical Field

[0001] The embodiments described herein generally relate to the manufacture of semiconductor devices. More specifically, the embodiments disclosed herein relate to semiconductor devices having die-to-wafer bonding and methods for forming the same, such semiconductor devices including a back-side profile. Background Technology

[0002] Performing die-to-wafer bonding (e.g., on a semiconductor chip) results in gaps between adjacent dies on the wafer. These gaps are called inter-die spacing. As semiconductor device technology advances, the length of inter-die spacing continues to decrease. Current die-to-wafer bonding typically results in inter-die spacing of 100 micrometers (µm) or less. However, as inter-die spacing decreases, the risk of residues trapped within it increases. Trapped residues can cause various problems during semiconductor device manufacturing, including challenges and risks in downstream processes.

[0003] Therefore, there is a need in the field for various methods and devices to solve the above problems. Summary of the Invention

[0004] To achieve the foregoing and related objectives, one or more aspects include the features fully described below and specifically pointed out in the claims. The following description and drawings set forth certain illustrative features of one or more aspects in detail. However, these features only illustrate a few of the various ways in which the principles of each aspect can be employed.

[0005] The embodiments disclosed in this application provide a method. The method generally includes removing a portion of a substrate layer comprised of a plurality of grains. The plurality of grains are arranged on and bonded to an insulating layer included in a support structure. The plurality of grains define a plurality of channels between adjacent grains. The method also generally includes forming corner features at multiple corners of the substrate layer adjacent to the plurality of channels.

[0006] The embodiments disclosed in this application provide an interconnect structure. The interconnect structure generally includes a support structure comprising an insulating layer and a plurality of grains arranged on and bonded to the insulating layer. The plurality of grains include a substrate layer, and the plurality of grains define a plurality of channels between adjacent grains. The interconnect structure also generally includes corner features included at multiple corners of the substrate layer adjacent to the plurality of channels.

[0007] This invention provides an interconnect structure. The interconnect structure generally includes: a support structure including an insulating layer; and a plurality of grains arranged on and bonded to the insulating layer. The plurality of grains include a substrate layer. The plurality of grains also define a plurality of channels between adjacent grains, and at least one sidewall of the plurality of grains is tapered.

[0008] The embodiments disclosed herein provide a semiconductor device having die-to-wafer bonding, including a back-side profile as described herein. Attached Figure Description

[0009] To gain a detailed understanding of the aforementioned features of the embodiments of this disclosure, a more specific description of the disclosure briefly summarized above can be obtained by referring to the embodiments, some of which are illustrated in the accompanying drawings. However, it should be noted that the drawings only illustrate typical embodiments of this disclosure and should not be considered as limiting its scope, as this disclosure allows for other equally effective embodiments.

[0010] Figure 1A A top view of a portion of a semiconductor device having die-to-wafer bonding is shown, in which embodiments of the present disclosure may be implemented.

[0011] Figure 1B Show along Figure 1A The cross-sectional view taken from section line 1B in the figure shows the implementation method of the content disclosed in this case.

[0012] Figure 2 This is a flowchart of a method for forming a back-side profile on a semiconductor device according to one or more embodiments described herein, the semiconductor device including die-to-wafer bonding.

[0013] Figure 3A , 3B The images 3C and 3D show schematic side cross-sectional views of a portion of a semiconductor element during its formation according to one or more embodiments described herein.

[0014] For ease of understanding, the same reference numerals are used as much as possible to denote the same elements in the figures. It is conceivable that elements disclosed in one embodiment may be advantageously used in other embodiments without specific description. Detailed Implementation

[0015] The embodiments disclosed herein generally relate to semiconductor devices with die-to-wafer bonding and methods for forming the same, such semiconductor devices including a back-side profile. The semiconductor device may include a plurality of dies bonded to a support structure including a wafer. The back-side profile described herein may be formed on the back side of one or more bonded dies included in the semiconductor device. The back-side profile may include one or both of the following: a plurality of corner features formed in the die and a plurality of tapered sidewalls formed on the die.

[0016] The back profile formed using the embodiments and techniques disclosed in this case can alleviate stress along the grain edges and reduce cracks in the insulating layers contained in the grains and support structures during planarization.

[0017] Example of die-to-wafer bonding of semiconductor devices

[0018] Figure 1A A top view of a portion of a semiconductor device 100 having grain-to-wafer bonding is shown, in which embodiments of the present disclosure may be implemented. Figure 1B It shows along Figure 1A The cross-sectional view taken by section line 1B in the document shows that the embodiments disclosed in this case can be implemented. Therefore, for clarity, in this document... Figure 1A and 1B Let's describe them together. Figure 1A and 1B It includes an XYZ coordinate system to show the direction of the bonding from the die to the wafer of the semiconductor element 100.

[0019] The die-to-wafer bonding of the semiconductor element 100 includes a plurality of dies 102 (e.g., semiconductor chips or blocks of semiconductor material on which a given functional circuit is fabricated). The height H of each die 102 may be between 30 micrometers (µm) and 150 µm. Each die 102 is arranged in a pattern on a support structure 106. Figure 1A and 1B As shown, the pattern of the grains 102 results in channels 104 (e.g., gaps) between adjacent grains 102. These channels 104 may be referred to as inter-grain spacing. In some embodiments, the length L1 of the channel 104 may be between 50 µm and 4 millimeters (mm). The length L1 of the channel may be measured from the corner of one grain 102 to the corner of another adjacent grain 102, as shown. In some cases, the length L1 of the channel 104 may be 100 µm or less. Each channel 104 may have the same length or different lengths.

[0020] As the inter-grain spacing (e.g., the length L1 of channel 104) decreases, the risk of residues trapped in the inter-grain spacing increases. Figure 1B A portion of the trapped residue 108 disposed in channel 104 is shown. The trapped residue 108 can cause several problems during semiconductor device manufacturing, including challenges and risks in downstream processes. In some cases, when processing a semiconductor device 100 with die-to-wafer bonding, oxide may deposit in the inter-die spacing, and the trapped residue 108 may inhibit and negatively affect oxide deposition. In some cases, oxide peeling may occur if the trapped residue is not removed.

[0021] Embodiments of the disclosure herein may involve forming a backside profile on the backside of a plurality of bonded dies included in a semiconductor device (e.g., semiconductor device 100). The backside profile may include or be implemented as at least one of a plurality of corner features formed in the die 102 or a plurality of tapered sidewalls formed on the die 102, as will be described herein. Using a backside profile reduces the occurrence of problematic trapped residue 108 in the channel 104 between adjacent dies 102. This mitigates downstream process risks and provides stress relief for the semiconductor device 100, particularly at the interface between the backside of the die 102 and the insulating layer. For example, reducing the presence of trapped residue 108 can release stress along the edges (e.g., sidewalls) of the die 102 and can reduce cracking in the insulating (e.g., dielectric) layer included in the die and support structure 106 during planarization.

[0022] Grain back profile formation and structure

[0023] Figure 2 This is a flowchart illustrating a method 200 for forming a back-side profile on a semiconductor element according to one or more embodiments described herein, the semiconductor element comprising die-to-wafer bonding. Figure 3A , 3B 3C and 3D illustrate one or more embodiments according to the description herein. Figure 2 A schematic side cross-sectional view of portion 300 of one or more semiconductor elements during operation is shown. Therefore, for clarity, in this document... Figure 2 and Figure 3A , 3B 3C and 3D are described together. A portion 300 of the semiconductor element can be considered or implemented as an interconnect structure included within the semiconductor element. It is assumed that portion 300 of the semiconductor element includes a plurality of previously manufactured dies (e.g., die 102) and a support structure (e.g., support structure 106). A back-side profile can be formed on the die 102 of the semiconductor element. Furthermore, Figure 3A The image shows the grain 102 and the support structure 106 before the grain 102 is bonded to the support structure 106. Although Figures 3A to 3D Only two grains 102 are depicted, but any number of grains 102 can exist. Figures 3A to 3D Includes an XYZ coordinate system to show the orientation of section 300 of the semiconductor element.

[0024] like Figure 3AAs shown, the die 102 may include a substrate layer 302, one or more insulating layers 304a, 304b, and one or more local interconnects 306a, 306b. One or more insulating layers 304a, 304b may be coupled to the substrate layer 302 and disposed beneath the substrate layer 302. One or more local interconnects 306a, 306b may be disposed within the insulating layers 304a, 304b. Although Figures 3A to 3D Two insulating layers, 304a and 304b, are shown, but any number of insulating layers can be used.

[0025] As used herein, the term "substrate layer" can refer to a layer of material that serves as the basis for subsequent processing operations and includes the surface to be cleaned. Substrate layer 302 can be a silicon-based material or, if necessary, any suitable insulating or conductive material. Substrate layer 302 can include materials such as crystalline silicon (e.g., Si). <100> or Si <111> Substrate layer 302 may be implemented as a wafer, including silicon oxide, strained silicon, silicon germanium, doped or undoped polycrystalline silicon, doped or undoped silicon wafers and patterned or unpatterned wafers, silicon-on-insulator (SOI), carbon-doped silicon oxide, silicon nitride, doped silicon, germanium, gallium arsenide, glass, or sapphire.

[0026] In some embodiments, substrate layer 302 may be or be implemented as, for example, a doped or undoped silicon substrate, a III-V compound substrate, a silicon-germanium (SiGe) substrate, an epitaxial substrate, a silicon-on-insulator (SOI) substrate, a display substrate (e.g., a liquid crystal display (LCD), a plasma display, an electroluminescent (EL) lamp display), a light-emitting diode (LED) substrate, a solar cell array, a solar panel, etc.

[0027] The substrate layer 302 is not limited to any particular size or shape. The substrate layer 302 can be a circular wafer with a diameter of 200 mm, 300 mm, or other diameters (e.g., 450 mm). The substrate layer 302 can also be any polygonal, square, rectangular, curved, or other non-circular workpiece, such as a polygonal glass substrate used to manufacture a flat panel display.

[0028] One or more insulating layers 304a, 304b may include or be implemented as one or more dielectric layers. The dielectric layers may include at least one of silicon nitride (Si3N4), silicon carbonitride (SiCN), silicon dioxide (SiO2), silicon carbide (SiC), aluminum oxide (Al2O3), aluminum nitride (AlN), etc. One or more local interconnects 306a, 306b may include or be implemented as at least one of damascene structures, through-holes, trenches, solder pads, etc. Local interconnects 306a, 306b may include chromium, titanium, gold, silver, copper, aluminum, indium tin oxide (ITO), combinations of the above, or other suitable conductive materials. Although... Figure 3AThe portion 300 of the semiconductor element shown has two local interconnects 306a, 306b, but may include any number of local interconnects.

[0029] like Figure 3A As shown, the support structure 106 may include a substrate layer 312, one or more insulating layers 314a, 314b, and one or more local interconnects 316a, 316b, 316c, 316d, 316e, 316f. One or more insulating layers 314a, 314b may be coupled to the substrate layer 312 and disposed above the substrate layer 312, such as... Figure 3A As shown. One or more local interconnects 316a, 316b, 316c, 316d, 316e, 316f may be disposed in insulating layers 314a, 314b. Although Figure 3A The portion 300 shown has six local interconnects 316a, 316b, 316c, 316d, 316e, and 316f, but any number of local interconnects can be used. Furthermore, even... Figure 3A The portion 300 of the semiconductor element shown has two insulating layers 314a, 314b, and may also include any number of insulating layers. As shown, some local interconnects (e.g., local interconnects 316c, 316d) may be implemented in a different manner than other local interconnects (e.g., local interconnects 316a, 316b, 316e, 316f), and may not extend to the entire height of the insulating layers 314a, 314b, as shown.

[0030] The substrate layer 312 of the support structure 106 may be implemented in the same or similar manner as the substrate layer 302 of the die 102 described above. One or more insulating layers 314a, 314b of the support structure 106 may be implemented in the same or similar manner as one or more insulating layers 304a, 304b of the die 102 described above. One or more local interconnects 316a, 316b of the support structure 106 may be implemented in the same or similar manner as one or more local interconnects 306a, 306b of the die 102 described above.

[0031] Die-to-wafer bonding can be performed on die 102, such that the die is bonded to the support structure 106, as... Figure 3B As shown. In some embodiments, the bottom insulating layer 304a of the die 102 may be bonded to the top insulating layer 314a of the support structure 106, such as... Figure 3B As shown. Furthermore, one or more local interconnects 306a, 306b of the die 102 may be bonded to adjacent local interconnects 316a, 316b, 316e, 316f of the support structure 106, as shown. Figure 3B As shown.

[0032] Multiple connections (e.g., connections configured to transmit power) can be formed between adjacent interconnects of local interconnects 306a, 306b and local interconnects 316a, 316b, 316e, 316f. Multiple connections between local interconnects 306a, 306b of die 102 and local interconnects 316a, 316b, 316c, 316d, 316e, 316f of support structure 106 can form multiple global interconnects 326a, 326b, 326c, 326d, such as... Figure 3B As shown. When the grain 102 is bonded to the support structure 106, the local interconnects 316c and 316d may not be configured to form the overall interconnect, as shown in the figure. Figure 3B As shown.

[0033] As described above, each bonded grain 102 can be arranged in a pattern on the support structure 106. For example... Figure 3B As shown (and above) Figure 1A and 1B As shown), the pattern of grain 102 results in channels 104 (e.g., gaps) between adjacent grains 102. Also as mentioned above, the length L1 of the channel 104 can be between 50 µm and 4 mm. The channel length L1 can be measured from the corner of one grain 102 to the corner of another adjacent grain 102, as shown. In some cases, the length L1 of the channel 104 can be 100 µm or less. The channels 104 can each have the same length or different lengths. Although... Figures 3A to 3D Only two grains 102 and one channel 104 are depicted, but any number of grains 102 and associated channels 104 can exist.

[0034] Method 200 includes removing a portion of a substrate layer 302 included in a plurality of grains 102 in activity 202, such as Figure 3B As shown. The removed portion of substrate layer 302 may be the top of substrate layer 302, and this removal is caused by an etching process (e.g., a first reactive ion etching (RIE) process described below), which is performed by an etching tool (not shown) disposed above substrate layer 302 (e.g., in the Z direction). As described above, a plurality of dies 102 may be arranged on and bonded to the top insulating layer 314a of support structure 106. Also as described above, the plurality of dies 102 may define a plurality of channels 104 between adjacent dies 102.

[0035] In some embodiments, removing a portion of the substrate layer 302 included in the plurality of dies 102 (e.g., activity 202) includes etching a portion of the substrate layer 302 by a first RIE process. The selectivity ratio of the first RIE process between the substrate layer 302 and the insulating layer 314a is at least 100:1. In some cases, the selectivity ratio of the first RIE process between the substrate layer 302 and the insulating layer 314a can be configured such that the first RIE process is primarily a vertical etching of the substrate layer 302, while etching a smaller portion of the insulating layer 314a.

[0036] The first RIE process may include the use of at least one of sulfur hexafluoride (SF6), fluoromethane (CH3F), or octafluorocyclobutane (C4F8). The first RIE process may include the use of a radio frequency between 400 kHz and 14 MHz, a radio frequency power of less than 7 kW, a flow rate of less than 2000 standard cubic centimeters per minute (sccm), and a pressure between 20 mT and 80 mT, for a duration of less than 10 minutes.

[0037] In some embodiments, the first RIE process can be configured to have high silicon-to-oxide selectivity. Polymer sidewall passivation can be used to prevent lateral etching of the sidewalls 340a, 340b and the insulating layer 314a.

[0038] The method 200 includes: forming corner features 330 at multiple corners of the substrate layer 302 adjacent to the plurality of channels 104 in activity 204, such as Figure 3C and 3D As shown. Although Figure 3C and Figure 3D Four corner features 330 are shown, but any number of corner features 330 can be formed at any number of corners of the substrate layer 302 of any number of grains 102. Figure 3C The corner feature 330 shown is implemented as a chamfer, while Figure 3D The corner feature 330 shown is implemented as a rounded corner (e.g., an edge).

[0039] In some implementations, when the corner feature 330 formed in activity 204 is a chamfer, the angle A2 of the corner feature 330 can be between 5 degrees and 45 degrees, such as... Figure 3C As shown. The angle A2 of each corner feature 330 can be the same or different. In some embodiments, when the corner feature 330 formed in activity 204 is a rounded corner, the radius R of the corner feature 330 can be between 5 μm and 20 μm, such as... Figure 3D As shown. The radius R of the corner feature 330 can be the same or different.

[0040] In some embodiments, at least one sidewall 340a, 340b of at least one of the plurality of grains 102 may be tapered, such as Figure 3C and 3D As shown. Tapered sidewalls 340a, 340b can be formed during an etching process (e.g., a second RIE process described below) performed during activity 204. The angle A1 of at least one tapered sidewall 340a, 340b can be between 60 degrees and 85 degrees. Tapered sidewalls 340a, 340b can contrast with straight sidewalls, which can be used in certain portions 300 of the semiconductor device, including die-to-wafer bonding.

[0041] In some embodiments, the distance between the sidewalls 340a, 340b of the plurality of dies 102 and all interconnects 326a, 326b, 326c, 326d included in the plurality of dies 102 and the support structure 106 can be at least 10µm. For example, the minimum distance between any portion of the tapered sidewalls 340a, 340b can be at least 10µm from all interconnects 326a, 326b, 326c, 326d included in the plurality of dies 102 and the support structure 106. In some embodiments, a corner feature 330 can be formed such that the distance D between the sidewalls 340a, 340b and the far edge of the corner feature 330 is configured to be at least 10µm. In some cases, the distance D can be less than the distance between the sidewalls 340a, 340b and all interconnects 326a, 326b, 326c, 326d of the plurality of dies, such as... Figure 3C and 3D As shown. In other cases, the distance D (e.g., the distance D between sidewalls 340a, 340b and the far edge of corner feature 330) can be the same as the distance between sidewalls 340a, 340b and all interconnects 326a, 326b, 326c, 326d of the multiple grains. The distance D can be referred to as a guard ring and can be configured to prevent etching of all interconnects 326a, 326b, 326c, 326d. The corner feature 330 can be arranged entirely between sidewalls 340a, 340b and all interconnects 326a, 326b, 326c, 326d.

[0042] In some embodiments, the length L2 of the plurality of channels 104 from the top of the corner feature 330 on one of the plurality of grains 102 to the top of the corner feature 330 on another adjacent grain 102 is between 50µm and 4mm, such as Figure 3C and 3DAs shown. In some cases, the length L2 of the channel can be measured from any portion of the sidewall 340a of the grain 102 to a corresponding portion of the sidewall 340b of the grain 102. In some cases, the length L2 of the channel 104 can be 100 µm or less. The length of each channel 104 can be the same or different.

[0043] In some embodiments, forming corner features 330 at multiple corners includes etching the corner features 330 using a second RIE process. The second RIE process may include using at least one of SF6, oxygen (O2), trifluoromethane (CHF3), C4F8, or CH3F. The second RIE process may include using a radio frequency between 400 kHz and 14 MHz, an RF power of less than 7 kW, a flow rate of less than 2000 sccm, and a pressure between 20 mT and 250 mT for a duration of less than 5 minutes. At least one of the first and second RIE processes may be implemented as a dry etching process.

[0044] In some implementations, the second RIE process can be configured to use sidewall passivation (e.g., sidewalls 340a, 340b) and vertical silicon etching to create Figure 3C and 3D The corner feature 330 and tapered sidewalls 340a, 340b are shown. The ratio of silicon etchant to various carbon passivators can be configured to adjust the profile angle of the silicon sidewalls of the bonded grain 102 (e.g., angle A1). Polymer gases (e.g., CHF3, C4F8) can more frequently promote the formation of polyfluorocarbon compounds. O2 can be configured to control the polymer to form the corner feature 330. Ar+ ions can provide physical ion sputtering.

[0045] In some implementations, forming a corner feature 330 in a portion 300 of a semiconductor element may involve performing multiple processes. These processes may include performing isotropic etching, performing thin polymer deposition, performing partially vertical etching, and performing other isotropic etching and stripping.

[0046] Performing isotropic etching may include removing a portion of the substrate layer 302 included in a plurality of grains 102 (e.g., activity 202), such as Figure 3BAs shown. After a portion of the substrate layer 302 has been removed, a thin polymer can be deposited on the portion 300 of the semiconductor element, such that the substrate layer 302 and the insulating layer 314a are covered by the deposited polymer. In some cases, tapered sidewalls 340a and 340b may have been formed during the deposition of the thin polymer. After the thin polymer deposition, a partial vertical etching can be performed on the portion 300 of the semiconductor element, such that at least a portion of the deposited polymer on the substrate layer 302 and the tapered sidewalls 340a and 340b is removed. In some cases, after the partial vertical etching, a portion of the polymer may still remain above at least several portions of the tapered sidewalls 340a and 340b and the insulating layer 314a. Isotropic etching and stripping can be performed after the partial vertical etching, such that corner features 330 are formed at several corners of the substrate layer 302 adjacent to the plurality of channels 104, and the remaining polymer is stripped from the portion 300 of the semiconductor element, as shown. Figure 3C and 3D As shown.

[0047] In some embodiments, the taper of sidewalls 340a and 340b can be formed by a second RIE process. For example, during the etching of corner feature 330, the top of sidewalls 340a and 340b may be etched faster than the bottom of sidewalls 340a and 340b, thereby forming... Figure 3C and 3D The tapered sidewalls 340a and 340b are shown.

[0048] Method 200 may optionally include planarizing substrate layer 302 via a chemical mechanical planarization (CMP) process in activity 206, such as... Figure 3D As shown above, after activity 206, the radius R of the corner feature 330 can be between 5µm and 20µm, regardless of whether the corner feature 330 is implemented as a chamfer or a fillet in activity 204. For example, when the corner feature 330 is implemented as a chamfer (e.g., as... Figure 3C As shown), corner feature 330 may look similar to [the previous one] after planarization (e.g., activity 206). Figure 3D The rounded corners are similar or identical. That is, the shape of the corner feature 330 can be substantially circular. In these embodiments, the radius R of the corner feature 330 can be between 5µm and 20µm, such as... Figure 3D As shown.

[0049] Method 200 reduces the occurrence of trap residues (e.g., trap residue 108) described herein and alleviates stress along the sidewalls 340a, 340b of grain 102. Furthermore, Method 200 reduces the formation of cracks in the insulating layers 304a, 304b, 314a, 314b included in grain 102 and support structure 106 during activity 206 and during other processes (e.g., gap-filling and planarization) used during the formation of a semiconductor device including grain-to-wafer bonding. Method 200 also mitigates defects in the semiconductor device portion 300 having grain-to-wafer bonding.

[0050] Additional considerations

[0051] Details have been illustrated in the foregoing description to facilitate understanding of the disclosed objectives. However, those skilled in the art will recognize that the disclosed embodiments are exemplary and not exhaustive of all possible embodiments. Therefore, it should be understood that references to the examples are not intended to limit the scope of this disclosure. Any changes and further modifications to the described apparatus, instruments, and methods, as well as any further applications of the principles of this disclosure, are fully considered, as would normally occur to those skilled in the art to which this disclosure pertains. Specifically, it is fully considered that features, elements, and / or steps described for one embodiment may be combined with features, components, and / or steps described for other embodiments of this disclosure. As used herein, the term “about” may refer to a variation of + / - 10% from a nominal value. It should be understood that such variation may be included in any values ​​provided herein.

[0052] As used herein, the phrase referring to a list of “at least one” items means any combination of these items, including a single member. For example, “at least one: a, b, or c” is intended to cover: a, b, c, ab, ac, bc, and abc, as well as any combination of multiples of the same element (e.g., aa, aaa, aab, aac, abb, acc, bb, bbb, bbc, cc, and ccc, or any other order of a, b, and c).

[0053] As used in this article, the vocabulary used to describe a range between two values ​​includes the values ​​at the endpoints of that range. For example, “values ​​between 1 and 10” is intended to cover the range of values ​​from 1 to 10, including both 1 and 10.

[0054] Although the foregoing describes the implementation of the disclosure in this case, other and further implementations of the disclosure can be designed without departing from the basic scope of the disclosure, and the scope of the disclosure is defined by the appended claims.

Claims

1. A method, the method comprising: Remove a portion of a substrate layer comprising a plurality of grains arranged on and bonded to an insulating layer included in a support structure; wherein the plurality of grains define a plurality of channels between adjacent grains; and Corner features are formed at multiple corners of the substrate layer adjacent to the plurality of channels.

2. The method of claim 1, wherein at least one sidewall of at least one of the plurality of grains is tapered, and the angle of the at least one tapered sidewall is between 60 degrees and 85 degrees.

3. The method of claim 1, wherein the radius of the corner feature is between 5 micrometers (µm) and 20 µm.

4. The method of claim 1, wherein the angle of the corner feature is between 5 degrees and 45 degrees.

5. The method of claim 1, wherein the distance between the sidewalls of the plurality of grains and the global interconnects included in the plurality of grains and the support structure is at least 10 micrometers (µm), and wherein the corner feature is disposed between the sidewalls and the global interconnects.

6. The method of claim 1, wherein the length of the plurality of channels from the top of the corner feature on the first grain of the plurality of grains to the top of the corner feature on the second grain of the plurality of grains is between 50 micrometers (µm) and 4 millimeters (mm).

7. The method of claim 1, further comprising: The substrate layer is planarized using a chemical mechanical planarization process.

8. The method of claim 1, wherein forming the corner features at the plurality of corners comprises: The corner feature is etched using a first reactive ion etching (RIE) process.

9. The method of claim 8, wherein the first RIE process comprises: Use at least one of sulfur hexafluoride (SF6), oxygen (O2), trifluoromethane (CHF3), octafluorocyclobutane (C4F8), or fluorinated methane (CH3F).

10. The method of claim 9, wherein the first RIE process comprises using a radio frequency between 400 kHz and 14 MHz, an RF power of less than 7 kW, a flow rate of less than 2000 standard cubic centimeters per minute (sccm), and a pressure between 20 mT and 250 mT for a duration of less than 5 minutes.

11. The method of claim 10, wherein removing the portion of the substrate layer included in the plurality of grains comprises: The portion of the substrate layer is etched using a second RIE process.

12. The method of claim 11, wherein the selectivity ratio of the second RIE process between the substrate layer and the insulating layer is at least 100:

1.

13. The method of claim 12, wherein the second RIE process comprises: Use at least one of SF6, CH3F, or C4F8.

14. The method of claim 13, wherein the second RIE process comprises using a radio frequency between 400 kHz and 14 MHz, an RF power of less than 7 kW, a flow rate of less than 2000 standard cubic centimeters per minute (sccm), and a pressure between 20 mT and 80 mT for a duration of less than 10 minutes.

15. An interconnect structure, the interconnect structure comprising: The support structure includes an insulating layer; A plurality of grains are arranged on and bonded to the insulating layer, wherein the plurality of grains include a substrate layer, and wherein the plurality of grains define a plurality of channels between adjacent grains; as well as Corner features, which are included at multiple corners of the substrate layer and adjacent to the multiple channels.

16. The interconnect structure of claim 15, wherein at least one sidewall of at least one of the plurality of grains is tapered, and wherein the angle of the at least one tapered sidewall is between 60 degrees and 85 degrees.

17. The interconnect structure of claim 15, wherein the radius of the corner feature is between 5 micrometers (µm) and 20 µm.

18. The interconnect structure of claim 15, wherein the angle of the corner feature is between 5 degrees and 45 degrees.

19. An interconnect structure, the interconnect structure comprising: The support structure includes an insulating layer; as well as A plurality of grains are arranged on and bonded to the insulating layer, wherein the plurality of grains include a substrate layer, wherein the plurality of grains define a plurality of channels between adjacent grains, and wherein at least one sidewall of at least one of the plurality of grains is tapered.

20. The interconnect structure of claim 15, wherein the interconnect structure further comprises: Corner features, which are included at multiple corners of the substrate layer and adjacent to the multiple channels.

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