Manufacturing method of semiconductor device

Abstract

The present invention addresses the problem of providing a method for manufacturing a semiconductor device in which Si atoms can be reduced or removed at the interface between a substrate or a semiconductor layer comprising InP or InGaAsP and another semiconductor layer grown thereon. This manufacturing method is a method for manufacturing a semiconductor device (1) provided with a first semiconductor (2) comprising InP or InGaAsP, and a second semiconductor (3) provided on the first semiconductor (2). The manufacturing method includes a first step and a second step. In the first step, the surface of the first semiconductor (2) is thermally cleaned in a growth furnace (C) provided with an atmosphere containing arsine. In the second step, a second semiconductor (3) is grown on the surface of the first semiconductor (2) in the growth furnace (C). The set temperature in the growth furnace (C) for thermal cleaning is set to be lower than the set temperature in the growth furnace (C) when the second semiconductor (3) is grown.

Description

Technical Field

[0001] This disclosure relates to a method for manufacturing semiconductor devices. Background Technology

[0002] Patent Document 1 discloses a vapor phase growth method for crystal growth on an InP substrate. In this method, before the crystal growth begins, a 5×10⁻⁶ vapor phase growth process is performed. -3 Phosphine (PH3) gas is supplied at a rate of mol / min or higher, and the InP substrate is heated to 700°C or higher. Patent Document 2 discloses a surface treatment method and a semiconductor device. Patent Document 3 discloses a semiconductor laser and its manufacturing method.

[0003] Existing technical documents

[0004] Patent documents

[0005] Patent Document 1: Japanese Patent Application Publication No. 1-197398

[0006] Patent Document 2: Japanese Patent Application Publication No. 2000-124138

[0007] Patent Document 3: Japanese Patent Application Publication No. 11-204877 Summary of the Invention

[0008] The problem that the invention aims to solve

[0009] Typically, in semiconductor devices such as high electron mobility transistors (HEMTs) made of GaAs-based semiconductors, an undoped epitaxial layer is grown on a substrate. However, if silicon (Si) impurities are present at the interface between the epitaxial layer and the substrate, the epitaxial layer becomes conductive, and the electrical characteristics of the semiconductor device deteriorate due to current leakage. To address this issue, various studies have been conducted on semiconductor devices made of GaAs-based semiconductors.

[0010] On the other hand, when growing another semiconductor layer on a substrate or semiconductor layer made of InP or InGaAsP, unintended Si atom incorporation occurs at the interface between the substrate or semiconductor layer and the other semiconductor layer. For example, in the fabrication of photodiodes made of InP-based semiconductors, problems arise such as the device capacitance increasing unintendedly due to Si atom incorporation. Therefore, it is desirable to reduce or remove Si atoms at the interface between the substrate or semiconductor layer and the other semiconductor layer. Typically, when growing a semiconductor on an InP substrate, heat treatment is performed in an atmosphere of phosphine (PH3), a group V raw material gas for the substrate material, to remove the native oxide film on the InP substrate. However, it is difficult to eliminate Si atoms during heat treatment in a PH3 atmosphere.

[0011] The purpose of this disclosure is to provide a method for manufacturing a semiconductor device that can reduce or remove Si atoms at the interface between a substrate or semiconductor layer made of InP or InGaAsP and another semiconductor layer grown thereon.

[0012] Technical means for solving problems

[0013] [1] One aspect of the present disclosure is a method for manufacturing a semiconductor device comprising a first semiconductor made of InP or InGaAsP and a second semiconductor disposed on the first semiconductor. The manufacturing method includes a first step and a second step. In the first step, the surface of the first semiconductor is thermally cleaned in a growth furnace provided with an atmosphere containing arsenic. In the second step, the second semiconductor is grown on the surface of the first semiconductor in a growth furnace. The set temperature in the thermally cleaned growth furnace is lower than the set temperature in the growth furnace during the growth of the second semiconductor.

[0014] The inventors have discovered that by performing thermal cleaning in an arsine (AsH3) atmosphere, Si atoms present on the surface of a substrate or semiconductor layer made of InP or InGaAsP can be eliminated. In addition, when performing thermal cleaning on the surface of a semiconductor made of InP or InGaAsP, if the substrate temperature is increased, P atoms will detach due to the thermal degradation of InP or InGaAsP, and In atoms will precipitate. If thermal cleaning is performed in an AsH3 atmosphere, P atoms will detach, and As atoms will be substituted, thereby As atoms will combine with In atoms, generating foreign matter on the surface. Therefore, the set temperature in the growth furnace for thermal cleaning is lower than the set temperature in the growth furnace for growing the second semiconductor. As a result, the thermal degradation of InP or InGaAsP can be prevented, the detachment of P atoms can be reduced, and the generation of foreign matter can be reduced. As a result of the above, according to the manufacturing method described above [1], the generation of foreign matter can be reduced and Si atoms can be reduced or removed at the interface between the substrate or semiconductor layer made of InP or InGaAsP, i.e., the first semiconductor, and the other semiconductor layer grown thereon, i.e., the second semiconductor.

[0015] [2] In the manufacturing method described in [1] above, the temperature of the first semiconductor to be thermally cleaned may be lower than 534°C. In this case, thermal degradation of InP or InGaAsP can be reliably prevented.

[0016] [3] In the manufacturing method described in [1] above, the temperature of the first semiconductor being thermally cleaned may be set to 476°C or below. In this case, thermal degradation of InP or InGaAsP can be prevented more reliably.

[0017] [4] In the manufacturing method described in [1] or [2] above, the temperature of the first semiconductor being thermally cleaned may be set to 417°C or higher. In this case, the number of Si atoms can be further reduced.

[0018] [5] In the manufacturing method described in [1] above, the temperature of the first semiconductor during thermal cleaning may be set to 417°C or higher and 476°C or lower. In this case, it is possible to further reduce the number of Si atoms and more reliably prevent the thermal degradation of InP or InGaAsP.

[0019] [6] In the manufacturing methods described in [1] to [5] above, the heat cleaning process time may be set to 30 minutes or more. In this case, the number of Si atoms can be further reduced.

[0020] [7] In the hot cleaning process of the manufacturing methods described in [1] to [6] above, the total supply of arsenic may be set to 50% or more relative to the volume of the growth furnace. In this case, the number of Si atoms can be further reduced.

[0021] [8] In the manufacturing methods described in [1] to [7] above, the root mean square roughness of the surface of the first semiconductor after thermal cleaning may be less than 0.3 nm. According to the manufacturing methods described in [1] to [6], a semiconductor device with less damage to the surface of the first semiconductor can be obtained.

[0022] [9] In the manufacturing methods described in [1] to [8] above, the thermal cleaning time may be longer than the growth time of the second semiconductor. In this case, the number of Si atoms can be further reduced.

[0023]

[10] The manufacturing methods described in [1] to [9] above may also include, between the thermal cleaning step and the second semiconductor growth step, a step of setting the growth furnace in an atmosphere containing phosphine instead of arsenic and raising the temperature inside the growth furnace. Furthermore, the flow rate of arsenic during thermal cleaning may be greater than the flow rate of phosphine during the heating step. In this way, by making the flow rate of arsenic greater than the flow rate of phosphine in the subsequent step, the number of Si atoms can be further reduced.

[0024]

[11] In the manufacturing methods described in [1] to

[10] above, the first semiconductor may also be made of (InP). 1-z (In 0.53 Ga 0.47 As) z (0≤z<1) configuration. In this case, a semiconductor device having a first semiconductor that is lattice-matched with InP can be obtained.

[0025] Invention Effects

[0026] According to this disclosure, a method for manufacturing a semiconductor device can be provided, which reduces or removes Si atoms at the interface between a substrate or semiconductor layer made of InP or InGaAsP and another semiconductor layer grown thereon. Attached Figure Description

[0027] Figure 1 This is a side view showing a portion of the structure of a semiconductor device manufactured by a manufacturing method according to one embodiment.

[0028] Figure 2 Parts (a) and (b) are diagrams illustrating a manufacturing method of one embodiment.

[0029] Figure 3 This is a graph showing the change in the set temperature over time inside the growth furnace.

[0030] Figure 4 This is a graph showing the time variation of the set temperature inside the growth furnace in the comparative example.

[0031] Figure 5 This is a graph showing the distribution of Si concentration along the thickness direction for the four samples prepared in the comparative example.

[0032] Figure 6 Microscopic photograph of the surface of an InP substrate after thermal cleaning.

[0033] Figure 7 This is a graph showing the time variation of the set temperature inside the growth furnace in the comparative example.

[0034] Figure 8 Parts (a) and (b) are diagrams showing microscopic photographs of the surface of an InP substrate.

[0035] Figure 9 Parts (a) and (b) are diagrams showing microscopic photographs of the surface of an InP substrate.

[0036] Figure 10 Parts (a) and (b) are diagrams showing microscopic photographs of the surface of an InP substrate.

[0037] Figure 11 Parts (a) and (b) are diagrams showing microscopic photographs of the surface of an InP substrate after thermal cleaning of a reference example.

[0038] Figure 12 Parts (a) and (b) are images showing microscopic photographs of the surface of an InP substrate after thermal cleaning of a reference example.

[0039] Figure 13 Part (a) is a diagram showing the foreign object magnified. Figure 13 Part (b) is a graph showing the results of foreign matter analysis by energy-dispersive X-ray spectrometry.

[0040] Figure 14 This is a graph showing the distribution of Si concentration in the thickness direction for the three sets of samples prepared in the examples.

[0041] Figure 15 Microscopic photograph of the surface of an InP substrate after thermal cleaning.

[0042] Figure 16 This is a graph showing the distribution of Si concentration in the thickness direction for the five groups of samples prepared in the examples.

[0043] Figure 17 This is a graph showing the ratio of the total AsH3 supply to the volume of the growth furnace and the amount of Si atoms taken in (Si concentration) for four samples after thermal cleaning.

[0044] Figure 18 This is a graph showing the distribution of Si concentration in the thickness direction for the five groups of samples prepared in the examples.

[0045] Figure 19 It is a graph showing the concentration distribution of oxygen (O) atoms along the thickness direction.

[0046] Figure 20 It is a graph showing the concentration distribution of carbon (C) atoms along the thickness direction.

[0047] Explanation of reference numerals in the attached figures

[0048] 1…Semiconductor device, 2…First semiconductor, 3…Second semiconductor, 4…Interface, A1~A7…Photographs, C…Growth furnace, D, F…Foreign matter, L…Linear, T1~T4…Set temperature Detailed Implementation

[0049] Specific examples of this disclosure are described below with reference to the accompanying drawings. Furthermore, the invention is not limited to these examples, as indicated by the claims, and is intended to include all modifications within the meaning and scope equivalent to the claims. In the following description, and in the description of the drawings, the same elements are labeled with the same reference numerals, and repeated descriptions are omitted.

[0050] Figure 1This is a side view showing a portion of the structure of a semiconductor device 1 manufactured by a manufacturing method according to one embodiment of the present disclosure. The semiconductor device 1 is, for example, a photodiode, and in one example, a waveguide-type photodiode monolithically formed on a waveguide substrate. Alternatively, the semiconductor device 1 may also be, for example, a transistor such as a HEMT. The semiconductor device 1 includes at least a first semiconductor 2 and a second semiconductor 3. The semiconductor device 1 may also have an additional semiconductor layer (not shown) above the second semiconductor 3. The first semiconductor 2 is a substrate or a semiconductor layer formed on a substrate. The first semiconductor 2 is composed of InP or InGaAsP. InGaAsP is, for example, (InP) lattice-matched with InP. 1-z (In 0.53 Ga 0.47 As) z (0≤z<1). The first semiconductor 2 must contain both indium (In) and phosphorus (P) in its composition. The first semiconductor 2 may contain arsenic (As) in its composition, or it may not contain As in its composition. The second semiconductor 3 is a semiconductor layer epitaxially grown on the first semiconductor 2 and is in contact with the first semiconductor 2. The second semiconductor 3 mainly comprises an InP-based semiconductor that is lattice-matched with the first semiconductor 2. The semiconductor device 1 has an interface 4 between the first semiconductor 2 and the second semiconductor 3.

[0051] Figure 2 This diagram illustrates a manufacturing method according to one embodiment of the present disclosure. The manufacturing method of this embodiment includes a first step and a second step. In the first step, as... Figure 2 As shown in (a), the surface of the first semiconductor 2 is thermally cleaned in a growth furnace C equipped with an atmosphere containing arsine (AsH3). Then, in the second process, as... Figure 2 As shown in (b), the second semiconductor 3 is grown on the surface of the first semiconductor 2 in the same growth furnace C.

[0052] Figure 3 This is a graph showing the change in the set temperature over time within growth furnace C. Figure 3 In the graph, the vertical axis represents temperature (°C), and the horizontal axis represents time (minutes). Figure 3 The document also shows the types of gas supplied at each time period.

[0053] like Figure 3 As shown, the manufacturing method includes at least six steps P1 to P6. Through steps P1 to P6, a carrier gas (e.g., H2) is supplied into the growth furnace C. In step P1, the first semiconductor 2 is preheated. The set temperature T1 inside the growth furnace C in step P1 is, for example, 200°C. Next, in step P2, the set temperature inside the growth furnace C is raised from the set temperature T1 to a set temperature T2, which is higher than the set temperature T1.

[0054] Next, step P3 is the first step described above. In step P3, AsH3 is supplied into the growth furnace C, setting the atmosphere inside the furnace C to contain AsH3. For example, the atmosphere inside the growth furnace C is set to contain only AsH3 and a carrier gas. In other words, the atmosphere inside the growth furnace C is set to contain no raw material gases for III-V semiconductors other than AsH3. The supply amount of AsH3 is, for example, 1 slm. Furthermore, 1 slm is related to 1.67 × 10 -5 m 3 The surface of the first semiconductor 2 is thermally cleaned by maintaining the set temperature T2 within the growth furnace C. The set temperature T2 is, for example, below 650°C or below 595°C. Alternatively, the set temperature T2 is, for example, above 540°C. In one embodiment, the set temperature T2 is 585°C. The thermal cleaning process time, i.e., the time for maintaining the set temperature T2 within the growth furnace C, is, for example, 30 minutes or more, or 60 minutes or more. In step P3, the total supply of AsH3 relative to the volume of the growth furnace C is, for example, 50% or more, or 100% or more. Furthermore, the total supply of AsH3 is the product of the AsH3 supply rate (flow rate) and the time. The root mean square roughness (RMS) of the surface of the first semiconductor 2 after thermal cleaning is, for example, below 0.3 nm.

[0055] Typically, the temperature of the article placed inside the growth furnace C deviates from the set temperature inside the growth furnace C. In the growth furnace used by the inventors, when the set temperatures inside the growth furnace C are 650°C, 595°C, and 540°C, the temperatures of the article placed inside the growth furnace C are 534°C, 476°C, and 417°C, respectively. Therefore, the temperature of the first semiconductor 2 during heat cleaning is, for example, below 534°C or below 476°C. Alternatively, the temperature of the first semiconductor 2 during heat cleaning is, for example, above 417°C. In one embodiment, the temperature of the first semiconductor 2 during heat cleaning is above 417°C and below 476°C.

[0056] Furthermore, the growth furnace C is set with a hydrogen atmosphere, and the temperature of the placed item relative to the set temperature within the growth furnace C is measured using the following method: The thermocouples are brought to their respective target temperatures and left to stabilize. After confirming the thermocouple temperatures are stable, the temperature of the substrate placement area within the growth furnace C during growth is measured using a radiation thermometer. At this time, the base is rotated, and the temperature of multiple locations within the substrate placement area is measured. Then, the average value of the measured temperatures is calculated. This average value is 534°C, 476°C, and 417°C, as mentioned above.

[0057] The relationship between the temperature of the item placed inside the growth furnace C and the set temperature inside the growth furnace C varies depending on the growth furnace used. Therefore, by investigating the relationship between the temperature of the item placed inside the growth furnace C and the set temperature inside the growth furnace C, and applying the temperature range of the first semiconductor 2 described above to this relationship, the set temperature inside the growth furnace C can be determined.

[0058] Next, in step P4, the supply of AsH3 is stopped and the supply of PH3 is started, thereby setting the growth furnace C to an atmosphere containing PH3 instead of AsH3. For example, the growth furnace C is set to an atmosphere containing only PH3 and a carrier gas. Furthermore, the temperature inside the growth furnace C is raised from a set temperature T2 to a set temperature T3, which is higher than T2. ​​In the hot cleaning of step P3 described above, the flow rate of AsH3 is made greater than the flow rate of PH3 in step P4.

[0059] Step P5 is the second step described above. Next, in step P5, the set temperature inside the growth furnace C is maintained at a set temperature T3, and other Group V and Group III raw material gases, in addition to PH3, are supplied to grow the second semiconductor 3 on the first semiconductor 2. Other semiconductor layers on the second semiconductor 3 are also grown continuously as needed. The other Group V and Group III raw material gases are selected according to the composition of the second semiconductor 3. In the case where the second semiconductor 3 is composed of InP, the Group III raw material gas is, for example, trimethylindium (TMI). The set temperature T3 is determined according to the composition of the second semiconductor 3. The set temperature T3 is, for example, 775°C or higher. The thermal cleaning time in step P3 is set longer than the growth time of the second semiconductor 3 in step P5. Finally, in step P6, the supply of PH3, other Group V and Group III raw material gases is stopped, the set temperature inside the growth furnace C is cooled down, and the semiconductor device 1 is removed from the growth furnace C.

[0060] The effects obtained by the manufacturing method of the semiconductor device 1 according to this embodiment, as described above, will be explained. The inventors have discovered that by performing thermal cleaning in an AsH3 atmosphere, Si atoms present on the surface of a substrate or semiconductor layer made of InP or InGaAsP can be eliminated. Furthermore, when thermal cleaning is performed on the surface of a semiconductor made of InP or InGaAsP, if the substrate temperature is increased, P atoms detach due to the thermal degradation of InP or InGaAsP, and In atoms precipitate. If thermal cleaning is performed in an AsH3 atmosphere, As atoms combine with these In atoms, generating foreign matter on the surface. Therefore, the set temperature T2 in the growth furnace C for thermal cleaning is lower than the set temperature T3 in the growth furnace C for growing the second semiconductor 3. This prevents the thermal degradation of InP or InGaAsP, reduces the detachment of P atoms, and reduces the generation of foreign matter. As described above, the manufacturing method of this embodiment can reduce the generation of foreign matter and reduce or remove Si atoms at the interface 4 between the substrate or semiconductor layer made of InP or InGaAsP, i.e., the first semiconductor 2, and the additional semiconductor layer grown thereon, i.e., the second semiconductor 3. Furthermore, according to the method of this embodiment, the native oxide film on the first semiconductor 2 can also be reduced or removed through thermal cleaning.

[0061] As described above, the temperature of the first semiconductor 2 during thermal cleaning can also be lower than 534°C. In this case, as shown in the embodiments described later, thermal degradation of InP or InGaAsP can be reliably prevented. Alternatively, the temperature of the first semiconductor 2 during thermal cleaning can be set to 476°C or lower. In this case, thermal degradation of InP or InGaAsP can be prevented more reliably.

[0062] As described above, the temperature of the first semiconductor 2 during thermal cleaning can also be set to 417°C or higher. In this case, as shown in the embodiments described later, the number of Si atoms can be further reduced.

[0063] As mentioned above, the temperature of the first semiconductor 2 undergoing thermal cleaning can also be set to 417°C or higher and 476°C or lower. In this case, it is possible to further reduce the number of Si atoms and more reliably prevent the thermal degradation of InP or InGaAsP.

[0064] As mentioned above, the thermal cleaning process time can also be set to 30 minutes or more. In this case, as shown in the embodiments described later, the Si atom count can be further reduced. If the process time is set to 60 minutes or more, the Si atom count can be significantly reduced.

[0065] As mentioned above, during hot cleaning, the total supply of AsH3 can be set to 50% or more relative to the volume of the growth furnace C. In this case, as shown in the embodiments described later, the number of Si atoms can be further reduced. If the total supply of AsH3 is set to 100% or more relative to the volume of the growth furnace C, the number of Si atoms can be significantly reduced.

[0066] As described above, the root mean square roughness of the surface of the first semiconductor 2 after thermal cleaning can also be less than 0.3 nm. According to the manufacturing method of this embodiment, a semiconductor device 1 with less damage to the surface of the first semiconductor 2 can be obtained.

[0067] As mentioned above, the thermal cleaning time can also be longer than the growth time of the second semiconductor 3. In this case, the thermal cleaning time is longer, thus enabling a further reduction in Si atoms.

[0068] As described above, the manufacturing method may also include, between the thermal cleaning step P3 and the second semiconductor 3 growth step P5, a step P4 in which the growth furnace C is set to an atmosphere containing phosphine instead of AsH3 and the growth furnace C is heated. Furthermore, the flow rate of AsH3 during thermal cleaning may be greater than the flow rate of phosphine in the heating step P4. Thus, by making the flow rate of AsH3 greater than the subsequent flow rate of phosphine, the flow rate of AsH3 increases, thereby further reducing the number of Si atoms.

[0069] As mentioned above, the first semiconductor 2 can also be made of (InP). 1-z (In 0.53 Ga 0.47 As) z (0≤z<1) configuration. In this case, a semiconductor device 1 having a first semiconductor 2 that is lattice-matched with InP can be obtained.

[0070] [First Comparative Example]

[0071] First, as a first comparative example, after the InP substrate (equivalent to the first semiconductor 2 mentioned above) was thermally cleaned with PH3, an InP layer (equivalent to the second semiconductor 3 mentioned above) was grown on the InP substrate. Figure 4 This is a graph showing the time-varying set temperature within the growth furnace in this comparative example. Figure 4 In the graph, the vertical axis represents temperature (°C), and the horizontal axis represents time (minutes). For example... Figure 4 As shown, the manufacturing method of this comparative example includes at least two steps, P5 and P7. Step P5 is the same as step P5 in the above embodiment. In step P5, the set temperature in the growth furnace is maintained at a set temperature T3, and in addition to PH3, In raw material gas (trimethylindium) is supplied to grow an InP layer on the InP substrate.

[0072] Process P7 is performed before process P5. In process P7, PH3 is supplied into the growth furnace to create an atmosphere containing only PH3 and carrier gas. The flow rate of PH3 is 1500 sccm. Furthermore, the surface of the InP substrate is thermally cleaned by maintaining the set temperature T4 within the growth furnace. For the three InP substrates, the set temperature T4 and processing time for thermal cleaning are set to 800°C for 15 minutes, 830°C for 5 minutes, and 830°C for 15 minutes, respectively. Additionally, an InP substrate that has not undergone thermal cleaning is prepared.

[0073] Figure 5 This is a graph showing the distribution of Si concentration along the thickness direction, based on the results of secondary ion mass analysis of four samples prepared in the comparative example. Figure 5 In the figure, the vertical axis represents the Si concentration (Atoms / cm³). 3 The horizontal axis represents the position in the thickness direction, i.e., the depth (μm). Figure 5 In the diagram, curve G11 represents the case where no hot cleaning is performed. Curve G12 represents the case where the hot cleaning setting temperature T4 and processing time are set to 800℃·15 minutes. Curve G13 represents the case where the hot cleaning setting temperature T4 and processing time are set to 830℃·5 minutes. Curve G14 represents the case where the hot cleaning setting temperature T4 and processing time are set to 830℃·15 minutes.

[0074] Reference Figure 5 At that time, in any sample, a Si concentration peak was present in the depth range of 0.4 μm to 0.7 μm, that is, near the interface between the InP substrate and the InP layer. Furthermore, compared with the sample without thermal cleaning (curve G11), the Si concentration was slightly lower in the samples that underwent thermal cleaning (curves G12–G14). Moreover, the higher the set temperature T4 and the longer the processing time, the further the Si concentration decreased. Therefore, it can be concluded that even with thermal cleaning using PH3, the number of Si atoms present at the interface between the InP substrate and the InP layer is slightly reduced.

[0075] Figure 6 A microscope image showing the surface of an InP substrate after thermal cleaning. Figure 6 In the images, photos A1-A4 show the cases where the set temperature T4 and processing time were set to 800℃·15 minutes, 815℃·15 minutes, 830℃·5 minutes, and 830℃·15 minutes, respectively. (See reference...) Figure 6It is evident that the higher the set temperature T4 and the longer the processing time, the worse the surface flatness. Surface roughness, an indicator of surface flatness, was measured. The results showed that the surface roughness was 0.1856 nm at 800℃ for 15 minutes, 1.745 nm at 815℃ for 15 minutes, 0.1877 nm at 830℃ for 5 minutes, and 3.141 nm at 830℃ for 15 minutes. Thus, the surface flatness of the InP substrate significantly deteriorates during high-temperature or prolonged thermal cleaning.

[0076] Based on the comparative examples described above, the reduction effect of Si atoms is small when PH3 is used in hot cleaning. In addition, if the processing temperature is increased and the processing time is extended in order to reduce Si atoms significantly, the surface flatness of the InP substrate will be damaged. Therefore, it can be said that it is difficult to apply to practical devices.

[0077] [Second Comparative Example]

[0078] Next, as a second comparative example, the InP substrate was subjected to thermal cleaning in an AsH3 atmosphere. Figure 7 This is a graph showing the time-varying set temperature within the growth furnace in this comparative example. Figure 7 In the graph, the vertical axis represents temperature (°C), and the horizontal axis represents time (minutes). For example... Figure 7 As shown, in this comparative example, after placing the InP substrate in the growth furnace, the set temperature inside the growth furnace was first maintained at 200°C, and then the set temperature inside the growth furnace was increased to 800°C. Thermal cleaning of the InP substrate was performed at this furnace temperature of 800°C. In this comparative example, multiple InP substrates were divided into a first group and a second group. The first group was supplied with AsH3 only during the period P10 (5 minutes) when the furnace temperature was maintained at 800°C. The second group was supplied with AsH3 during the period P11 (15 minutes), which included the period when the furnace temperature increased from 200°C to 800°C and the period when the furnace temperature was maintained at 800°C. For a portion of the InP substrates in the first group, the AsH3 supply was set to 100 sccm. For the remaining InP substrates in the first group, the AsH3 supply was set to 400 sccm. For the InP substrates in the second group, the AsH3 supply was set to 100 sccm. Furthermore, 1 sccm and 1.67 × 10⁻⁶... -8 m 3 / s are equal.

[0079] Figures 8-10 This is a photograph showing the surface of an InP substrate based on a microscope. Figure 8 This refers to the surface of an InP substrate in the first group where the AsH3 supply is set to 400 sccm. Figure 9This refers to the surface of an InP substrate in the first group where the AsH3 supply is set to 100 sccm. Figure 10 This represents the surface of the InP substrate in the second group. Figures 8-10 In the image, part (b) is an enlarged representation of part (a). (See reference...) Figures 8-10 It is known that when AsH3 is supplied to the surface of an InP substrate at a high temperature such as 800°C, the P atoms detach due to the thermal degradation of InP, and the precipitated In atoms combine with As atoms to generate multiple foreign matter F on the surface.

[0080] Based on the comparative examples described above, even when AsH3 is used for thermal cleaning, if the processing temperature is increased, foreign matter F is generated on the surface of the InP substrate. Therefore, it can be said that it is difficult to apply to practical devices.

[0081] [Reference Example]

[0082] Next, as a reference example, the InP substrates were thermally cleaned without supplying AsH3 and PH3 (only carrier gas) into the growth furnace. In this reference example, multiple InP substrates were divided into four groups. Figure 7 In the time variation of the set temperature shown, only the set temperature for hot cleaning (in) Figure 7 (The temperature is 800℃) and the four groups are set to 590℃, 595℃, 600℃ and 620℃ respectively.

[0083] Figure 11 and Figure 12 This is a microscopic photograph of the surface of an InP substrate after thermal cleaning, representing the reference example. Figure 11 Parts (a) and (b) indicate cases where the set temperature for hot cleaning is set to 590°C and 595°C, respectively. Figure 12 Parts (a) and (b) indicate cases where the set temperature for hot cleaning is set to 600°C and 620°C, respectively. For example... Figure 12 As shown, when the set temperature for thermal cleaning is above 600°C, foreign matter D was confirmed to be generated on the surface of the InP substrate. Figure 11 As shown, if the set temperature for thermal cleaning is below 595°C, no foreign matter D was found to be generated on the surface of the InP substrate.

[0084] Figure 13 Part (a) is to Figure 12 The diagram shows the enlarged representation of the foreign object D in part (b). Figure 13 Part (b) is a graph showing the results of energy-dispersive X-ray spectroscopy (EDS) analysis of foreign matter D along the straight line L. Figure 13In section (b), line G21 represents the X-ray intensity caused by In, i.e., the In concentration, and line G22 represents the X-ray intensity caused by P, i.e., the P concentration. According to this analysis, foreign matter D is a product of In precipitation caused by the detachment of P due to high temperature. Therefore, if the set temperature for thermal cleaning is below 595°C, which translates to below 476°C for the InP substrate, In will not precipitate at all, making this a more preferable option.

[0085] [First Embodiment]

[0086] Next, as a first embodiment, after thermal cleaning of the InP substrate under an AsH3 atmosphere, an InP layer is grown on the InP substrate. In this embodiment, the application... Figure 3 The temperature variation over time is shown, with the thermal cleaning temperature T2 set to 585°C and the InP layer growth temperature T3 set to 775°C. Furthermore, multiple InP substrates are divided into three groups, and the thermal cleaning processing time (the length of time during which the set temperature T2 is maintained and AsH3 is supplied) is set to 0 minutes, 30 minutes, and 60 minutes for the three groups, respectively. The AsH3 supply amount for thermal cleaning is 1 slm.

[0087] Figure 14 This is a graph showing the distribution of Si concentration along the thickness direction, based on the results of secondary ion mass analysis of the three sets of samples prepared in this embodiment. Figure 14 In the figure, the vertical axis represents the Si concentration (Atoms / cm³). 3 The horizontal axis represents the position in the thickness direction, i.e., the depth (μm). Figure 14 In the diagram, curve G31 represents the case where the hot cleaning processing time is 0 minutes, i.e., no hot cleaning is performed. Curve G32 represents the case where the hot cleaning processing time is set to 30 minutes. Curve G33 represents the case where the hot cleaning processing time is set to 60 minutes.

[0088] When reference Figure 14 At that time, in any sample, a Si concentration peak was present in the depth range of 0.4 μm to 0.7 μm, that is, near the interface between the InP substrate and the InP layer. Furthermore, compared with the sample without thermal cleaning (curve G31), the Si concentration was significantly reduced in the samples that underwent thermal cleaning (curves G32, G33). Moreover, the longer the thermal cleaning time, the further the Si concentration was reduced. Additionally, even compared to... Figure 5 Compared to the graph shown, the Si concentration is reduced by an order of magnitude. This demonstrates that thermal cleaning at a temperature lower than the InP layer growth temperature, under an AsH3 atmosphere, can significantly reduce the number of Si atoms present at the interface between the InP substrate and the InP layer.

[0089] Figure 15A microscope image showing the surface of an InP substrate after thermal cleaning. Figure 15 In the images, A5-A7 represent the cases where the processing time was set to 0 minutes, 30 minutes, and 60 minutes, respectively. (Refer to...) Figure 15 It can be seen that the surface flatness is maintained regardless of the processing time. The surface roughness, an indicator of surface flatness, was measured. The results showed that the surface roughness was 0.1781 nm in the sample with a processing time of 0 minutes, 0.1583 nm in the sample with a processing time of 30 minutes, and 0.1822 nm in the sample with a processing time of 60 minutes. Thus, in any sample, the surface roughness was below 0.3 nm, which is considered a standard for good flatness. Therefore, by using thermal cleaning at a temperature lower than the growth temperature of the InP layer under an AsH3 atmosphere, good surface flatness of the InP substrate can be maintained even with an increased processing time. Therefore, increasing the processing time can improve the reduction effect of Si atoms. Furthermore, in this embodiment, foreign matter F (referring to...) was identified during high-temperature thermal cleaning. Figures 8-10 It was not detected at all, even in the dynamic force mode (DFM) of a scanning probe microscope.

[0090] [Second Embodiment]

[0091] Next, as a second embodiment, after thermal cleaning of the InP substrate under an AsH3 atmosphere, an InP layer is grown on the InP substrate. In this embodiment, the following method is also applied: Figure 3 The temperature variation over time is shown, with the thermal cleaning temperature T2 set to 585°C and the InP layer growth temperature T3 set to 775°C. Furthermore, multiple InP substrates were divided into five groups, and the AsH3 supply rate and duration during thermal cleaning were set to 0 slm·0 min, 0.5 slm·30 min, 1.0 slm·15 min, 1.0 slm·30 min, and 1.0 slm·60 min for each group, respectively. The growth furnace used had a volume of approximately 50265 cm³. 3 .

[0092] Figure 16 This is a graph showing the distribution of Si concentration along the thickness direction, based on the results of secondary ion mass analysis of five sets of samples prepared in this embodiment. Figure 16 In the figure, the vertical axis represents the Si concentration (Atoms / cm³). 3 The horizontal axis represents the position in the thickness direction, i.e., the depth (μm). Figure 16In the diagram, curve G41 represents a hot cleaning process of 0 minutes, i.e., no hot cleaning is performed. Curve G42 represents a supply of AsH3 with a supply rate and time of 0.5 slm·30 minutes. Curve G43 represents a supply of AsH3 with a supply rate and time of 1.0 slm·15 minutes. Curve G44 represents a supply of AsH3 with a supply rate and time of 1.0 slm·30 minutes. Curve G45 represents a supply of AsH3 with a supply rate and time of 1.0 slm·60 minutes.

[0093] When reference Figure 16 Compared to the sample without thermal cleaning (curve G41), the Si concentration was significantly lower in the samples that underwent thermal cleaning (curves G42–G45). Furthermore, the higher the total AsH3 supply (the product of supply amount and supply time), the further the Si concentration was reduced. Therefore, thermal cleaning at a temperature lower than the InP layer growth temperature in an AsH3 atmosphere can significantly reduce the number of Si atoms present at the interface between the InP substrate and the InP layer.

[0094] Figure 17 This is a graph showing the ratio of the total AsH3 supply S to the growth furnace volume M (S / M) and the amount of Si atoms introduced (Si concentration) for four samples that underwent thermal cleaning. The ratio (S / M) is expressed as a percentage. The amount of Si atoms introduced is set to 1 for the case without thermal cleaning and then converted. (Refer to...) Figure 17 It can be seen that when the ratio (S / M) is above 50%, in other words, when the total supply of AsH3 is above 50% of the volume of the growth furnace, the amount of Si atoms taken in decreases significantly (by more than an order of magnitude).

[0095] [Third Embodiment]

[0096] Next, as a third embodiment, after thermal cleaning of the InP substrate in an AsH3 atmosphere, an InP layer was grown on the InP substrate. In this embodiment, [the following method was also applied] Figure 3 The time variation of the set temperature is shown. However, multiple InP substrates are divided into five groups, and the set temperature T2 for thermal cleaning is set to 450°C, 500°C, 540°C, and 585°C for four groups, respectively. Thermal cleaning is not performed on the remaining group. The set temperature T3 for InP layer growth is set to 775°C. The supply amount and supply time of AsH3 are 1.0 slm·30 minutes.

[0097] Figure 18 This is a graph showing the distribution of Si concentration along the thickness direction, based on the results of secondary ion mass analysis of five sets of samples prepared in this embodiment. Figure 18 In the figure, the vertical axis represents the Si concentration (Atoms / cm³).3 The horizontal axis represents the position in the thickness direction, i.e., the depth (μm). Figure 18 In the diagram, curve G51 represents the case where no thermal cleaning was performed. Curve G52 represents the case where the set temperature T2 is set to 450℃. Curve G53 represents the case where the set temperature T2 is set to 500℃. Curve G54 represents the case where the set temperature T2 is set to 540℃. Curve G55 represents the case where the set temperature T2 is set to 585℃.

[0098] Reference Figure 18 Compared to the sample without thermal cleaning (curve G51), the Si concentration decreased in the samples that underwent thermal cleaning (curves G52–G55). Particularly when the set temperature T2 was above 540°C (equivalent to above 417°C for the InP substrate), the Si concentration decreased significantly (by more than an order of magnitude). This demonstrates that thermal cleaning at a temperature lower than the growth temperature of the InP layer under an AsH3 atmosphere can significantly reduce the number of Si atoms present at the interface between the InP substrate and the InP layer.

[0099] Figure 19 This is a graph showing the concentration distribution of oxygen (O) atoms in the thickness direction in this embodiment. Figure 20 This is a graph showing the concentration distribution of carbon (C) atoms along the thickness direction in this embodiment. Figure 19 and Figure 20 In the diagram, curves G61 and G71 indicate the case where thermal cleaning was not performed. Curves G62 and G72 indicate the case where the set temperature T2 is set to 450℃. Curves G63 and G73 indicate the case where the set temperature T2 is set to 500℃. Curves G64 and G74 indicate the case where the set temperature T2 is set to 540℃. Curves G65 and G75 indicate the case where the set temperature T2 is set to 585℃. For example... Figure 19 and Figure 20 As shown, by using a temperature lower than the growth temperature of the InP layer and thermal cleaning in an AsH3 atmosphere, not only Si atoms, but also O atoms and C atoms are reduced at the interface between the InP substrate and the InP layer.

[0100] The method for manufacturing the semiconductor device disclosed herein is not limited to the embodiments described above, and various other modifications can be made. For example, the set temperature for thermal cleaning and the temperature of the first semiconductor are not limited to the temperatures shown in the above embodiments and examples; various temperatures can be used as long as they are lower than the set temperature for growing the second semiconductor and the temperature of the first semiconductor.

Claims

1. A method for manufacturing a semiconductor device, wherein, The semiconductor device includes a first semiconductor made of InP or InGaAsP, and a second semiconductor disposed on the first semiconductor. The method for manufacturing the semiconductor device comprises: A process of thermally cleaning the surface of the first semiconductor in a growth furnace containing an arsine atmosphere; and The process of growing the second semiconductor on the surface of the first semiconductor within the growth furnace. The set temperature inside the growth furnace during the heat cleaning is lower than the set temperature inside the growth furnace during the growth of the second semiconductor.

2. The method for manufacturing a semiconductor device according to claim 1, wherein, The temperature of the first semiconductor during the heat cleaning is kept below 534°C.

3. The method for manufacturing a semiconductor device according to claim 1, wherein, The temperature of the first semiconductor during the heat cleaning is set to below 476°C.

4. The method for manufacturing a semiconductor device according to claim 1 or 2, wherein, The temperature of the first semiconductor during the heat cleaning is set to 417°C or higher.

5. The method for manufacturing a semiconductor device according to claim 1, wherein, The temperature of the first semiconductor during the heat cleaning is set to be above 417°C and below 476°C.

6. The method for manufacturing a semiconductor device according to any one of claims 1 to 5, wherein, The hot cleaning process time is set to 30 minutes or more.

7. The method for manufacturing a semiconductor device according to any one of claims 1 to 6, wherein, In the hot cleaning process, the total supply of arsenic is set to be 50% or more relative to the volume of the growth furnace.

8. A method for manufacturing a semiconductor device according to any one of claims 1 to 7, wherein, The root mean square roughness of the surface of the first semiconductor after thermal cleaning is below 0.3 nm.

9. A method for manufacturing a semiconductor device according to any one of claims 1 to 8, wherein, The thermal cleaning time is longer than the growth time of the second semiconductor.

10. A method for manufacturing a semiconductor device according to any one of claims 1 to 9, wherein, Between the thermal cleaning process and the process of growing the second semiconductor, It also includes a step of setting the growth furnace in an atmosphere containing phosphine instead of arsenic and raising the temperature inside the growth furnace. The flow rate of arsenic in the hot cleaning process is greater than the flow rate of phosphine in the heating process.

11. A method for manufacturing a semiconductor device according to any one of claims 1 to 10, wherein, The first semiconductor is made of (InP) 1-z (In 0.53 Ga 0.47 As) z (0≤z<1) constitutes the structure.

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