Driving control method of phased array, time schedule controller, and driving method and driving system of phased array

Abstract

The invention provides a phased array driving control method, a time schedule controller, a phased array driving method and a phased array driving system, belongs to the technical field of phased arrays, and can solve the problems that an existing phased array antenna is low in beam flexibility and low in scanning speed. According to the driving control method of the phased array, the phased array comprises at least one phase adjusting unit; the phase adjusting unit comprises a plurality of grid lines and a plurality of data lines; the grid lines and the data lines are crossed to define a plurality of phase shift regions; each phase shift region is provided with a switch element and a phase shift unit; the switch elements in the same row are connected with the same grid line, and the switch elements in the same column are connected with the same data line; the control method comprises the following steps: controlling each phase adjustment unit; the step of controlling any phase adjusting unit comprises the following steps of: controlling the phase shifting unit to be written into driving voltage line by line; and controlling the phase shift units in any row to be written with the driving voltage, comprising: in response to the data lines being written with the driving voltage, controlling the gate driver to provide scanning signals to the gate lines.

Description

Technical Field

[0001] This disclosure belongs to the field of phased array technology, specifically relating to a phased array driving control method, timing controller, phased array driving method and driving system. Background Technology

[0002] Liquid crystal phased arrays are electronically controlled programmable optical phased array devices based on liquid crystals, offering advantages such as small size, light weight, low power consumption, and ease of control. Liquid crystal phased arrays precisely control beam steering by modulating the phase of the incident beam, possessing advantages such as wide wavelength range, wide birefringence range, small size, low power consumption, wide field of view, and ease of microelectronic circuit control. They have been widely used in lidar, antennas, and high-energy lasers.

[0003] Liquid crystal is a uniaxial crystal. The long axis of liquid crystal molecules has a fixed orientation. Under the influence of an external electric field, the orientation of liquid crystal molecules will deflect, and their dielectric constant will change accordingly. A liquid crystal phased array is a phase modulation device that uses liquid crystal as the phase modulation material and combines it with an electronically programmable electrode array. Each electrode and the liquid crystal in the region it controls form a controllable unit. When different driving voltages are applied to each controllable unit, the orientation of the liquid crystal molecules will deflect to varying degrees, thus affecting the effective refractive index of the liquid crystal molecules. This phase modulation of the light beam incident on the device changes the exit direction of the beam, generating far-field interference in a specified direction, and achieving beam deflection.

[0004] In short, liquid crystal phased arrays possess advantages such as wide bandwidth, wide birefringence range, high damage threshold, small size, low power consumption, wide field of view, and ease of control by microelectronic circuits, and have shown broad application prospects in many fields, such as satellite mobile communication and lidar. The demand for mobile communication antenna terminals is booming; however, due to the wide range of technologies involved in liquid crystal phased arrays, the incomplete industrial chain, and the high technical difficulty, especially the imperfect design of the drive system, there is currently a lack of commercially available liquid crystal phased arrays in the domestic market that can be applied to mobile communication antennas and meet the requirements for flexible and rapid beam switching. Summary of the Invention

[0005] This invention aims to at least solve one of the technical problems existing in the prior art. On one hand, it provides a driving control method for a phased array, the phased array including at least one phase adjustment unit; the phase adjustment unit includes multiple gate lines and multiple data lines; the gate lines and the data lines intersect to define multiple phase-shifting regions; each phase-shifting region is provided with a switching element and a phase-shifting unit; the switching elements located in the same row are connected to the same gate line, and the switching elements located in the same column are connected to the same data line; wherein, the control method includes: controlling each of the phase adjustment units; controlling any one of the phase adjustment units includes: controlling the phase-shifting unit to be written with a driving voltage row by row; for controlling any row of the phase-shifting units to be written with a driving voltage includes: in response to the data line being written with the driving voltage, controlling the gate driver to provide a scan signal to the gate line.

[0006] In some embodiments, before the control phase-shifting unit is written with the drive voltage row by row, it further includes:

[0007] In response to frame drive data, the frame drive data is transmitted line by line to the source driver so that the source driver converts the received drive data into drive voltage.

[0008] In some embodiments, before transmitting the frame driving data line by line to the source driver in response to the frame driving data, the method further includes:

[0009] The frame-driven data is received via the LVDS interface in accordance with the LVDS interface protocol.

[0010] In some embodiments, the data line is written with the drive voltage, including:

[0011] The TP1 signal of the source driver is controlled to be at the working level for a first preset time, so that the source driver receives the driving data and latches it in the data register of the source driver;

[0012] After the TP1 signal is kept at the working level for a first preset time, the TP1 signal is controlled to be at the non-working level, and the drive data in the data register is transmitted to the digital-to-analog converter. After being converted into the drive voltage by the digital-to-analog converter, the drive voltage is written to the data line.

[0013] In some embodiments, controlling the gate driver to provide a scan signal to the gate line includes:

[0014] The CPV signal of the gate driver is controlled to be at the working level for a second preset time, and the OE signal of the gate driver is controlled to be at the working level for a third preset time, so as to provide a scan signal for the gate line, thereby turning on the switching element connected to the gate line for a third preset time.

[0015] In some embodiments, the phased array includes a plurality of the phase adjustment units;

[0016] The control of each of the phase adjustment units includes:

[0017] The phase-shifting units in each phase adjustment unit are synchronously controlled to have their driving voltages written line by line.

[0018] Secondly, this disclosure provides a timing controller that uses the control method provided in any of the above embodiments to control the driving of a phased array.

[0019] Thirdly, this disclosure provides a driving method for a phased array, the phased array including at least one phase adjustment unit; the phase adjustment unit including multiple gate lines and multiple data lines; the gate lines and the data lines intersect to define multiple phase-shifting regions; each phase-shifting region is provided with a switching element and a phase-shifting unit; the switching elements located in the same row are connected to the same gate line, and the switching elements located in the same column are connected to the same data line; wherein, the driving method includes:

[0020] The timing controller receives frame drive data and transmits it line by line to the source driver;

[0021] The source driver converts the received drive data into a corresponding drive voltage and writes it to the data line;

[0022] In response to a first control signal, the gate driver provides a scan signal to the gate line to turn on the switching element and control the phase shifting unit to phase shift the received microwave signal; the first control signal is the control signal output by the timing controller in response to the data line being written with the drive voltage.

[0023] In some embodiments, the source driver converts the received drive data into a corresponding drive voltage, including:

[0024] Based on the gamma reference voltage provided by the gamma voltage module, the driving data is converted into the corresponding driving voltage.

[0025] In some embodiments, the source driver converts the received drive data into a corresponding drive voltage and writes it to the data line, including:

[0026] The TP1 signal of the source driver is set to the working level and held for a first preset time. The source driver receives the driving data and latches it in the data register of the source driver.

[0027] After the TP1 signal is kept at the working level for a first preset time, it is set to the non-working level. The source driver transmits the drive data in the data register to the digital-to-analog converter, which converts it into the drive voltage and then writes the drive voltage into the data line.

[0028] In some embodiments, the gate driver, in response to a first control signal, provides a scan signal to the gate line to turn on the switching element, including:

[0029] The gate driver sets the CPV signal to the operating level for a second preset time, sets the OE signal to the operating level for a third preset time, and provides a scan signal to the gate line to turn on the switching element connected to the gate line for a third preset time.

[0030] Fourthly, this disclosure provides a phased array driving system, which uses the driving method provided in any of the above embodiments to drive the phased array. Attached Figure Description

[0031] Figure 1 This is a block diagram of a phased array antenna.

[0032] Figure 2 This is a schematic diagram of the phased array structure.

[0033] Figure 3 This is an exploded view of the three-dimensional structure of a liquid crystal phased array.

[0034] Figure 4 This is an example diagram of the phased array provided in this disclosure.

[0035] Figure 5 This is a flowchart of the phased array driving and control method provided in this disclosure.

[0036] Figure 6 The timing diagram of the gate driver signals provided in this disclosure is shown.

[0037] Figure 7 This is a flowchart of the phased array driving method provided in this disclosure.

[0038] The attached figures are labeled as follows:

[0039] 1. Power supply structure; 2. Phased array; 3. Radial structure; 11. Grid line; 12. Data line; 101. First substrate; 103. Reference electrode; 102. Signal line; 301. Liquid crystal layer; 201. Second substrate; 202. Patch electrode; M1. Phase adjustment unit; Z1. Phase shifting region; 4. Phase shifting unit; 5. Switching element. Detailed Implementation

[0040] To enable those skilled in the art to better understand the technical solution of the present invention, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0041] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Similarly, the terms “an,” “a,” or “the,” and similar terms do not indicate a quantity limitation, but rather indicate the presence of at least one. The terms “including,” “comprising,” or “containing,” and similar terms mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. The terms “connected,” “linked,” or similar terms are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. The terms “upper,” “lower,” “left,” and “right,” etc., are used only to indicate relative positional relationships, and these relative positional relationships may change accordingly when the absolute position of the described objects changes.

[0042] As used herein, “parallel” and “perpendicular” include the described situation and situations that are similar to the described situation, within an acceptable range of deviation, which is determined by those skilled in the art taking into account the measurement under discussion and the error associated with the measurement of a particular quantity (i.e., the limitations of the measurement system). For example, “parallel” includes absolute parallelism and approximate parallelism, where an acceptable range of deviation for approximate parallelism may be, for example, within 5°; “perpendicular” includes absolute perpendicularity and approximate perpendicularity, where an acceptable range of deviation for approximate perpendicularity may also be, for example, within 5°.

[0043] It should be understood that when a layer or element is referred to as being on another layer or substrate, it can mean that the layer or element is directly on the other layer or substrate, or that there is an intermediate layer between the layer or element and the other layer or substrate.

[0044] In this article, "electrical connection" includes the situation where constituent elements are connected together by a component that has a certain electrical function. There are no particular restrictions on the "component that has a certain electrical function" as long as it enables the transmission and reception of electrical signals between the connected constituent elements. Examples of "components that have a certain electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other components with various functions.

[0045] This document describes exemplary embodiments with reference to sectional views and / or plan views, which are idealized exemplary drawings. In the drawings, the thickness of layers and regions is enlarged for clarity. Therefore, variations in shape relative to the drawings are contemplated due to, for example, manufacturing techniques and / or tolerances. Therefore, exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing processes. Thus, the regions shown in the drawings are schematic in nature, and their shapes are not intended to show the actual shapes of the regions of the device, nor are they intended to limit the scope of the exemplary embodiments.

[0046] Figure 1 This is a block diagram of a phased array antenna. Figure 1 As shown, a phased array antenna, according to the function of its components, typically includes a feeding structure 1, a phased array 2, and a radiating structure 3. When the phased array antenna is used as a transmitting antenna, its operation is roughly as follows: the microwave signal emitted by the transmitter is transmitted to the phased array 2 through the feeding structure 1; after phase shifting by the phased array 2, the microwave signal is transmitted to the radiating structure 3, and then radiated into external space through the radiating structure 3. Similarly, when the phased array antenna is used as a receiving antenna, its operation is roughly as follows: the radiating structure 3 receives the microwave signal propagating in external space; after phase shifting by the phased array 2, the signal is transmitted to the receiver through the feeding structure 1.

[0047] Phased array antennas used in mobile communication systems, such as those in vehicle-mounted, shipboard, or intercom systems, are primarily responsible for signal transmission between vehicles, ships, and satellites. However, since vehicles, ships, and satellites are constantly in motion, these antennas need to have rapid beam tracking capabilities; otherwise, tracking failures will occur, leading to communication interruptions. In other words, when a phased array antenna moves with the carrier device, to achieve accurate satellite alignment, the phased array must rapidly adjust the beam phase within a very short time (e.g., 5ms). Taking a liquid crystal phased array as an example, it needs to rapidly control the deflection of liquid crystal molecules within 5ms, thereby controlling the azimuth angle of the phased array antenna. Therefore, for phased array antennas, how to control the phased array to quickly achieve beam phase adjustment is particularly important in their design.

[0048] To clearly illustrate the technical solution of this disclosure, this article takes liquid crystal phased array as an example to briefly introduce the structure, working principle and driving process of phased array in related technologies.

[0049] First, let's introduce the structure of phased array 2. Figure 2 The image shown is a partial top view of the liquid crystal phased array structure. Figure 3 This is an exploded view of the three-dimensional structure of a liquid crystal phased array. (Example:) Figure 2 As shown, the phased array 2 includes multiple gate lines 11 and multiple data lines 12. The multiple gate lines 11 extend horizontally and are arranged side by side vertically; the multiple data lines 12 extend vertically and are arranged side by side horizontally. The multiple gate lines 11 and multiple data lines 12 intersect to define multiple phase-shifting regions Z1. Each phase-shifting region Z1 is provided with a phase-shifting unit 4 and a switching element 5. The switching element 5 can be a thin-film transistor (TFT), and the gates of switching elements 5 located in the same row are connected to the same gate line 11, and the sources of switching elements 5 located in the same column are connected to the same data line 12.

[0050] like Figure 3 As shown, the phased array 2 includes a first substrate 101, a second substrate 201, and a liquid crystal layer 301 disposed between the first substrate 101 and the second substrate 201. In addition, the phased array 2 also includes a plurality of patch electrodes 202 disposed on the side of the second substrate 201 near the liquid crystal layer 301, signal lines 102 disposed on the side of the first substrate 101 near the liquid crystal layer 301, and a reference electrode 103 disposed on the side of the first substrate 101 away from the signal lines 102. Both the first substrate 101 and the second substrate 201 can be glass substrates. The liquid crystal layer 103 contains liquid crystal molecules and has a thickness between tens and hundreds of micrometers. The liquid crystal molecules are anisotropic and exhibit different dielectric constants in the long axis and short axis directions.

[0051] Those skilled in the art will understand that, for Figure 3 The phased array shown has signal lines 102, a first substrate 101, and a reference electrode 103 forming a microstrip line for transmitting microwave signals. Of course, in other examples, a coplanar waveguide (CPW) can be used as the microwave signal transmission structure, in which case the structure of phased array 2 is similar to... Figure 3 The difference in the phased array shown is that instead of setting signal lines 102 and reference electrodes 103 on both sides of the first substrate 101, signal lines and two ground lines are set on the side of the first substrate 101 near the liquid crystal layer 301. The signal lines and the two ground lines extend horizontally, with the signal lines located between the two ground lines. Of course, in other examples, coplanar coupled dual lines can also be used as the transmission structure for microwave signals. In this case, the phased array 2 and... Figure 3The difference in the phased array 2 shown is that instead of setting signal lines 102 and reference electrodes 103 on both sides of the first substrate 101, two signal lines are set on the side of the first substrate 101 closer to the liquid crystal layer 301, and the reference electrode 103 is set on the side of the first substrate 101 away from the two signal lines. Both signal lines extend horizontally and are arranged in parallel, and the signals transmitted by the two signal lines are out of phase, i.e., 180° apart. It should be noted that when using microstrip lines or coplanar coupled dual lines as the transmission structure, the reference electrode 103 is not limited to being set on the first substrate 101, but can also be set on the side of the second substrate 201 away from the patch electrode 202.

[0052] Next, we will introduce... Figures 2-3 The working principle of the phased array 2 shown is as follows: A patch electrode 202 and its opposite reference electrode 103, as well as the liquid crystal molecules between the patch electrode 202 and the opposite reference electrode 103, can be regarded as a phase-shifting unit 4. During phase shifting, a driving voltage needs to be applied to each phase-shifting unit 4, that is, a driving voltage is applied between the patch electrode 202 and the opposite reference electrode 103 in each phase-shifting unit 4, so as to form a vertical electric field between the patch electrode 202 and the reference electrode 103, thereby driving the liquid crystal molecules in the vertical electric field to deflect, thereby changing the dielectric constant of the liquid crystal layer 301, and ultimately changing the phase of the microwave signal transmitted by the signal line 102, realizing phase shift. In this process, the deflection angle of the liquid crystal molecules is determined by the bias voltage applied between the patch electrode 202 and the reference electrode 103. Typically, the voltage supplied to the reference electrode 103 can be a fixed value. In this case, providing a driving voltage to the phase-shifting unit 4 means applying a voltage to the patch electrode 202 in the phase-shifting unit 4. Providing a driving voltage to each phase-shifting unit 4 in the liquid crystal phase array 2 can be achieved through the cooperation of the source driver (Source-IC) and the gate driver (Gate-IC).

[0053] Next, we will introduce the driving process of the phased array. Before that, we will first introduce several concepts of phased array 2, such as a frame, frame rate, frame driving data, and line driving data. It can be understood that for a thin-film transistor liquid crystal display (TFT-LCD), a frame refers to a complete image, and the frame rate refers to the number of frames refreshed per second. For example, for a display with a frame rate of 60Hz, it refreshes 60 frames per second. The liquid crystal display panel includes multiple gate lines and multiple data lines. The gate lines and data lines intersect to define multiple pixel areas, and each pixel area is equipped with thin-film transistors and pixel units. The driving method of the liquid crystal display panel is roughly as follows: During the display of a frame image, multiple gate lines are responsible for turning on the thin-film transistors in each row sequentially, while the data lines are responsible for providing driving voltage to the pixel units connected to the thin-film transistors. This driving voltage can control the deflection of liquid crystal molecules in the pixel units, causing the light beam passing through the liquid crystal molecules to be deflected, changing the color or brightness of the light beam to display the preset image. For the phased array antenna discussed in this paper, a frame refers to the set of signals transmitted or received by the antenna within a time period (e.g., one cycle); the frame rate of the phased array antenna is the number of frames refreshed per second by the phased array. For example, for a phased array antenna with a frame rate of 200 fps, the phased array refreshes 200 frames per second. In other words, for a single frame of signal, the phase shifting time of phased array 2 should be limited to within 5 ms. Figure 2 When the phased array 2 shown includes M grid lines and N data lines, that is, when the phased array includes M×N phase shifting units 4, the opening time of each row of switching elements 5 should be limited to [time range missing]. Within; if the value of M is large, it means that the opening time of each row of switching elements 5 is very short. For example, for a phased array with M=74 and N=74, the opening time of each row of switching elements 5 should be limited to within 65μs. Generally, for a frame signal, the driving process of the phased array is as follows: 1. Preparation stage: pre-calculate the frame driving data. Here, the frame driving data refers to the data corresponding to the driving voltage that should be applied to each phase shifting unit 4 in the phased array 2, calculated according to the phase shifting requirements of the frame signal; 2. Scanning stage: first, turn on one row of switching elements 5; then transmit the row driving data of that row to the source driver. Here, the row driving data refers to the data corresponding to the driving voltage of the phase shifting unit 4 in that row. It can be understood that by dividing the frame driving data into M rows according to preset conditions, the row driving data corresponding to the M rows of phase shifting units 4 can be obtained; finally, the source driver converts the row driving data into driving voltage and transmits it to the row of phase shifting units 4. However, because the opening time of the switching element 5 is extremely short, this method can easily cause the phase shifting unit 4 to be unable to fully receive the driving voltage, which in turn causes the liquid crystal molecules inside to be unable to deflect or to be difficult to deflect to the correct angle, ultimately affecting the scanning speed of the antenna and resulting in insufficient flexibility of the antenna tracking beam.

[0054] In order to solve at least one of the technical problems existing in the related technologies, in one aspect, embodiments of this disclosure provide a driving control method for a phased array. Figure 4 This is a schematic diagram of the phased array disclosed herein, with reference to... Figure 2 and Figure 4 The phased array 2 disclosed herein includes at least one phase adjustment unit M1, wherein the phase adjustment unit M1 includes multiple gate lines 11 and multiple data lines 12. The gate lines 11 and data lines 12 intersect to define multiple phase shifting regions Z1, each phase shifting region Z1 being provided with a switching element 5 and a phase shifting unit 4, and as shown... Figure 2 As shown, switching elements 5 located in the same row are connected to the same gate line 11, and switching elements 5 located in the same column are connected to the same data line 12. The phased array driving control method provided in this disclosure includes: controlling the driving process of each phase adjustment unit M1; specifically, controlling any one phase adjustment unit M1 includes: controlling each phase shifting unit 4 in the phase adjustment unit M1 to be written with a row-by-row driving voltage; more specifically, controlling any row of phase shifting units 4 to be written with a driving voltage includes: in response to the data line 12 being written with a driving voltage, controlling the gate driver to provide a scan signal to the gate line.

[0055] In the process of controlling the writing of a driving voltage to any row of phase shifting units 4, this embodiment of the present disclosure adopts a control method of "providing a scanning signal to the gate line 11 after responding to the driving voltage being written to the data line 12". That is, by writing the pre-prepared driving voltage onto the data line 12 and applying it directly to the phase shifting unit 4 after the switching element 5 is turned on, compared with the common driving process of "first turning on the switching element 5 of a row, then transmitting the driving data of that row to the source driver, the source driver converting the driving data into a driving voltage, writing it onto the corresponding data line 12 of that row, and applying it to the phase shifting unit 4", it has at least the following beneficial effects: On the one hand, it can avoid the problem that the driving voltage cannot be fully applied to the phase shifting unit 4 due to the short opening time of the switching element 5. For liquid crystal phased arrays, it can avoid the problem that the liquid crystal molecules in the phase shifting unit 4 cannot be deflected to the correct angle, thus affecting the phase shifting effect. On the other hand, this can correspondingly shorten the opening time of the switching element 5, thereby increasing the phase shifting speed of the phased array 2, thereby improving the beam flexibility of the phased array antenna.

[0056] In other examples, the phased array 2 may include multiple phase adjustment units M1, such as Figure 4As shown, at this time, the above-mentioned "controlling each phase adjustment unit M1" includes: synchronously controlling the phase shifting unit 4 in each phase adjustment unit M1 to be written with the driving voltage row by row. In this example, synchronously controlling the phase shifting unit 4 in each phase adjustment unit M1 to be written with the driving voltage row by row can ensure that multiple phase adjustment units M1 can complete beam phase adjustment simultaneously and quickly, thereby improving the beam scanning speed and beam tracking flexibility of the phased array antenna.

[0057] For the above example, which includes multiple phase adjustment units M1, preferably, the circuit traces in each phase adjustment unit M1 can be designed with copper plating to reduce transmission loss; in addition, the lengths of the gate lines 11 in each phase adjustment unit M1 should be kept as consistent as possible, for example, the difference in length between the gate lines 11 should not be greater than 10mm, and the lengths of the data lines 12 in each phase adjustment unit M1 should be as similar as possible. This can ensure that the impedance of signal transmission in each phase adjustment unit M1 is the same, thereby ensuring the consistency of signal transmission delay and improving the synchronization between each phase adjustment unit M1.

[0058] Figure 5 This is a flowchart of the phased array drive control method provided in this disclosure. The following section will combine... Figure 5 This paper will introduce the control method in detail, taking the control of any one phase adjustment unit M1 as an example. Figure 5 As shown, the phased array drive control method provided in this disclosure is implemented by a timing controller (TCON).

[0059] First, before the timing controller controls each phase shifting unit 4 in the phase adjustment unit M1 to be written with the drive voltage line by line, it first receives frame drive data through the LVDS interface according to the LVDS interface protocol.

[0060] LVDS (Low Voltage Differential Signal) refers to signals that use differential signals to transmit data. Therefore, the LVDS interface is a type of differential signal transmission interface. Specifically, the LVDS interface uses the voltage difference between the "Pair+" and "Pair-" signal lines in a differential pair to represent data. When the voltage difference is positive (V[Pair+] - V[Pair-] > 0), it represents the data "1", and when the voltage difference is negative (V[Pair+] - V[Pair-] < 0), it represents the data "0". Compared to other types of differential signals, LVDS signals have the characteristics of high transmission rate, strong anti-interference, low noise, low power consumption, and long transmission distance. Therefore, transmitting frame drive data in the form of LVDS signals through the LVDS interface has the advantages of high speed, high accuracy, and low power consumption, which helps to reduce the cost of cables and connectors and can also improve the scanning speed of phased array antennas.

[0061] Next, in response to the frame drive data, the frame drive data is transmitted to the source driver line by line through the Mini-LVDS interface in accordance with the Mini-LVDS interface protocol.

[0062] Those skilled in the art will understand that frame-driven data can be decomposed into multiple lines of drive data based on the number of rows in the phase-shifting unit 4. Controlling any phase adjustment unit M1 includes controlling the phase-shifting unit 4 in that phase adjustment unit M1 to be written with drive voltage line by line. Before controlling the phase-shifting unit 4 to be written with drive voltage line by line, the frame-driven data needs to be transmitted line by line to the source driver via the Mini-LVDS interface according to the Mini-LVDS interface protocol. The Mini-LVDS (Mini Low Voltage Differential Signal) signal is similar to the LVDS signal, also transmitting data using differential signal pairs consisting of positive and negative signal pairs. The Mini-LVDS interface is mainly used between the timing controller and the source driver. Similar to the LVDS interface, the Mini-LVDS interface also transmits data signals using differential signal pairs. Besides its advantages of high-speed transmission, low power consumption, and strong electromagnetic interference resistance, the Mini-LVDS interface also reduces the number of signal pairs and simplifies circuit design, thereby further reducing costs.

[0063] Next, the source driver receives a line of drive data transmitted by the timing controller through the Mini-LVDS interface according to the Mini-LVDS interface protocol. After the source driver receives a line of drive data, it converts the received line of drive data into a drive voltage and writes the drive voltage onto data line 12.

[0064] Specifically, the aforementioned "controlling the source driver to receive a line of drive data transmitted by the timing controller through the Mini-LVDS interface according to the Mini-LVDS interface protocol, and after the source driver receives a line of drive data, causing the source driver to convert the received line of drive data into a drive voltage and write the drive voltage onto data line 12" includes:

[0065] Step S1: Control the TP1 signal of the source driver to be at the working level for a first preset time, so that the source driver receives drive data and latches it in the data register of the source driver.

[0066] Step S2: After the TP1 signal is kept at the working level for a first preset time, the TP1 signal is controlled to be at the non-working level so as to transfer the drive data in the data register to the digital-to-analog converter. After being converted into a drive voltage by the digital-to-analog converter, the drive voltage is written onto the data line 12.

[0067] The source driver's functional modules include digital and analog sections. The digital section mainly includes bidirectional shift registers, line buffers, and level shifters; the analog section mainly includes a digital-to-analog converter (DAC), buffers, and an output multiplexer. The bidirectional shift registers are configured to adjust the data transmission direction under the control of the input data shift direction signal SHL / DIR; typically, there are two data transmission directions, corresponding to SHL=H and SHL=L respectively. The line buffer includes a first line latch at the input and a second line latch at the output. The first and second line latches operate in parallel. Under the control of the TP1 signal, the first line latch sequentially receives each line of data and simultaneously transfers it to the second line latch for latching, before transferring it to the next stage of the circuit. In this context, the TP1 signal refers to the data transmission control signal. Typically, the rising edge of the TP1 signal indicates that the data signal is latched into the second data register, and the falling edge indicates that the data signal latched in the second data register is released to the next stage circuit, which is usually a level converter. The function of the level converter is to convert the digital data voltage in the data buffer into another digital data voltage; for example, converting the 3.3V data voltage output from the second data register into a 15V data voltage. Then, the data signal output by the level converter is transmitted to the digital-to-analog converter (DAC) in the analog section. The main function of the DAC is to convert the digital data signal into a corresponding analog voltage data signal. In this disclosure, the DAC's function is to convert the drive data received by the source driver into the corresponding drive voltage.

[0068] In some examples, in step S1 above, the operating level of the TP1 signal is high, and the non-operating level is low, with a first preset time of 1μs. In this case, the specific operation of step S1 is as follows: the TP1 signal of the source driver is controlled to be high for 1μs, so that the first data register receives a row of drive data and transfers it to the second data register for latching. The specific operation of step S2 is as follows: after the source driver stores the drive data in the second data register, that is, after the TP1 signal of the source driver remains high for 1μs, the TP1 signal of the source driver is controlled to be low, so that the drive data latched in the second data register is transmitted to the digital-to-analog converter (DAC), converted into the corresponding drive voltage by the DAC, and written into the data line 12 connected to the row switching element 5.

[0069] Finally, for any row phase shifting unit 4, in response to the data line 12 being written with a drive voltage, the control gate driver provides a scan signal to the gate line 11, causing the row switching element 5 to turn on, so that the row phase shifting unit 4 reads the drive voltage on the data line 12.

[0070] Gate drivers, also known as scan driver integrated circuits or row driver integrated circuits, are used to turn on the array of switching elements 5 row by row. Under the control of control signals, they cooperate with source drivers to input the driving voltage of the turned-on row to the corresponding phase-shifting unit 4. Common control signals for gate drivers include STV (Start Vertical), CPV (Clock Pulse Vertical), and OE (Output Vertical). The signal includes the Enable signal, etc., where STV is the frame scan start signal, representing the start of a frame scan; CPV is the vertical clock pulse signal, which is the clock signal of the gate driver and controls the activation of the row scan signal. One CPV cycle represents the output of one row scan signal; OE is the output enable signal of the gate driver, and its setting affects the output waveform of the scan signal. When OE is "1", all output signals of the gate driver are low level, and when OE is "0", all output signals of the gate driver are high level. In addition, the high and low levels of the row output signal of the gate driver are represented by Vgh and Vgl, respectively. Those skilled in the art will understand that the switching element 5 can be a thin film transistor. According to the characteristics of thin film transistors, they can be divided into N-type and P-type. For N-type thin film transistors, when the gate input is high level Vgh, the source and drain are turned on, while for P-type thin film transistors, when the gate input is low level Vgl, the source and drain are turned on. The following example uses an N-type thin film transistor as an example. It can be imagined that using a P-type thin film transistor is something that those skilled in the art can easily think of without creative effort, and therefore it is also within the protection scope of the embodiments of this disclosure.

[0071] Typically, the functional circuitry inside a gate driver includes logic control circuitry, a bidirectional shift register, a level shifter, and an output buffer. The bidirectional shift register is used to determine the output direction of the row scan signal. The level shifter is configured to perform level conversion, for example, converting the digital 0V low level DVss and 3.3V high level DVdd input to the bidirectional shift register into a low level of approximately -8V Vgl and a high level of approximately 30V Vgh, respectively. The output buffer is used to increase the driving capability of the row scan signal through an analog buffer amplifier.

[0072] In some examples, the aforementioned "controlling the gate driver to provide a scan signal to the gate line 11" specifically includes: controlling the CPV signal of the gate driver to be at a working level for a second preset time, and controlling the OE signal of the gate driver to be at a working level for a third preset time, so as to provide a scan signal to the gate line 11, causing the switching element 5 connected to the gate line 11 to open for the third preset time. For example, Figure 6 The following shows the timing relationship of each signal of the gate driver, as follows: Figure 6 As shown, STV is the frame start signal, indicating the start of a frame scan, and its rising edge is valid; the CPV signal is also valid on the rising edge; for the N-type thin-film transistor used in this disclosure, the OE signal is valid on the falling edge. In some examples, the frame rate of the phased array is 200fps, and the scan time of each phase adjustment unit M1 per frame should be limited to within 5ms. Each phase adjustment unit M1 includes 74 gate lines 11 and 74 data lines 12, and the scan time of each line should be limited to within 65μs. At this time, when the first rising edge of the CPV signal arrives after the rising edge of the STV signal and lasts for 2μs, the falling edge of the OE signal arrives, and the first row scan signal begins to be output (Output1). Since the OE signal is a falling edge, Output1 is at a high level Vgh. Subsequently, when the second rising edge of the CPV signal arrives and lasts for 2μs, the falling edge of the OE signal arrives, and the second row scan signal begins to be output (Output2). Similarly, since the OE signal is a falling edge, Output2 is also at a high level Vgh. This process continues, providing scan signals to each gate line 11 row by row, causing the switching element 5 to turn on row by row, and causing the phase shifting unit 4 to read the drive voltage on the data line 12 row by row. Specifically, the period of the CPV signal should be limited to 65μs, and its rising edge can last for 9μs, that is, the second preset time can be 9μs. Figure 6 As shown, the CPV signal is pulled low after a rising edge lasts for 9μs, and enters the second cycle after a falling edge lasts for 56μs; the third preset time can be 60μs, that is, the OE signal is pulled high after a falling edge lasts for 60μs, to provide a high level Vgh for 60μs for the gate line 11. For example, the high level Vgh corresponding to the switching element 5 provided in this disclosure is 24V, and the low level Vgl is -8V.

[0073] In this embodiment, by employing a drive control method that "first transmits the row drive data to the source driver, the source driver converts the row drive data into a corresponding drive voltage and writes it to the data line 12; then provides a scan signal to the gate line 11 to open the switching element 5 and apply the drive voltage to the phase shifting unit 4", the pre-prepared drive voltage is latched on the data line 12 and directly released to the phase shifting unit 4 after the switching element 5 is opened. Compared with related technologies, this method has at least the following advantages: On the one hand, it avoids the driving voltage from being unable to be fully applied to the phase shifting unit 4 due to the short opening time of the switching element 5, thereby preventing the liquid crystal molecules in the phase shifting unit 4 from being unable to deflect to the correct angle and affecting the phase shifting effect; on the other hand, it can correspondingly shorten the opening time of the switching element 5, thereby increasing the phase shifting speed of the liquid crystal phased array 2 and thus improving the beam flexibility of the liquid crystal phased array antenna.

[0074] Secondly, based on the same inventive concept, this disclosure provides a timing controller (TCON) that uses the control method provided in the first aspect to achieve drive control of the phased array.

[0075] Thirdly, based on the same inventive concept, embodiments of this disclosure provide a method for driving a phased array. A phased array, such as... Figure 4 As shown, it includes at least one phase adjustment unit M1, and the phase adjustment unit M1 includes multiple gate lines 11 and multiple data lines 12; as Figure 2 As shown, the grid line 11 and the data line 12 intersect to define multiple phase shifting regions Z1; each phase shifting region Z1 is provided with a switching element 5 and a phase shifting unit 4; the switching elements 5 located in the same row are connected to the same grid line 11, and the switching elements 5 located in the same column are connected to the same data line.

[0076] Figure 7 This is a flowchart of the phased array driving method provided in this disclosure. Figure 7 As shown, the phased array driving method provided in this disclosure includes:

[0077] First, the timing controller receives frame drive data through the LVDS interface according to the LVDS interface protocol, and then transmits the frame drive data line by line to the source driver through the Mini-LVDS interface according to the Mini-LVDS interface protocol.

[0078] LVDS signals are characterized by high transmission rate, strong anti-interference capability, low noise, low power consumption, and long transmission distance. Therefore, transmitting frame-driven data in LVDS signal form via an LVDS interface offers advantages such as high speed, high accuracy, and low power consumption, helping to reduce the cost of cables and connectors and improving the scanning speed of phased array antennas. Furthermore, in addition to high-speed transmission, low power consumption, and strong electromagnetic interference resistance, the Mini-LVDS interface also reduces the number of signal pairs and simplifies circuit design, further reducing costs.

[0079] Next, for any row of driving data, the TP1 signal of the source driver is controlled to be at the working level for a first preset time, so that the first data register of the source driver receives the row of driving data and transfers the driving data to the second data register for latching. After the TP1 signal is kept at the working level for the first preset time, it is set to the non-working level, so that the second data register in the source driver releases the latched driving data to the digital-to-analog converter. The digital-to-analog converter converts the driving data into a driving voltage based on the gamma reference voltage provided by the gamma voltage module and writes it onto the data line 12. For example, the first preset time can be 1 μs, and the operating level of the TP1 signal is high. That is, the TP1 signal controlling the source driver is high for 1 μs, causing the first data register of the source driver to receive the line of drive data and transfer the drive data to the second data register for latching. After the TP1 signal remains high for 1 μs, it is set to low, causing the second data register in the source driver to release the latched drive data to the digital-to-analog converter. The digital-to-analog converter converts the drive data into a drive voltage based on the gamma reference voltage provided by the gamma voltage module and writes it onto data line 12. In addition, in some examples, the gamma voltage module, in addition to providing the gamma reference voltage to the source driver, is also responsible for providing a common voltage VCOM to the reference electrode 103 in the phase shifting unit 4 to improve the accuracy of the drive voltage applied to the phase shifting unit 4.

[0080] Finally, in response to the first control signal, the gate driver provides a scan signal to the gate line 11 to turn on the switching element 5, controlling the phase shifting unit 4 to phase-shift the received microwave signal; wherein, the first control signal is the control signal output by the timing controller in response to the data line 12 being written with a drive voltage; "the gate driver provides a scan signal to the gate line 11 in response to the first control signal to turn on the switching element 5" as shown in the example. Figure 6As shown, specifically, this includes: setting the CPV signal of the gate driver to the operating level for a second preset time (e.g., rising edge lasting 9μs), and setting the OE signal to the operating level for a third preset time (e.g., falling edge lasting 60μs) after the rising edge of the CPV signal lasts for 2μs, causing the gate driver to provide a scan signal (e.g., high level Vgh) to the gate line 11, turning on the switching element 5 connected to the gate line 11 for the third preset time (60μs), during which a driving voltage is applied to the phase shifting unit 4 to control the phase shifting unit 4 to phase shift the received microwave signal. Specifically, the period of the CPV signal should be limited to 65μs, and its rising edge can last 9μs, that is, the second preset time can be 9μs, as shown. Figure 6 As shown, the CPV signal is pulled low after a rising edge lasts for 9μs, and enters the second cycle after a falling edge lasts for 56μs; the third preset time can be 60μs, that is, the OE signal is pulled high after a falling edge lasts for 60μs, to provide a high level Vgh for 60μs for the gate line 11. For example, the high level Vgh corresponding to the switching element 5 provided in this disclosure is 24V, and the low level Vgl is -8V.

[0081] Similarly, in the above embodiments, by adopting the driving method of "providing a scanning signal to the gate line 11 after responding to the data line 12 being written with a driving voltage," that is, by writing the pre-prepared driving voltage onto the data line 12 and directly applying it to the phase shifting unit 4 after the switching element 5 is turned on, compared with the common driving process of "first turning on a row of switching elements 5, then transmitting the driving data of that row to the source driver, and the source driver converting the driving data into a driving voltage, writing it onto the corresponding data line 12 of that row, and applying it to the phase shifting unit 4," at least the following beneficial effects are achieved: On the one hand, it can avoid the problem that the driving voltage cannot be fully applied to the phase shifting unit 4 due to the short opening time of the switching element 5. For liquid crystal phased arrays, it can avoid the problem that the liquid crystal molecules in the phase shifting unit 4 cannot be deflected to the correct angle, thus affecting the phase shifting effect. On the other hand, this can correspondingly shorten the opening time of the switching element 5, thereby increasing the phase shifting speed of the phased array 2, and thus improving the beam flexibility of the phased array antenna.

[0082] Fourthly, based on the same inventive concept, embodiments of this disclosure provide a phased array driving system, which includes a timing controller, a source driver, a gate driver, and a gamma voltage module. The driving system uses the driving method provided in the third aspect above to drive the phased array.

[0083] Those skilled in the art will understand that the phased array driving system provided in this disclosure also includes a power management integrated circuit (PMIC), which is mainly used to provide the timing controller, gamma voltage module, source driver, and gate driver with their respective required digital or analog operating voltages. For example, the power management integrated circuit is responsible for providing the digital operating voltage DVdd to the timing controller, source driver, and gate driver. Typically, DVdd is generated by the Buck circuit and LDO (Low Dropout) circuit in the power management integrated circuit; it is also responsible for generating the reference voltage AVdd for the gamma voltage module. Typically, AVdd is generated by the Boost circuit in the power management integrated circuit; in addition, it is responsible for generating high-level voltages Vgh and Vgl for the switching element 5 to turn on and off.

[0084] It is understood that the above embodiments are merely exemplary implementations used to illustrate the principles of the present invention, and the present invention is not limited thereto. For those skilled in the art, various modifications and improvements can be made without departing from the spirit and essence of the present invention, and these modifications and improvements are also considered to be within the scope of protection of the present invention.

Claims

1. A driving control method for a phased array, the phased array comprising at least one phase adjustment unit; the phase adjustment unit comprising multiple grid lines and multiple data lines; the grid lines and the data lines intersect to define multiple phase shifting regions; each phase shifting region is provided with a switching element and a phase shifting unit; the switching elements located in the same row are connected to the same grid line, and the switching elements located in the same column are connected to the same data line; in, The control method includes: controlling each of the phase adjustment units; Controlling any of the phase adjustment units includes: controlling the phase shifting unit to be written with a drive voltage line by line; For controlling any row of the phase shifting unit to be written with a drive voltage, the method includes: in response to the data line being written with the drive voltage, controlling the gate driver to provide a scan signal to the gate line.

2. The driving and control method for a phased array according to claim 1, wherein, Before the control phase-shifting unit is written with the drive voltage line by line, it also includes: In response to frame drive data, the frame drive data is transmitted line by line to the source driver so that the source driver converts the received drive data into drive voltage.

3. The phased array driving and control method according to claim 2, wherein, Before transmitting the frame-driven data line by line to the source driver in response to the frame-driven data, the method further includes: The frame-driven data is received via the LVDS interface in accordance with the LVDS interface protocol.

4. The phased array driving and control method according to claim 3, wherein, The data line is written with the driving voltage, including: The TP1 signal of the source driver is controlled to be at the working level for a first preset time, so that the source driver receives the driving data and latches it in the data register of the source driver; After the TP1 signal is kept at the working level for a first preset time, the TP1 signal is controlled to be at the non-working level, and the drive data in the data register is transmitted to the digital-to-analog converter. After being converted into the drive voltage by the digital-to-analog converter, the drive voltage is written to the data line.

5. The phased array driving and control method according to claim 4, wherein, The step of controlling the gate driver to provide a scan signal to the gate line includes: The CPV signal of the gate driver is controlled to be at the working level for a second preset time, and the OE signal of the gate driver is controlled to be at the working level for a third preset time, so as to provide a scan signal for the gate line, thereby turning on the switching element connected to the gate line for a third preset time.

6. The driving and control method for a phased array according to any one of claims 1-5, wherein, The phased array includes multiple phase adjustment units; The control of each of the phase adjustment units includes: The phase-shifting units in each phase adjustment unit are synchronously controlled to have their driving voltages written line by line.

7. A timing controller that uses the control method described in any one of claims 1-6 to control the driving of a phased array.

8. A driving method for a phased array, the phased array comprising at least one phase adjustment unit; the phase adjustment unit comprising multiple grid lines and multiple data lines; the grid lines and the data lines intersect to define multiple phase shifting regions; each phase shifting region is provided with a switching element and a phase shifting unit; the switching elements located in the same row are connected to the same grid line, and the switching elements located in the same column are connected to the same data line; in, The driving method includes: The timing controller receives frame drive data and transmits it to the source driver line by line; The source driver converts the received drive data into a corresponding drive voltage and writes it to the data line; In response to a first control signal, the gate driver provides a scan signal to the gate line to turn on the switching element and control the phase shifting unit to phase shift the received microwave signal; the first control signal is the control signal output by the timing controller in response to the data line being written with the drive voltage.

9. The phased array driving method according to claim 8, wherein, The source driver converts the received drive data into a corresponding drive voltage, including: Based on the gamma reference voltage provided by the gamma voltage module, the driving data is converted into the corresponding driving voltage.

10. The phased array driving method according to claim 9, wherein, The source driver converts the received drive data into a corresponding drive voltage and writes it to the data line, including: The TP1 signal of the source driver is set to the working level and held for a first preset time. The source driver receives the driving data and latches it in the data register of the source driver. After the TP1 signal is kept at the working level for a first preset time, it is set to the non-working level. The source driver transmits the drive data in the data register to the digital-to-analog converter. After being converted into the drive voltage by the digital-to-analog converter, the drive voltage is written to the data line.

11. The phased array driving method according to claim 10, wherein, The gate driver, in response to a first control signal, provides a scan signal to the gate line to turn on the switching element, including: The gate driver sets the CPV signal to the operating level for a second preset time, sets the OE signal to the operating level for a third preset time, and provides a scan signal to the gate line to turn on the switching element connected to the gate line for a third preset time.

12. A phased array driving system, wherein the phased array is driven by the driving method described in any one of claims 8-11.

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