Power line carrier communication data processing method and device

Abstract

The invention relates to the technical field of power line carrier communication, and particularly provides a power line carrier communication data processing method and device, and the method comprises the steps: carrying out the mapping of a plurality of target data through a first mapping rule, and writing the target data into a plurality of memories; in the reading stage of each iterative operation cycle, mapping the logic reading address according to a first mapping rule to obtain a physical reading address, and performing data reading on the corresponding target data according to the physical reading address; performing fast Fourier calculation according to the plurality of parallel radix-4 operation modules to obtain a calculation result; in a writing stage of a non-last iterative operation period, writing a calculation result back to an original physical address to cover original data according to a first mapping rule; and in the write-in stage of the last iterative operation period, generating a physical write-in address corresponding to the calculation result according to a second mapping rule, and writing the calculation result into the corresponding physical write-in address. According to the method, the calculation speed and the read-write speed are effectively improved, the processing time is shortened, and the timeliness is ensured.

Description

Technical Field

[0001] This invention relates to the field of power line carrier communication technology, and in particular to a power line carrier communication data processing method and apparatus. Background Technology

[0002] Power line communication (PLC) transmits data over power lines. In existing PLC systems, signal modulation is primarily achieved through Orthogonal Frequency Division Multiplexing (OFDM), while time-frequency conversion is performed using Fast Fourier Transform (FFT) or Inverse Fast Fourier Transform (FFT / IFFT). The amount of data processed in PLC FFT calculations is relatively large, typically around 1024 bytes. This large data volume increases processing time, leading to data loss and communication failure.

[0003] In existing technologies, the main approach is to use a single radix-4 arithmetic module to perform parallel data read and write operations from four single-port read / write memories. This method has relatively slow computation and read / write speeds, resulting in long data processing times for Fast Fourier Transform (FFT) calculations, which cannot meet the requirements of next-generation power line carrier communication. Summary of the Invention

[0004] The power line carrier communication data processing method and apparatus provided in this invention at least solve the problem of long processing time required by existing data processing methods, effectively improve the calculation speed and read / write speed, shorten the processing time, and meet the timeliness requirements of power line carrier communication.

[0005] In a first aspect, the present invention provides a power line carrier communication data processing method, comprising the steps of: storing multiple target data according to their original natural order, mapping their addresses according to a first mapping rule, and writing them into multiple memories, so that the physical addresses of the multiple target data read by multiple parallel radix-4 operation modules are distributed in different memories; in the reading phase of each iterative operation cycle, mapping the logical reading addresses generated by the multiple parallel radix-4 operation modules according to the first mapping rule to obtain physical reading addresses, and reading the corresponding multiple target data according to the physical reading addresses; wherein, the physical reading addresses are configured to distribute the physical addresses of the multiple target data to be read in a single reading phase in different memories; according to the multiple parallel radix-4 operation modules The block performs Fast Fourier Transform (FFT) calculations to obtain calculation results for multiple target data. The calculation results of the last iteration cycle are arranged in bit-reverse order. During the write phase of non-last iteration cycles, the calculation results are written back to the original physical address according to the first mapping rule, overwriting the original data before calculation at the original physical address. During the write phase of the last iteration cycle, a physical write address corresponding to the calculation result is generated according to the second mapping rule, and the calculation result is written to the corresponding physical write address. The second mapping rule is configured to adjust the intra-group mapping relationship of the memory, optimizing the distribution of the calculation results in multiple memories, so that during subsequent reading according to the original natural order, parallel, conflict-free access to multiple calculation results can be achieved in a single read phase.

[0006] In one embodiment of the present invention, multiple target data stored according to their original natural order are written into multiple memories after address mapping using a first mapping rule. The steps include: calculating the mapped physical address based on the logical sequence number of the target data in the original natural order using the first mapping rule; wherein the physical address includes a storage group index, a memory index, and a memory address index; the multiple memories are divided into multiple storage groups, each storage group includes four memories, and each memory includes multiple memory addresses; and the target data is stored in the physical address corresponding to the logical sequence number.

[0007] In one embodiment of the present invention, the physical address mapped according to the logical sequence number of the target data in the original natural order is calculated by the first mapping rule, including the steps of: representing the logical sequence number in binary and dividing it into multiple fields with a fixed number of bits; calculating the storage group index by a modulo algorithm based on the sum of the fields of the first field group of the logical sequence number; wherein the first field group includes a first preset number of multiple high-order fields; calculating the storage index by a modulo algorithm based on the sum of the fields of the second field group of the logical sequence number; wherein the second field group includes the first field group and the low-order fields adjacent to the first field group; and using a second preset number of bits of the ten-bit binary representation of the logical sequence number as the storage address index.

[0008] In one embodiment of the present invention, the number of radix-4 operation modules, the number of storage groups, and the number of memories in each storage group are all set to 4. The iteration operation cycle is four parallel iteration cycles of radix-4 fast Fourier transform calculations. The storage group index is calculated using a modulo algorithm based on the sum of the fields in the first field group of the logical index, and is expressed as follows: In the formula, For the storage group index, The first logical number in binary representation The position and the first Bit, , , and For the first field group, "" indicates the sum of the corresponding fields; based on the sum of the fields in the second field group of the logical sequence number, the memory index is calculated using a modulo algorithm, and is expressed as: In the formula, For the memory index, The lower-order field adjacent to the first field group; the first 6 high-order bits of the logical sequence number are used as the storage address index, represented as .

[0009] In one embodiment of the present invention, during the writing phase of a non-last iteration operation cycle, the calculation result is written back to the original physical address according to the first mapping rule, overwriting the original data before the calculation at the original physical address. This includes the following steps: obtaining the logical read address of the target data corresponding to the calculation result of the current iteration operation cycle; calculating the logical read address according to the first mapping rule to obtain the original physical address that is consistent with the corresponding physical read address; and writing the calculation result to the corresponding original physical address, overwriting the original data at the original physical address.

[0010] In one embodiment of the present invention, during the write phase of the last iteration operation cycle, a physical write address corresponding to the calculation result is generated according to a second mapping rule, and the calculation result is written to the corresponding physical write address. This includes the steps of: obtaining the logical read address of the target data corresponding to the calculation result of the last iteration operation cycle; calculating the logical read address according to the second mapping rule to obtain the physical write address; wherein the physical write address is configured to distribute the physical addresses of the calculation results of multiple target data to be read in a single read phase across different memories, and the physical write address includes a write memory group index, a write memory index, and a write memory address index; and writing the calculation result according to the corresponding physical write address.

[0011] In one embodiment of the present invention, the physical write address is obtained by calculating the logical read address according to the second mapping rule, including the following steps: representing the logical read address in binary and dividing it into multiple fields with a fixed number of bits; calculating the write memory group index by using a modulo algorithm based on the sum of the fields of the first field group of the logical read address; wherein the first field group includes a first preset number of multiple high-order fields; calculating the write memory index by using a modulo algorithm based on the sum of the fields of the third field group of the logical read address; wherein the third field group includes the first field group, the highest-order field in the first field group, and the low-order field adjacent to the first field group; and using a second preset number of bits of the ten-bit binary representation of the logical read address as the write memory address index.

[0012] In one embodiment of the present invention, the memory index is calculated using a modulo algorithm based on the sum of the fields in the third field group of the logical sequence number, and is expressed as follows: In the formula, For the memory index, The first logical read address in binary representation The position and the first Bit, The highest-order field in the first field group, "" indicates that the sum of the corresponding fields is calculated.

[0013] In one embodiment of the present invention, before writing multiple target data stored according to their original natural order into multiple memories after address mapping according to a first mapping rule, the method further includes the step of: calculating the total number of iterations in the iterative operation cycle based on the total number of the target data, expressed as: ， In the formula, The total number of iterations, The total number of target data; based on the total number of iterations, calculate the number of butterfly operation groups and the inter-butterfly data index difference in each iteration operation cycle, expressed as: , In the formula, For the first The number of butterfly operation groups in each of the aforementioned iterative operation cycles. The loop variable for the iteration operation period. , For the first The inter-butterfly data index difference for each of the aforementioned iterative operation cycles; the intra-butterfly data index difference is calculated based on the inter-butterfly data index difference, expressed as: In the formula, For the first The intra-butterfly data index difference for each of the iterative operation cycles; the logical read address is determined based on the number of butterfly operation groups, the inter-butterfly data index difference, and the intra-butterfly data index difference.

[0014] Secondly, the present invention also provides a power line carrier communication data processing apparatus, applied to the power line carrier communication data processing method as described in any one of the above claims, comprising: a first module, configured to write multiple target data stored according to their original natural order into multiple memories after address mapping according to a first mapping rule, so that the physical addresses of the multiple target data read by multiple parallel radix-4 operation modules are distributed in different memories; a second module, configured to, in the reading phase of each iterative operation cycle, map the logical reading addresses generated by the multiple parallel radix-4 operation modules according to the first mapping rule to obtain physical reading addresses, and read the corresponding multiple target data according to the physical reading addresses; wherein, the physical reading addresses are configured to distribute the physical addresses of the multiple target data to be read in a single reading phase in different memories; a third module, The module is used to perform Fast Fourier Transform calculations based on multiple parallel radix-4 operation modules to obtain calculation results for multiple target data; wherein the calculation results of the last iteration operation cycle are arranged in reverse bit order; the fourth module is used to write the calculation results back to the original physical address according to the first mapping rule during the write phase of non-last iteration operation cycles, overwriting the original data before the calculation at the original physical address; the fifth module is used to generate the physical write address corresponding to the calculation result according to the second mapping rule during the write phase of the last iteration operation cycle, and write the calculation result to the corresponding physical write address; wherein the second mapping rule is configured to adjust the intra-group mapping relationship of the memory, optimize the distribution of the calculation results in multiple memories, so that when reading according to the original natural order in a subsequent reading phase, parallel and conflict-free access to multiple calculation results can be achieved in a single reading phase.

[0015] Compared with the prior art, the above-described technical solution of the present invention has the following advantages:

[0016] The power line carrier communication data processing method described in this invention utilizes multiple parallel radix-4 operation modules in conjunction with multiple memories to achieve parallel reading or writing. Essentially, the power line carrier communication data processing method described in this embodiment of the invention still employs radix-4 operations, requiring no significant modifications to the existing radix-4 operation architecture. Compared to existing radix-4 operation methods, it effectively improves computation speed. Simultaneously, compared to radix-16 operation methods, it effectively reduces hardware resource consumption. Furthermore, different mapping rules are employed for different iterative operation cycles. The first mapping rule ensures that the data to be read or written each time is distributed across different memories, achieving efficient read / write operations; the second mapping rule ensures that the reverse calculation results after the Fast Fourier Transform calculation are distributed across different memories, so that multiple final calculation results to be read can be retrieved simultaneously within one clock cycle during subsequent readings. Thus, the overall data processing time is effectively shortened, meeting the timeliness requirements of power line carrier communication. Attached Figure Description

[0017] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the accompanying drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are merely some embodiments of the present invention. For those skilled in the art, other embodiments can be obtained based on these drawings without creative effort. In the drawings:

[0018] Figure 1 This is a flowchart illustrating the power line carrier communication data processing method in a preferred embodiment of the present invention.

[0019] Figure 2 This is a schematic diagram of the target data location stored according to the original natural order in a preferred embodiment of the present invention.

[0020] Figure 3 This is a schematic diagram of the target data that needs to be read for the Fast Fourier Transform calculation in the first iteration cycle of the preferred embodiment of the present invention.

[0021] Figure 4 This is a schematic diagram of the target data location after being processed by the first rule mapping before the first iteration operation cycle in a preferred embodiment of the present invention.

[0022] Figure 5 This is a schematic diagram of the target data location after being processed by the first rule mapping before the last iteration operation cycle in a preferred embodiment of the present invention.

[0023] Figure 6 This is a schematic diagram of the target data that needs to be read for the Fast Fourier Transform calculation in the last iteration cycle of the preferred embodiment of the present invention.

[0024] Figure 7 This is a schematic diagram showing the location of the calculation results after data processing in a preferred embodiment of the present invention.

[0025] Figure 8 This is a schematic diagram showing the position of the calculation result after processing by reversing the formula in a preferred embodiment of the present invention.

[0026] Figure 9 This is a schematic diagram of the target data location after processing according to the first mapping rule during the writing stage of the last iteration operation cycle in a preferred embodiment of the present invention.

[0027] Figure 10 This is a schematic diagram of the target data location after processing according to the second mapping rule during the writing stage of the last iteration operation cycle in a preferred embodiment of the present invention.

[0028] Figure 11 This is a schematic diagram of the structure of the power line carrier communication data processing device in a preferred embodiment of the present invention.

[0029] Figure 12 This is a schematic diagram of the structure of an electronic device in a preferred embodiment of the present invention.

[0030] The above-mentioned figures include the following reference numerals: 11, first module; 12, second module; 13, third module; 14, fourth module; 15, fifth module; 16, sixth module; 201, computing unit; 202, ROM; 203, RAM; 204, bus; 205, I / O interface; 206, input unit; 207, output unit; 208, storage unit; 209, communication unit. Detailed Implementation

[0031] Embodiments of the present invention will now be described in more detail with reference to the accompanying drawings. While some embodiments of the invention are shown in the drawings, it should be understood that the invention can be implemented in various forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided to provide a more thorough and complete understanding of the invention. It should be understood that the accompanying drawings and embodiments are for illustrative purposes only and are not intended to limit the scope of protection of the invention.

[0032] It should be noted that, in the existing technology, fast Fourier transform calculations for power line communication mainly use one radix-4 operation module, combined with four single-port read / write memories.

[0033] A single-port read / write memory contains a separate set of address lines, data lines, and control signals, and can only perform one read or write operation at a time through a single port. Therefore, compared to setting up a single 4-port read / write memory, setting up four single-port read / write memories can effectively reduce hardware complexity and resource consumption.

[0034] Taking the processing of 16 target data as an example, during the calculation process, each target data is sequentially stored in four single-port read / write memories. Before the Fast Fourier Transform (FFT) processing, data needs to be read in parallel from the four single-port read / write memories; after the FFT processing, data needs to be written in parallel from the four single-port read / write memories.

[0035] With the development of technology, the requirements for rapid data processing in power line carrier communication are becoming increasingly stringent. Faced with massive amounts of data, data processing methods based on radix-4 Fast Fourier Transform (FFT) calculations are no longer sufficient to meet the demands of power line carrier communication.

[0036] Therefore, existing technologies also employ processing methods with higher radix counts, such as radix-16 Fast Fourier Transform (FFT). For example, one radix-16 operation module can be configured with 16 single-port read / write memories. Compared to radix-4 FFT calculation, radix-16 FFT calculation effectively improves computation speed. However, correspondingly, radix-16 FFT calculation consumes significant hardware resources, especially with a large number of multipliers.

[0037] To address the aforementioned problems, this invention provides a power line carrier communication data processing method that utilizes multiple parallel radix-4 arithmetic modules in conjunction with multiple memories to achieve parallel reading or writing. Compared to the existing radix-4 arithmetic method, this significantly improves computation speed. Furthermore, compared to the radix-16 arithmetic method, it effectively reduces hardware resource consumption.

[0038] The execution entity of the power line carrier communication data processing method described in this embodiment of the invention can be a digital signal processor, such as a certain processing chip; or it can be a combination of hardware and software to achieve simulation.

[0039] Specifically, refer to Figure 1 As shown, the power line carrier communication data processing method according to an embodiment of the present invention includes the following steps:

[0040] First, multiple target data stored according to their original natural order are mapped to addresses using a first mapping rule and then written into multiple memories, so that the physical addresses of the multiple target data read by multiple parallel radix-4 operation modules are distributed in different memories.

[0041] The target data can be either time-domain data or frequency-domain data. Time-domain data refers to the high-frequency signal transmitted over the power line, which is obtained by the receiver through radio frequency reception and processing. Frequency-domain data refers to the values ​​of the data to be transmitted at the transmitter, mapped to constellation points on each subcarrier.

[0042] Taking signal reception as an example, the receiving end can obtain a certain number of discrete target data by sampling the continuous signal within uniform time intervals. The number of target data items can be 1024.

[0043] After obtaining the target data, this data is initially stored in its original natural order. For example, storage can be implemented using a round-robin allocation method. Preferably, the memory is configured as a single-port read / write memory.

[0044] To ensure that the multiple target data read by the multiple parallel radix-4 operation modules are distributed in different memories during the subsequent fast Fourier transform operation, i.e., there will be no situation where two or more target data are distributed in one memory at the same time, it is necessary to first perform address mapping and rewrite of each target data according to the first mapping rule.

[0045] In memory, the address of data storage is usually represented by a binary number, i.e., a physical address. After obtaining the physical address corresponding to the target data through the first mapping rule, the target data is written into the corresponding memory according to the physical address to achieve storage.

[0046] Through address mapping and rewriting, multiple radix-4 operation modules can read data from multiple memories in parallel during subsequent iterations, requiring only one clock cycle for reading and writing data. Compared to the existing technology that uses one radix-4 operation module with four memories for data processing, this significantly improves data processing efficiency, shortens the processing time, and effectively meets the demand for processing large amounts of data in a short time in power line carrier communication. Furthermore, compared to radix-16 operation, it effectively reduces hardware resource consumption.

[0047] After completing the initial address mapping and rewriting, the Fast Fourier Transform (FFT) calculation can begin. Taking the processing of 1024 target data points as an example, with 16 single-port read / write memory modules and 4 parallel radix-4 operation modules, each operating in parallel, the FFT calculation requires 5 iterations. This effectively achieves radix-16 FFT computation.

[0048] Each iteration cycle includes a reading phase, a calculation phase, and a writing phase. Data is read in the reading phase, Fast Fourier Transform calculation is performed in the calculation phase, and the calculation results are written in the writing phase.

[0049] During the reading phase of each iterative operation cycle, the logical read addresses generated by multiple parallel radix-4 operation modules are mapped according to the first mapping rule to obtain the physical read addresses, and the corresponding multiple target data are read according to the physical read addresses.

[0050] The logical read address is the physical address in memory when the target data required by the radix-4 operation module is stored in its original natural order. For example, if 1024 data items from 0 to 1023 are stored in 16 memories using a round-robin allocation method, then data 0 is stored at the first memory address (bit 0) of the first memory (memory 0), and data 256 is stored at the seventeenth memory address (bit 16) of the first memory.

[0051] After mapping according to the first mapping rule, the physical address of the target data changes. Therefore, when reading data, it is also necessary to map the logical read address to ensure that the logical read address corresponds to the mapped target data.

[0052] In the reading phase of each iterative operation cycle, the logical read address of the required target data can be calculated based on the Fast Fourier Transform formula and the total number of target data, or it can be calculated in advance and called directly when needed.

[0053] Because the memory is a single-port read / write memory, each memory can only be read once through a single port during data retrieval. Therefore, the mapped physical read addresses are configured to distribute the physical addresses of multiple target data items to be read in a single read phase across different memories, ensuring that the corresponding target data can be read in parallel. This ensures that data can be read in parallel within one clock cycle, shortening data processing time.

[0054] After the required target data is read, the computation phase begins. During this phase, Fast Fourier Transform (FFT) calculations are performed using multiple parallel radix-4 operation modules to obtain the computation results for the target data. FFT calculations are common knowledge, and the specific computation steps will not be elaborated further.

[0055] In this process, the calculation results of the last iteration are arranged in bit-reversed order, meaning that the calculation results of the last iteration are in reverse order relative to the original natural order. When performing Fast Fourier Transform (FFT) calculations in the radix-4 module, a divide-and-conquer strategy is used. This strategy results in the index binary bits being reversed, meaning the final data output order is the base4 reverse of the original input address. Specifically, the address is represented in binary, with each two bits arranged in reverse order, satisfying the following reversal formula:

[0056] .

[0057] In the formula, This is the inverted address of the data, represented by ten binary bits. The first one in the original input address in binary representation The position and the first Bit.

[0058] Taking the ten-bit binary representation of decimal number 64 as an example: 00 01 00 00 00 That is, 00, That is, 01, That is, 00, That is, 00, That is, 00. Therefore, the corresponding The result is 00 00 00 01 00 in ten-bit binary, which is equivalent to number 4 after conversion. This means that the final calculation result corresponding to number 64 is actually stored in number 4, and the final calculation result corresponding to number 4 is actually stored in number 64.

[0059] Taking the ten-bit binary representation of the decimal number 866 as 11 01 10 00 10 as an example, That is, 11. That is, 01, That is, 10. That is, 00, That is, 10. Therefore, the corresponding The result is 10 00 10 01 11 in ten-bit binary, which is equivalent to number 551. This means that the final calculation result corresponding to number 866 is actually stored in number 551, and the final calculation result corresponding to number 551 is actually stored in number 866.

[0060] It should be noted that while existing technologies also offer storage methods for parallel reading of specified data points in G4FFT or G16FFT operations, when applying these methods to implement a G16FFT using four parallel G4 calculations, the reverse-order results after the Fast Fourier Transform (FFT) calculation cannot be read simultaneously without changing the final result reading method. This necessitates multiple clock cycles for reading, increasing the overall data processing time and failing to meet the timeliness requirements of power line carrier communication.

[0061] Therefore, in this embodiment of the invention, different mapping rules are adopted for different writing stages. Specifically, in the writing stage that is not the last iteration operation cycle, according to the first mapping rule, the calculation result is written back to the original physical address, overwriting the original data before the calculation at the original physical address.

[0062] The original physical address can be understood as the physical read address of the corresponding target data during the read phase. The calculation result overwrites the original data, and in the next iteration cycle, the calculation result is used as the target data for a new Fast Fourier Transform calculation.

[0063] Taking the processing of 1024 target data points, with 16 single-port read / write memories and 4 parallel radix-4 operation modules as an example, the Fast Fourier Transform (FFT) iterative operation requires 5 iterations. During the write phase of the first to fourth iteration cycles, the calculation results are written back to the original physical address to overwrite the original data using the first mapping rule.

[0064] Thus, in the reading phase of the next iteration operation cycle, the corresponding data can be read using the physical read address that is also mapped by the first mapping rule.

[0065] Unlike non-final iteration operation cycles, in the write phase of the final iteration operation cycle, the physical write address corresponding to the calculation result is generated according to the second mapping rule, and the calculation result is written to the corresponding physical write address. The second mapping rule is configured to adjust the intra-group mapping relationship of the memory and optimize the distribution of the calculation result across multiple memories, so that when reading according to the original natural order in subsequent cycles, parallel and conflict-free access to multiple calculation results can be achieved in a single read phase.

[0066] The final calculation result is in reverse order, but when reading the final result, it is required to retrieve the numbers in their original natural order. Therefore, in the existing architecture for reading the final calculation result, the inversion formula mentioned above needs to be used to reverse the original natural order of the numbers to obtain the reversed number. Then, after the last iteration cycle is completed, the physical address where the final calculation result is actually located is read according to the reversed number.

[0067] However, if the write phase of the last iteration cycle still maps the calculation result to the original physical address according to the first mapping rule, a problem will occur. Specifically, among the multiple final calculation results that need to be read in one clock cycle, several final calculation results may be located in the same memory. This means that it is impossible to read all these final results at once in one clock cycle.

[0068] Therefore, during the write phase of the final iteration operation cycle, a physical write address is generated using a second mapping rule, ensuring that the multiple final calculation results to be read in each clock cycle are distributed across different memories. This allows the subsequent read phase of the final calculation results to retrieve all the required results simultaneously within a single clock cycle, eliminating the need for multiple clock cycles and effectively shortening the overall data processing time, thus meeting the timeliness requirements of power line carrier communication.

[0069] In summary, the power line carrier communication data processing method of this invention utilizes multiple parallel radix-4 operation modules in conjunction with multiple memories to achieve parallel reading or writing. Essentially, the power line carrier communication data processing method described in this embodiment is still based on radix-4 operations, requiring no significant modifications to the existing radix-4 operation architecture. Compared to existing radix-4 operation methods, it effectively improves computation speed. Simultaneously, compared to radix-16 operation methods, it effectively reduces hardware resource consumption. Furthermore, different mapping rules are employed for different iterative operation cycles. The first mapping rule ensures that the data to be read or written each time is distributed across different memories, achieving efficient read / write operations. The second mapping rule ensures that the reverse calculation results after the Fast Fourier Transform calculation are distributed across different memories, so that multiple final calculation results to be read can be retrieved simultaneously within one clock cycle during subsequent readings. Thus, the overall data processing time is effectively shortened, meeting the timeliness requirements of power line carrier communication.

[0070] In some embodiments of the power line carrier communication data processing method of the present invention, before writing multiple target data stored according to their original natural order into multiple memories after address mapping according to a first mapping rule, the method further includes the following steps:

[0071] First, calculate the total number of iterations in the iterative operation cycle based on the total number of target data.

[0072] Secondly, based on the total number of iterations, calculate the number of butterfly operation groups and the difference in data index between butterflies in each iteration cycle.

[0073] Next, the intra-butterfly data index difference is calculated based on the inter-butterfly data index difference.

[0074] Finally, the logical read address is determined based on the number of butterfly operation groups, the difference in data index between butterflies, and the difference in data index within butterflies.

[0075] In this way, by calculating sequentially based on the total number of target data, the total number of iterations in the iterative operation cycle can be determined, as well as the number of butterfly operation groups, the inter-butterfly data index difference, and the intra-butterfly data index difference in each iteration cycle. When dealing with the same total number of target data, only one calculation is required, which can be reused in subsequent processes.

[0076] Specifically, the total number of iterations in the iterative operation cycle is calculated based on the total number of target data points, and is expressed as:

[0077] .

[0078] In the formula, This represents the total number of iterations. The total number of target data.

[0079] For example, the total number of target data If the value is 1024, then the total number of iterations is... It is 5.

[0080] Based on the total number of iterations, calculate the number of butterfly operation groups and the inter-butterfly data index difference in each iteration cycle, as follows:

[0081] .

[0082] .

[0083] In the formula, For the first The number of butterfly operation groups per iteration cycle. The loop variable is the cycle number for the iterative calculation, and it is an integer. , For the first The inter-butterfly data index difference in each iteration cycle can be understood as the distance between groups in each iteration.

[0084] For example, the total number of target data 1024, total number of iterations If it is 5, then The range is from 0 to 4. Correspondingly, =1, It is 4. It is 16. It is 64. It is 256; It is 1024. It is 256. It is 64. It is 16. The value is 4.

[0085] The intra-butterfly data index difference is calculated based on the inter-butterfly data index difference, and is expressed as:

[0086] .

[0087] In the formula, For the first The difference in the data index within each iteration cycle. The difference in the data index within each butterfly can be understood as the distance between points in each group of butterfly operations, and also the number of butterfly operations contained in each group.

[0088] For example, the total number of target data 1024, total number of iterations 5. From 0 to 4 For 1024, For 256, For 64, For 16, If it is 4, then It is 256. It is 64. It is 16. It is 4. The value is 1.

[0089] Taking 1024 target data items (numbers 0 to 1023) stored across 16 memory locations using a round-robin allocation method as an example, we can calculate the number of butterfly operation groups, the difference in data indices between butterflies, and the difference in data indices within butterflies. Thus, the 1024 target data items can be divided into 256 groups of four adjacent data items each, with each number within a group differing by 256. For example, the first group includes numbers 0, 256, 512, and 768.

[0090] The power line carrier communication data processing method of the present invention, in some embodiments, writes multiple target data stored according to their original natural order into multiple memories after address mapping according to a first mapping rule, including the following steps:

[0091] The physical address of the mapping is calculated based on the logical sequence number of the target data in the original natural order, using the first mapping rule.

[0092] The target data is stored in the physical address corresponding to the logical sequence number.

[0093] The physical address includes the memory group index, the memory index, and the memory address index. Multiple memories are divided into multiple memory groups, each memory group includes four memories, and each memory includes multiple memory addresses.

[0094] For example, there are 16 memory devices in total, divided into 4 groups of 4 memory devices, which can be labeled as group 0 to group 3. The memory devices within each memory group are labeled as device 0 to device 3, or the 16 memory devices can be directly labeled as device 0 to device 15.

[0095] When dealing with 1024 target data items numbered from 0 to 1023, each memory requires at least 64 memory addresses. For example, the target data items stored in memory 0 include numbers 0, 16, 32, 48, 64, ..., 1008; the target data items stored in memory 1 include numbers 1, 17, 33, 49, 65, ..., 1009; ...; and the target data items stored in memory 15 include numbers 15, 31, 47, 63, 79, ..., 1023.

[0096] The first mapping rule ensures that the target data to be read during the reading phase of each iteration cycle is distributed across different memories. In subsequent calculations, this data can be retrieved within a single clock cycle, achieving efficient reading, shortening the overall data processing time, and meeting the timeliness requirements of power line carrier communication.

[0097] Specifically, based on the logical sequence number of the target data in its original natural order, the physical address of the mapping is calculated using the first mapping rule, including the following steps:

[0098] First, the logical sequence number is represented in binary and divided into multiple fields with a fixed number of bits. The fixed number of bits can be set according to actual needs, for example, to 2.

[0099] Next, in the first aspect, the storage group index is calculated using a modulo algorithm based on the sum of the fields in the first field group of logical sequence numbers. The first field group includes a first preset number of high-order fields.

[0100] The initial preset number can be set according to actual needs. Taking the ten-bit binary representation of number 588 as 10 01 0011 00 as an example, with a fixed number of 2 digits, the ten-bit number can be divided into 5 fields: Field 5: 10, Field 4: 01, Field 3: 00, Field 2: 11, and Field 1: 00. If the initial preset number is set to 4, then Field 5: 10, Field 4: 01, Field 3: 00, and Field 2: 11 are all high-order fields.

[0101] The modulo algorithm can use the modulo-4 algorithm. For example, 17%4 = 4 remainder 1, so the storage group index is calculated to be 1, and the corresponding target data is stored in storage group 1. For reference, the decimal representation of binary 00 is 0, the decimal representation of binary 01 is 1, the decimal representation of binary 10 is 2, and the decimal representation of binary 11 is 3.

[0102] Taking 256 as an example, the ten-bit binary representation of 256 is 01 00 00 00 00. The sum of the fields in its first field group is 1, and 1%4 = 0 remainder 1, so the storage group index is 1. Therefore, the target data with the number 256, after processing, should be stored in storage group 1.

[0103] Binary calculations are relatively difficult for humans. To make them easier to understand, the two-bit binary representation can be converted to decimal representation before summation and modulo operations. The value obtained in this way is equal to the value obtained by direct calculation.

[0104] Secondly, the memory index is calculated using a modulo algorithm based on the sum of the fields in the second field group of logical sequence numbers. The second field group includes the first field group and the lower-order fields adjacent to the first field group.

[0105] The second preset quantity can be set according to actual needs. Taking the ten-bit binary representation of number 588 as 1001 00 11 00 as an example, with a fixed number of 2 bits, the tens digit divided into 5 fields, and the first preset quantity set to 4, its lower-order field is field one: 00.

[0106] The modulo algorithm can use the modulo-4 algorithm. For example, 17%4 = 4 remainder 1, so the memory index is calculated as 1, and the corresponding target data is stored in memory 1 of the corresponding memory group.

[0107] Taking 256 as an example, the sum of the fields in its second field group is also 1, resulting in a memory index of 1. Therefore, the target data with number 256, after processing, is to be stored in memory 1 of storage group 1.

[0108] In the third aspect, the second preset number of bits, represented by the ten-bit binary representation of the logical sequence number, is used as the storage address index.

[0109] The second preset quantity can be set according to actual needs. For example, the second preset quantity can be set to 6. Taking 256 as an example, the storage address index is 010000, which is 16 in decimal. That is to say, the target data with the number 256 is stored in the 16th position of device 1 in group 1 after processing.

[0110] In power line carrier communication, the amount of target data to be processed is typically 1024. Therefore, preferably, the number of radix-4 operation modules, the number of memory groups, and the number of memories in each memory group are all set to 4. The iteration cycle is four parallel radix-4 fast Fourier transform calculations.

[0111] Correspondingly, the storage group index is calculated using the modulo algorithm based on the sum of the fields in the first field group of the logical sequence number, and is represented as follows:

[0112] .

[0113] In the formula, For storage group indexes, The logical index in binary representation is the first The position and the first Bit, , , and For the first field group, " indicates that the sum of the corresponding fields is calculated. 4 indicates modulo 4.

[0114] Simultaneously, based on the sum of the fields in the second field group of the logical sequence number, the memory index is calculated using a modulo algorithm, and is represented as:

[0115] .

[0116] In the formula, For memory indexing, This is the lower-order field adjacent to the first field group.

[0117] Furthermore, the first 6 high-order bits of the 10-bit binary representation of the logical sequence number are used as the storage address index, represented as: .

[0118] In some other embodiments, the 16 memories can be directly divided into groups 0 to 15: memories 0 to 3 form group 0, memories 4 to 7 form group 1, memories 8 to 11 form group 2, and memories 12 to 15 form group 3. In this way, the physical address can be determined by the memory index and the memory address index.

[0119] In some embodiments of the power line carrier communication data processing method of the present invention, during the writing phase of a non-final iteration calculation cycle, the calculation result is written back to the original physical address according to a first mapping rule, overwriting the original data before the calculation at the original physical address, including the following steps:

[0120] First, obtain the logical read address of the target data corresponding to the calculation result of the current iteration cycle.

[0121] Secondly, the logical read address is calculated according to the first mapping rule to obtain the original physical address that is consistent with the corresponding physical read address.

[0122] Finally, the calculation results are written to the corresponding original physical address, overwriting the original data at the original physical address.

[0123] Taking the first iteration cycle as an example, before the first iteration cycle, each target data is adjusted by the first mapping rule. The physical addresses of the target data that the radix-4 operation module needs to read in the calculation stage are distributed in different memories.

[0124] For example, target data numbered 256, originally stored in bit 16 of device 0 in group 0, is now stored in bit 16 of device 1 in group 1 after mapping. After the target data numbered 256, together with other target data, performs a fast Fourier transform calculation to obtain the calculation result for the first iteration cycle, the calculation result needs to be written to bit 16 of device 1 in group 1.

[0125] However, without mapping, the address corresponding to the calculation result is still a logical read address. Therefore, it is necessary to process the logical read address using the first mapping rule to obtain the original physical address.

[0126] Taking target data number 256 as an example, the address of its corresponding calculation result is still bit 16 of device 0 in group 0. It needs to be processed by the first mapping rule to obtain bit 16 of device 1 in group 1. After obtaining bit 16 of device 1 in group 1, the calculation result of number 256 can be written to the corresponding position.

[0127] In the writing phase of non-final iteration operation cycles, the steps for writing the calculation results are similar to the steps for calculating the physical address mapped by the logical sequence number through the first mapping rule, and will not be repeated here.

[0128] The first mapping rule ensures that the data to be written during the write phase of each iteration cycle is distributed across different memories. In subsequent writes, this data can be stored within a single clock cycle, achieving efficient writing, shortening the overall data processing time, and meeting the timeliness requirements of power line carrier communication.

[0129] In some embodiments of the power line carrier communication data processing method of the present invention, during the writing phase of the last iteration calculation cycle, a physical write address corresponding to the calculation result is generated according to a second mapping rule, and the calculation result is written to the corresponding physical write address, including the following steps:

[0130] First, obtain the logical read address of the target data corresponding to the calculation result of the last iteration cycle.

[0131] Next, the logical read address is calculated according to the second mapping rule to obtain the physical write address. The physical write address is configured to distribute the physical addresses of the calculation results of multiple target data to be read in a single read phase across different memories. The physical write address includes the write memory group index, the write memory index, and the write memory address index.

[0132] Finally, the calculation results are written to the corresponding physical write addresses.

[0133] Taking the data processing of 1024 target data in 5 iterative operation cycles using 4 radix-4 operation modules and 16 memory as an example, in the first 4 iterative operation cycles, the data to be read and written in each cycle is exactly distributed in different memory, which can ensure that the required data is read or written within one clock cycle.

[0134] However, in the write phase of the last iteration operation cycle, if the first mapping rule is still used for processing, then when reading the final calculation results in the original natural order, there will be multiple final calculation results that need to be read in one clock cycle. These multiple final calculation results are distributed in the same memory, and it is impossible to read all of these final results at once in one clock cycle.

[0135] For example, when reading the final calculation result, it can be determined according to the inversion formula that the numbers of the 16 calculation results read in the first reading are 0, 256, 512, 768, 64, 320, 576, 832, 128, 384, 640, 896, 192, 448, 704 and 960.

[0136] However, if the first mapping rule is still used for processing, when reading the final calculation results, it will be found that the calculation results numbered 0, 448, 640, and 832 are all stored in device 0; the calculation results numbered 64, 256, 704, and 896 are all stored in device 5; the calculation results numbered 128, 320, 512, and 960 are all stored in device 10; and the calculation results numbered 192, 384, 576, and 768 are all stored in device 15. This means that it is impossible to read all these final results at once within one clock cycle, resulting in a relatively long data processing time.

[0137] After processing the corresponding logical read addresses through the second mapping rule, the calculation result with number 0 can be stored in device 0, the calculation result with number 448 in device 1, the calculation result with number 640 in device 2, the calculation result with number 832 in device 3, the calculation result with number 896 in device 4, the calculation result with number 64 in device 5, the calculation result with number 256 in device 6, the calculation result with number 704 in device 7, the calculation result with number 512 in device 8, the calculation result with number 960 in device 9, the calculation result with number 128 in device 10, the calculation result with number 320 in device 11, the calculation result with number 384 in device 12, the calculation result with number 576 in device 13, the calculation result with number 768 in device 14, and the calculation result with number 192 in device 15.

[0138] Thus, during the write phase of the final iteration operation cycle, the physical write address is generated through the second mapping rule, so that the multiple final calculation results that need to be read in each clock cycle are distributed in different memories.

[0139] In the subsequent reading of the final calculation results, multiple final calculation results that need to be read can be retrieved at the same time within one clock cycle, without having to spend multiple clock cycles. This effectively shortens the overall data processing time and meets the timeliness requirements of power line carrier communication.

[0140] Specifically, the logical read address is calculated according to the second mapping rule to obtain the physical write address, including the following steps:

[0141] First, the logical read address is represented in binary and divided into multiple fields with a fixed number of bits. The fixed number of bits can be set according to actual needs, for example, to 2.

[0142] Secondly, in the first aspect, the write storage group index is calculated by using a modulo algorithm based on the sum of the fields in the first field group of the logical read address.

[0143] The first field group includes a first preset number of high-order fields. The modulo algorithm, the first preset number, and the definitions of the high-order fields have been explained above and will not be repeated here. The calculation method for writing to the storage group index is similar to that for the storage group index and will not be repeated here either.

[0144] Secondly, the write-to-memory index is calculated using a modulo algorithm based on the sum of the fields in the third field group of the logical read address.

[0145] Unlike calculating the memory index, the write memory index is calculated based on the sum of the fields in the third field group of the logical read address. The third field group includes the first field group, the most significant bit of the first field group, and the least significant bit adjacent to the first field group.

[0146] Taking 256 as an example, the ten-bit binary representation of 256 is 01 00 00 00 00. Therefore, the highest bit in the first field group is field five: 10, and the lowest bit adjacent to the first field group is field one: 00. Based on this, the sum of the fields in the third field group is 2, and 2%4 = 0 remainder 2. Thus, the final calculation result for number 256 is ultimately stored in memory 2 of storage group 1.

[0147] In the third aspect, the second preset number of bits in the ten-bit binary representation of the logical read address is used as the write storage address index.

[0148] The calculation method for writing the memory address index is similar to that for the memory address index, and will not be repeated here. Taking 256 as an example, it is still located at bit 16.

[0149] Taking the data processing of 1024 target data points through 5 iterative operation cycles using 4 radix-4 operation modules and 16 memory units as an example, the index to be written to memory is calculated using the modulo algorithm based on the third field of the logical sequence number, as follows:

[0150] .

[0151] In the formula, For writing to memory index, The logical read address in binary representation is the first The position and the first Bit, It is the highest-order field in the first field group.

[0152] In some other embodiments, the 16 memories can be directly divided into groups 0 to 15, with memories 0 to 3 in group 0, memories 4 to 7 in group 1, memories 8 to 11 in group 2, and memories 12 to 15 in group 3. In this way, the physical write address can be determined by writing the memory index and writing the memory address index.

[0153] To more clearly illustrate the method described herein, the following example illustrates how four radix-4 arithmetic modules, in conjunction with 16 memory units, process 1024 target data points.

[0154] Based on the total number of target data The value of 1024 confirms that:

[0155] Total number of iterations It is 5.

[0156] Butterfly operation group number =1, It is 4. It is 16. It is 64. It is 256.

[0157] Inter-butterfly data index difference It is 1024. It is 256. It is 64. It is 16. The value is 4.

[0158] Difference in in-butterfly data index It is 256. It is 64. It is 16. It is 4. The value is 1.

[0159] After obtaining 1024 target data points, refer to Figure 2As shown, it is stored in 16 memory locations using a round-robin allocation method.

[0160] Among them, the target data numbers stored in device 0 include 0, 16, 32, 48, 64, ..., 1008; the target data numbers stored in device 1 include 1, 17, 33, 49, 65, ..., 1009; ...; the target data numbers stored in device 15 include 15, 31, 47, 63, 79, ..., 1023.

[0161] Understandably, target data numbered 0 is located in bit 0 of device 0 in group 0, and target data numbered 256 is located in bit 16 of device 0 in group 0.

[0162] Reference Figure 3 As shown, in the first iteration cycle, the 16 target data that need to be read at one time include 0, 256, 512, 768, 1, 257, 513, 769, 2, 258, 514, 770, 3, 259, 515, and 771. If read directly, it is impossible to retrieve the two target data numbers 0 and 256 within the same clock cycle.

[0163] Therefore, we first process it using the first mapping rule. (Refer to...) Figure 4 As shown, the target data to be read is distributed in different memories after processing.

[0164] For example, target data with number 0 is stored in bit 0 of device 0 in group 0; target data with number 1 is stored in bit 0 of device 1 in group 0; target data with number 2 is stored in bit 0 of device 2 in group 0; target data with number 3 is stored in bit 0 of device 3 in group 0; target data with number 259 is stored in bit 16 of device 0 in group 1; target data with number 256 is stored in bit 16 of device 1 in group 1; target data with number 257 is stored in bit 16 of device 2 in group 1; target data with number 258 is stored in bit 16 of device 3 in group 1; and target data with number 259 is stored in bit 16 of device 0 in group 1; target data with number 259 is stored in bit 16 of device 0 in group 1; target data with number 259 is stored in bit 16 of device 0 in group 1; and ...1 in group 1. The target data for number 514 is stored in bit 32 of device 0 in group 2; the target data for number 515 is stored in bit 32 of device 1 in group 2; the target data for number 512 is stored in bit 32 of device 2 in group 2; the target data for number 513 is stored in bit 32 of device 3 in group 2; the target data for number 769 is stored in bit 48 of device 0 in group 3; the target data for number 770 is stored in bit 48 of device 1 in group 3; the target data for number 771 is stored in bit 48 of device 2 in group 3; and the target data for number 768 is stored in bit 48 of device 3 in group 3.

[0165] Thus, the target data is retrieved, a Fast Fourier Transform calculation is performed, and the results are written. After four iteration cycles, the data storage status is as follows: Figure 5 As shown, the target data that needs to be read in one go is as follows: Figure 6 As shown.

[0166] The final calculation result is in reverse order; therefore, the original natural order of the numbers needs to be reversed using a reversal formula to obtain the reversed numbers. Then, after the last iteration cycle, the physical address where the final calculation result is located is read based on the reversed number. The storage methods for the calculation results of the corresponding numbers before and after reversal are described in detail below. Figure 7 and Figure 8 As shown.

[0167] Thus, within one clock cycle, the final calculation results numbered 0, 256, 512, 768, 64, 320, 576, 832, 128, 384, 640, 896, 192, 448, 704, and 960 need to be read.

[0168] If the first mapping rule is still used for processing, refer to... Figure 9 As shown, when reading the final calculation results, it can be found that the calculation results numbered 0, 448, 640, and 832 are stored in device 0; the calculation results numbered 64, 256, 704, and 896 are stored in device 5; the calculation results numbered 128, 320, 512, and 960 are stored in device 10; and the calculation results numbered 192, 384, 576, and 768 are stored in device 15. This means that it is impossible to read all these final results at once in one clock cycle, and the data processing time is relatively long.

[0169] Therefore, in the writing phase of the final iteration operation cycle, in order to minimize changes to the existing radix-4 operation architecture and ensure that when reading the final calculation results later, multiple final calculation results that need to be read can be retrieved at the same time within one clock cycle, without spending multiple clock cycles, the second mapping rule is used for processing.

[0170] Reference Figure 10As shown, after processing the corresponding logical read addresses through the second mapping rule, the calculation result with number 0 can be stored in device 0, the calculation result with number 448 in device 1, the calculation result with number 640 in device 2, the calculation result with number 832 in device 3, the calculation result with number 896 in device 4, the calculation result with number 64 in device 5, the calculation result with number 256 in device 6, the calculation result with number 704 in device 7, the calculation result with number 512 in device 8, the calculation result with number 960 in device 9, the calculation result with number 128 in device 10, the calculation result with number 320 in device 11, the calculation result with number 384 in device 12, the calculation result with number 576 in device 13, the calculation result with number 768 in device 14, and the calculation result with number 192 in device 15.

[0171] Thus, during the write phase of the final iteration operation cycle, the physical write address is generated through the second mapping rule, so that the multiple final calculation results that need to be read in each clock cycle are distributed in different memories.

[0172] In the subsequent reading of the final calculation results, multiple final calculation results that need to be read can be retrieved at the same time within one clock cycle, without having to spend multiple clock cycles. This effectively shortens the overall data processing time and meets the timeliness requirements of power line carrier communication.

[0173] For example, the above method can be implemented using the following Verilog code:

[0174] “moduleaddr_map(input [9:0] addr_in, output [5:0]addr_map, output [3:0] mem_bank, input last_round_wr); wire [1:0] mem_sel = addr_in[3:2]+addr_in[5:4]+addr_in[7:6]+addr_in[9:8]; wire [1:0] addr_bank_tmp = addr_in[1:0]+addr_in[3:2]+addr_in[5:4]+addr_in[7:6]+addr_in[9:8]; wire [1:0] addr_bank_tmp1 = addr_bank_tmp+addr_in[9:8]; mem_bank = (mem_sel<<2)+(last_round_wr ? addr_bank_tmp1 : addr_bank_tmp); / / Chip select signal for 16 memory chips addr_map = addr_in[9:4]; endmodule.

[0175] The code defines each memory location using modules 0 through 15. "module" and "endmodule" are keywords in the Verilog language.

[0176] The input is a 10-bit binary value called addr_in, and the output is a 6-bit binary value called addr_map and a 4-bit binary value called mem_bank.

[0177] “wire [1:0]” means to retrieve the lower-order bits of the corresponding binary representation. Using the input ten-bit binary value of addr_in, mem_sel, addr_bank_tmp, and addr_bank_tmp1 are calculated respectively.

[0178] The expression "last_round_wr ? addr_bank_tmp1 : addr_bank_tmp" indicates whether it is the last iteration cycle. If not, addr_bank_tmp is summed with mem_sel shifted two bits to the left. Otherwise, addr_bank_tmp1 is summed with mem_sel shifted two bits to the left.

[0179] Taking the input 714 as an example, its ten-bit binary representation, addr_in, is 1011001010. Correspondingly, addr_in[1:0] is 10, addr_in[3:2] is 10, addr_in[5:4] is 00, addr_in[7:6] is 11, and addr_in[9:8] is 10.

[0180] Thus, mem_sel is set to 11 for the lower-order field, addr_bank_tmp is set to 01 for the lower-order field, and addr_bank_tmp1 is set to 11 for the lower-order field.

[0181] In non-final iteration cycles, mem_sel is shifted left by two bits, summed with addr_bank_tmp, and the result is assigned to mem_bank. Shifting mem_sel left by two bits results in 1100, yielding mem_bank as 13 and addr_map as 44. Thus, bit 44 of display 13 is bit 44 of display 1 in group 3.

[0182] In the final iteration cycle, mem_sel is shifted left by two bits, summed with addr_bank_tmp1, and the result is assigned to mem_bank. Shifting mem_sel left by two bits gives 1100, resulting in mem_bank being 15 and addr_map being 44. Thus, bit 44 of display 15 is bit 44 of display 3 in group 3.

[0183] On the other hand, refer to Figure 11 This invention also provides a power line carrier communication data processing apparatus, which is applied to the power line carrier communication data processing method described in any of the above embodiments.

[0184] The power line carrier communication data processing device includes a first module 11, a second module 12, a third module 13, a fourth module 14, and a fifth module 15.

[0185] The first module 11 is used to write multiple target data stored according to the original natural order into multiple memories after address mapping through the first mapping rule, so that the physical addresses of the multiple target data read by multiple parallel radix-4 operation modules are distributed in different memories.

[0186] The second module 12 is used to map the logical read addresses generated by multiple parallel radix-4 operation modules according to the first mapping rule during the read phase of each iterative operation cycle, thereby obtaining physical read addresses, and then read data from multiple target data according to the physical read addresses. Specifically, the physical read addresses are configured to distribute the physical addresses of the multiple target data to be read in a single read phase across different memories.

[0187] The third module 13 is used to perform Fast Fourier Transform calculations based on multiple parallel radix-4 operation modules to obtain the calculation results for multiple target data. Among them, the calculation results of the last iteration operation cycle are arranged in reverse bit order.

[0188] The fourth module 14 is used to write the calculation result back to the original physical address according to the first mapping rule during the write phase of non-final iteration operation cycle, overwriting the original data before the calculation at the original physical address.

[0189] The fifth module 15 is used to generate the physical write address corresponding to the calculation result according to the second mapping rule during the write phase of the last iteration operation cycle, and write the calculation result to the corresponding physical write address. The second mapping rule is configured to adjust the intra-group mapping relationship of the memory and optimize the distribution of the calculation result in multiple memories, so that when reading according to the original natural order in a subsequent process, multiple calculation results can be accessed in parallel without conflict in a single read phase.

[0190] In some embodiments, the power line carrier communication data processing apparatus of the present invention further includes a sixth module 16. The sixth module 16 is used to calculate the total number of iterations in the iterative operation cycle based on the total number of target data. Based on the total number of iterations, it calculates the number of butterfly operation groups and the inter-butterfly data index difference in each iterative operation cycle. It calculates the intra-butterfly data index difference based on the inter-butterfly data index difference. Based on the number of butterfly operation groups, the inter-butterfly data index difference, and the intra-butterfly data index difference, it determines the logical read address.

[0191] In some embodiments, the power line carrier communication data processing apparatus of the present invention, the first module 11 is specifically used to: calculate the mapped physical address according to the logical sequence number of the target data in the original natural order, using a first mapping rule; and store the target data in the physical address corresponding to the logical sequence number. The physical address includes a storage group index, a memory index, and a storage address index. Multiple memories are divided into multiple storage groups, each storage group includes four memories, and each memory includes multiple storage addresses.

[0192] In some embodiments, in the power line carrier communication data processing apparatus of the present invention, the first module 11 is specifically used for: representing the logical sequence number in binary and dividing it into multiple fields with a fixed number of bits; calculating a storage group index using a modulo algorithm based on the sum of the fields of the first field group of the logical sequence number; wherein the first field group includes a first preset number of high-order fields; calculating a memory index using a modulo algorithm based on the sum of the fields of the second field group of the logical sequence number; wherein the second field group includes the first field group and the low-order fields adjacent to the first field group; and using a second preset number of bits representing the ten-bit binary representation of the logical sequence number as a storage address index.

[0193] In some embodiments, in the power line carrier communication data processing apparatus of the present invention, the fourth module 14 is specifically used for: obtaining the logical read address of the target data corresponding to the calculation result of the current iteration operation cycle; calculating the logical read address according to the first mapping rule to obtain the original physical address consistent with the corresponding physical read address; writing the calculation result to the corresponding original physical address and overwriting the original data at the original physical address.

[0194] In some embodiments, in the power line carrier communication data processing apparatus of the present invention, the fifth module 15 is specifically used for: obtaining the logical read address of the target data corresponding to the calculation result of the last iteration operation cycle; calculating the logical read address according to the second mapping rule to obtain the physical write address; wherein, the physical write address is configured to distribute the physical addresses of the calculation results of multiple target data to be read in a single read stage in different memories; the physical write address includes a write memory group index, a write memory index, and a write memory address index; and writing the calculation result according to the corresponding physical write address.

[0195] In some embodiments, the fifth module 15 of the power line carrier communication data processing apparatus of the present invention is specifically used for: representing the logical read address in binary and dividing it into multiple fields with a fixed number of bits; calculating a write memory group index based on the sum of the fields of the first field group of the logical read address using a modulo algorithm; wherein the first field group includes a first preset number of high-order fields; calculating a write memory index based on the sum of the fields of the third field group of the logical read address using a modulo algorithm; wherein the third field group includes the first field group, the highest-order field in the first field group, and the low-order fields adjacent to the first field group; and using a second preset number of bits in the ten-bit binary representation of the logical read address as the write memory address index.

[0196] This invention also provides a non-transitory machine-readable medium storing a computer program. When executed by a computer's processor, the computer program causes the computer to perform the power line carrier communication data processing method described in any of the above embodiments.

[0197] This invention also provides a computer program product, including a computer program. When executed by a computer's processor, the computer program causes the computer to perform the power line carrier communication data processing method described in any of the above embodiments.

[0198] This invention also provides an electronic device, including at least one processor and a memory communicatively connected to the at least one processor. The memory stores a computer program executable by the at least one processor, which, when executed by the at least one processor, causes the electronic device to perform the power line carrier communication data processing method described in any of the above embodiments.

[0199] Reference Figure 12 The diagram illustrates a structural block diagram of an electronic device that can serve as an embodiment of the present invention, representing an example of a hardware device applicable to various aspects of the invention. The term "electronic device" is intended to represent various forms of digital electronic computer devices, such as laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The electronic device can also represent various forms of mobile devices, such as personal digital processors, cellular phones, smartphones, wearable devices, and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely illustrative and are not intended to limit the implementation of the invention described and / or claimed herein.

[0200] Reference Figure 12As shown, the electronic device includes a computing unit 201, which can perform various appropriate actions and processes based on a computer program stored in a read-only memory (ROM) 202 or a computer program loaded from a storage unit 208 into a random access memory (RAM) 203. The RAM 203 may also store various programs and data required for the operation of the electronic device. The computing unit 201, ROM 202, and RAM 203 are interconnected via a bus 204. An input / output (I / O) interface 205 is also connected to the bus 204.

[0201] Multiple components in the electronic device are connected to I / O interface 205, including: input unit 206, output unit 207, storage unit 208, and communication unit 209. Input unit 206 can be any type of device capable of inputting information into the electronic device. Input unit 206 can receive input digital or character information and generate key signal inputs related to user settings and / or function control of the electronic device. Output unit 207 can be any type of device capable of presenting information and may include, but is not limited to, a display, speaker, video / audio output terminal, vibrator, and / or printer. Storage unit 208 may include, but is not limited to, disks and optical discs. Communication unit 209 allows the electronic device to exchange information / data with other devices through computer networks such as the Internet and / or various telecommunications networks, and may include, but is not limited to, modems, network cards, infrared communication devices, and / or wireless communication transceivers, such as Bluetooth devices, WiFi devices, WiMax devices, cellular communication devices, and / or the like.

[0202] The computing unit 201 can be a variety of general-purpose and / or special-purpose processing components with processing and computing capabilities. Some examples of the computing unit 201 include, but are not limited to, CPUs, graphics processing units (GPUs), various special-purpose artificial intelligence (AI) computing units, various computing units running machine learning model algorithms, digital signal processors (DSPs), and any suitable processor, controller, microcontroller, etc. The computing unit 201 performs the various methods and processes described above. For example, in some embodiments, the method embodiments of the present invention can be implemented as a computer program tangibly contained in a machine-readable medium, such as storage unit 208. In some embodiments, part or all of the computer program can be loaded and / or installed on an electronic device via ROM 202 and / or communication unit 209. In some embodiments, the computing unit 201 can be configured to perform the methods described above by any other suitable means (e.g., by means of firmware).

[0203] Computer programs for implementing the methods of embodiments of the present invention may be written in any combination of one or more programming languages. These computer programs may be provided to a processor or controller of a general-purpose computer, a special-purpose computer, or other programmable data processing apparatus, such that when executed by the processor or controller, the computer programs cause the functions / operations specified in the flowcharts and / or block diagrams to be implemented. The computer programs may be executed entirely on a machine, partially on a machine, or as a standalone software package, partially on a machine and partially on a remote machine, or entirely on a remote machine or server.

[0204] In the context of embodiments of the present invention, a machine-readable medium can be a tangible medium that may contain or store a program for use by or in conjunction with an instruction execution system, apparatus, or device. A machine-readable medium can be a machine-readable signal medium or a machine-readable storage medium. A machine-readable signal medium may include, but is not limited to, electronic, magnetic, optical, electromagnetic, or infrared systems, apparatus, or devices, or any suitable combination of the foregoing. More specific examples of machine-readable storage media include electrical connections based on one or more wires, portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fibers, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination of the foregoing.

[0205] It should be noted that the term "comprising" and its variations used in the embodiments of the present invention are open-ended, meaning "including but not limited to". The term "based on" means "at least partially based on". The term "one embodiment" means "at least one embodiment"; the term "another embodiment" means "at least one additional embodiment"; the term "some embodiments" means "at least some embodiments". The modifications of "one" and "a plurality" mentioned in the embodiments of the present invention are illustrative and not restrictive, and those skilled in the art should understand that unless explicitly indicated otherwise in the context, they should be understood as "one or more".

[0206] The steps described in the method embodiments provided by the present invention can be performed in different orders and / or in parallel. Furthermore, the method embodiments may include additional steps and / or omit the steps shown. The scope of protection of the present invention is not limited in this respect.

[0207] The term "embodiment" in this specification refers to a specific feature, structure, or characteristic described in connection with an embodiment that may be included in at least one embodiment of the invention. The appearance of this phrase in various places in the specification does not necessarily imply the same embodiment, nor does it imply independence or alternativeity from other embodiments. The various embodiments in this specification are described in a related manner, with reference to each other for similar or identical parts. In particular, for apparatus, device, and system embodiments, since they are substantially similar to method embodiments, the description is relatively simple, and relevant details are referred to in the description of the method embodiments.

[0208] The embodiments described above are merely illustrative of several implementations of the present invention, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of protection. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these all fall within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the appended claims.

Claims

1. A power line carrier communication data processing method, characterized in that, Including the following steps: Multiple target data stored according to their original natural order are written into multiple memories after address mapping according to the first mapping rule, so that the physical addresses of the multiple target data read by multiple parallel radix-4 operation modules are distributed in different memories; During the reading phase of each iterative operation cycle, the logical reading addresses generated by multiple parallel radix-4 operation modules are mapped according to the first mapping rule to obtain physical reading addresses, and the corresponding multiple target data are read according to the physical reading addresses; wherein, the physical reading addresses are configured to distribute the physical addresses of the multiple target data to be read in a single reading phase in different memories; Fast Fourier transform calculations are performed using multiple parallel radix-4 operation modules to obtain calculation results for multiple target data; wherein the calculation results of the last iteration are arranged in reverse bit order. During the write phase of a non-last iteration operation cycle, the calculation result is written back to the original physical address according to the first mapping rule, overwriting the original data before the calculation at the original physical address; During the write phase of the last iteration operation cycle, a physical write address corresponding to the calculation result is generated according to the second mapping rule, and the calculation result is written to the corresponding physical write address; wherein, the second mapping rule is configured to adjust the intra-group mapping relationship of the memory and optimize the distribution of the calculation result in multiple memories, so that when reading according to the original natural order in a subsequent process, multiple calculation results can be accessed in parallel without conflict in a single read phase.

2. The power line carrier communication data processing method according to claim 1, characterized in that, Multiple target data stored according to their original natural order are written into multiple memories after address mapping according to a first mapping rule, including the following steps: Based on the logical sequence number of the target data in the original natural order, the mapped physical address is calculated using the first mapping rule; wherein, the physical address includes a storage group index, a memory index, and a storage address index; the multiple memories are divided into multiple storage groups, each storage group includes 4 memories, and each memory includes multiple storage addresses; The target data is stored in the physical address corresponding to the logical sequence number.

3. The power line carrier communication data processing method according to claim 2, characterized in that, Based on the logical sequence number of the target data in the original natural order, the mapped physical address is calculated using the first mapping rule, including the following steps: The logical sequence number is represented in binary and divided into multiple fields with a fixed number of bits. The storage group index is calculated using a modulo algorithm based on the sum of the fields in the first field group of the logical sequence number; wherein, the first field group includes a first preset number of multiple high-order fields; The memory index is calculated using a modulo algorithm based on the sum of the fields in the second field group of the logical sequence number; wherein the second field group includes the first field group and the low-order field adjacent to the first field group; The second preset number of bits in the ten-bit binary representation of the logical sequence number is used as the storage address index.

4. The power line carrier communication data processing method according to claim 3, characterized in that: The number of radix-4 operation modules, the number of storage groups, and the number of memories in each storage group are all set to 4. The iterative operation cycle is four parallel iterative cycles of radix-4 fast Fourier calculation. The storage group index is calculated using a modulo algorithm based on the sum of the fields in the first field group of the logical sequence number, and is represented as follows: ， In the formula, For the storage group index, The logical number in binary representation of the first The position and the first Bit, , , and For the first field group, " " indicates that the sum of the corresponding fields is calculated; The memory index is calculated using a modulo algorithm based on the sum of the fields in the second field group of the logical sequence number, and is expressed as follows: ， In the formula, For the memory index, The lower-order field adjacent to the first field group; The first 6 high-order bits of the logical sequence number are used as the storage address index, represented as follows: .

5. The power line carrier communication data processing method according to claim 1, characterized in that, During the write phase of a non-final iteration operation cycle, according to the first mapping rule, the calculation result is written back to the original physical address, overwriting the original data at the original physical address before the calculation, including the following steps: Obtain the logical read address of the target data corresponding to the calculation result of the current iteration cycle; The logical read address is calculated according to the first mapping rule to obtain the original physical address that is consistent with the corresponding physical read address; The calculation result is written to the corresponding original physical address, overwriting the original data at the original physical address.

6. The power line carrier communication data processing method according to claim 1, characterized in that, In the writing phase of the final iteration cycle, a physical write address corresponding to the calculation result is generated according to the second mapping rule, and the calculation result is written to the corresponding physical write address, including the following steps: Obtain the logical read address of the target data corresponding to the calculation result of the last iteration operation cycle; The logical read address is calculated according to the second mapping rule to obtain the physical write address; wherein, the physical write address is configured to distribute the physical addresses of the calculation results of multiple target data to be read in a single read stage in different memories, and the physical write address includes a write memory group index, a write memory index and a write memory address index; The calculation results are written to the corresponding physical write address.

7. The power line carrier communication data processing method according to claim 6, characterized in that, The logical read address is calculated according to the second mapping rule to obtain the physical write address, including the following steps: The logical read address is represented in binary and divided into multiple fields with a fixed number of bits. The write storage group index is calculated using a modulo algorithm based on the sum of the fields in the first field group of the logical read address; wherein, the first field group includes a first preset number of multiple high-order fields; The write-to-memory index is calculated using a modulo algorithm based on the sum of the fields in the third field group of the logical read address; wherein the third field group includes the first field group, the highest-order field in the first field group, and the lowest-order field adjacent to the first field group. The second preset number of bits in the ten-bit binary representation of the logical read address is used as the write storage address index.

8. The power line carrier communication data processing method according to claim 7, characterized in that: The write-to-memory index is calculated using a modulo algorithm based on the sum of the fields in the third field group of the logical sequence number, and is expressed as follows: ， In the formula, For the write memory index, The first logical read address in binary representation The position and the first Bit, For the highest-order field in the first field group, " "" indicates that the sum of the corresponding fields is calculated.

9. The power line carrier communication data processing method according to claim 1, characterized in that, Before writing multiple target data stored according to their original natural order into multiple memories after address mapping according to the first mapping rule, the process also includes the following steps: The total number of iterations in the iterative operation cycle is calculated based on the total number of target data, and is expressed as follows: ， In the formula, The total number of iterations, The total number of the target data; Based on the total number of iterations, the number of butterfly operation groups and the inter-butterfly data index difference in each iteration cycle are calculated and expressed as follows: ， ， In the formula, For the first The number of butterfly operation groups in each of the aforementioned iterative operation cycles. The loop variable for the iteration operation period. , For the first The inter-butterfly data index difference for each of the said iterative operation cycles; The intra-butterfly data index difference is calculated based on the inter-butterfly data index difference, and is expressed as follows: ， In the formula, For the first The difference in the in-butterfly data index for each of the said iterative operation cycles; The logical read address is determined based on the number of butterfly operation groups, the difference in data index between butterflies, and the difference in data index within butterflies.

10. A power line carrier communication data processing apparatus, applied to the power line carrier communication data processing method as described in any one of claims 1 to 9, characterized in that, include: The first module is used to write multiple target data stored according to the original natural order into multiple memories after address mapping through a first mapping rule, so that the physical addresses of the multiple target data read by multiple parallel radix-4 operation modules are distributed in different memories; The second module is used to map the logical read addresses generated by multiple parallel radix-4 operation modules according to the first mapping rule during the read phase of each iterative operation cycle to obtain physical read addresses, and to read data from the corresponding multiple target data according to the physical read addresses; wherein, the physical read addresses are configured to distribute the physical addresses of the multiple target data to be read in a single read phase in different memories; The third module is used to perform fast Fourier transform calculations based on multiple parallel radix-4 operation modules to obtain calculation results for multiple target data; wherein the calculation results of the last iteration operation cycle are arranged in reverse bit order. The fourth module is used to write the calculation result back to the original physical address according to the first mapping rule during the write phase of non-last iteration calculation cycle, overwriting the original data before the calculation at the original physical address. The fifth module is used to generate the physical write address corresponding to the calculation result according to the second mapping rule during the write phase of the last iteration operation cycle, and write the calculation result to the corresponding physical write address; wherein, the second mapping rule is configured to adjust the intra-group mapping relationship of the memory and optimize the distribution of the calculation result in multiple memories, so that when reading according to the original natural order in a subsequent process, parallel and conflict-free access to multiple calculation results can be achieved in a single read phase.

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