Wafer level packaging method

Abstract

The application discloses a wafer level packaging method, comprising the following steps: a substrate marking step: etching at least one set of foolproof marks and position marks on one surface of a substrate; a wafer marking step: forming alignment marks same as the position marks on each wafer, the alignment marks being aligned with the position marks, and wafer flat edges or notches being aligned with the foolproof marks; a packaging processing step: forming protrusions on an active surface of the wafer, the protrusions being matched with the foolproof marks and the position marks; after encapsulation, transferring the marks at the protrusions to the package to form plastic packaging marks, and wiring; and then, according to the plastic packaging marks, dividing and cutting the wafer into single finished products. The wafer position is accurately positioned through the position marks, the foolproof marks, the multi-ball combined feature shape and the plastic packaging marks on the substrate, cutting injury is prevented, a plurality of wafers can be operated under the same process, small-size wafers can also be compatible on the equipment, the processing time is shortened, and the production cost is reduced.

Description

Technical Field

[0001] This invention application belongs to the field of chip packaging technology, and particularly relates to a wafer-level packaging method. Background Technology

[0002] With the rapid development of the electronics industry, the integration capabilities of electronic products are constantly improving, their functions are becoming more powerful, and their size is becoming smaller. Chip processing is crucial in electronic products, and the processes in each stage of chip processing are also being improved. For example, packaging, wafer-level packaging is a type of packaging. Wafer-level packaging uses wafers as the processing object, and many chips are packaged, wired, and tested on the wafer at the same time. Finally, it is cut into individual devices that can be directly mounted onto a substrate or printed circuit board, reducing the package size to the size of the IC chip and significantly reducing production costs. Many chip micro-modules are formed by wafer-level packaging followed by cutting, such as small chips like transient voltage suppressor diodes (TVS), which are protective devices.

[0003] Currently, the mainstream wafer-level packaging for small chips is for 6-inch and larger wafers. Since advanced packaging is currently used, it is difficult to achieve equipment compatibility for small wafers. Moreover, under the same process flow, the size of a single wafer is smaller, resulting in fewer chips produced. This leads to lower packaging efficiency and higher average cost per chip. Furthermore, the placement of wafers is determined only by the V-groove or flat edge on the wafer. For packaging structures that place multiple wafers, it is difficult to determine the wafer position after encapsulation. Therefore, how to accurately align wafers to achieve equipment compatibility and increase production to complete wafer-level packaging is a technical problem that urgently needs to be solved. Summary of the Invention

[0004] To address the problems in the prior art, this invention provides a wafer-level packaging method.

[0005] To achieve the above objectives, this invention application proposes a wafer-level packaging method, comprising the following steps: Substrate marking steps: At least one set of anti-mistake marks and position marks are etched on one surface of the substrate, with each set of anti-mistake marks and position marks located on an extension line of equal length of the wafer diameter at that location; Wafer marking steps: Form alignment marks on each wafer that are identical to the position marks, align the alignment marks with the position marks, align the wafer's flat edge or notch with the mistaken mark, and initially locate the wafer's placement position on the substrate; Packaging process steps: Make protrusions on the active surface of the wafer that match the error prevention marks and position marks. After encapsulation, transfer the marks on the protrusions onto the package body to form plastic encapsulation marks. Then, make wiring. Finally, separate the board according to the plastic encapsulation marks and cut it into individual finished products.

[0006] Furthermore, in the substrate marking step, the wafer diameter < the spacing between the position marks < 1.2 times the wafer diameter.

[0007] Furthermore, in the substrate marking step, after marking, adhesive is applied to the surface of the substrate to bond the wafer, and the adhesive is a semi-transparent adhesive.

[0008] Furthermore, in the substrate marking step, each set of anti-foolproof marks and position marks is located on the side length of the outer square concentric with the wafer at this location.

[0009] Furthermore, in the wafer marking step, the thickness of the wafer is ≤400μm, and a pre-cutting is performed at the dicing channel of the wafer to form a pre-cutting channel, the depth of which is 0.5 to 0.7 times the thickness of the wafer.

[0010] Furthermore, in the wafer marking step, pre-cut tracks are formed between chips that are close to each other on the wafer, and their width ranges from ≥60μm.

[0011] Furthermore, the packaging process also includes: S1, grinding after encapsulation to expose protrusions to transfer markings onto the package; S2, sequentially exposing, developing, and electroplating each wafer to form wiring and leads; S3, re-encapsulating, removing the substrate and adhesive thereon, and grinding the wafer from that side to the pre-cut track; S4, cutting the encapsulation material from the pre-cut track after separation to form a single product.

[0012] This invention application: By using position marks and error-proof marks on the substrate to correspond to the groove edges and alignment marks of the wafer, the placement positions of multiple wafers are initially located, and protrusions are formed on the chips of the wafers. Multiple spheres are assembled into a characteristic shape, and the alignment marks are recorded. In subsequent process flows, the recorded marks are transferred to the molding mark to accurately locate the wafer position, prevent accidental damage during cutting, ensure that multiple wafers can be processed under the same process, and achieve equipment compatibility for small-sized wafers, shorten processing time, and reduce production costs. Attached Figure Description

[0013] Figure 1 This is a top view of the wafer after it has been pasted, which is a wafer-level packaging method according to the present invention. Figure 2 A top view of the wafer encapsulation process after grinding to expose the protrusions, as described in this invention application, for a wafer-level packaging method. Figure 3 A cross-sectional view showing the protrusions exposed by grinding after wafer encapsulation in the packaging process of a wafer-level packaging method for this invention application; Figure 4 This is a schematic diagram of the wafer electroplating and encapsulation steps in the wafer-level packaging method of this invention application; Figure 5This is a schematic diagram of the substrate removal step in the packaging process of a wafer-level packaging method according to the present invention. Figure 6 This is a schematic diagram of wafer bottom grinding in the packaging process of a wafer-level packaging method according to the present invention. Figure 7 This invention application provides a cross-sectional view of a wafer-level packaging method cut into individual products.

[0014] The markings in the diagram are as follows: 1. Substrate; 2. Wafer; 3. Bump; 4. Mistake-proof mark; 5. Position mark; 6. Alignment mark; 7. Molding mark; 8. Lead; 9. Pre-cut track. Detailed Implementation

[0015] Embodiments of the present invention are described in detail below, examples of which are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention, and should not be construed as limiting the present invention.

[0016] In the description of this invention, it should be understood that the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," and "counterclockwise," etc., indicating orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, are only for the convenience of describing the invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of the invention. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, features defined with "first" and "second" may explicitly or implicitly include one or more of the stated features. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified.

[0017] To better understand the purpose, structure, and function of this invention application, the following description is provided in conjunction with the appendix. Figure 1-7 The present invention provides a wafer-level packaging method, which includes the following steps: Substrate marking steps: At least one set of anti-mistake marks 4 and position marks 5 are etched on one surface of substrate 1, and each set of anti-mistake marks 4 and position marks 5 is located on each equal extension line of the diameter of wafer 2. Wafer marking steps: Form alignment marks 6 on each wafer 2 that are identical to position marks 5. Align alignment marks 6 with position marks 5. Align the flat edge or notch of wafer 2 with the anti-fool mark 4 to initially locate the placement position of wafer 2 on substrate 1. Packaging process steps: Make a protrusion 3 on the active surface of wafer 2 that matches the anti-foolproof mark 4 and the position mark 5. After encapsulation, transfer the mark on the protrusion 3 to the package body to form the plastic encapsulation mark 7, and then wire it. Finally, according to the plastic encapsulation mark 7, separate the board and cut it into individual finished products.

[0018] In the substrate marking step, substrate 1 is a commonly used material in the art, such as FR-4 or other substrates 1. In this application, four sets of marks are formed on substrate 1 by burning. Four wafers 2 are placed on substrate 1, with each wafer 2 placed between a set of marks. In this application, each set of anti-mistake marks 4 and position marks 5 are distributed on the side length of an outer square concentric with the wafer 2. The marks need to be spaced differently according to the size of the wafer 2. The diameter of the wafer 2 < the spacing between the position marks 5 < 1.2 times the diameter of the wafer 2. The position marks 5 and anti-mistake marks 4 on substrate 1 can be crosses, polygons, or other shapes, and can be formed by laser burning. The position marks 5 and anti-mistake marks 4 are different. In this application, position marks 5 are crosses and anti-mistake marks 4 are triangles, for example. Anti-mistake marks 4 are used to correspond to the V-groove (notch) or flat edge (flat edge) of wafer 2, i.e., the Flat / Notch in the wafer 2 fabrication process. The Grinning step helps subsequent processes determine the placement position of wafer 2. After marking, adhesive is applied to the surface of substrate 1 to bond wafer 2, that is, the active side of wafer 2 is bonded away from the adhesive surface. The adhesive is semi-transparent and does not affect the observation of position mark 5 and error prevention mark 4, thus initially positioning the placement position of wafer 2. Multiple wafers 2 can be mounted and processed simultaneously on substrate 1, solving the problem of low packaging efficiency in advanced packaging. Under the same process, the output of multiple wafers 2 increases and the cost decreases.

[0019] In the wafer marking step, wafer 2 needs to be pre-processed, including the following steps: S1, firstly, the passive surface of wafer 2 is ground and thinned, and the thickness of wafer 2 after thinning is ≤400μm. This application takes 400μm as an example. Then, a bump 3 is formed on the active surface of wafer 2. In this application, the bump 3 is a ball bearing, which is specifically introduced into wafer 2 by a scanning device. The MAP diagram corresponds to the internal chip pattern of wafer 2, achieving complete matching. Multiple balls are assembled to form alignment marks 6 that match the anti-mistake mark 4 and position mark 5, used to distinguish the position of wafer 2; S2, next, the active surface of wafer 2 is pre-cut at the dicing channel. The dicing channel width of wafer 2 is ≥80μm. This application takes 80μm as an example. Pre-cutting refers to cutting a certain depth perpendicularly along the dicing channel cutting direction without completely cutting through, forming a pre-cutting channel 9. The depth range of the pre-cutting channel 9 is 0.5 to 0.7 times the thickness of wafer 2. This can reduce the difficulty of subsequent wafer 2 grinding and ensure that the chips on wafer 2 are not broken, thus enabling stable subsequent processing of the chips. The structure is stable. This application takes 0 For example, 0.6 times, the pre-cut channel 9 is formed between chips that are close to each other on the wafer 2, and its width range is ≥60μm. This application takes 60μm as an example. The pre-cut channel 9 is cut at the cutting channel, so its width is less than the cutting channel width; S3, finally, cross or polygonal feature patterns are laser etched at the designated edge position of the wafer 2. The markings on the wafer 2 are the same as the markings on the substrate 1, and are used to align with the markings on the substrate 1; In this application, the substrate 1 is suitable for placing wafers 2 with a size of 8 inches and below, which solves the problem of incompatibility of small-sized wafers 2 on the device. Small-sized wafers 2 of 6 inches and above used for wafer-level packaging of small chips (TVS, etc.) can be compatible with the device.

[0020] The encapsulation process includes the following steps: S1. After encapsulation, grinding exposes the protrusions 3 to transfer the markings onto the package. The multiple balls of the protrusions 3 are assembled to form alignment marks 6 that match the anti-mistake markings 4 and position markings 5. After encapsulation, grinding exposes the top surface of the protrusions 3, that is, it exposes the alignment marks 6 formed by the multi-ball protrusions 3. The markings on the wafer 2 and the substrate 1 are completely covered by the encapsulating material, which is black. Therefore, the alignment marks 6 formed by the protrusions 3 are etched onto the package at a certain distance to form the molding mark 7. This distance is the same as the distance between the protrusions 3 and the markings on the substrate 1 before encapsulation. The molding mark 7 marks the position of the wafer 2; S2. Each wafer 2 is sequentially exposed, developed, and electroplated to form wiring and leads 8. The leads 8 are connected to the wiring and S3. Re-encapsulate and grind to expose the top surface of pins 8. Remove the substrate 1 and adhesive on the bottom of wafer 2. The position mark 5 and the foolproof mark 4 on wafer 2 are fully exposed. Grind the wafer from this surface to the pre-cut track 9. Chips that are close to each other on wafer 2 are separated. S4. After separation, cut the encapsulation material of the pre-cut track 9 to form a single product. That is, first, according to the marks on wafer 2, four wafers 2 are separated into a single wafer 2 package. Then, a blade is used to cut at the pre-cut track 9. The blade width is ≤ the pre-cut blade width. This ensures that the blade only cuts the encapsulation material without damaging the chip, wiring, and pins 8, ensuring the integrity of the product. Under the same process flow, more chips are produced in a single work, reducing processing time and cost.

[0021] All electroplating processes in this application involve first forming an electroplating protection layer on the surface using photolithography techniques such as exposure and development, and then forming a metal seed layer in the area to be electroplated by sputtering or copper deposition. The metal seed layer in this application is made of copper. The metal seed layer is used to ensure the bonding force between the metal to be electroplated and the molding compound, and at the same time to provide a surface for conductive ions to adhere to during electroplating, thus ensuring the electroplating effect.

[0022] All encapsulation processes in this application involve injection molding with molding compound to form the encapsulation. The encapsulating compound used in this application is epoxy resin encapsulating compound, which is low in cost and has good curing performance.

[0023] This application uses position marks 5 and anti-mistake marks 4 on substrate 1 to correspond to the groove edge and alignment marks 6 of wafer 2 to initially locate the placement position of multiple wafers 2, and forms bumps 3 on the chips of wafer 2. Multiple balls are assembled into a characteristic shape, and the alignment marks 6 are recorded. In subsequent process flows, the recorded marks are transferred to the molding mark 7 to accurately locate the position of wafer 2, prevent accidental damage during cutting, ensure that multiple wafers 2 can be processed under the same process, and small-sized wafers 2 can also achieve equipment compatibility, shorten processing time, and reduce production costs.

[0024] It is understood that this invention application has been described through some embodiments, and those skilled in the art will recognize that various changes or equivalent substitutions can be made to these features and embodiments without departing from the spirit and scope of this invention application. Furthermore, under the teachings of this invention application, these features and embodiments can be modified to adapt to specific situations and materials without departing from the spirit and scope of this invention application. Therefore, this invention application is not limited to the specific embodiments disclosed herein, and all embodiments falling within the scope of the claims of this invention application are within the protection scope of this invention application.

Claims

1. A wafer-level packaging method, characterized in that, Includes the following steps: Substrate marking steps: At least one set of anti-mistake marks and position marks are etched on one surface of the substrate, with each set of anti-mistake marks and position marks located on an extension line of equal length of the wafer diameter at that location; Wafer marking steps: First, the passive surface of the wafer is ground and thinned. Alignment marks identical to the position marks are formed on each wafer. Alignment marks are aligned with position marks. The flat edge or notch of the wafer is aligned with the error prevention mark to initially locate the placement position of the wafer on the substrate. Wafer diameter < spacing between position marks < 1.2 times wafer diameter; Packaging process steps: Make protrusions on the active surface of the wafer that match the error prevention marks and position marks. After encapsulation, transfer the marks on the protrusions onto the package body to form plastic encapsulation marks. Then, make wiring. Finally, separate the board according to the plastic encapsulation marks and cut it into individual finished products.

2. The wafer-level packaging method according to claim 1, characterized in that, In the substrate marking step, after marking, adhesive is applied to the surface of the substrate to bond the wafers, and the adhesive is a semi-transparent adhesive.

3. The wafer-level packaging method according to claim 2, characterized in that, In the substrate marking step, each set of anti-foolproof marks and position marks is located on the side length of the outer square concentric with the wafer at this location.

4. The wafer-level packaging method according to claim 3, characterized in that, In the wafer marking step, the thickness of the wafer is ≤400μm, and a pre-cutting is performed at the dicing channel of the wafer to form a pre-cutting channel. The depth of the pre-cutting channel is 0.5 to 0.7 times the thickness of the wafer.

5. The wafer-level packaging method according to claim 4, characterized in that, In the wafer marking step, pre-cut tracks are formed between chips that are close to each other on the wafer, and their width ranges from ≥60μm.

6. The wafer-level packaging method according to claim 5, characterized in that, The encapsulation process further includes: S1, grinding after encapsulation to expose protrusions to transfer markings onto the package; S2, sequentially exposing, developing, and electroplating each wafer to form wiring and leads; S3, encapsulating again, removing the substrate and adhesive thereon, and grinding the wafer from that side to the pre-cut track; S4, cutting the encapsulation material from the pre-cut track after separation to form a single product.

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