Polling arbitration method and device supporting access of multiple master control peripheral devices

Abstract

The invention discloses a polling arbitration method and device supporting access of multiple master control peripheral devices, and the method comprises the steps: monitoring an access request of the master control devices to a target resource, judging whether the target resource can be arbitrated or not according to an arbiter enable signal when the access requests of the multiple master control devices to the target resource are detected at the same time, and if yes, judging whether the target resource can be arbitrated or not; if the target resource can be arbitrated, determining an arbitration mode according to the mode selection signal, selecting a corresponding arbiter to arbitrate the plurality of main control devices according to the determined arbitration mode so as to enable the main control devices to access the target resource according to an arbitration authorization sequence, ending and exiting; otherwise, not authorizing access to all the main control devices. The arbitration mode can be determined through the mode selection signal, fusion of multiple arbitration modes can be achieved, the effect of the multiple arbitration modes is achieved, the arbitration modes and the arbiter can be expanded according to needs, and the advantages of being good in expansibility and high in flexibility are achieved.

Description

Technical Field

[0001] This invention belongs to the field of priority scheduling technology for chip resources, specifically relating to a method and apparatus for supporting polling arbitration of access to multiple master peripheral devices. Background Technology

[0002] With the development of integrated circuits, the integration density within chips is constantly increasing, and the coupling between different devices is becoming increasingly tight. In terms of chip resource usage, a resource or device may be accessed by multiple devices simultaneously. Therefore, priority scheduling and control of chip resources has become particularly important. A peripheral device within a chip can only be occupied by one master device at a time. When multiple master devices simultaneously initiate access requests, access conflicts occur. How to avoid conflicts arising from multiple master devices accessing peripherals simultaneously has become a critical technical problem that urgently needs to be solved. Summary of the Invention

[0003] The technical problem to be solved by the present invention is to provide a method and device for polling arbitration that supports access to multiple master peripheral devices, in view of the above-mentioned problems of the prior art. The present invention can determine the arbitration mode through the mode selection signal, realize the fusion of multiple arbitration modes, achieve the effect of multiple arbitration modes, and can expand the arbitration mode and arbitrator as needed, with the advantages of good scalability and high flexibility.

[0004] To solve the above-mentioned technical problems, the technical solution adopted by the present invention is as follows: A polling arbitration method supporting access from multiple master peripheral devices includes the following steps: S101, monitor the access requests of the master control device to the target resource. When multiple master control devices simultaneously send access requests to the target resource, proceed to step S102. S102, determine whether the target resource is arbitrable based on the arbitrator enable signal. If the target resource is arbitrable, proceed to step S103; otherwise, do not authorize access to any master control device, end and exit. S103, determine the arbitration mode according to the mode selection signal, select the corresponding arbitrator according to the determined arbitration mode to arbitrate multiple master control devices so that the master control devices can access the target resource in the order of arbitration authorization, and then end and exit.

[0005] Optionally, in step S102, when determining whether the target resource is arbitrable based on the arbitrator enable signal, the generation of the arbitrator enable signal includes: if no master device is currently accessing the target resource or the data transmission has ended, then the arbitrator enable signal is set to 1; if a master device is currently accessing the target resource and the data transmission has not ended, then the arbitrator enable signal is set to 0; when determining whether the target resource is arbitrable based on the arbitrator enable signal, if the arbitrator enable signal is 1, then the target resource is determined to be arbitrable; otherwise, the target resource is determined to be non-arbitrable.

[0006] Optionally, in step S103, when determining the arbitration mode based on the mode selection signal, the mode selection signal is set to 1 or 0, which is used to determine whether the arbitration mode is fair round-robin or weighted round-robin. When the arbitration mode is fair round-robin, the fair round-robin arbitrator authorizes a single master device to access the target resource sequentially according to the order of the master devices until there are no more access requests. When the arbitration mode is weighted round-robin, the weighted round-robin arbitrator arbitrates a single master device to access the target resource sequentially according to the weight of the master devices until there are no more access requests.

[0007] Optionally, the fair polling arbitrator includes a first state update control module, a first response module, and multiple first arbitration circuits corresponding one-to-one with the master control devices. Each first arbitration circuit includes a first authorization control module and a first shielding control module. The first state update control module generates a request signal req[N:0] based on access requests from multiple master control devices. It then inverts the shielding signal mask[N:0] returned by the first shielding control module in the first arbitration circuit and performs a bitwise AND operation with the request signal req[N:0] to obtain a new request signal new_reqs[2N:0] to control the enabling of the first authorization control modules in each first arbitration circuit. This ensures that only one of the N first authorization control modules has an enable signal of 1, while the enable signals of the remaining modules are 0, where N is the number of all master control devices. The first authorization control module generates authorization signals for the first shielding control module and the first response module respectively when the enable signal is 1. The first shielding control module generates authorization signals based on the access requests from multiple master control devices. The authorization signal generates a masking signal bit and outputs it to the first state update control module. The first masking control module is connected to the output of the first authorization control module in the same first arbitration circuit, the input of the first state update control module, the output of the first masking control module in the previous first arbitration circuit, and the input of the first masking control module in the next first arbitration circuit. If the authorization signal output by the first authorization control module is high, the first masking control module generates a corresponding masking signal mask[N:0] and sends it to the first state update control module. If the authorization result is low, the masking signal mask[N:0] is kept unchanged from the authorization signal of the first masking control module in the previous first arbitration circuit. The first response module is connected to the output of the first authorization control module in each first arbitration circuit and is used to authorize the corresponding single master control device to access the target resource sequentially according to the authorization signal output by the first masking control module in each first arbitration circuit until there is no more access request.

[0008] Optionally, the fair polling arbitrator includes four first arbitration circuits. When the first shielding control module generates a corresponding shielding signal mask[N:0] and sends it to the first state update control module, if the first shielding control module is the first shielding control module in the first first arbitration circuit, then the generated corresponding shielding signal mask[N:0] is 4'b0001; if the first shielding control module is the first shielding control module in the second first arbitration circuit, then the generated corresponding shielding signal mask[N:0] is 4'b0011; if the first shielding control module is the first shielding control module in the third first arbitration circuit, then the generated corresponding shielding signal mask[N:0] is 4'b0111; if the first shielding control module is the first shielding control module in the fourth first arbitration circuit, then the generated corresponding shielding signal mask[N:0] is 4'b1111.

[0009] Optionally, the weighted polling arbitrator includes a second state update control module, a weight control module, a second response module, and multiple second arbitration circuits corresponding one-to-one with the master control devices. The second arbitration circuit includes a second authorization control module and a second masking control module. The second state update control module generates a request signal req[N:0] based on the access requests from multiple master control devices. It inverts the masking signal mask[N:0] returned by the second masking control module in the second arbitration circuit and performs a bitwise AND operation with the request signal req[N:0] to obtain a new request signal new_reqs[2N:0], which is then used as the input to the weight control module. The weight control module uses the new request signal new_reqs[2N:0] and an externally input weight signal to control the enabling of the second authorization control module in each second response module, such that only one of the N second authorization control modules has an enable signal of 1, while the enable signals of the remaining second authorization control modules are 0, where N is the number of all master control devices. The second authorization control module generates authorization signals for the first... The system has two shielding control modules and a second response module. The second shielding control module generates a shielding signal bit based on the authorization signal and outputs it to the second state update control module. The second shielding control module is connected to the output of the second authorization control module in the same second arbitration circuit, the input of the second state update control module, the output of the second shielding control module in the previous second arbitration circuit, and the input of the second shielding control module in the next second arbitration circuit. If the authorization signal output by the second authorization control module is high, the second shielding control module generates a corresponding shielding signal mask[N:0] and sends it to the second state update control module. If the authorization result is low, the shielding signal mask[N:0] remains unchanged from the authorization signal of the second shielding control module in the previous second arbitration circuit. The second response module is connected to the output of the second authorization control module in each second arbitration circuit and is used to authorize the corresponding single master control device to access the target resource sequentially according to the authorization signal output by the second shielding control module in each second arbitration circuit until there is no more access request.

[0010] Optionally, when the weight control module controls the enabling of the second authorization control module in each second response module by using the new request signal new_reqs[2N:0] and the externally input weight signal, it includes generating an internal weight signal weight based on the externally input weight signal. The internal weight signal weight includes 2N bits, where N is the number of all master control devices. The high N bits represent the weight information of the master control devices in one polling cycle, and the low N bits represent the weight information of the master control devices in one polling cycle. The difference between the high N bits and the low N bits is that when the weight is reset, the low N bits will contain the master control device information of the last authorization in the previous polling cycle, while the high N bits will not. The module iteratively checks the value of each bit in the new request signal new_reqs[2N:0] and finds the first 1 value starting from the low bit. Assuming the first 1 value is located at new_reqs[i], indicating that the i%Nth master device has been polled, where i = 0, 1, ..., 2N-1, then we check if the weight[i] of the i%Nth master device is non-zero. If it is non-zero, it means that the master device still has authorization attempts, so the enable signal of the corresponding second arbitration circuit is set to 1, enabling the second arbitration circuit to start working. Otherwise, when the weight[i] of the i%Nth master device is 0, it means that the master device has been polled sequentially, but at this time the master device has no authorization attempts, the second arbitration circuit cannot take effect, and the master device cannot obtain authorization. We continue to look for the next 1 value and check whether the second arbitration circuit is working in the same way until a working second arbitration circuit is found.

[0011] The present invention also provides a polling arbitration device for supporting access to multiple master peripheral devices, comprising a microprocessor and a memory interconnected thereto, wherein the microprocessor is programmed or configured to execute the polling arbitration method for supporting access to multiple master peripheral devices.

[0012] The present invention also provides a computer-readable storage medium storing a computer program or instructions that are programmed or configured to execute the polling arbitration method for supporting access to multiple master peripheral devices via a processor.

[0013] The present invention also provides a computer program product, including a computer program or instructions, which are programmed or configured to execute the polling arbitration method for supporting access to multiple master peripheral devices via a processor.

[0014] Compared with existing technologies, the present invention mainly achieves the following beneficial effects: The method of the present invention includes monitoring access requests from master control devices to target resources. When multiple master control devices simultaneously issue access requests to the target resource, it determines whether the target resource is arbitrable based on the arbitrator enable signal. If the target resource is arbitrable, it determines the arbitration mode based on the mode selection signal, and selects the corresponding arbitrator to arbitrate the multiple master control devices according to the determined arbitration mode, so that the master control devices access the target resource in the order of arbitration authorization, and then terminates and exits; otherwise, it does not authorize access to any master control devices. The present invention can determine the arbitration mode through the mode selection signal, realize the fusion of multiple arbitration modes, achieve the effect of multiple arbitration modes, and can expand the arbitration modes and arbitrators as needed, with the advantages of good scalability and high flexibility. Attached Figure Description

[0015] Figure 1 This is a schematic diagram of the basic process of the method in an embodiment of the present invention.

[0016] Figure 2 This is a schematic diagram illustrating the selection process for two arbitration modes in an embodiment of the present invention.

[0017] Figure 3 This is a schematic diagram of the structure of the fair polling arbitrator in an embodiment of the present invention.

[0018] Figure 4 This is a schematic diagram of the weighted round-robin arbitrator in an embodiment of the present invention. Detailed Implementation

[0019] To enable those skilled in the art to better understand the technical solutions of the present invention, the technical solutions of the present invention will be further described in detail below with reference to the accompanying drawings in the embodiments of the present invention.

[0020] When multiple master devices simultaneously request access to the same peripheral, access conflicts can occur. To avoid these conflicts, a method is needed to arbitrate the access permissions of the master devices, establishing rules to specify which master device is authorized to use the peripheral. This invention relates to an arbitration method with mode switching. After the chip reset phase, when multiple master devices simultaneously access the same peripheral, a polling mode can be selected. This mode can choose to process each request fairly and sequentially, or it can choose to increase the access frequency of frequently requesting master devices by setting weights, thus resolving access conflicts when master devices access peripherals. Figure 1 As shown, this embodiment supports a multi-master peripheral device access polling arbitration method, which includes the following steps: S101, monitor the access requests of the master control device to the target resource (chip resource). When multiple master control devices simultaneously issue access requests to the target resource, proceed to step S102. S102, determine whether the target resource is arbitrable based on the arbitrator enable signal. If the target resource is arbitrable, proceed to step S103; otherwise, do not authorize access to any master control device, end and exit. S103, determine the arbitration mode according to the mode selection signal, select the corresponding arbitrator according to the determined arbitration mode to arbitrate multiple master control devices so that the master control devices can access the target resource in the order of arbitration authorization, and then end and exit.

[0021] Step S102 is used to determine whether a request can enter the arbitration device. If the arbitration device is enabled, the request can participate in arbitration; otherwise, the request cannot enter the arbitration device, and the request sent by the master control device will not be authorized. In this embodiment, when determining whether the target resource is arbitrable based on the arbitrator enable signal in step S102, the generation of the arbitrator enable signal includes: if no master control device is currently accessing the target resource or the data transmission has ended, then the arbitrator enable signal is set to 1; if a master control device is currently accessing the target resource and the data transmission has not ended, then the arbitrator enable signal is set to 0. When determining whether the target resource is arbitrable based on the arbitrator enable signal, if the arbitrator enable signal is 1, then the target resource is determined to be arbitrable; otherwise, the target resource is determined to be unarbitrable.

[0022] When multiple master control devices access the same peripheral, authorization restrictions need to be applied to the requests. This embodiment offers two modes: either sequential fair polling of all requests, or polling all requests by configuring weights. The former treats all requests fairly, ensuring all users have an equal opportunity to access resources, preventing any user from being consistently denied access and effectively resolving the request starvation phenomenon. The latter allows different master control devices to be configured with different weights; devices with higher weights receive more authorization opportunities, thus improving chip operating efficiency to some extent. Specifically... Figure 2As shown, in step S103 of this embodiment, when determining the arbitration mode based on the mode selection signal, the mode selection signal takes the value 1 or 0, used to determine whether the arbitration mode is fair round-robin or weighted round-robin. When the arbitration mode is fair round-robin, the fair round-robin arbitrator authorizes individual master devices to access the target resource sequentially according to the order of the master devices until there are no more access requests. When the arbitration mode is weighted round-robin, the weighted round-robin arbitrator arbitrates individual master devices to access the target resource sequentially according to the weight of the master devices until there are no more access requests. The arbitrator enable signal needs to be determined based on the current usage of the peripherals. When a master device is accessing a peripheral resource and data transmission is not yet complete, the arbitrator enable signal is low (i.e., 0), and the request cannot enter the arbitration device. When no master device is accessing a peripheral resource or data transmission is completed during the access process, the arbitrator enable signal is high (i.e., 1), and the request enters the arbitration device for arbitration. Figure 2 As shown, when multiple master devices simultaneously request access, the arbitrator's enable signal determines whether each request can enter the arbitration device. Access is permitted if no master device is currently accessing the peripheral or if data transmission has ended. If the arbitrator enable signal is 1, it indicates no device is accessing the resource or data transmission has ended, allowing the request to participate. If the signal is 0, it indicates a request is currently accessing the peripheral resource and data transmission is not yet complete; the request cannot participate and must wait until the current request finishes before proceeding. After multiple requests are granted access, the arbitration mode is determined by the mode selection signal. A mode selection signal of 0 indicates fair round-robin, where each master device accesses the peripheral sequentially until no further requests are received. A mode selection signal of 1 indicates weighted arbitration, where the number of responses received by each master device is configurable. More authorizations can be granted to master devices that frequently access peripherals, increasing their chances of gaining control. Once the arbitration mode is determined, the corresponding arbitrator will start working. After the arbitration is completed, the arbitration result will be output. Based on the arbitration result, you can view the specific authorized master control device number.

[0023] Arbitration rules can be selected based on the access needs of the master control devices. If there is no requirement for the urgency of the master control devices' requests for peripheral access, a fair round-robin method can be selected, ensuring all master control devices receive equal access opportunities and all requests are treated fairly, preventing any user from being consistently denied resources. If there is a requirement for the urgency of the master control devices' requests for peripheral access, a weighted round-robin method can be selected, increasing the authorization opportunities for master control devices through weight configuration. Before a request enters the arbitration device, the arbitrator's enable signal determines whether the request should proceed to arbitration. On one hand, once a request enters the arbitration device, a fair round-robin method can be selected, ensuring each master control device receives authorization fairly. When a request is authorized, this request and higher-priority master control devices are blocked, meaning the priority of this master control device is reduced, and the next higher-priority master control device request is arbitrated. Suppose four master devices need to access the same peripheral. Requests starting with 0 have the highest priority by default. Once request 0 is authorized, it is blocked. Then request 1 is authorized, and requests 0 and 1 are blocked again. Request 2 is then authorized, and requests 0, 1, and 2 are blocked. Similarly, request 3 is authorized, blocking requests 0, 1, 2, and 3. After one round-robin cycle, the blocking signal is released, and the four requests are re-arbitrated in the same manner. On the other hand, after a request enters the arbitration device, a weighted round-robin method can be selected. Each master device can be configured with different weights. The higher the weight, the more times the master device is authorized, and the greater the probability of the master device accessing the peripheral resource. During weight configuration, when the weight is configured to 0, the default number of authorizations for a request is 1, meaning the master device has at least one authorization attempt. During a round-robin process, when the master device has not exhausted its authorization attempts, each master device is polled fairly to prevent a starvation phenomenon caused by a single master device not receiving a response. Once a master device has exhausted its authorization attempts, it can no longer receive authorization until its weight is updated. If the authorization attempts of all master devices simultaneously requesting access are 0, the weight is updated to prevent situations where a master device continuously initiates requests while the peripheral device is in a ready state but no request is authorized.

[0024] like Figure 3 As shown, the fair polling arbitrator in this embodiment includes a first state update control module, a first response module, and multiple first arbitration circuits corresponding one-to-one with the main control device. Each first arbitration circuit includes a first authorization control module and a first shielding control module. The number of first arbitration circuits corresponds one-to-one with the number of main control devices, and the number of requests processed simultaneously is parameter-configurable, that is, the number of first arbitration circuits is configurable, thereby improving the flexibility of the arbitration device.

[0025] The first state update control module is used to determine the next first arbitration circuit to be polled, receive the shielding signal from the first shielding control module and the requests from all master control devices to generate polling information, which includes the master control device that should be polled at present, and transmit the polling information to the first arbitration weight control module. Specifically, in this embodiment, the first state update control module is used to generate a request signal req[N:0] based on the access requests from multiple master control devices, invert the shielding signal mask[N:0] returned by the first shielding control module in the first arbitration circuit, and perform a bitwise AND operation with the request signal req[N:0] to obtain a new request signal new_reqs[2N:0] to control the enabling of the first authorization control modules in each first arbitration circuit, so that the enabling signal of only one of the N first authorization control modules is 1 and the enabling signals of the remaining first authorization control modules are 0, where N is the number of all master control devices. Figure 3 For the example of N=4, the first state update control module is used to generate request signals req[3:0] based on the access requests from multiple master control devices. Figure 3Requests #1 to #4 represent access requests from four different master control devices. Request #1 corresponds to req[0], request #2 corresponds to req[1], request #3 corresponds to req[2], and request #4 corresponds to req[3]. A value of 1 for each bit indicates a request, and 0 indicates no request. The first state update control module determines the next working first arbitration circuit based on the request req[3:0] sent by the master control device and the mask signal mask from the first arbitration circuit. After a master control device is authorized, it needs to mask the requests sent by this master control device and poll the next master control device in sequence. Specifically, the mask signal is inverted and then ANDed with the request to update the request state. The request state of the authorized master control device is updated to 0. If requests #1 through #4 simultaneously request access (i.e., req[3:0] is 4'hF) and the masking signal mask[N:0] is also 4'hF, then inverting the masking signal mask[N:0] and ANDing it with req[3:0] yields the unmasked request signal nmask_req. It will be found that regardless of which master device sends the request, the unmasked signal is always 4'h0. If all master device requests are arbitrated at this point, it will be found that no request can be authorized because all request signals are masked. Therefore, a new request signal new_reqs[2N:0] is introduced to record each new request and unmasked request to avoid the situation where all requests are masked and no request is authorized. The new request signal new_req... The data width of s[2N:0] is twice the number of all requests, that is, N is 4 in this embodiment. The width of the new request signal new_reqs[2N:0] is 8 bits. The first four bits record the requests sent by the master device, and the last four bits record the request signals that are not currently blocked. That is, the value of the new request signal new_reqs[2N:0] is 8'hF0 at this time. The value of each bit in new_reqs is judged in a loop. The first 1 value from the low bit is found. The position of the first 1 value from the low bit indicates which master device the arbiter is currently polling. Since the last four bits are all 0, it means that all requests are blocked. It also means that one polling cycle has been completed. That is, one round of fair polling has been completed in the order of requests #1 to #4. It is necessary to release the blocking signal and re-polle all requests sent by the master devices. At this time, the value of the first four bits of the new request signal new_reqs[2N:0] will be judged. Since new_reqs[5] is the first 1 value of the low bit at this time, and this value comes from request #1, the peripheral control will be handed over to request #1, and the grant_id of 4'b0001 will be output to the first arbitration circuit. The enable signal of the first authorization control module #1 is valid, and the first arbitration circuit of request #1 starts to work.

[0026] In this embodiment, the first authorization control module generates authorization signals to the first shielding control module and the first response module respectively when the enable signal is 1. The first authorization control module is part of the first arbitration circuit. It determines whether to enable based on the enable signal and outputs the authorization result to the first shielding control module and the first response module respectively. The first authorization control module receives the grant_id signal from the first state update control module and outputs authorization signal 1 or 0. Each bit of grant_id can be regarded as the authorization control enable signal. Only one authorization control is valid at a time, that is, only one first arbitration circuit works at a time. For example, taking the first authorization control module #1 as an example, the valid enable signal of the first authorization control module #1 is grant_id[0]. When grant[0] is 1, it means that #1 is requested to obtain authorization. The first authorization control module #1 outputs authorization signal 1 to the first shielding control module #1 to facilitate the shielding signal update. It outputs the authorization result to the first state update control module to facilitate distinguishing which first arbitration circuit's shielding signal is received. It outputs the authorization result to the response control to facilitate notifying the peripheral device. At this time, which master control device gains control? Similarly, the effective enable signal of the first authorization control module #2 is grant_id[1]. When grant[1] is 1, it means that #2 is requested to be authorized. The first authorization control module #2 outputs an authorization signal to the first shield control module #2. The effective enable signal of the first authorization control module #3 is grant_id[2]. When grant[2] is 1, it means that #3 is requested to be authorized. The first authorization control module #3 outputs an authorization signal to the first shield control module #3. The effective enable signal of the first authorization control module #4 is grant_id[3]. When grant[3] is 1, it means that #4 is requested to be authorized. The first authorization control module #4 outputs an authorization signal to the first shield control module #4.

[0027] The first shielding control module is part of the first arbitration circuit. It is used to ensure fair polling of access by master devices. Each time a master device is authorized, its requests and requests with higher priority are temporarily blocked until all master device requests have been polled. Then all shielding signals are refreshed. This module contains two input ports and two output ports. One input port comes from the authorization control module of the first arbitration circuit, and the other input port comes from the output of the shielding module of the previous first arbitration circuit. One output port outputs a shielding signal to the first state update control module, and the other output port outputs a shielding signal to the shielding control module of the next first arbitration circuit. In this embodiment, the first shielding control module is used to generate a shielding signal bit according to the authorization signal and output it to the first state update control module. The first shielding control module is connected to the output terminal of the first authorization control module in the same first arbitration circuit, the input terminal of the first state update control module, the output terminal of the first shielding control module in the previous first arbitration circuit, and the input terminal of the first shielding control module in the next first arbitration circuit. If the authorization signal output by the output terminal of the first authorization control module is high, the first shielding control module generates the corresponding shielding signal mask[N:0] and sends it to the first state update control module. If the authorization result is low, the shielding signal mask[N:0] is kept unchanged from the authorization signal of the first shielding control module in the previous first arbitration circuit. Since the first shielding control module is connected to the output terminal of the first shielding control module in the previous first arbitration circuit and the input terminal of the first shielding control module in the next first arbitration circuit, a closed loop is formed between each first arbitration circuit. The shielding circuit of the previous first arbitration circuit will affect the shielding signal of the next first arbitration circuit. Figure 3 For an example with N=4, the masking signal mask[N:0] is mask[3:0]. Request #1 corresponds to mask[0], request #2 corresponds to mask[1], request #3 corresponds to mask[2], and request #4 corresponds to mask[3]. A value of 1 for each bit indicates that the request is masked, and 0 indicates that it is not masked. The first arbitration circuit enable information for each request corresponds to the signal grant_id[3:0], where request #1 corresponds to grant_id[0], request #2 corresponds to grant_id[1], request #3 corresponds to grant_id[2], and request #4 corresponds to grant_id[3]. A value of 1 for each bit indicates that the corresponding first arbitration circuit is enabled, and 0 indicates that the corresponding first arbitration circuit is invalid. Figure 3Taking the first shielding control module #1 as an example, when the first shielding control module #1 receives the authorization result from the first authorization control module #1, if the result is high, it sets the shielding signal mask[N:0] to 4'b0001 and sends it to the first state update control module. If the authorization result is low, the shielding signal remains unchanged from the result of the first shielding control module #4 in the previous first arbitration circuit. When the first shielding control module #2 receives the authorization result from the first authorization control module #2, if the result is high, it sets the shielding signal mask[N:0] to 4'b0011 and sends it to the first state update control module. If the authorization result is low, the shielding signal remains unchanged from the result of the first shielding control module #4 in the previous first arbitration circuit. The result of 1 remains unchanged; the first shielding control module #3 receives the authorization result from the first authorization control module #3. If the result is high, it sets the shielding signal mask[N:0] to 4'b0111 and sends it to the first state update control module. If the authorization result is low, the shielding signal remains unchanged from the result of the first shielding control module #2 in the previous first arbitration circuit; the first shielding control module #4 receives the authorization result from the first authorization control module #4. If the result is high, it sets the shielding signal mask[N:0] to 4'b1111 and sends it to the first state update control module. If the authorization result is low, the shielding signal remains unchanged from the result of the first shielding control module #4 in the previous first arbitration circuit.

[0028] In this embodiment, the first response module is connected to the output terminal of the first authorization control module in each of the first arbitration circuits. It is used to authorize the corresponding single master control device to access the target resource sequentially according to the authorization signal output by the first shielding control module in each of the first arbitration circuits until no further access requests are received. The first response module receives the authorization results from all authorization controls. Only one authorization control module operates at a time, and the response control outputs the arbitration result of the entire arbitrator, completing the arbitration when a master control device accesses the same peripheral. In this embodiment, the first response module has four input ports and one output port. The four inputs are respectively from the authorization results of the first arbitration circuits. It outputs the authorization (grant_num) signal to the peripheral, informing it which master control device can obtain access control at this time, thereby completing the arbitration function of the arbitrator.

[0029] As an optional implementation, the fair polling arbitrator includes four first arbitration circuits. When the first shielding control module generates a corresponding shielding signal mask[N:0] and sends it to the first state update control module, if the first shielding control module is the first shielding control module in the first first arbitration circuit, the generated corresponding shielding signal mask[N:0] is 4'b0001; if the first shielding control module is the first shielding control module in the second first arbitration circuit, the generated corresponding shielding signal mask[N:0] is 4'b0011; if the first shielding control module is the first shielding control module in the third first arbitration circuit, the generated corresponding shielding signal mask[N:0] is 4'b0111; if the first shielding control module is the first shielding control module in the fourth first arbitration circuit, the generated corresponding shielding signal mask[N:0] is 4'b1111.

[0030] In this embodiment, the arbitration process of the fair polling arbitrator is as follows: When the chip reset ends, no request is masked, that is, the value of the masking signal mask[N:0] is 0. After the reset ends, all requests from the master control devices enter the first state update control module. If all master control devices initiate access to peripheral devices, that is, requests #1 to #4 arrive at the same time, the masking signal is inverted and combined with the request to form a new request signal new_reqs[2N:0]. At this time, the value of the new request signal new_reqs[2N:0] is 8'hFF. Then, iterate through each bit and finds the first 1 value starting from the low bit, i.e., new_reqs[0]. If the first arbitration circuit enable signal grant_id[0] is set to 1 and the remaining bits are set to 0, it is sent to each first arbitration circuit. The first arbitration circuit of request #1 is activated, and the first arbitration circuits of the other requests are deactivated. The first authorization control module #1 outputs authorization result 1 to the first response module, indicating that request #1 has obtained peripheral control rights. The first authorization control module #1 outputs authorization result 1 to the first mask control module #1. The first mask control module #1 updates the mask value to the first state update control module and starts the next round of arbitration, thus completing the arbitration function of a fair polling arbitrator.

[0031] like Figure 4As shown, the weighted round-robin arbitrator in this embodiment includes a second state update control module, a weight control module, a second response module, and multiple second arbitration circuits corresponding one-to-one with the master control device. Each second arbitration circuit includes a second authorization control module and a second shielding control module. When the master control device initiates a request and is polled to receive this request, it needs to determine whether the master control device can obtain peripheral control rights based on the weight information. If there are no authorization attempts, even if the master control device is polled to receive the request, it still cannot obtain authorization. Compared to the fair round-robin arbitrator, the weighted round-robin arbitrator has an additional weight control module. The difference between the weighted round-robin authorization method and the fair round-robin method is that the fair round-robin method polls each master control device in a fixed order. As long as the master control device requests access and is polled to receive it in the correct order, the master control device can obtain peripheral control rights. However, in the weighted round-robin mode, when the master control device requests access and is polled to receive it in the correct order, the master control device may not necessarily obtain peripheral control rights. It is also necessary to analyze which second arbitration circuit is effective based on the weight information. Weight control determines the number of authorizations a master device can receive in a single polling cycle. A single polling cycle refers to the period between one weight reset and the next weight reset. Weight reset refers to reconfiguring new weights for all master devices. The reset rule is that the system enters a reset state when the weights of all requesting master devices are 0, without waiting for all master devices to have weights of 0. A single polling cycle can contain multiple polling periods. Taking four master devices as an example, a single polling period refers to polling all requests in the order of requests #5 to #8 corresponding to the four master devices.

[0032] In this embodiment, the second state update control module generates a request signal req[N:0] based on access requests from multiple master control devices. It inverts the mask signal mask[N:0] returned by the second mask control module in the second arbitration circuit and performs a bitwise AND operation with the request signal req[N:0] to obtain a new request signal new_reqs[2N:0], which serves as the input to the weight control module. The second state update control module determines the next pollable second arbitration circuit based on the requests from the master control devices and the mask signal from the second arbitration circuit. Unlike the first state update control module in the fair polling arbitrator, the second state update control module is no longer used to determine the next enabled second arbitration circuit, but rather to determine the next pollable second arbitration circuit. The next enabled second arbitration circuit refers to the next valid and working second arbitration circuit, and the next pollable second arbitration circuit refers to the second arbitration circuit that is polled sequentially. However, whether this second arbitration circuit is working depends on the weight control. The second state update control module determines the next polling circuit by inverting the shielding signal and then ANDing it with the request to update the request state. This is the same as the method in the fair polling arbitrator. The new request signal new_reqs[2N:0] is used to store the request state. The first four bits represent the request initiated by the master control device, and the last four bits represent the request that is not currently shielded. The difference is that the fair polling arbitrator outputs the second arbitration circuit enable information to the second arbitration circuit, while the weighted polling arbitrator needs to output the request polling information to the weight control module. If requests #5 to #8 request access simultaneously, i.e., req[3:0] is 4'hF and if the masking signal mask[N:0] is 4'h3, then invert mask[N:0] and AND it with req[3:0] to obtain the value of the unmasked request signal nmak_req, which is 4'hC. At this time, the value of the new request signal new_reqs[2N:0] is 8'hFC. The value of each bit in the new request signal new_reqs[2N:0] is checked in a loop, and the first 1 value from the least significant bit is found. Since new_reqs[2] is the first 1 value from the least significant bit, and this value comes from request #7, the next request polled is request #7. However, this does not mean that the next authorized request is request #7. The value of the new request signal new_reqs[2N:0] is output to the weight control module, and the weight control module determines the next authorized request number.

[0033] The weight control module is used to determine the device request of the next authorized master control device. It receives polling information and enables the next authorized first arbitration circuit under the combined effect of polling information and weight information. If a requesting master control device is polled sequentially and its weight information is not 0, the enable signal of this master control device is output to the first arbitration circuit. After the master control device is authorized, its corresponding weight will be decremented by 1. When the number of authorization attempts for the requested master control device is exhausted, the weight control enters a reset state. Specifically, in this embodiment, the weight control module is used to control the enabling of the second authorization control module in each second response module by combining the new request signal new_reqs[2N:0] with the externally input weight signal, so that only one of the N second authorization control modules has an enable signal of 1 and the enable signals of the rest of the second authorization control modules are 0, where N is the number of all master control devices. The weight control module controls the number of times each master device can be authorized during a single round-robin polling cycle. When a master device is polled sequentially, the weight information determines whether that device should be authorized. Weight control assigns a weight to each master device. When a master device is polled, if its weight is non-zero, its corresponding second arbitration circuit is enabled high, and the second arbitration circuit begins operation. After the second arbitration circuit finishes operating, its corresponding weight is decremented by 1. Otherwise, the next master device is polled until a working second arbitration circuit is found.

[0034] As an optional implementation, when the weight control module controls the enabling of the second authorization control module in each second response module by using the new request signal new_reqs[2N:0] and the externally input weight signal, it includes generating an internal weight signal weight based on the externally input weight signal. The internal weight signal weight includes 2N bits, where N is the number of all master control devices. The high N bits represent the weight information of the master control devices in one polling cycle, and the low N bits represent the weight information of the master control devices in one polling cycle. The difference between the high N bits and the low N bits is that when the weight is reset, the low N bits will contain the master control device information of the last authorization in the previous polling cycle, while the high N bits will not. The module iteratively judges the value of each bit in the new request signal new_reqs[2N:0] and finds the first bit from the low bit. If the first value is 1, and the position of the first 1 value is in new_reqs[i], it means that the i%Nth master device has been polled, where i=0,1,…,2N-1. Then, it is determined whether the weight[i] of the i%Nth master device is non-zero. If it is non-zero, it means that the master device still has authorization times, and the enable signal of the corresponding second arbitration circuit is set to 1 so that the second arbitration circuit starts working. Otherwise, when the weight[i] of the i%Nth master device is 0, it means that the master device has been polled in sequence, but at this time the master device has no authorization times, the second arbitration circuit cannot be effective, and the master device cannot get authorization. Continue to find the next 1 value, and judge whether the second arbitration circuit is working in the same way, until a working second arbitration circuit is found. The weight control module determines the next enabled second arbitration circuit by receiving the new request signal `new_reqs[2N:0]` from the second state update control module and the externally input weight signal. The number of master devices corresponds one-to-one with the number of externally input weights. However, since the next enabled second arbitration circuit needs to be determined based on the new request signal `new_reqs[2N:0]`, the number of internal weight values ​​must also correspond one-to-one with the `new_reqs[2N:0]` signal. The weight control module decrements the weight of the authorized master device by 1 by receiving the authorization result from the second arbitration circuit. Since the high four bits and low four bits of the weight value both correspond to the weight of the master device, when the authorization result of the second arbitration circuit is high, the high four bits and low four bits of the weight value corresponding to that master device must be decremented by 1, indicating that the authorization count for that master device is reduced by one; otherwise, the weight remains unchanged.When the weights of all requesting master control devices are 0, the system enters a weight reset state. This means that multiple master control devices initiate access requests, but none of them can be authorized. After entering the weight reset state, the weights are updated according to the externally input weights. The update rule is that the high four bits of the weight are consistent with the externally input weight, while the low four bits need to be determined based on the master control device sequence number authorized at the end of the last loop. The weight corresponding to the master control device authorized last time is reduced by 1 based on the externally input weight, while the weights of the other master control devices are consistent with the externally input weight.

[0035] In this embodiment, the second authorization control module is used to generate authorization signals to the second shielding control module and the second response module respectively when the enable signal is 1. The second authorization control module is part of the second arbitration circuit. It determines whether to enable based on the enable signal. The authorization result is output to the first shielding control module, the weight control module and the first response module respectively. The second authorization control module receives the grant_id signal from the second weight control module and outputs authorization signal 1 or 0. Each bit of grant_id can be regarded as the authorization control enable signal. Only one authorization control is valid at a time, that is, only one second arbitration circuit works at a time. The effective enable signal of the second authorization control module #1 is grant_id[0]. When grant[0] is 1, it means that request #5 is authorized. The second authorization control module #1 outputs authorization signal 1 to the second shielding control module #1 to facilitate the shielding signal update. It outputs the authorization result to the second state update control module to facilitate distinguishing which second arbitration circuit's shielding signal is received. It outputs the authorization result to the second response control module to facilitate notifying the peripheral which master control device is at this time. The second authorization control module #2 has the following effective enable signal: grant_id[1]. When grant[1] is 1, it means that request #6 has been granted authorization. The second authorization control module #2 outputs an authorization signal to the second shield control module #2. The second authorization control module #3 has the following effective enable signal: grant_id[2]. When grant[2] is 1, it means that request #7 has been granted authorization. The second authorization control module #3 outputs an authorization signal to the second shield control module #3. The second authorization control module #4 has the following effective enable signal: grant_id[3]. When grant[3] is 1, it means that request #8 has been granted authorization. The second authorization control module #4 outputs an authorization signal to the second shield control module #4.

[0036] The second shielding control module is part of the second arbitration circuit. When the authorization control is enabled, the shielding signal is updated, and the current authorization request and requests with higher priority are shielded. The shielding signal is then sent to the state update control, which sends request polling information to the weight control module. The weight control module determines the next authorized second arbitration circuit based on the weight information. When the second arbitration circuit is disabled, the shielding signal remains unchanged from the shielding signal of the previous second arbitration circuit. In this embodiment, the second shielding control module generates a shielding signal bit based on the authorization signal and outputs it to the second state update control module. The second shielding control module is connected to the output of the second authorization control module in the same second arbitration circuit, the input of the second state update control module, the output of the second shielding control module in the previous second arbitration circuit, and the input of the second shielding control module in the next second arbitration circuit. If the authorization signal output by the second authorization control module is high, the second shielding control module generates a corresponding shielding signal mask[N:0] and sends it to the second state update control module. If the authorization result is low, the shielding signal mask[N:0] remains unchanged from the authorization signal of the second shielding control module in the previous second arbitration circuit. The second shielding control module is used to ensure fair polling of master control device access. Each time a master control device is authorized, its requests and requests with higher priority are temporarily shielded until all master control device requests have been polled, and then all shielding signals are refreshed. This module contains two input ports and two output ports. One input port comes from the second authorization control module of the second arbitration circuit, and the other input port comes from the output of the shielding module of the previous second arbitration circuit. One output port outputs a shielding signal to the second state update control module, and the other output port outputs a shielding signal to the shielding control module of the next second arbitration circuit. The output shielding signal mask[N:0] mainly indicates which requests are currently shielded. The shielding control module only updates the shielding signal output to the second state update control module if the authorization result of the current second arbitration circuit is 1. If the authorization result of the shielding control input is 0, the shielding signal mask[N:0] remains unchanged from the previous shielding control request. Figure 4In the second state update control module, the second shielding control module #1 receives the authorization result from the second authorization control module #1. If the result is high, it sets the shielding signal mask to 4'b0001 and sends it to the second state update control module. If the authorization result is low, the shielding signal remains unchanged from the result of the second shielding control module #4 in the previous second arbitration circuit. Similarly, the second shielding control module #2 receives the authorization result from the second authorization control module #2. If the result is high, it sets the shielding signal mask to 4'b0011 and sends it to the second state update control module. If the authorization result is low, the shielding signal remains unchanged from the result of the second shielding control module #1 in the previous second arbitration circuit. The second shielding control module #3 receives the authorization result from the second authorization control module #3. If the result is high, it sets the shielding signal mask to 4'b0111 and sends it to the second state update control module. If the authorization result is low, the shielding signal remains unchanged from the result of the second shielding control module #2 in the previous second arbitration circuit. The second shielding control module #4 receives the authorization result from the second authorization control module #4. If the result is high, it sets the shielding signal mask to 4'b1111 and sends it to the second state update control module. If the authorization result is low, the shielding signal remains unchanged from the result of the second shielding control module #3 in the previous second arbitration circuit.

[0037] In this embodiment, the second response module is connected to the output terminal of the second authorization control module in each of the second arbitration circuits. It is used to authorize the corresponding single master control device to access the target resource sequentially until no further access requests are received, based on the authorization signals output by the second shielding control modules in each of the second arbitration circuits. The second response module has four input ports and one output port. The four inputs are from the authorization results of the second arbitration circuits, and the authorization signal is output to the peripheral device, informing it which master control device can obtain access control at this time, thereby completing the arbitration function of the weighted arbitrator.

[0038] In this embodiment, the arbitration process of the weighted round-robin arbitrator is as follows: When the chip reset ends, no requests are masked, that is, the value of mask[N:0] is 0, and the weight of each master device is set to 4. After the reset ends, all requests from the master devices enter the second state update control module. If all master devices initiate peripheral access requests, that is, requests #5 to #8 arrive at the same time, the mask signal is inverted and combined with the requests to form a new request signal new_reqs[4:0]. At this time, the value of the new request signal new_reqs[4:0] is 8'hFF. The new request signal new_reqs[4:0] is input to the weight control module, and each bit is judged in a loop. The first 1 value is found starting from the low bit. At this time, new_reqs[0] is low. The first 1 value at the beginning of the bit is determined because the first 1 value in the lower bit comes from request #1. Therefore, the weight value of request #1 is judged. The weight value is not 0, so the second arbitration circuit enable signal grant_id[0] is set to 1, and the remaining bits are set to 0 and sent to each second arbitration circuit. The second arbitration circuit of request #5 is effective, and the second arbitration circuits of the other requests are ineffective. The second authorization control module #1 outputs the authorization result 1 to the second response module, indicating that request #5 has obtained peripheral control rights. The second authorization control module #1 outputs the authorization result 1 to the second shielding control module #1. The second shielding control module #1 updates the mask[N:0] value to the second status update control module and starts the next round of arbitration, thus completing one arbitration process of the weighted round-robin arbitrator. In this embodiment, the authorization status of the master control device during the weighted round-robin process is shown in Table 1.

[0039] Table 1: Authorization Status of the Main Control Device During Weighted Round Robin Process

[0040] As shown in Table 1, initially, all four master control devices request access and none of them have a weight of 0. Following a fixed order, request #5 is granted access, and its weight is reduced by 1. During the second arbitration process, since request #6 did not initiate an access request, request #7 is polled sequentially and has a weight of 0, so request #7 grants access, and its weight is reduced by 1. During the third arbitration process, request #8 is polled sequentially and has a weight of 0, so request #8 grants access, and its weight is reduced by 1, completing one polling cycle. During the fourth polling process, request #5 did not initiate an access request, so request #6 is polled sequentially and has a weight of 0, so request #6 grants access, and its weight is reduced by 1. During the fifth polling process, request #7 is polled sequentially and has a weight of 0, so request #7 grants access, and its weight is reduced by 1. During the sixth polling process, request #8 is polled sequentially and has a weight of 0, so request #8 cannot obtain authorization. Request #5 is polled sequentially and has a weight of 0, so request #5 grants access, and its weight is reduced by 1.

[0041] In summary, to avoid conflicts arising when the master device simultaneously accesses peripherals, this embodiment designs a method to arbitrate the access permissions of the master device. The arbitrator establishes a rule specifying which request uses a resource, effectively scheduling access to shared resources or devices. When multiple users or master devices need to share the same resource, the requests need to be arbitrated to determine which master device gains access. The arbitrator's polling rules affect chip performance. If a master device continuously occupies peripheral access permissions, requests from other master devices will be "starved," significantly impacting chip performance. The arbitration design in this embodiment considers the request starvation phenomenon and can solve the starvation problem. Simultaneously, when a master device frequently requests access, the number of authorizations for that master device can be increased by configuring weights, effectively improving system operating efficiency. The method in this embodiment can select which arbitration method the master control device uses to obtain peripheral control according to the mode, and fairly poll each master control device to prevent requests from being starved. At the same time, if a master control device frequently requests access to peripherals, the number of authorizations for the master control device can be increased by configuring weights, which improves the utilization rate of resources within the chip to a certain extent. In addition, the one-to-one correspondence between the number of master control devices and the arbitration circuit improves the flexibility and portability of the arbitration device.

[0042] This embodiment also provides a multi-master peripheral device access polling arbitration device, including a microprocessor and a memory interconnected, wherein the microprocessor is programmed or configured to execute the multi-master peripheral device access polling arbitration method. This embodiment also provides a computer-readable storage medium storing a computer program or instructions programmed or configured to execute the multi-master peripheral device access polling arbitration method via a processor. This embodiment also provides a computer program product including a computer program or instructions programmed or configured to execute the multi-master peripheral device access polling arbitration method via a processor.

[0043] The above description is merely a preferred embodiment of the present invention. The scope of protection of the present invention is not limited to the above embodiments. All technical solutions falling within the scope of the present invention's concept are within the scope of protection of the present invention. It should be noted that for those skilled in the art, any improvements and modifications made without departing from the principles of the present invention should also be considered within the scope of protection of the present invention.

Claims

1. A method for supporting polling arbitration for access to multiple master peripheral devices, characterized in that, Includes the following steps: S101, monitor the access requests of the master control device to the target resource. When multiple master control devices simultaneously send access requests to the target resource, proceed to step S102. S102, determine whether the target resource is arbitrable based on the arbitrator enable signal. If the target resource is arbitrable, proceed to step S103. Otherwise, do not authorize access to any master control device, terminate and exit; S103, determine the arbitration mode according to the mode selection signal, select the corresponding arbitrator according to the determined arbitration mode to arbitrate multiple master control devices so that the master control devices can access the target resource in the order of arbitration authorization, and then end and exit.

2. The method for supporting multi-master peripheral device access polling arbitration according to claim 1, characterized in that, In step S102, when determining whether the target resource is arbitrable based on the arbitrator enable signal, the generation of the arbitrator enable signal includes: if no master device is currently accessing the target resource or the data transmission has ended, then the arbitrator enable signal is set to 1; if a master device is currently accessing the target resource and the data transmission has not ended, then the arbitrator enable signal is set to 0; when determining whether the target resource is arbitrable based on the arbitrator enable signal, if the arbitrator enable signal is 1, then the target resource is determined to be arbitrable; otherwise, the target resource is determined to be non-arbitrable.

3. The method for supporting multi-master peripheral device access polling arbitration according to claim 1, characterized in that, In step S103, when determining the arbitration mode based on the mode selection signal, the mode selection signal is set to 1 or 0, which is used to determine whether the arbitration mode is fair round-robin or weighted round-robin. When the arbitration mode is fair round-robin, the fair round-robin arbitrator authorizes a single master device to access the target resource in sequence according to the order of the master devices until there are no more access requests. When the arbitration mode is weighted round-robin, the weighted round-robin arbitrator arbitrates the access of individual master devices to the target resource in turn according to the weight of the master device until there are no more access requests.

4. The method for supporting multi-master peripheral device access polling arbitration according to claim 3, characterized in that, The fair polling arbitrator includes a first state update control module, a first response module, and multiple first arbitration circuits corresponding one-to-one with the master control devices. Each first arbitration circuit includes a first authorization control module and a first shielding control module. The first state update control module generates a request signal `req[N:0]` based on access requests from multiple master control devices. It then inverts the shielding signal `mask[N:0]` returned by the first shielding control module in the first arbitration circuit and performs a bitwise AND operation with the request signal `req[N:0]` to obtain a new request signal `new_reqs[2N:0]`. This new request signal controls the enabling of the first authorization control modules in each first arbitration circuit, ensuring that only one of the N first authorization control modules has an enable signal of 1, while the enable signals of the remaining modules are 0, where N is the number of all master control devices. The first authorization control module generates authorization signals for the first shielding control module and the first response module when the enable signal is 1. The first shielding module generates authorization signals based on the authorization signal... The first shielding control module generates a shielding signal bit and outputs it to the first state update control module. The first shielding control module is connected to the output of the first authorization control module in the same first arbitration circuit, the input of the first state update control module, the output of the first shielding control module in the previous first arbitration circuit, and the input of the first shielding control module in the next first arbitration circuit. If the authorization signal output by the first authorization control module is high, the first shielding control module generates a corresponding shielding signal mask[N:0] and sends it to the first state update control module. If the authorization result is low, the shielding signal mask[N:0] is kept unchanged from the authorization signal of the first shielding control module in the previous first arbitration circuit. The first response module is connected to the output of the first authorization control module in each first arbitration circuit and is used to authorize the corresponding single master control device to access the target resource sequentially according to the authorization signal output by the first shielding control module in each first arbitration circuit until there is no more access request.

5. The method for supporting multi-master peripheral device access polling arbitration according to claim 4, characterized in that, The fair polling arbitrator includes four first arbitration circuits. When the first shielding control module generates a corresponding shielding signal mask[N:0] and sends it to the first state update control module, if the first shielding control module is the first shielding control module in the first first arbitration circuit, the generated corresponding shielding signal mask[N:0] is 4'b0001; if the first shielding control module is the first shielding control module in the second first arbitration circuit, the generated corresponding shielding signal mask[N:0] is 4'b0011; if the first shielding control module is the first shielding control module in the third first arbitration circuit, the generated corresponding shielding signal mask[N:0] is 4'b0111; if the first shielding control module is the first shielding control module in the fourth first arbitration circuit, the generated corresponding shielding signal mask[N:0] is 4'b1111.

6. The method for supporting multi-master peripheral device access polling arbitration according to claim 3, characterized in that, The weighted polling arbitrator includes a second state update control module, a weight control module, a second response module, and multiple second arbitration circuits corresponding one-to-one with the master control devices. Each second arbitration circuit includes a second authorization control module and a second shielding control module. The second state update control module generates a request signal req[N:0] based on access requests from multiple master control devices. It inverts the shielding signal mask[N:0] returned by the second shielding control module in the second arbitration circuit and performs a bitwise AND operation with the request signal req[N:0] to obtain a new request signal new_reqs[2N:0], which serves as the input to the weight control module. The weight control module uses the new request signal new_reqs[2N:0] and an externally input weight signal to control the enabling of the second authorization control modules in each second response module, such that only one of the N second authorization control modules has an enable signal of 1, while the enable signals of the remaining second authorization control modules are 0, where N is the number of all master control devices. The second authorization module generates authorization signals for the second screen when the enable signal is 1. The system comprises a masking control module and a second response module. The second masking control module generates a masking signal bit based on the authorization signal and outputs it to the second state update control module. The second masking control module is connected to the output of the second authorization control module in the same second arbitration circuit, the input of the second state update control module, the output of the second masking control module in the previous second arbitration circuit, and the input of the second masking control module in the next second arbitration circuit. If the authorization signal output by the second authorization control module is high, the second masking control module generates a corresponding masking signal mask[N:0] and sends it to the second state update control module. If the authorization result is low, the masking signal mask[N:0] remains unchanged from the authorization signal of the second masking control module in the previous second arbitration circuit. The second response module is connected to the output of the second authorization control module in each second arbitration circuit and is used to authorize the corresponding single master control device to access the target resource sequentially until there are no more access requests based on the authorization signal output by the second masking control module in each second arbitration circuit.

7. The method for supporting multi-master peripheral device access polling arbitration according to claim 6, characterized in that, The weight control module is used to control the enabling of the second authorization control module in each second response module by using the new request signal new_reqs[2N:0] and the externally input weight signal. This includes generating an internal weight signal weight based on the externally input weight signal. The internal weight signal weight includes 2N bits, where N is the number of all master control devices. The high N bits represent the weight information of the master control devices in one polling cycle, and the low N bits represent the weight information of the master control devices in one polling cycle. The difference between the high N bits and the low N bits is that when the weight is reset, the low N bits will contain the master control device information from the last authorization in the previous polling cycle, while the high N bits will not. The module iteratively checks the value of each bit in the new request signal new_reqs[2N:0], finding the first 1 value starting from the low bit. Assuming... The first 1 value in new_reqs[i] indicates that the i%Nth master device has been polled, where i=0,1,…,2N-1. Then, it is checked whether the weight[i] of the i%Nth master device is non-zero. If it is non-zero, it means that the master device still has authorization attempts, and the enable signal of the corresponding second arbitration circuit is set to 1 to enable the second arbitration circuit to start working. Otherwise, when the weight[i] of the i%Nth master device is 0, it means that the master device has been polled in sequence, but at this time the master device has no authorization attempts, the second arbitration circuit cannot be effective, and the master device cannot obtain authorization. Continue to find the next 1 value, and check whether the second arbitration circuit is working in the same way, until a working second arbitration circuit is found.

8. A polling arbitration device supporting access to multiple master peripheral devices, comprising a microprocessor and a memory interconnected, characterized in that, The microprocessor is programmed or configured to execute the polling arbitration method for supporting access to multiple master peripheral devices as described in any one of claims 1 to 7.

9. A computer-readable storage medium storing a computer program or instructions, characterized in that, The computer program or instructions are programmed or configured to execute, via a processor, the polling arbitration method for supporting access to multiple master peripheral devices as described in any one of claims 1 to 7.

10. A computer program product, comprising a computer program or instructions, characterized in that, The computer program or instructions are programmed or configured to execute, via a processor, the polling arbitration method for supporting access to multiple master peripheral devices as described in any one of claims 1 to 7.

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