Real-time frequency domain signal editing and processing system and method

Abstract

The invention discloses a real-time frequency domain signal editing and processing system and method, and belongs to the technical field of signal processing. The system comprises an ADC acquisition module, an FPGA signal processing module, a DAC output module and a control and interaction module. The ADC module digitizes an input analog signal; an FFT (Fast Fourier Transform) unit, a frequency domain editing unit and an IFFT (Inverse Fast Fourier Transform) unit which adopt a parallel pipeline architecture are integrated in the FPGA module, so that real-time frequency domain transformation of signals, user interactive amplitude / phase adjustment and noise superposition are realized, and time domain signals are reconstructed through IFFT; and the DAC module outputs the edited analog signal. The method is based on the system, and full-process real-time processing of collection, frequency domain editing and reconstruction output is achieved. The invention solves the problem that the existing signal equipment has a single function and cannot edit and reconstruct in real time, has the advantages of low processing delay, flexibility in editing and high integration level, and is suitable for scenes such as communication test, circuit debugging and scientific research experiment.

Description

Technical Field

[0001] This invention relates to the field of signal processing technology, specifically to a system and method capable of real-time frequency domain analysis, editing, and reconstruction of the output of an input signal, applicable to scenarios such as communication testing, electronic circuit debugging, industrial measurement, and scientific experiments. Background Technology

[0002] In the field of signal testing, analysis, and simulation, the functions of common instruments and equipment are often independent of each other. Signal generators (or arbitrary waveform generators) are mainly used to generate preset or standard time-domain signals (such as sine waves, square waves, noise, etc.). Their core function is "generation," and they usually do not have the ability to analyze external input signals in real time and dynamically modify the signal content based on the analysis results. On the other hand, spectrum analyzers or oscilloscopes with FFT functions can convert input time-domain signals into frequency-domain representations (i.e., spectra), thereby revealing the frequency components, amplitude, and phase information of the signal. However, their function is limited to "analysis" and they cannot reconstruct the modified spectrum into a time-domain signal in real time and output it.

[0003] This separation of "generation" and "analysis" devices results in cumbersome and inefficient workflows when simulating complex electromagnetic environments, testing filter responses, injecting circuit faults, or verifying real-time signal processing algorithms. Engineers or researchers typically need to design or edit the signal spectrum in computer software, download it to the signal generator output, and then observe the effect using an analyzer, failing to achieve "what you see is what you get" real-time interaction and closed-loop testing. Existing integrated solutions are often based on general-purpose computer software processing, limited by the operating system and non-real-time hardware, introducing large and variable delays that cannot meet the application requirements with strict requirements for processing latency (such as communication protocol testing and real-time control system simulation).

[0004] Therefore, existing technologies lack a hardware system that can deeply integrate functions such as high-bandwidth signal acquisition, real-time frequency domain transformation, flexible human-computer interaction editing, and low-latency signal reconstruction output, making it difficult to support efficient real-time signal processing and simulation tasks. Summary of the Invention

[0005] The purpose of this invention is to provide a high real-time performance and high integration frequency domain signal editing and processing system and method to solve the problem that the functions of signal generation and analysis equipment are separated in the prior art, and that frequency domain editing and reconstruction output cannot be performed in real time.

[0006] To achieve the above objectives, the present invention provides the following technical solution: In a first aspect, the present invention provides a real-time frequency domain signal editing and processing system, which mainly includes: an analog-to-digital converter (ADC) signal acquisition module, a signal processing module, a digital-to-analog converter (DAC) signal output module connected in sequence, and a control and interaction module communicatively connected to the signal processing module; The ADC signal acquisition module is used to acquire analog input signals in real time and convert the analog input signals into digital signal sequences at a configurable sampling rate (preferably not less than 100 MSPS). The signal processing module is the core of the entire system, and its functions are implemented by a field-programmable gate array (FPGA). This module further integrates three key functional units: an FFT unit, a frequency domain editing unit, and an IFFT unit.

[0007] The FFT unit performs a Fast Fourier Transform (FFT) on the digital signal sequence from the ADC, converting the time-domain signal into its frequency-domain complex representation, thereby obtaining the amplitude and phase information of the signal at each frequency point.

[0008] The frequency domain editing unit, serving as the execution end of the human-computer interaction, receives user commands and parameters from the control and interaction module. Users can select specific frequency points or bands on the spectrum and perform operations such as amplitude adjustment (e.g., amplification or attenuation) and phase adjustment (e.g., rotation) on these frequency components. Furthermore, this unit also supports directly superimposing analog noise of specified types and intensities (e.g., white noise, pink noise, Gaussian noise) in the frequency domain to construct complex signal environments.

[0009] The IFFT unit performs an inverse fast Fourier transform (IFFT) on the spectral data processed by the frequency domain editing unit, converting the modified frequency domain signal back into a time domain digital signal sequence.

[0010] The DAC signal output module receives the time-domain digital sequence from the IFFT unit and converts it into an analog voltage signal at an update rate matching the ADC sampling rate, and finally outputs it to an external load or the next stage system.

[0011] The control and interaction module typically runs on a host computer (such as a PC) and interacts with the FPGA via a high-speed communication interface (such as PCIe or Gigabit Ethernet). This module provides a graphical user interface that displays the spectrum of the ADC input signal in real time. Simultaneously, the interface offers a rich set of controls (such as sliders, input boxes, and graphical selection tools), allowing users to intuitively select frequencies and set editing parameters. All user operations are encoded into control commands in real time and sent to the frequency domain editing unit within the FPGA.

[0012] The FFT unit, frequency domain editing unit, and IFFT unit adopt a parallel pipeline architecture within the FPGA, enabling the signal processing flow to be executed continuously and the total system processing delay to be fixed.

[0013] The key improvement of this invention lies in the fact that the FFT unit, frequency domain editing unit, and IFFT unit are not executed serially within the FPGA chip, but are designed and deployed using a parallel pipeline architecture. This means that while one frame of data is being transformed by the FFT unit, the previous frame of data may be being processed in the frequency domain editing unit, while the data from the frame before that is simultaneously being inversely transformed and output in the IFFT unit. The units are connected through an efficient data buffering mechanism (such as the ping-pong buffer described later). This architecture ensures that the entire data processing flow from signal acquisition to edited output is continuous and uninterrupted, resulting in a fixed total processing latency that is much smaller than the processing cycle of a single frame of data (e.g., stably less than 1 millisecond), achieving truly high real-time performance.

[0014] Furthermore, to facilitate independent amplitude and phase operations on the complex-form spectral data, the signal processing module also includes a coordinate rotating digital computer (CORDIC) processing unit. Before the frequency domain editing operation, this unit decomposes the complex signal output by the FFT into amplitude and phase vectors; after the editing operation, it reassembles the modified amplitude and phase vectors into a complex signal for use by the IFFT unit. Accordingly, the frequency domain editing unit can be specifically divided into an amplitude adjustment module and a phase adjustment module, which respectively perform multiplier-based gain scaling and adder-based phase rotation.

[0015] Furthermore, the parallel pipeline architecture typically includes dedicated data buffer units, such as the classic "ping-pong buffer" structure or a deeply optimized pipeline register set, to ensure that data can be smoothly and conflict-free transferred between the three main processing stages of FFT, edit and IFFT. This is a key hardware guarantee for maintaining low latency and high throughput.

[0016] Furthermore, in addition to providing real-time graphical interaction, the control and interaction module can also be extended to support remote control protocols (such as SCPI commands) and script programming interfaces (such as Python API), enabling the entire signal processing flow to be integrated into an automated testing system to achieve batch and repeatable testing tasks.

[0017] Secondly, the present invention also provides a real-time frequency domain signal editing and processing method based on the above system, comprising the following steps: 1. Signal Acquisition and Digitization: Analog input signals are acquired in real time at a high sampling rate using an ADC module and converted into digital signal sequences.

[0018] 2. Time-domain to frequency-domain transformation: Inside the FPGA, the FFT unit performs an FFT on the digital signal sequence to obtain the frequency-domain complex representation of the signal.

[0019] 3. Interactive Frequency Domain Editing: The control and interaction module receives user editing instructions (including amplitude adjustment, phase adjustment, and noise superposition parameters) for specific frequency components in the spectrum and sends them to the FPGA. The frequency domain editing unit in the FPGA modifies the corresponding frequency domain data in real time according to these instructions.

[0020] 4. Frequency Domain to Time Domain Reconstruction: The edited frequency domain data is inversely transformed by the IFFT unit to restore the edited time domain digital signal sequence.

[0021] 5. Analog signal output: The DAC module converts the reconstructed time-domain digital sequence into an analog signal and outputs it.

[0022] The core transformation, editing, and inverse transformation steps (i.e., steps 2-4) are executed in a parallel pipeline within the FPGA. This means that the processing is overlapped rather than executed sequentially, thus ensuring that the total end-to-end processing delay from acquisition to output is fixed and minimized.

[0023] Furthermore, before the editing operation in step 3, the CORDIC algorithm can be used to decompose the complex spectrum into amplitude and phase components to facilitate independent mathematical operations; after the editing operation is completed, the CORDIC algorithm is used to resynthesize the adjusted amplitude and phase into a complex form, and then IFFT is performed.

[0024] Compared with the prior art, the beneficial effects of the present invention are: 1. Achieved true real-time closed-loop processing: Signal analysis (spectrum display) and signal generation (edited output) are deeply integrated at the hardware level, with extremely low (millisecond-level) and deterministic processing latency, allowing users to adjust parameters in real time and immediately observe changes in the output signal.

[0025] 2. Provides unprecedented frequency domain editing flexibility: Users can directly perform precise editing (amplitude modulation, phase modulation, noise addition) on any frequency component on an intuitive spectrogram, greatly simplifying the construction process of complex test signals.

[0026] 3. High integration, simplified test system: A single device replaces the combination of "signal generator + spectrum analyzer + possible real-time processor", reducing the complexity of connection and synchronization between devices and improving test efficiency and equipment utilization.

[0027] 4. Wide range of applications: It can be widely used in many fields that require dynamic and interactive signal processing, such as communication transceiver testing, filter characteristic analysis, electronic warfare signal simulation, audio effects processing, vibration and acoustic experiments, and teaching demonstrations. Attached Figure Description

[0028] The accompanying drawings are provided to further illustrate the invention and form part of the specification. They are used in conjunction with embodiments of the invention to explain the invention and do not constitute a limitation thereof. In the drawings: Figure 1 This is a schematic diagram of the system of the present invention; Figure 2 This is a schematic diagram of the internal flow of the signal processing module of the present invention; Figure 3 The example image used to verify the algorithm shows a comparison of the time-domain and frequency-domain waveforms before and after processing. Detailed Implementation

[0029] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0030] Example 1: System Hardware Configuration and Data Flow like Figure 1 As shown, the real-time frequency domain signal editing and processing system of the present invention consists of the following four main parts: including an ADC signal acquisition module, a signal processing module (implemented by FPGA), a DAC signal output module, and a control and interaction module (usually running on a host computer and communicating with the FPGA through high-speed interfaces such as PCIe and Ethernet).

[0031] 1. ADC signal acquisition module: Employs a high-speed, high-precision analog-to-digital converter chip (such as Analog Devices' AD92xx series), with a sampling rate of... It can be configured via FPGA, with typical values ​​set to 100 MSPS or higher, to accommodate input signals of different bandwidths.

[0032] 2. Signal Processing Module (FPGA): This is the core of the system's computation. An FPGA chip with sufficient logic resources, DSP units, and high-speed interfaces (such as the Xilinx Kintex-7 series or Intel Arria 10 series) is selected. The x[n] sequence is input to the FPGA via a high-speed parallel bus (such as LVDS) or a JESD204B interface.

[0033] 3. DAC Signal Output Module: Employs a high-speed digital-to-analog converter chip matched to the ADC performance. Its update rate is synchronized with the ADC sampling rate fs to ensure the integrity of signal sampling and reconstruction. This module outputs the time-domain digital sequence processed by the FPGA. Convert to analog signal Output.

[0034] 4. Control and Interaction Module: This is typically an industrial PC or laptop running customized host computer software. It connects to the FPGA development board via a PCIe card or Gigabit Ethernet cable to enable high-speed data upload (for spectrum display) and control command issuance.

[0035] Example 2: FPGA Internal Pipeline Processing Flow See Figure 2 This demonstrates in detail the parallel pipelined processing of data input to output within an FPGA. The process is based on "frames," with each frame containing N consecutive sampling points (e.g., N=1024 or 2048).

[0036] The input analog signal x(t) is sampled to obtain a discrete digital signal sequence x[n], where n is the sampling point index, indicating the time nT. s The signal value at T, where T s The sampling period.

[0037] Step 1: FFT Transformation The FFT unit receives a frame of data x[n] from the ADC. This digital sequence is fed into the FFT unit in the FPGA to perform an N-point Fast Fourier Transform, resulting in a frequency domain complex representation X[k], where each frequency point contains amplitude and phase information. in As a frequency index, the physical frequency corresponding to each frequency point k is: in The sampling frequency.

[0038] Step 2: CORDIC Decomposition and Frequency Domain Editing Complex numbers output by FFT Immediately sent to the CORDIC processing unit. CORDIC operates in vector mode, processing each... Decompose it into its amplitude and phase .

[0039] The decomposed amplitude and phase data flow into the frequency domain editing unit. This unit maintains an editing parameter table that is sent in real-time from the host computer. This table defines the gain factor for each frequency point k. (Used for amplitude adjustment); phase shift (Used for phase adjustment); noise spectrum (If noise superposition is enabled). The frequency domain editing unit will then perform the following edits: Amplification adjustment: Harmonic components are amplified or attenuated using a multiplier. Phase adjustment: Adjusting the phase via an adder: Noise superposition (optional): A specified type of noise spectrum can be directly superimposed on the adjusted frequency domain signal. .

[0040] Adjusted amplitude value and phase Using the CORDIC IP rotation mode, the real and imaginary parts of complex numbers can be directly output: The frequency domain editing unit performs multiplicative adjustments on amplitude and additive adjustments on phase according to user settings, and can also select to add noise. The edited amplitude and phase are resynthesized into a complex signal using a CORDIC unit. Then, through the IFFT unit, Transform back to time-domain digital sequence Finally, the update rate of the DAC module is matched with the ADC sampling rate to convert the digital signal... Convert to analog signal Output.

[0041] Step 4: Data Buffering and Pipeline Parallelism Figure 2The "data buffer unit" is key to achieving low latency: the entire processing flow employs a deeply optimized parallel pipeline architecture within the FPGA. Units such as FFT, CORDIC, editing logic, and IFFT are organized into multi-stage pipelines, with data buffering between stages via ping-pong buffers or register sets. This allows the system to process different stages of multiple frames of data simultaneously in a "pipelined" manner (e.g., while processing the IFFT of frame M, frequency domain editing is being performed on frame M+1, and FFT is being performed on frame M+2). By rationally designing the pipeline depth and clock frequency, and ensuring that the processing time of a single module is shorter than the length of a single frame of data, the system achieves a fixed total processing latency from acquisition to output, which is less than the processing cycle of a single frame of signal (e.g., for a frame length of 1ms, the system latency can be controlled in the hundreds of microseconds).

[0042] The control and interaction module supports remote control and script programming, enabling automated testing processes. The user interface displays the spectrum in real time, supports interactive frequency domain editing, and sends edited parameters to the FPGA in real time, achieving a "what you see is what you get" signal processing effect.

[0043] Example 3: User Interaction and Verification Users operate the system through the host computer software interface (control and interaction module). The main window of the interface displays the dynamic spectrum of the ADC input signal in real time.

[0044] 1. The user uses the mouse to select a frequency range on the spectrum (e.g., a narrow band with a center frequency of f0).

[0045] 2. In the parameter panel, set the gain G for this frequency band to +6 dB (i.e., amplification by 2 times), and the phase shift... Set it to 90 degrees (π / 2 radians), check "Add Gaussian white noise", and set the signal-to-noise ratio.

[0046] 3. User clicks "Apply" or parameter adjustments take effect immediately (depending on the mode). Parameters are instantly sent to the FPGA's frequency domain editing unit via the communication interface.

[0047] To verify the effect, using a standard 1MHz sine wave input as an example, the user can enhance the amplitude of a certain harmonic, adjust its phase, and superimpose Gaussian white noise. Before processing: The time-domain waveform is a standard sine wave; the frequency-domain waveform is a single 1MHz spectral line. After processing: The time-domain waveform is distorted, with increased amplitude and phase shift, and random fluctuations are superimposed; in the frequency-domain graph, the spectral line amplitude at 1MHz is significantly increased, the phase changes, and a uniformly raised noise floor appears against the background. A comparison of the time-domain and frequency-domain waveforms before and after processing is provided. Figure 3As shown in the figure, from top to bottom, are: time-domain waveform before processing, frequency-domain waveform before processing, time-domain waveform after processing, and frequency-domain waveform after processing, indicating that the system can effectively achieve frequency-domain editing and signal reconstruction.

[0048] The results directly demonstrate that the system of the present invention can accurately and in real time respond to any editing operation performed by the user in the frequency domain and successfully reconstruct the corresponding time domain signal.

[0049] In summary, this invention, through innovative hardware architecture design, successfully constructs a high-real-time and highly flexible frequency domain signal editing and processing platform, effectively filling the gap in existing test and measurement equipment.

[0050] Finally, it should be noted that the above descriptions are merely preferred embodiments of the present invention and are not intended to limit the present invention. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art can still modify the technical solutions described in the foregoing embodiments or make equivalent substitutions for some of the technical features. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A real-time frequency domain signal editing and processing system, characterized in that, The analog-to-digital converter (ADC) signal acquisition module, the signal processing module, and the digital-to-analog converter (DAC) signal output module are connected in sequence. And a control and interaction module that is communicatively connected to the signal processing module; The ADC signal acquisition module is used to convert analog input signals into digital signal sequences at a configurable sampling rate; The signal processing module includes an FFT unit, a frequency domain editing unit, and an IFFT unit integrated within a field-programmable gate array (FPGA); The FFT unit is used to perform a fast Fourier transform on the digital signal sequence to obtain a frequency domain complex signal; The frequency domain editing unit is used to adjust at least one of the amplitude and phase of a specified frequency component in the frequency domain complex signal according to the parameters set by the user through the control and interaction module, and / or to superimpose analog noise in the frequency domain; The IFFT unit is used to perform an inverse fast Fourier transform on the frequency domain signal processed by the frequency domain editing unit to restore it to a time domain digital signal sequence. The DAC signal output module is used to convert the time-domain digital signal sequence into an analog signal output; The FFT unit, frequency domain editing unit, and IFFT unit adopt a parallel pipeline architecture within the FPGA, enabling the signal processing flow to be executed continuously and the total system processing delay to be fixed.

2. The real-time frequency domain signal editing and processing system according to claim 1, characterized in that, The signal processing module also includes a coordinate rotating digital computer (CORDIC) processing unit, which decomposes the complex signal output by FFT into amplitude and phase before frequency domain editing, and resynthesizes the edited amplitude and phase into a complex signal after frequency domain editing.

3. The real-time frequency domain signal editing and processing system according to claim 2, characterized in that, The frequency domain editing unit includes: The amplitude adjustment module is used to amplify or attenuate the amplitude of selected frequency components according to the gain factor set by the user. The phase adjustment module is used to adjust the phase of selected frequency components according to the phase offset set by the user.

4. The real-time frequency domain signal editing and processing system according to claim 1, characterized in that, The frequency domain editing unit further includes a noise superposition unit, used to add at least one of white noise, pink noise, or Gaussian noise to the signal in the frequency domain.

5. The system according to claim 1, characterized in that, The parallel pipeline architecture includes a data buffer unit, which adopts a ping-pong buffer structure or a pipeline register group to perform data buffering and connection between the FFT unit, the frequency domain editing unit and the IFFT unit.

6. The real-time frequency domain signal editing and processing system according to claim 1, characterized in that, The control and interaction module supports remote control and script programming, allowing users to select frequency points or frequency bands and adjust editing parameters in real time. The frequency domain editing unit updates in real time in response to parameter changes.

7. The system according to claim 6, characterized in that, The control and interaction module supports remote control interfaces and script programming to implement automated signal processing procedures.

8. The real-time frequency domain signal editing and processing system according to claim 1, characterized in that, The sampling rate of the ADC signal acquisition module is not less than 100 MSPS, the update rate of the DAC signal output module matches the sampling rate, and the total processing delay of the system is less than 1 millisecond.

9. A real-time frequency domain signal editing and processing method based on the system described in any one of claims 1-8, characterized in that, Includes the following steps: Real-time acquisition of analog input signals and conversion into digital signal sequences; Perform a Fast Fourier Transform on the digital signal sequence to obtain a complex signal in the frequency domain; Receive user editing instructions to adjust at least one of the amplitude and phase of a specified frequency component in the frequency domain, and / or add analog noise; The edited frequency domain signal is then subjected to an inverse fast Fourier transform to restore it to a time-domain digital signal sequence. Convert the time-domain digital signal sequence into an analog signal output; The transformation, editing, and inverse transformation steps are executed in parallel pipeline mode in the FPGA, so that the total processing delay from acquisition to output is fixed.

10. The method according to claim 9, characterized in that, Before adjusting the frequency components, the CORDIC algorithm is used to decompose the frequency domain complex signal into amplitude and phase; after adjustment, the CORDIC algorithm is used to resynthesize the adjusted amplitude and phase into a complex signal.

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