Multilayer ceramic capacitor and method of manufacturing the same

Abstract

The invention provides a multilayer ceramic capacitor and a method of manufacturing the same. The multilayer ceramic capacitor includes a capacitor body and an outer electrode disposed on an outer surface of the capacitor body. The capacitor body includes an active region in which first dielectric layers and inner electrode layers are alternately disposed, and a cover region in which second dielectric layers are disposed on upper and lower surfaces of the active region in a stacking direction, and an outer electrode including an interface layer disposed on a surface of the active region and an outer layer covering the interface layer, the interface layer has a bridge structure including a body region, a plurality of pillar regions, and a spanning region disposed between the plurality of pillar regions, the pillar regions of the interface layer being connected to the inner electrode layer, the spanning region of the interface layer being disposed on a surface of the first dielectric layer. The ratio of the number of inner electrode layers of the pillar strip region connected to the interface layer is 90% or more and 100% or less based on the total number of inner electrode layers in the active region.

Description

Technical Field

[0001] This disclosure relates to a multilayer ceramic capacitor and a method for manufacturing a multilayer ceramic capacitor. Background Technology

[0002] Ceramic electronic components include capacitors, inductors, piezoelectric elements, varistors, and thermistors. Among ceramic electronic components, multilayer ceramic capacitors (MLCCs) are used in various electronic devices due to their advantages such as small size, high capacitance, and ease of installation.

[0003] For example, a multilayer ceramic capacitor can be a chip capacitor mounted on a printed circuit board of various electronic products, such as imaging devices (e.g., liquid crystal displays (LCDs), plasma display panels (PDPs)), computers, personal portable terminals, and smartphones, for charging or discharging from them.

[0004] Recently, with the miniaturization and increasing capacitance of MLCCs, research is underway on miniaturizing the thickness of the inner electrode and dielectric layer, and efforts are being made to improve the contact between the inner and outer electrodes. To improve the connectivity between the inner and outer electrodes, a paste containing small-sized metal particles for forming the outer electrode should be used.

[0005] However, as the metal particles used become smaller, the cost per particle increases due to the difficulty of synthesis. Additionally, the content of other polymers (such as dispersants and binders) required to improve the dispersibility and adhesion of the paste used to form the external electrode also increases relatively. With the increase in the content of other polymers, the metal solids content becomes relatively low, which alters the viscosity and rheological properties, affecting printability. Summary of the Invention

[0006] This disclosure provides a multilayer ceramic capacitor with improved connectivity between the inner electrode layer and the outer electrode, thereby exhibiting excellent capacitance characteristics and moisture resistance reliability.

[0007] This disclosure provides a method for manufacturing multilayer ceramic capacitors.

[0008] A multilayer ceramic capacitor according to one aspect of this disclosure includes: a capacitor body comprising a plurality of dielectric layers and a plurality of internal electrode layers, the plurality of dielectric layers including a first dielectric layer and a second dielectric layer, the plurality of internal electrode layers being stacked such that the first dielectric layer is interposed therebetween; and an external electrode disposed on an outer surface of the capacitor body, wherein the capacitor body includes an effective region and a cover region, the effective region including the first dielectric layer and the internal electrode layers, the cover region including the second dielectric layer, the second dielectric layer being disposed on a first surface and a second surface of the effective region, wherein the first surface is opposite to the second surface in a stacking direction, and the external electrode is disposed on a first surface and a second surface of the effective region. The device includes an interface layer and an outer layer. The interface layer is disposed on a third surface and / or a fourth surface of the effective region. The outer layer covers the interface layer. The interface layer has a bridge structure, which includes a main region, a plurality of pillar regions, and a crossing region. The pillar regions are connected to the main region, and the crossing region is disposed between the plurality of pillar regions. The pillar regions of the interface layer are connected to the inner electrode layer. The crossing region of the interface layer is disposed on the surface of the first dielectric layer. Based on the total number of inner electrode layers in the effective region, the ratio of the number of inner electrode layers connected to the pillar regions of the interface layer is greater than or equal to about 90% and less than or equal to about 100%.

[0009] The columnar region of the interface layer can extend into the interior of the capacitor body and connect to the inner electrode layer.

[0010] The column region of the interface layer may include an alloy containing a conductive metal.

[0011] The columnar region of the interface layer may include a Cu-Ni alloy.

[0012] The column region of the interface layer may include an amount of the alloy ranging from about 60 vol% to about 100 vol% based on the total amount of the column region.

[0013] The spanning area of ​​the interface layer may include glass.

[0014] The glass may include at least one selected from alumina (Al2O3) and silicon dioxide (SiO2).

[0015] The cross-region of the interface layer may include approximately 60% to approximately 100% of the glass, based on the total amount of the cross-region.

[0016] The main area of ​​the interface layer may include conductive metal.

[0017] The main region of the interface layer may include copper (Cu).

[0018] The main region of the interface layer may include approximately 60% to approximately 100% of the conductive metal based on the total amount of the main region.

[0019] The column region of the interface layer may include an alloy containing a conductive metal, the span region of the interface layer may include glass, and the body region of the interface layer may include the conductive metal.

[0020] The columnar region of the interface layer may include a Cu-Ni alloy, the cross region of the interface layer may include glass, and the body region of the interface layer may include copper (Cu).

[0021] The inner electrode layer may include an alloy at the interface with the interface layer, and the alloy may include a conductive metal.

[0022] According to another aspect of this disclosure, a multilayer ceramic capacitor includes: a capacitor body comprising a plurality of dielectric layers and a plurality of internal electrode layers, the plurality of dielectric layers including a first dielectric layer and a second dielectric layer, the plurality of internal electrode layers being stacked such that the first dielectric layer is interposed therebetween; and an external electrode disposed on an outer surface of the capacitor body, wherein the capacitor body includes an effective region and a cover region, the effective region including the first dielectric layer and the internal electrode layers, the cover region including the second dielectric layer, the second dielectric layer being disposed on a first surface and a second surface of the effective region, wherein the first surface is opposite to the second surface in a stacking direction, and the external electrode... The electrode includes an interface layer and an outer layer. The interface layer is disposed on a third surface and / or a fourth surface of the effective region. The outer layer covers the interface layer. The interface layer has a bridge structure, which includes a main region, a plurality of pillar regions, and a crossing region. The pillar regions are connected to the main region, and the crossing region is disposed between the plurality of pillar regions. The pillar regions of the interface layer are connected to the inner electrode layer. The crossing region of the interface layer is disposed on the surface of the first dielectric layer. The main region of the interface layer includes a conductive metal, the pillar regions of the interface layer include an alloy containing the conductive metal, and the crossing region of the interface layer includes glass.

[0023] The conductive metal may include copper (Cu), the alloy may include Cu-Ni alloy, and the glass may include aluminum oxide (Al2O3) and silicon dioxide (SiO2).

[0024] A method for manufacturing a multilayer ceramic capacitor according to one aspect of this disclosure includes: forming an external electrode on the surface of a capacitor body, the capacitor body including a plurality of dielectric layers and a plurality of internal electrode layers, the plurality of internal electrode layers being stacked such that the dielectric layers are interposed therebetween, wherein the external electrode includes an interface layer and an outer layer covering the interface layer, the step of forming the external electrode including: coating a metal-organic decomposition (MOD) ink onto the surface of the capacitor body, reducing the coated metal-organic decomposition (MOD) ink to form a metal particle film; coating a paste comprising a conductive metal and a glass composition onto the metal particle film; and firing the metal particle film and the coated paste to form the interface layer and the outer layer, wherein the interface layer has a bridge structure, the bridge structure including a body region, a plurality of pillar regions and a crossing region, the pillar regions being connected to the body region, the crossing region being disposed between the plurality of pillar regions, the pillar regions of the interface layer being connected to the internal electrode layers, and the crossing region of the interface layer being disposed on the surface of the dielectric layer.

[0025] The metal-organic decomposition (MOD) ink may include metal ligand materials, amine compounds, binders, antioxidants, and solvents.

[0026] The metal particle film may include metal nanoparticles with a size of about 10 nm to about 100 nm.

[0027] Based on the total amount of the paste, the paste may include about 20 wt% to about 40 wt% of the glass composition.

[0028] A method for manufacturing a multilayer ceramic capacitor according to another aspect of this disclosure includes: forming an external electrode on a surface of a capacitor body, the capacitor body including a plurality of dielectric layers and a plurality of inner electrode layers, the plurality of inner electrode layers being stacked such that the dielectric layers are interposed therebetween, wherein the external electrode includes an interface layer and an outer layer covering the interface layer, the step of forming the external electrode including: coating a metal ligand material onto the surface of the capacitor body; reducing the coated metal ligand material to form a film comprising metal particles; coating the film with a paste comprising a composition of a conductive metal and a glass; and firing the film and the coated paste to form the interface layer and the outer layer, wherein the interface layer comprises glass.

[0029] The interface layer may have a bridge structure, which includes a main body region, a plurality of pillar regions and a crossing region. The pillar regions are connected to the main body region, and the crossing region is disposed between the plurality of pillar regions. The pillar regions of the interface layer may extend from the inner electrode layer to the main body region, and the crossing region of the interface layer may be disposed on the surface of the dielectric layer.

[0030] The step of reducing the coated metal ligand material can be carried out in a nitrogen atmosphere at a temperature of 170°C to 300°C for 30 minutes to 3 hours.

[0031] The metal ligand material may include copper formate.

[0032] The multilayer ceramic capacitor according to this disclosure has excellent capacitance characteristics and moisture resistance reliability due to the improved connectivity between the inner electrode layer and the outer electrode. Attached Figure Description

[0033] Figure 1 This is a perspective view showing a multilayer ceramic capacitor according to an embodiment.

[0034] Figure 2 It is along Figure 1 A cross-sectional view of a multilayer ceramic capacitor taken by line I-I'.

[0035] Figure 3 It is along Figure 1 A cross-sectional view of a multilayer ceramic capacitor taken from line II-II'.

[0036] Figure 4 It is shown Figure 1 An exploded perspective view of the stacked structure in the capacitor body.

[0037] Figure 5A This is a schematic diagram showing the external electrodes of a multilayer ceramic capacitor according to an embodiment.

[0038] Figure 5B yes Figure 5A A magnified view of region R in the image.

[0039] Figure 6 This is a schematic diagram illustrating a method for manufacturing the external electrode of a multilayer ceramic capacitor according to an embodiment.

[0040] Figure 7 The images are scanning electron microscope (SEM) analysis images of the external electrodes of the multilayer ceramic capacitor according to Example 1. Figure 7 In the diagram, (b) is an enlarged view of the framed area shown in (a), and (c) is an enlarged view of the framed area shown in (b).

[0041] Figure 8 The images are based on scanning electron microscopy (SEM) analysis of the external electrodes of the multilayer ceramic capacitor in Comparative Example 1. Figure 8 In the diagram, (b) is an enlarged view of the framed area shown in (a), and (c) is an enlarged view of the framed area indicated in (b).

[0042] Figure 9The images are based on scanning electron microscopy-energy dispersive spectroscopy (SEM-EDS) mapping analysis images of the external electrodes of the multilayer ceramic capacitor in Example 1.

[0043] Figure 10 The images are based on scanning electron microscopy-energy dispersive spectroscopy (SEM-EDS) mapping analysis images of the external electrodes of the multilayer ceramic capacitor in Comparative Example 1.

[0044] Figure 11 This is a diagram showing the capacitance characteristics of the multilayer ceramic capacitors according to Example 1 and Comparative Example 1.

[0045] Figure 12 This is a diagram illustrating the moisture resistance reliability of the multilayer ceramic capacitor according to Example 1.

[0046] Figure 13 This is a diagram showing the moisture resistance reliability of the multilayer ceramic capacitor according to Comparative Example 1. Detailed Implementation

[0047] The present disclosure will now be described in detail with reference to the accompanying drawings, in which embodiments of the disclosure are illustrated. The drawings and description are to be considered illustrative rather than restrictive in nature. Throughout the specification, the same reference numerals denote the same elements. In the drawings, some components are exaggerated, omitted, or shown schematically, and the dimensions of each component do not perfectly reflect their actual dimensions.

[0048] The accompanying drawings are intended only to facilitate understanding of the embodiments disclosed in this specification, and it should be understood that the technical concepts disclosed herein are not limited to the drawings, and all variations, equivalents or alternatives within the scope of the technical concepts disclosed herein are included within the scope of this disclosure.

[0049] Although terms such as "first," "second," etc., are used to describe various components, the components are not limited by these terms. These terms are only used to distinguish one component from another.

[0050] Furthermore, it should be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" another element, the element may be directly on the other element, or there may be an intermediate element present. Conversely, when an element is referred to as being "directly on" another element, there is no intermediate element present. Additionally, when an element is referred to as being "on" or "above" a reference element, the element may be positioned above or below the reference element, and the element is not necessarily positioned "on" or "above" the reference element in a direction opposite to the direction of gravity.

[0051] Throughout this specification, the words “comprising” and variations such as “including” or “having” are intended to specify the presence of the said features, quantities, steps, operations, components, parts, and / or combinations thereof, but do not exclude the presence or addition of one or more other features, quantities, steps, operations, components, parts, and / or combinations thereof. Therefore, unless explicitly stated otherwise, the words “comprising” and variations such as “including” or “having” are to be understood as implying the inclusion of the said elements but not excluding any other elements.

[0052] Furthermore, throughout the instruction manual, the phrase "in plan view" or "on a plane" indicates the target portion as viewed from the top, while the phrase "in cross-sectional view" or "on a cross-section" indicates the cross-section formed by vertically cutting the target portion as viewed from the side.

[0053] Throughout this specification, the term "connection" may refer not only to a situation where two or more constituent components are directly connected, but also to a situation where two or more constituent components are indirectly connected through another constituent component, or to a situation where two or more constituent components are electrically or physically connected, or to a situation where two or more constituent components are called by different names according to their location or function but are integrated.

[0054] Furthermore, throughout the specification, when it is mentioned that "the region includes one component as the main component," it means that among the at least two components present in the region, that one component has the highest content based on the total amount of the components.

[0055] In the following text, reference will be made to Figures 1 to 4 A multilayer ceramic capacitor according to an embodiment will be described.

[0056] Figure 1 This is a perspective view showing a multilayer ceramic capacitor according to an embodiment. Figure 2 It is along Figure 1 A cross-sectional view of a multilayer ceramic capacitor taken by line I-I'. Figure 3 It is along Figure 1 A cross-sectional view of a multilayer ceramic capacitor taken from line II-II', and Figure 4 It is shown Figure 1 An exploded perspective view of the stacked structure in the capacitor body.

[0057] Figures 1 to 4The L-axis, W-axis, and T-axis directions shown represent the length, width, and thickness directions of the capacitor body 110, respectively. Here, the thickness direction (T-axis) can be perpendicular to the wide surface (main surface) of the sheet assembly and can be used, for example, as the same concept as the stacking direction of the stacked dielectric layers 111. The length direction (L-axis) can be a direction extending parallel to the wide surface (main surface) of the sheet assembly and can be substantially perpendicular to the thickness direction (T-axis). For example, the length direction (L-axis) can be the direction in which the first external electrode 131 and the second external electrode 132 are opposite each other. The width direction (W-axis) can be a direction extending parallel to the wide surface (main surface) of the sheet assembly and can be substantially perpendicular to both the thickness direction (T-axis) and the length direction (L-axis). The length of the sheet assembly in the length direction (L-axis) can be greater than the width of the sheet assembly in the width direction (W-axis).

[0058] Reference Figures 1 to 4 According to an embodiment, the multilayer ceramic capacitor 100 includes a capacitor body 110 and external electrodes 131 and 132 disposed on the outer surface of the capacitor body 110. The external electrodes 131 and 132 may include a first external electrode 131 and a second external electrode 132 disposed at opposite ends of the capacitor body 110 in the longitudinal direction (L-axis direction).

[0059] For example, the capacitor body 110 may have a generally hexahedral shape.

[0060] For ease of description of the embodiments, the two surfaces of the capacitor body 110 that are opposite to each other in the thickness direction (T-axis direction) are referred to as the first surface and the second surface, the two surfaces connected to the first surface and the second surface and opposite to each other in the length direction (L-axis direction) are referred to as the third surface and the fourth surface, and the two surfaces connected to the first surface and the second surface, as well as the third surface and the fourth surface and opposite to each other in the width direction (W-axis direction) are referred to as the fifth surface and the sixth surface.

[0061] As an example, the first surface, which serves as the lower surface, can be a mounting surface. Alternatively, the first to sixth surfaces can be flat, but the embodiment is not limited to this. For example, the first to sixth surfaces can be curved surfaces with a convex central portion, and the edges that form the boundaries of each surface can be rounded.

[0062] The shape and size of the capacitor body 110 and the number of stacked dielectric layers 111 are not limited to the shape and size of the capacitor body and the number of stacked dielectric layers shown in the accompanying drawings of the embodiment.

[0063] The capacitor body 110 includes a plurality of dielectric layers 111 and inner electrode layers 121 and 122. Specifically, the capacitor body 110 includes a plurality of dielectric layers 111 and a first inner electrode layer 121 and a second inner electrode layer 122 alternately disposed in the thickness direction (T-axis direction), and the dielectric layer 111 is located between the first inner electrode layer 121 and the second inner electrode layer 122.

[0064] At this point, the adjacent dielectric layers 111 of the capacitor body 110 can be integrated to such an extent that the boundaries between them are difficult to distinguish without the use of a scanning electron microscope (SEM).

[0065] The capacitor body 110 may include an effective area A and coverage areas 112 and 113.

[0066] The effective region A is a region where dielectric layer 111 and inner electrode layers 121 and 122 are alternately disposed, and the effective region A contributes to the capacitance of the multilayer ceramic capacitor 100. Specifically, the effective region A may be a region where the first inner electrode layer 121 and the second inner electrode layer 122 are stacked along the thickness direction (T-axis direction).

[0067] Cover regions 112 and 113 are thickness-direction edges and can be respectively disposed on the upper and lower surfaces of the effective region A in the thickness direction (T-axis direction). Cover regions 112 and 113 can be a single dielectric layer or two or more dielectric layers stacked on the upper and lower surfaces of the effective region A, respectively.

[0068] In addition, the capacitor body 110 may also include a side edge region.

[0069] The side edge region is the edge portion in the width direction and can be respectively disposed on the opposite side surfaces of the effective region in the width direction (W-axis direction), that is, it can be respectively disposed on the surfaces of the effective region corresponding to the fifth surface and the sixth surface. The side edge region can be formed in the following manner: when a conductive paste layer for the internal electrode is coated on the surface of the dielectric green sheet, the conductive paste layer is coated only in a portion of the surface of the dielectric green sheet, and the conductive paste layer is not coated on both sides of the surface of the dielectric green sheet, and the dielectric green sheets coated with the conductive paste layer are stacked and then fired, but the formation method is not limited to this.

[0070] Covered areas 112 and 113, as well as side edge areas, are used to prevent damage to the inner electrode layers 121 and 122 due to physical or chemical stress.

[0071] A detailed description of dielectric layer 111 and inner electrode layers 121 and 122 will be provided later.

[0072] external electrode According to the embodiment, the external electrodes 131 and 132 are provided with voltages of different polarities and can be electrically connected to the exposed portions of the first inner electrode layer 121 and the second inner electrode layer 122, respectively.

[0073] According to the above structure, when a predetermined voltage is applied to the first external electrode 131 and the second external electrode 132, charge accumulates between the first inner electrode layer 121 and the second inner electrode layer 122 facing each other. At this time, the capacitance of the multilayer ceramic capacitor 100 is proportional to the stacked area of ​​the first inner electrode layer 121 and the second inner electrode layer 122 stacked together along the T-axis direction in the effective region.

[0074] The first external electrode 131 may include a first connecting portion disposed on the third surface of the capacitor body 110 and connected to the first inner electrode layer 121, and a first strip portion disposed on the edge where the third surface of the capacitor body 110 intersects with the first surface and the second surface and / or the fifth surface and the sixth surface. The second external electrode 132 may include a second connecting portion disposed on the fourth surface of the capacitor body 110 and connected to the second inner electrode layer 122, and a second strip portion disposed on the edge where the fourth surface of the capacitor body 110 intersects with the first surface and the second surface and / or the fifth surface and the sixth surface.

[0075] The first strip may extend from the first connecting portion to a portion of the first surface and a portion of the second surface and / or a portion of the fifth surface and a portion of the sixth surface of the capacitor body 110, and the second strip may extend from the second connecting portion to a portion of the first surface and a portion of the second surface and / or a portion of the fifth surface and a portion of the sixth surface of the capacitor body 110. The first strip and the second strip can be used to improve the bonding strength between the first external electrode 131 and the second external electrode 132 and the capacitor body 110.

[0076] Figure 5A This is a schematic diagram showing the external electrodes of a multilayer ceramic capacitor according to an embodiment, and Figure 5B yes Figure 5A A magnified view of region R in the image.

[0077] Reference Figure 2 as well as Figure 5A and Figure 5BAccording to the embodiment, the external electrodes 131 and 132 include interface layers 10 and 30 disposed on the surface of the effective region A of the capacitor body 110, and outer layers 20 and 40 covering the interface layers 10 and 30. The interface layers 10 and 30 are configured to be connected to the inner electrode layers 121 and 122. Specifically, the first external electrode 131 includes a first interface layer 10 connected to the first inner electrode layer 121 and a first outer layer 20 covering the first interface layer 10. In addition, the second external electrode 132 includes a second interface layer 30 connected to the second inner electrode layer 122 and a second outer layer 40 covering the second interface layer 30.

[0078] For example, interface layers 10 and 30 can be defined as regions in a direction perpendicular to the stacking direction (i.e., in the length direction (L-axis direction) of the multilayer ceramic capacitor), extending from the interface between the outer electrodes 131 and 132 and the inner electrode layers 121 and 122 toward the outer electrodes to a depth of about 1 μm to about 5 μm from the interface (e.g., a depth of about 2 μm to about 4 μm from the interface).

[0079] Interface layers 10 and 30 (i.e., the first interface layer 10 and the second interface layer 30) may have a bridge structure, which includes a main body region 12, a plurality of column regions 14 connected to the main body region 12 (e.g., the first part of the main body region 12), and a spanning region 16 disposed between the plurality of column regions 14.

[0080] Here, the column region 14 can be connected to the inner electrode layers 121 and 122, and specifically, can extend into the interior of the capacitor body 110 to connect to the inner electrode layers 121 and 122. Furthermore, a cross region 16 can be provided on the surface of the dielectric layer 111.

[0081] For example, the main body region 12 may be a region extending from the interface between interface layers 10 and 30 and outer layers 20 and 40 toward a depth of approximately 5% to approximately 15% of the thickness of interface layers 10 and 30. Furthermore, the pillar region 14 may be located in a region extending from the interface between outer electrodes 131 and 132 and inner electrode layers 121 and 122 toward a depth of approximately 85% to approximately 95% of the thickness of interface layers 10 and 30. Additionally, the crossing region 16 may be located in a region extending from the interface between outer electrodes 131 and 132 and dielectric layer 111 toward a depth of approximately 85% to approximately 95% of the thickness of interface layers 10 and 30.

[0082] The outer electrode, including an interface layer with a bridge structure, improves contact with the inner electrode layer and forms a hermetically sealed structure that prevents external moisture from entering. Therefore, a multilayer ceramic capacitor with excellent capacitance characteristics and moisture resistance reliability can be ensured.

[0083] According to an embodiment, the column regions 14 of interface layers 10 and 30 are connected to the inner electrode layers 121 and 122. Specifically, based on the total number of inner electrode layers 121 and 122 in the effective region A, the ratio of the number of inner electrode layers 121 and 122 connected to the column regions 14 of interface layers 10 and 30 can be greater than or equal to about 90% and less than or equal to about 100% (e.g., it can be about 93% to 100%, or it can be about 95% to 100%). When the column regions of the inner electrode layers and the interface layers are connected within the above-mentioned ratio range, as the contact between the outer electrode and the inner electrode layers increases, the column regions of the inner electrode layers and the interface layers can form an airtight sealing structure, which is a completely closed and sealed structure that completely blocks the entry of external moisture.

[0084] The interface layers 10 and 30 with the bridge structure may include conductive metal and glass.

[0085] The interface layers 10 and 30 of the external electrodes 131 and 132 according to the embodiment can be formed by coating the surface of the capacitor body 110 with metal-organic decomposition (MOD) ink including a metal ligand material.

[0086] Typically, when small-sized Cu particles are used in pastes for forming external electrodes to improve contact properties, the specific surface area of ​​the particles becomes very large, leading to an increase in dispersant content. Furthermore, the increased specific surface area due to the increased particle size can cause friction, resulting in a significant increase in the static viscosity of the paste, thus causing numerous problems when forming external electrodes using conventional impregnation methods. In addition, small Cu particles are difficult to obtain and have high production costs, making them uneconomical.

[0087] In the embodiments, when the interface layers 10 and 30 of the outer electrodes 131 and 132 are formed by coating with MOD ink, the metal, such as Cu, forms a complex with the organic material and exists as ions, thus offering advantages such as no dispersibility issues, very low static viscosity, and inexpensive raw materials. The organic material can be removed using a simple reduction process to obtain fine Cu particles with a very small size of less than or equal to about 100 nm. These fine Cu particles can be used to improve the contact characteristics between the inner electrode layer and the outer electrode.

[0088] The conductive metals included in interface layers 10 and 30 may include at least one metal selected from copper (Cu), nickel (Ni), silver (Ag), palladium (Pd), gold (Au), platinum (Pt), tin (Sn), tungsten (W), titanium (Ti), and lead (Pb). Furthermore, interface layers 10 and 30 may also include alloys of the aforementioned conductive metals.

[0089] Specifically, the main body region 12 of the interface layers 10 and 30 may include a conductive metal such as Cu, the pillar region 14 of the interface layers 10 and 30 may include an alloy of conductive metals (such as a Cu-Ni alloy), and the cross region 16 of the interface layers 10 and 30 may include glass.

[0090] The external electrodes 131 and 132, including interface layers 10 and 30 and outer layers 20 and 40, can be formed by coating a MOD ink comprising a metal ligand material onto the surface of the capacitor body 110 and reducing the MOD ink to form a metal particle film, coating a paste comprising a conductive metal and glass composition onto the metal particle film, and then firing the metal particle film and the paste. As another example, the steps of forming the external electrodes 131 and 132 may include: coating a metal ligand material onto the surface of the capacitor body 110; reducing the coated metal ligand material to form a film comprising metal particles; coating a paste comprising a conductive metal and glass composition onto the film; and firing the film and the coated paste to form interface layers 10 and 30 and outer layers 20 and 40.

[0091] Here, during firing, because small-sized metal particles such as Cu constitute a metal particle film at the interface between the inner electrode layer and the outer electrode, an alloy can first be formed between the metal particles such as Cu and the metal such as Ni in the inner electrode layer, and then the glass composition of the paste can permeate. Therefore, because an alloy such as Cu-Ni is formed at the interface between the inner electrode layer and the outer electrode, the inner electrode layer and the outer electrode are firmly connected to each other, and the glass component of the glass composition can permeate to the surface of the dielectric layer during firing, thereby forming an interface layer with a bridge structure. The outer electrode, including the interface layer with the bridge structure, not only improves the connection with the inner electrode layer, but also has an airtight sealing structure due to the glass on the surface of the dielectric layer. This airtight sealing structure is a completely sealed and closed structure that completely blocks external moisture.

[0092] Each region is shown in more detail below.

[0093] The main body region 12 of the interface layers 10 and 30 may include a conductive metal, such as copper (Cu). Alternatively, the main body region 12 may also include a Cu-Ni alloy.

[0094] The conductive metal included in the main body region 12 may be derived from the metal ligand material of the MOD ink, may be formed by the MOD ink, and may be fine metal particles of about 100 nm or smaller.

[0095] The body region 12 may include a conductive metal as a main component. Specifically, based on the total amount of the body region 12, the body region 12 may include copper (Cu) in an amount of about 60 vol% to about 100 vol% (e.g., about 65 vol% to about 95 vol% or about 70 vol% to about 90 vol%). Including a conductive metal within the above-mentioned content range in the body region 12 can improve the connectivity between the outer electrode and the inner electrode layer. The content of the conductive metal in the body region 12 can be determined by scanning electron microscopy-energy dispersive spectroscopy (SEM-EDS). Other methods and / or tools understood by those skilled in the art may be used even if not described in this disclosure.

[0096] The main area 12 may also include glass.

[0097] The column regions 14 of the interface layers 10 and 30 that connect to the inner electrode layers 121 and 122 (specifically, extending into the interior of the inner electrode layers 121 and 122 to connect with the inner electrode layers 121 and 122) may comprise an alloy of conductive metal.

[0098] The conductive metal alloy can be an alloy formed from two or more metals selected from the following conductive metals: copper (Cu), nickel (Ni), silver (Ag), palladium (Pd), gold (Au), platinum (Pt), tin (Sn), tungsten (W), titanium (Ti), and lead (Pb), for example, it can be a Cu-Ni alloy.

[0099] The alloy of conductive metals included in the column region 14 (such as a Cu-Ni alloy) can be formed as an alloy of a metal such as Cu, which is a metal ligand material derived from MOD ink, and a metal such as Ni, which is the main component of the inner electrode layer. If an alloy is formed in the column region 14, the inner electrode layer and the outer electrode can be firmly connected.

[0100] The column region 14 may include an alloy of conductive metal as a main component. Specifically, based on the total amount of the column region 14, the column region 14 may include an alloy of conductive metal in an amount of about 60 vol% to about 100 vol% (e.g., about 65 vol% to about 95 vol%, or about 70 vol% to about 90 vol%). Including an alloy of conductive metal within the above-described content range in the column region 14 can significantly improve the connectivity between the inner electrode layer and the outer electrode. The content of the alloy in the column region 14 can be determined by scanning electron microscopy-energy dispersive spectroscopy (SEM-EDS) and / or calculated from the amount of metal constituting the alloy determined by scanning electron microscopy-energy dispersive spectroscopy (SEM-EDS). Other methods and / or tools understood by those skilled in the art may be used even if not described in this disclosure.

[0101] The column section 14 may also include glass.

[0102] The spanning area 16 of interface layers 10 and 30 may include glass.

[0103] In interface layers 10 and 30, if glass is included in the crossing region 16 disposed between the plurality of column regions 14 and on the surface of dielectric layer 111, the external electrodes 131 and 132 according to the embodiment may have an airtight sealing structure, i.e., a completely closed and sealed structure that prevents external moisture from entering.

[0104] The glass included in spanning zone 16 may be derived from a glass composition of paste coated on a formed metal particle film.

[0105] The glass may include corrosion-resistant glass. Specifically, the glass may include at least one selected from alumina (Al2O3) and silicon dioxide (SiO2). For example, the glass may include alumina (Al2O3) and silicon dioxide (SiO2). If the spanning region 16 of the interface layers 10 and 30 includes glass, the moisture resistance reliability can be greatly improved.

[0106] Cross-region 16 may include glass as a main component. Specifically, based on the total amount of cross-region 16, cross-region 16 may include an amount of glass ranging from about 60 vol% to about 100 vol% (e.g., about 65 vol% to about 95 vol% or about 70 vol% to about 90 vol%). Including glass within the above-mentioned content range in cross-region 16 can significantly improve moisture resistance reliability. The glass content in cross-region 16 can be calculated by measuring the amount of elements constituting the glass (e.g., Si, Al, Li, Na, Zn, Ba, and / or Ca) using scanning electron microscopy-energy dispersive spectroscopy (SEM-EDS). Other methods and / or tools understood by those skilled in the art may be used even if not described in this disclosure.

[0107] The cross region 16 may also include at least one selected from conductive metals and alloys of conductive metals.

[0108] For example, the main body region 12 of the interface layers 10 and 30 may include copper (Cu), the column region 14 of the interface layers 10 and 30 may include a Cu-Ni alloy, and the cross region 16 of the interface layers 10 and 30 may include glass, for example, a glass comprising alumina (Al2O3) and silicon dioxide (SiO2).

[0109] In the interface layers 10 and 30, which have a bridge structure and are disposed at the interface between the effective region A of the capacitor body 110 and the outer electrodes 131 and 132, the outer electrodes and inner electrode layers not only maintain a strong connection, but also have a completely closed and sealed structure that completely prevents external moisture from entering, thus ensuring a multilayer ceramic capacitor with excellent capacitance characteristics and moisture-proof reliability. This is because the column region 14 connected to the inner electrode layers 121 and 122 includes a Cu-Ni alloy, the crossing region 16 disposed on the surface of the dielectric layer 111 includes glass, and the body region 12 in contact with the outer layers 20 and 40 includes Cu.

[0110] The outer layers 20 and 40 covering the interface layers 10 and 30 may include conductive metal and glass. The types of conductive metal and glass are the same as described above and will not be repeated.

[0111] The structure, composition, and content of the external electrodes 131 and 132 according to the embodiments were measured by scanning electron microscopy (SEM) (specifically, scanning electron microscopy-energy dispersive spectroscopy (SEM-EDS) analysis).

[0112] Specifically, a multilayer ceramic capacitor 100 is mounted on an adhesive tape with its L-axis and T-axis surfaces (LT surfaces) facing upwards, then immersed in an epoxy resin mixture and allowed to cure. Next, the LT surface of the capacitor body 110 is ground to a point halfway down the W-axis (e.g., the center of the capacitor body 110 in the W-axis direction), thus obtaining a cross-sectional sample with the LT surface, allowing observation of the external electrode. Subsequently, a scanning electron microscope (SEM) image of the cross-sectional sample is taken, making the capacitor body and external electrode visible on one side of the sample, to examine the interface layer of the external electrode and, additionally, to check whether the interface layer has a bridge structure including a body region, a column region, and a crossing region. For example, SEM measurements can be performed at an accelerating voltage of approximately 20 kV and a magnification of approximately 10 kV.

[0113] Additionally, in the SEM images of the obtained cross-sectional samples, the ratio of the total number of inner electrode layers in the effective region to the number of inner electrode layers connected to the columnar region of the interface layer can be examined. Other methods and / or tools understood by those skilled in the art may be used, even if not described in this disclosure.

[0114] In addition, energy dispersive spectroscopy (EDS) analysis was performed on the SEM images of the obtained cross-sectional samples to examine the composition and content of the interface layer with the bridge structure.

[0115] The outer layers 20 and 40 may comprise about 60 wt% to about 80 wt% of conductive metal and about 20 wt% to about 40 wt% of glass, for example, about 65 wt% to about 75 wt% of conductive metal and about 25 wt% to about 35 wt% of glass. If the outer layers have the above composition, a multilayer ceramic capacitor with excellent capacitance characteristics and moisture resistance reliability can be obtained.

[0116] The external electrodes 131 and 132 may also include a conductive resin layer disposed on the outer layers 20 and 40 to cover the outer layers 20 and 40, and a plating layer configured to cover the conductive resin layer.

[0117] The conductive resin layer can extend to the first and second surfaces and / or the fifth and sixth surfaces of the capacitor body 110. The outer layers 20 and 40 can also extend to the first and second surfaces and / or the fifth and sixth surfaces of the capacitor body 110. The length of the region (i.e., the strip portion) where the conductive resin layer extends and is disposed on the first and second surfaces and / or the fifth and sixth surfaces of the capacitor body 110 can be longer than the length of the region (i.e., the strip portion) where the outer layers 20 and 40 extend and are disposed on the first and second surfaces and / or the fifth and sixth surfaces of the capacitor body 110. In other words, the conductive resin layer can be formed on the outer layers 20 and 40 and can be shaped to completely cover the outer layers 20 and 40.

[0118] The conductive resin layer may include resin and conductive metal.

[0119] The resin included in the conductive resin layer can be, but is not limited to, a material that has adhesive and damping properties and can form a paste when mixed with conductive metal powder. For example, the resin may include phenolic resin, acrylic resin, silicone resin, epoxy resin, or polyimide resin.

[0120] The conductive metal included in the conductive resin layer is used to electrically connect to the inner electrode layers 121 and 122 through the interface layers 10 and 30 and the outer layers 20 and 40.

[0121] The conductive metal included in the conductive resin layer may have a spherical shape, a sheet shape, or a combination thereof. That is, the conductive metal may be formed only in a sheet shape, only in a spherical shape, or in a mixed shape of sheet and spherical shapes.

[0122] Here, spherical shape can also include shapes that are not perfect spheres. For example, a spherical shape can be one where the ratio of the major axis to the minor axis (major axis / minor axis) is less than or equal to about 1.45. A sheet shape refers to a flat and elongated shape, and there are no particular limitations. For example, a sheet shape can be one where the ratio of the major axis to the minor axis (major axis / minor axis) is greater than or equal to about 1.95.

[0123] The external electrodes 131 and 132 may also include a plating layer disposed on the outer surface of the conductive resin layer.

[0124] The coating may include individual nickel (Ni), copper (Cu), tin (Sn), palladium (Pd), platinum (Pt), gold (Au), silver (Ag), tungsten (W), titanium (Ti), or lead (Pb), or alloys thereof. For example, the coating may be a nickel (Ni) coating or a tin (Sn) coating, which may be in the form of a sequential stack of nickel (Ni) and tin (Sn) coatings, or in the form of a sequential stack of tin (Sn), nickel (Ni), and tin (Sn) coatings. Alternatively, the coating may include multiple nickel (Ni) coatings and / or multiple tin (Sn) coatings.

[0125] The coating can improve the mountability, structural reliability, external durability, heat resistance and equivalent series resistance (ESR) of the multilayer ceramic capacitor 100 on the substrate.

[0126] Dielectric layer and inner electrode layer According to an embodiment, the dielectric layer 111 may include a barium titanate-based compound (including barium (Ba) and titanium (Ti)) as a main component. The barium titanate-based compound is a dielectric matrix material with a high dielectric constant and contributes to the dielectric constant of the multilayer ceramic capacitor 100. For example, the barium titanate-based compound may include compounds selected from BaTiO3, Ba(TiO3) and other similar compounds. , At least one of Zr)O3, Ba(Ti, Sn)O3, (Ba, Ca)TiO3, (Ba, Ca)(Ti, Zr)O3, (Ba, Ca)(Ti, Sn)O3, (Ba, Sr)TiO3, (Ba, Sr)(Ti, Zr)O3 and (Ba, Sr)(Ti, Sn)O3.

[0127] The dielectric layer 111 may also include secondary components. These secondary components may include one or more selected from, for example, manganese (Mn), chromium (Cr), silicon (Si), aluminum (Al), magnesium (Mg), tin (Sn), antimony (Sb), germanium (Ge), gallium (Ga), indium (In), barium (Ba), lanthanum (La), yttrium (Y), actinium (Ac), praseodymium (Pr), neodymium (Nd), promethium (Pm), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), holmium (Ho), erbium (Er), thulium (Tm), ytterbium (Yb), lutetium (Lu), hafnium (Hf), and vanadium (V).

[0128] The average thickness (average length in the T-axis direction) of the dielectric layer 111 can be from about 0.1 μm to about 8.0 μm, for example, from about 0.1 μm to about 6.0 μm. When the average thickness of the dielectric layer 111 is within the above range, the reliability of the multilayer ceramic capacitor can be improved.

[0129] The average thickness of dielectric layer 111 can be measured by immersing the multilayer ceramic capacitor 100 in an epoxy resin mixture, curing it, polishing it, ion milling it, and then analyzing it using a scanning electron microscope (SEM). The SEM can be, for example, a Verios G4 from Thermofisher Scientific, with measurement conditions of 10 kV and 0.2 nA, an analytical magnification of 100x, and the ability to measure at least one, three, five, or ten or more dielectric layers. In the SEM image of the measured cross-sectional sample, the center point of dielectric layer 111 in the length direction (L-axis direction) or width direction (W-axis direction) is used as a reference point, and the arithmetic mean of the thickness of dielectric layer 111 at 10 points separated from this reference point at predetermined intervals can be obtained. The spacing between any two adjacent points among the 10 points can be adjusted according to the scale of the SEM image, and can be, for example, approximately 1 μm to approximately 100 μm, approximately 1 μm to approximately 50 μm, or approximately 1 μm to approximately 10 μm. In this case, all 10 points should be located within the dielectric layer 111. If not all 10 points are located within the dielectric layer 111, the position of the reference point can be changed, or the spacing between any two adjacent points among the 10 points can be adjusted.

[0130] The inner electrode layers 121 and 122 (i.e., the first inner electrode layer 121 and the second inner electrode layer 122) are electrodes with different polarities and are alternately arranged to face each other along the T-axis direction, with a dielectric layer 111 between them, and one end of the first inner electrode layer 121 and one end of the second inner electrode layer 122 can be exposed through the third surface and the fourth surface of the capacitor body 110, respectively.

[0131] The first inner electrode layer 121 and the second inner electrode layer 122 are electrically insulated from each other by a dielectric layer 111 disposed therebetween.

[0132] The ends of the first inner electrode layer 121 and the second inner electrode layer 122, which are alternately exposed through the third and fourth surfaces of the capacitor body 110, can be electrically connected to the first outer electrode 131 and the second outer electrode 132, respectively.

[0133] The inner electrode layers 121 and 122 comprise conductive metals and may include at least one selected from, for example, Ni, Cu, Ag, Pd, Au and alloys thereof.

[0134] The inner electrode layers 121 and 122 can be connected to the interface layers 10 and 30 of the outer electrodes 131 and 132, and specifically, can be connected to the column region 14 of the interface layers 10 and 30 having a bridge structure.

[0135] Specifically, the inner electrode layers 121 and 122 may include an alloy such as Cu-Ni at the interface with the interface layers 10 and 30 of the outer electrodes 131 and 132.

[0136] In addition, the inner electrode layers 121 and 122 may also include dielectric particles having the same composition as the ceramic material included in the dielectric layer 111.

[0137] The inner electrode layers 121 and 122 can be formed using a conductive paste comprising a conductive metal. The printing method for the conductive paste can be either screen printing or gravure printing.

[0138] The average thickness of the inner electrode layers 121 and 122 can be from about 0.1 μm to about 2 μm. When the average thickness of the inner electrode layers 121 and 122 is within the above range, the reliability of the multilayer ceramic capacitor is improved.

[0139] The average thickness of the inner electrode layers 121 and 122 can be measured by scanning electron microscopy (SEM) analysis. Specifically, in the SEM image of the cross-sectional sample measured as described above, the central point of the inner electrode layers 121 and 122 in the length direction (L-axis direction) or width direction (W-axis direction) is used as a reference point, and the arithmetic mean of the thickness of the inner electrode layers 121 and 122 at 10 points separated from the reference point at predetermined intervals can be obtained. The interval between two adjacent points among the 10 points can be adjusted according to the scale of the SEM image, and can be, for example, about 1 μm to about 100 μm, about 1 μm to about 50 μm, or about 1 μm to about 10 μm. At this time, all 10 points should be located within the inner electrode layers 121 and 122, and if not all 10 points are located within the inner electrode layers 121 and 122, the position of the reference point can be changed, or the interval between two adjacent points among the 10 points can be adjusted.

[0140] The capacitor body 110 can be formed by firing a stacked structure in which multiple dielectric layers 111 and internal electrode layers 121 and 122 are stacked.

[0141] In the following, a method for manufacturing a multilayer ceramic capacitor 100 according to an embodiment will be described.

[0142] Methods for manufacturing multilayer ceramic capacitors The multilayer ceramic capacitor 100 according to the embodiment can be manufactured by: coating a metal-organic decomposition (MOD) ink onto the surface of a capacitor body 110 and reducing the metal-organic decomposition (MOD) ink to form a metal particle film; coating a paste comprising a composition of conductive metal and glass onto the surface of the capacitor body on which the metal particle film is formed; and firing the paste to form external electrodes 131 and 132, the external electrodes 131 and 132 comprising interface layers 10 and 30 formed of the metal particle film and outer layers 20 and 40 formed of the paste and covering the interface layers.

[0143] The method of manufacturing the capacitor body 110 will be described below.

[0144] The capacitor body 110 can be manufactured by: using dielectric paste to manufacture dielectric green sheets and forming a conductive paste layer on the surface of the dielectric green sheets; manufacturing a dielectric green sheet stack by stacking dielectric green sheets on which the conductive paste layer is formed; and firing the dielectric green sheet stack.

[0145] Dielectric pastes can be prepared by mixing barium titanate-based main component powders and optional secondary component powders.

[0146] Since the barium titanate-based main component powder is the same as the barium titanate-based main component included in the dielectric layer, the description of the barium titanate-based main component powder is omitted here.

[0147] The secondary component powder may include, but is not limited to, manganese (Mn), chromium (Cr), silicon (Si), aluminum (Al), magnesium (Mg), tin (Sn), antimony (Sb), germanium (Ge), gallium (Ga), indium (In), barium (Ba), lanthanum (La), yttrium (Y), actinium (Ac), cerium (Ce), praseodymium (Pr), neodymium (Nd), promethium (Pm), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), holmium (Ho), erbium (Er), thulium (Tm), ytterbium (Yb), lutetium (Lu), hafnium (Hf), vanadium (V), or combinations thereof. Based on 100 moles of barium titanate-based primary component powder, each of the secondary component powders may be included in amounts from about 0.01 moles to about 5 moles.

[0148] The by-product powder can be used in the form of an oxide or salt compound comprising each metal, or in the form of a sol dispersed in an organic solvent.

[0149] In addition, dielectric pastes can be prepared by further mixing with additives such as dispersants, binders, plasticizers, lubricants, antistatic agents, and solvents.

[0150] The barium titanate-based main component powder and optional secondary component powder can be mixed using a wet ball mill or a stirred mill. When using zirconia balls in a wet ball mill, multiple zirconia balls with a diameter of about 0.1 mm to about 10 mm can be used for wet mixing for about 8 hours to about 48 hours or about 10 hours to about 24 hours.

[0151] The prepared dielectric paste forms a dielectric layer after firing.

[0152] As a method for forming the prepared dielectric paste into a sheet, a strip forming method such as a doctor blade method or a calendering roll method can be used. For example, a coating head discharge type roller forming coating machine can be used to form the prepared dielectric paste into a sheet, and then the dielectric sheet can be obtained by drying the formed body.

[0153] To form a conductive paste layer that becomes the inner electrode layer after firing, the conductive paste can be prepared by mixing conductive powder made of conductive metals or alloys thereof, a binder, and a solvent. Additionally, barium titanate powder can be mixed in as a co-material if desired. The co-material can be used to suppress the sintering of the conductive powder during the firing process. In the step of manufacturing the dielectric green sheet, a dielectric paste can be prepared by mixing a barium titanate-based compound as the main component powder and optional secondary component powders.

[0154] The conductive powder may include nickel (Ni) or nickel (Ni) alloys.

[0155] Next, the dielectric green sheet stack is manufactured by stacking multiple layers of dielectric green sheets on which internal electrode patterns (i.e., conductive paste layers) are formed, and then pressing the multiple layers of dielectric green sheets in the stacking direction. At this time, dielectric green sheets without internal electrode patterns can be stacked on top of the stack, such that the dielectric green sheets without internal electrode patterns are located at the upper and lower parts of the dielectric green sheet stack in the stacking direction.

[0156] The following processes can be optionally performed: cutting the manufactured dielectric green sheet stack into predetermined sizes by cutting or the like.

[0157] Additionally, if necessary, the dielectric green sheet stack can be cured and dried to remove plasticizers, etc., and after curing and drying, the dielectric green sheet stack can be tumble polished using a horizontal centrifugal tumbler or similar device. In tumble polishing, the dielectric green sheet stack is placed in a tumbler container containing a dielectric and polishing fluid, and rotational motion or vibration is applied to the tumbler container to polish unwanted parts (such as burrs generated during cutting). After tumble polishing, the dielectric green sheet stack can be washed with a cleaning solution such as water and then dried.

[0158] Subsequently, the adhesive is removed from the dielectric sheet stack and then fired to obtain the capacitor body.

[0159] The conditions for adhesive removal can be appropriately adjusted according to the composition of the dielectric layer or inner electrode layer. For example, the heating rate during adhesive removal can be from about 5°C / hour to about 300°C / hour, the holding temperature can be from about 180°C to about 400°C, and the temperature holding time can be from about 0.5 hours to about 24 hours. Adhesive removal can be performed in an air atmosphere or a reducing atmosphere.

[0160] The firing conditions can be appropriately adjusted according to the main composition of the dielectric layer or the main composition of the inner electrode layer. For example, firing can be performed at a temperature of about 1100°C to about 1400°C (e.g., at a temperature of about 1200°C to about 1350°C). Furthermore, firing can be performed for about 0.5 hours to about 8 hours (e.g., about 1 hour to about 3 hours). Additionally, firing can be performed in a reducing atmosphere (e.g., in an atmosphere humidified with a mixture of nitrogen and hydrogen). When the inner electrode layer comprises nickel (Ni) or a nickel (Ni) alloy, the oxygen partial pressure in the firing atmosphere can be about 1.0 × 10⁻⁶. -14 MPa to approximately 1.0 × 10 -10 MPa.

[0161] After firing, annealing can be performed as needed. Annealing is a process that re-oxidizes the dielectric layer. If firing is performed in a reducing atmosphere, annealing can be performed. The annealing conditions can also be adjusted appropriately according to the composition of the dielectric layer. For example, the annealing temperature can be from about 950°C to about 1150°C, the annealing time can be from about 0 hours to about 20 hours, and the heating rate can be from about 50°C / hour to about 500°C / hour. The annealing atmosphere can be a moistened nitrogen (N2) atmosphere, and the oxygen partial pressure can be about 1.0 × 10⁻⁶. -9 MPa to approximately 1.0 × 10 -5 MPa.

[0162] In the binder removal process, firing process, and / or annealing process, a wetting agent may be used to wet the nitrogen or mixed gas, for example. In this case, the wetting agent temperature can be from about 5°C to about 75°C. The binder removal process, firing process, and annealing process can be performed sequentially or independently.

[0163] Optionally, surface treatments such as sandblasting, laser irradiation, and tumble polishing can be performed on the third and fourth surfaces of the prepared capacitor body 110. By performing this surface treatment, the ends of the first inner electrode and the second inner electrode can be exposed to the third and fourth surfaces, respectively, thereby improving the electrical connection between the first inner electrode layer and the first outer electrode, as well as the electrical connection between the second inner electrode layer and the second outer electrode, and making it easier to form an alloy portion.

[0164] Next, we will refer to Figure 6 A method for manufacturing external electrodes 131 and 132 is described.

[0165] Figure 6 This is a schematic diagram illustrating a method for manufacturing the external electrode of a multilayer ceramic capacitor according to an embodiment.

[0166] Reference Figure 6 The surface of the capacitor body 110 manufactured above is coated with metal-organic decomposition (MOD) ink and the metal-organic decomposition (MOD) ink is reduced to form a metal particle film.

[0167] Metal-organic decomposition (MOD) ink is applied to at least the third and fourth surfaces of the capacitor body 110, and optionally, metal-organic decomposition (MOD) ink is also applied to portions of the first, second, fifth, and / or sixth surfaces on which the first and second external electrodes are formed.

[0168] Organometallic decomposition (MOD) inks may include metal ligand materials, amine compounds, binders, antioxidants, and solvents.

[0169] Metal ligand materials may include conductive metal formate formed by reacting a conductive metal precursor with formic acid.

[0170] The conductive metal precursor may be a precursor comprising a conductive metal, including at least one metal selected from copper (Cu), nickel (Ni), silver (Ag), palladium (Pd), gold (Au), platinum (Pt), tin (Sn), tungsten (W), titanium (Ti), and lead (Pb); alloys thereof; or combinations thereof. Examples of such conductive metal precursors may include metal oxides, metal hydroxides, metal nitrates, metal carbonates, metal sulfates, metal chlorides, metal acetates, or combinations thereof.

[0171] Based on the total amount of the metal-organic decomposition (MOD) ink, the metal-organic decomposition (MOD) ink may include approximately 20 wt% to approximately 40 wt% of a metal ligand material.

[0172] Examples of amine compounds may include butylamine, hexylamine, octylamine, dibutylamine, triethylamine, diethylenetriamine, ethylenediamine, cyclohexylamine, aminomethylpropanol, 2-amino-2-methyl-1-propanol (AMP), or combinations thereof.

[0173] Based on the total amount of the organometallic decomposition (MOD) ink, the organometallic decomposition (MOD) ink may include an amount of amine compounds ranging from about 20 wt% to about 60 wt%.

[0174] Adhesives may include thermoplastic resins, thermosetting resins, natural polymers, or combinations thereof. Examples of thermoplastic resins include acrylic resins, cellulose resins, aliphatic or copolyester resins, vinyl resins, polyamide resins, polyurethane resins, polyether resins, urea resins, alkyd resins, silicone resins, fluoropolymers, olefin resins, etc. Acrylic resins may be, for example, polyacrylic acid, polyacrylates, etc. Examples of thermosetting resins include epoxy resins, unsaturated resins or vinyl polyester resins, diallyl phthalate resins, phenolic resins, oxetane resins, oxazine resins, bismaleimide resins, modified silicone resins, melamine resins, etc. Examples of natural polymers include ethylene propylene rubber (EPR), styrene-butadiene rubber (SBR), starch, gelatin, etc.

[0175] Based on the total amount of the metal-organic degradable (MOD) ink, the metal-organic degradable (MOD) ink may include a binder in an amount of about 0.1 wt% to about 5 wt%.

[0176] Antioxidants can include organic acids such as oleic acid.

[0177] Based on the total amount of the organometallic degradable (MOD) ink, the organometallic degradable (MOD) ink may include an amount of antioxidant from about 0.1 wt% to about 5 wt%.

[0178] Solvents may include: water; alcohol solvents, such as methanol, ethanol, isopropanol, 1-methoxypropanol, butanol, ethylhexanol, and terpineol; glycol solvents, such as ethylene glycol and glycerol; acetate solvents, such as ethyl acetate, butyl acetate, methoxypropyl acetate, carbitol acetate, and ethyl carbitol acetate; ether solvents, such as methyl cellosolve, butyl cellosolve, diethyl ether, tetrahydrofuran, and dioxane; ketone solvents, such as methyl ethyl ketone, acetone, dimethylformamide, and 1-methyl-2-pyrrolidone; hydrocarbon solvents, such as hexane, heptane, dodecane, paraffin oil, and mineral oil; aromatic solvents, such as benzene, toluene, and xylene; halogen-substituted solvents, such as chloroform, dichloromethane, and carbon tetrachloride; or combinations thereof.

[0179] Based on the total amount of organometallic decomposition (MOD) ink, organometallic decomposition (MOD) ink may include a balance amount of solvent.

[0180] Metal-organic decomposition (MOD) inks can be coated with a thickness of about 50 μm to about 400 μm (e.g., about 80 μm to about 350 μm). When metal-organic decomposition (MOD) inks are coated within the above thickness range, the interface layer formed after firing can be formed with an appropriate thickness, thereby enhancing the contact between the inner electrode layer and the outer electrode.

[0181] Reduction can be performed in a nitrogen atmosphere at a temperature of about 170°C to about 300°C (e.g., at a temperature of about 180°C to about 250°C) for about 30 minutes to about 3 hours (e.g., about 40 minutes to about 2 hours). When reduction is performed under conditions within the above range, the contact between the inner electrode layer and the outer electrode is enhanced due to the formation of the interface layer.

[0182] When the metal-organic decomposition (MOD) ink is coated onto the surface of the capacitor body 110 and reduced, a metal particle film comprising very small and uniform metal nanoparticles can be formed. For example, the metal particle film may comprise metal nanoparticles with a size of about 10 nm to about 100 nm, such as metal nanoparticles with a size of about 15 nm to about 90 nm. The size of the metal nanoparticles can be determined by scanning electron microscopy (SEM). Other methods and / or tools understood by those skilled in the art may be used, even if not described in this disclosure.

[0183] Subsequently, the paste is applied to the surface of the capacitor body 110 on which a metal particle film is formed, and then it is fired.

[0184] The paste comprises a composition of conductive metals and glass.

[0185] Based on the total amount of the paste, the paste may include about 20 wt% to about 40 wt% (e.g., about 22 wt% to about 38 wt% or about 24 wt% to about 36 wt%) of the glass composition.

[0186] Since the description of the conductive metal and glass composition is the same as that described above, the description of the conductive metal and glass composition is omitted here.

[0187] Pastes may also include adhesives, solvents, dispersants, plasticizers, oxide powders, etc.

[0188] The adhesive can be, for example, ethyl cellulose, acrylic acid, butyral, etc., and the solvent can be, for example, an organic solvent (such as terpineol, butyl carbitol, ethanol, methyl ethyl ketone, acetone, toluene, etc.) or an aqueous solvent.

[0189] Methods for applying paste to the surface of capacitor body 110 may include dipping, various printing methods (such as screen printing), coating methods using a dispenser, and spraying methods using a sprayer. The paste may be applied to at least the third and fourth surfaces of capacitor body 110, and optionally to portions of the first, second, fifth, and / or sixth surfaces on which the first and second external electrodes are formed.

[0190] It can be fired for about 0.5 hours to about 3 hours (e.g., about 1 hour to about 2 hours) at about 600°C to about 800°C (e.g., about 650°C to about 750°C) in a reducing atmosphere with a wetting agent temperature of about 0°C to about 40°C.

[0191] During firing, such as Figure 6 As shown, due to the fine metal nanoparticles constituting the metal particle film, the material at the interface between the outer electrode and the inner electrode layer can first be sintered to form an alloy (such as a Cu-Ni alloy), and then glass can permeate through it. The alloy formed at the interface between the inner and outer electrode layers firmly maintains the connection between them, and the glass can permeate to the surface of the dielectric layer, thereby forming a bridge-structured interface layer for the outer electrode. Therefore, due to the bridge-structured interface layer, the inner and outer electrode layers can be firmly connected, and the glass (specifically, corrosion-resistant glass) can exist on the surface of the dielectric layer, thus forming a completely sealed and airtight structure that completely blocks the ingress of external moisture.

[0192] Optionally, a paste for forming a conductive resin layer is applied to the outer surface of the capacitor body 110 (the portion of the outer surface of the capacitor body 110 in which the outer layers 20 and 40 are formed on the interface layers 10 and 30), and then cured to form a conductive resin layer.

[0193] The paste used to form the conductive resin layer may include conductive metals and resins, and optionally include non-conductive fillers. Since the descriptions of the conductive metals and resins are the same as described above, repeated descriptions will be omitted. Additionally, the paste used to form the conductive resin layer may optionally include binders, solvents, dispersants, plasticizers, oxide powders, etc. Binders may be, for example, ethyl cellulose, acrylic acid, butyral, etc., and solvents may be organic solvents (such as terpineol, butyl carbitol, ethanol, methyl ethyl ketone, acetone, and toluene) or aqueous solvents.

[0194] For example, the conductive resin layer can be formed by immersing the capacitor body 110 in a paste for forming the conductive resin layer and then curing it, or by printing the paste for forming the conductive resin layer onto the surface of the capacitor body 110 by screen printing or gravure printing, or by applying the paste for forming the conductive resin layer onto the surface of the capacitor body 110 and then curing it.

[0195] Next, a plating layer can be formed on the outer surface of the conductive resin layer.

[0196] For example, a coating can be formed by plating methods (such as electroplating) or sputtering.

[0197] The present disclosure is described in more detail below with reference to examples. However, these examples are exemplary, and the scope of the claims is not limited thereto.

[0198] (Manufacturing of multilayer ceramic capacitors) Example 1 Dielectric green sheets are fabricated using BaTiO3 powder. A conductive paste layer including Ni is printed on the surface of the green sheets, and the green sheets with the conductive paste layer formed on them are stacked and pressed to fabricate a dielectric green sheet stack. The capacitor body is fabricated by calcining the dielectric green sheet stack at 400°C or lower in a nitrogen atmosphere, followed by firing at a firing temperature of less than or equal to 1300°C and a hydrogen concentration of less than or equal to 1.0% H2.

[0199] A metal-organic decomposition (MOD) ink comprising 30 wt% copper formate (Cu formate), 25 wt% octylamine, 25 wt% 2-amino-2-methyl-1-propanol (AMP), 0.5 wt% oleic acid, 0.5 wt% acrylic resin (SPB 80), and a balanced amount of dihydroterpineol (DHT) was coated onto the surface of the capacitor body to a thickness of 100 μm and reduced at 200 °C for 1 hour under a nitrogen atmosphere to form a Cu particle film composed of Cu nanoparticles with an average size of less than or equal to 100 nm.

[0200] On the surface of the capacitor body where a Cu particle film is formed, a paste comprising 70 wt% Cu, 20 wt% glass composition, 5 wt% acrylic resin (SPB 80), and a metric amount of dihydroterpineol (DHT) is coated. Then, under a reducing atmosphere with a wetting agent temperature of 35°C, it is fired at 690°C for 90 minutes to form an interface layer and an outer layer. Here, the glass composition comprises 9.1 mol% lithium oxide (Li₂O), 10 mol% sodium oxide (Na₂O), 1.5 mol% iron(III) oxide (Fe₂O₃), 6.3 mol% zinc oxide (ZnO), 21 mol% barium oxide (BaO), 11 mol% silicon dioxide (SiO₂), 8 mol% calcium oxide (CaO), 12 mol% aluminum oxide (Al₂O₃), 20.2 mol% boron trioxide (B₂O₃), and 1 mol% tin(IV) oxide (SnO₂).

[0201] Next, a coating is formed through processes such as plating, thereby obtaining a multilayer ceramic capacitor.

[0202] Comparative Example 1 On the surface of the capacitor body prepared in Example 1, a paste comprising 70 wt% Cu, 20 wt% glass composition, 5 wt% acrylic resin (SPB 80), and a metric amount of dihydroterpineol (DHT) was coated, and then fired at 690°C for 90 minutes in a reducing atmosphere with a wetting agent temperature of 35°C.

[0203] Next, a coating is formed through processes such as plating, thereby obtaining a multilayer ceramic capacitor.

[0204] Evaluation 1: SEM Analysis The multilayer ceramic capacitors manufactured in Example 1 and Comparative Example 1 were analyzed by scanning electron microscopy (SEM) using the following methods, and the results are shown in [Figure / Table / Text]. Figure 7 and Figure 8 middle.

[0205] Each multilayer ceramic capacitor was mounted on tape with its L-axis and T-axis surfaces (LT surfaces) facing upwards, then immersed in an epoxy resin mixture and allowed to cure. Next, the LT surface of the capacitor body was ground to half its length in the W-axis direction (e.g., the center of the capacitor body 110 in the W-axis direction), thus obtaining a cross-sectional sample with the LT surface, allowing observation of the external electrodes. Subsequently, one side of the obtained cross-sectional sample was measured by SEM to observe the capacitor body and external electrodes. SEM measurements were performed at an accelerating voltage of 20 kV and a magnification of 10 k.

[0206] Figure 7 The images are based on scanning electron microscopy (SEM) analysis of the external electrodes of the multilayer ceramic capacitor in Example 1. Figure 8 The images are based on scanning electron microscopy (SEM) analysis of the external electrodes of the multilayer ceramic capacitor of Comparative Example 1.

[0207] Reference Figure 7 In Example 1, the external electrode has an interface layer on the surface of the effective region of the capacitor body. This interface layer has a bridge structure comprising a main body region, multiple column regions connected to the lower part of the main body region, and a crossing region disposed between the multiple column regions. Furthermore, the column regions in the interface layer are connected to the inner electrode layers, and the crossing regions are disposed on the surface of the dielectric layer. Additionally, when the bonding region between the external electrode and the capacitor body is divided into three parts (such as an upper, central, and lower part) in the stacking direction (i.e., the thickness direction (T-axis direction) of the multilayer ceramic capacitor), the external electrodes in the upper, central, and lower parts all have an interface layer with a bridge structure. Furthermore, based on the total number of inner electrode layers in the effective region, the ratio of the number of inner electrode layers connected to the column regions of the interface layer is 90% or greater.

[0208] On the other hand, refer to Figure 8In Comparative Example 1, no bridge structure was formed in the external electrode; instead, glass was dispersed at the interface between the external electrode and the capacitor body.

[0209] Therefore, since the outer electrode manufactured by the MOD method according to the embodiment includes an interface layer with a bridge structure at the interface with the effective area of ​​the capacitor body, excellent moisture-proof reliability is ensured by completely blocking the inflow of external moisture, and excellent connectivity between the outer electrode and the inner electrode layer is ensured.

[0210] Evaluation 2: SEM-EDS Analysis Scanning electron microscopy-energy dispersive spectroscopy (SEM-EDS) analysis was performed on the multilayer ceramic capacitors according to Example 1 and Comparative Example 1, and the results are shown in... Figure 9 and Figure 10 middle.

[0211] Energy dispersive spectroscopy (EDS) analysis was performed on the SEM images of the cross-sectional samples obtained in Evaluation 1 for Cu mapping analysis.

[0212] Figure 9 The images are based on scanning electron microscopy-energy dispersive spectroscopy (SEM-EDS) mapping analysis images of the external electrodes of the multilayer ceramic capacitor in Example 1. Figure 10 The images are based on scanning electron microscopy-energy dispersive spectroscopy (SEM-EDS) mapping analysis images of the external electrodes of the multilayer ceramic capacitor in Comparative Example 1.

[0213] Reference Figure 9 In Example 1, the interface layer has a bridge structure, and Cu is mainly distributed in the main body region and pillar region of the interface layer. Furthermore, since copper is observed to diffuse even into the inner electrode layer and the pillar region of the interface layer, it is confirmed that Cu forms a Cu-Ni alloy with Ni in the inner electrode layer, and this Cu-Ni alloy exists in both the pillar region of the interface layer and the inner electrode layer.

[0214] On the other hand, refer to Figure 10 In Comparative Example 1, no bridge structure and Cu were present at the interface between the outer electrode and the inner electrode layer, which deteriorated the connectivity between the outer electrode and the inner electrode layer.

[0215] Therefore, the outer electrode manufactured by the MOD method according to the embodiment exhibits excellent moisture resistance due to the glass on the surface of the dielectric layer completely blocking the inflow of external moisture, and exhibits excellent connectivity with the inner electrode layer due to the formation of an alloy at the interface with the inner electrode layer.

[0216] Evaluation 3: Capacitor Characteristics The capacitance and dielectric loss (DF) of the multilayer ceramic capacitors according to Example 1 and Comparative Example 1 were measured at 1000 Hz and 0.5 V, and the results are shown in... Figure 11 middle.

[0217] Figure 11 This is a diagram showing the capacitance characteristics of the multilayer ceramic capacitor according to Example 1 and Comparative Example 1.

[0218] Reference Figure 11 Compared with the multilayer ceramic capacitor of Comparative Example 1, in the multilayer ceramic capacitor of Example 1, where the interface layer with a bridge structure is formed at the interface between the effective area of ​​the capacitor body and the external electrode, the capacitance dispersion caused by the deterioration of the contact characteristics of the external electrode and the inner electrode layer is reduced, and the dielectric loss (DF) dispersion is also reduced.

[0219] Evaluation 4: Moisture Resistance Reliability The moisture resistance reliability of the multilayer ceramic capacitors according to Example 1 and Comparative Example 1 was evaluated, and the results are shown in... Figure 12 and Figure 13 middle.

[0220] Specifically, 20 multilayer ceramic capacitors of Example 1 and 20 multilayer ceramic capacitors of Comparative Example 1 were prepared and then mounted on a measurement substrate to evaluate the moisture resistance reliability by using an ESPEC (PR-3J, 8585) device at 85°C and 85% relative humidity (RH) for 24 hours.

[0221] Figure 12 This is a diagram illustrating the moisture resistance reliability of the multilayer ceramic capacitor according to Example 1. Figure 13 This is a diagram showing the moisture resistance reliability of the multilayer ceramic capacitor according to Comparative Example 1.

[0222] Reference Figure 12 and Figure 13 Compared to Comparative Example 1, the multilayer ceramic capacitor of Example 1, in which an interface layer with a bridge structure is formed at the interface between the effective region of the capacitor body and the external electrode, exhibits excellent moisture resistance reliability.

[0223] Although this disclosure has been described in conjunction with embodiments now considered practical, it should be understood that this disclosure is not limited to the disclosed embodiments, but rather is intended to cover various variations and equivalents included within the spirit and scope of the appended claims.

Claims

1. A multilayer ceramic capacitor, comprising: A capacitor body includes multiple dielectric layers and multiple internal electrode layers, wherein the multiple dielectric layers include a first dielectric layer and a second dielectric layer, and the multiple internal electrode layers are stacked such that the first dielectric layer is sandwiched between them; and External electrodes are disposed on the outer surface of the capacitor body. The capacitor body includes an effective region and a cover region. The effective region includes a first dielectric layer and an inner electrode layer, and the cover region includes a second dielectric layer. The second dielectric layer is disposed on a first surface and a second surface of the effective region, wherein the first surface is opposite to the second surface in the stacking direction. The external electrode includes an interface layer and an outer layer. The interface layer is disposed on the third and / or fourth surfaces of the effective region, and the outer layer covers the interface layer. The interface layer has a bridge structure, which includes a main body area, multiple column areas, and a crossing area. The column areas are connected to the main body area, and the crossing area is disposed between the multiple column areas. The columnar region of the interface layer is connected to the inner electrode layer. The crossing region of the interface layer is disposed on the surface of the first dielectric layer, and Based on the total number of inner electrode layers in the effective region, the ratio of the number of inner electrode layers connected to the column region of the interface layer is greater than or equal to 90% and less than or equal to 100%.

2. The multilayer ceramic capacitor according to claim 1, wherein, The columnar region of the interface layer extends into the interior of the capacitor body and connects to the inner electrode layer.

3. The multilayer ceramic capacitor according to claim 1, wherein, The column region of the interface layer comprises an alloy containing a conductive metal.

4. The multilayer ceramic capacitor according to claim 1, wherein, The columnar region of the interface layer comprises a Cu-Ni alloy.

5. The multilayer ceramic capacitor according to claim 3, wherein, The column region of the interface layer comprises 60% to 100% of the alloy based on the total amount of the column region.

6. The multilayer ceramic capacitor according to claim 1, wherein, The spanning area of ​​the interface layer includes glass.

7. The multilayer ceramic capacitor according to claim 6, wherein, The glass comprises at least one selected from Al2O3 and SiO2.

8. The multilayer ceramic capacitor according to claim 6, wherein, The cross-region of the interface layer comprises 60% to 100% of the glass based on the total amount of the cross-region.

9. The multilayer ceramic capacitor according to claim 1, wherein, The main region of the interface layer includes a conductive metal.

10. The multilayer ceramic capacitor according to claim 1, wherein, The main region of the interface layer includes Cu.

11. The multilayer ceramic capacitor according to claim 9, wherein, The main region of the interface layer comprises, based on the total amount of the main region, 60% to 100% of the conductive metal.

12. The multilayer ceramic capacitor according to claim 1, wherein, The columnar region of the interface layer comprises an alloy containing a conductive metal. The spanning region of the interface layer includes glass, and The main area of ​​the interface layer includes the conductive metal.

13. The multilayer ceramic capacitor according to claim 1, wherein, The columnar region of the interface layer comprises a Cu-Ni alloy. The spanning region of the interface layer includes glass, and The main region of the interface layer includes Cu.

14. The multilayer ceramic capacitor according to claim 1, wherein, The inner electrode layer comprises an alloy at its interface with the interface layer, and The alloy includes a conductive metal.

15. A multilayer ceramic capacitor, comprising: A capacitor body includes multiple dielectric layers and multiple internal electrode layers, wherein the multiple dielectric layers include a first dielectric layer and a second dielectric layer, and the multiple internal electrode layers are stacked such that the first dielectric layer is sandwiched between them; and External electrodes are disposed on the outer surface of the capacitor body. The capacitor body includes an effective region and a cover region. The effective region includes a first dielectric layer and an inner electrode layer, and the cover region includes a second dielectric layer. The second dielectric layer is disposed on a first surface and a second surface of the effective region, wherein the first surface is opposite to the second surface in the stacking direction. The external electrode includes an interface layer and an outer layer. The interface layer is disposed on the third and / or fourth surfaces of the effective region, and the outer layer covers the interface layer. The interface layer has a bridge structure, which includes a main body area, multiple column areas, and a crossing area. The column areas are connected to the main body area, and the crossing area is disposed between the multiple column areas. The columnar region of the interface layer is connected to the inner electrode layer. The crossing region of the interface layer is disposed on the surface of the first dielectric layer. The main region of the interface layer includes a conductive metal. The column region of the interface layer includes an alloy containing the conductive metal, and The spanning area of ​​the interface layer includes glass.

16. The multilayer ceramic capacitor according to claim 15, wherein, The conductive metal includes Cu. The alloy includes a Cu-Ni alloy, and The glass comprises Al2O3 and SiO2.

17. A method for manufacturing a multilayer ceramic capacitor, comprising: An external electrode is formed on the surface of a capacitor body, the capacitor body comprising multiple dielectric layers and multiple inner electrode layers, the multiple inner electrode layers being stacked such that the dielectric layers are interposed between them, wherein the external electrode comprises an interface layer and an outer layer covering the interface layer. The step of forming the external electrode includes: coating the surface of the capacitor body with a metal-organic decomposition ink, reducing the coated metal-organic decomposition ink to form a metal particle film; coating the metal particle film with a paste comprising a conductive metal and a glass composition; and firing the metal particle film and the coated paste to form the interface layer and the outer layer. The interface layer has a bridge structure, which includes a main body area, multiple column areas, and a crossing area. The column areas are connected to the main body area, and the crossing area is disposed between the multiple column areas. The column region of the interface layer is connected to the inner electrode layer, and The crossing region of the interface layer is disposed on the surface of the dielectric layer.

18. The method according to claim 17, wherein, The organometallic decomposition ink comprises metal ligand materials, amine compounds, binders, antioxidants, and solvents.

19. The method of claim 17, wherein, The metal particle film comprises metal nanoparticles with a size of 10 nm to 100 nm.

20. The method of claim 17, wherein, Based on the total amount of the paste, the paste comprises 20 wt% to 40 wt% of the glass composition.

21. A method for manufacturing a multilayer ceramic capacitor, comprising: An external electrode is formed on the surface of a capacitor body, the capacitor body comprising multiple dielectric layers and multiple inner electrode layers, the multiple inner electrode layers being stacked such that the dielectric layers are interposed between them, wherein the external electrode comprises an interface layer and an outer layer covering the interface layer. The step of forming the external electrode includes: coating a metal ligand material onto the surface of the capacitor body; reducing the coated metal ligand material to form a film comprising metal particles; coating the film with a paste comprising a conductive metal and a glass composition; and firing the film and the coated paste to form the interface layer and the outer layer. The interface layer includes glass.

22. The method according to claim 21, wherein, The interface layer has a bridge structure, which includes a main body area, multiple column areas, and a crossing area. The column areas are connected to the main body area, and the crossing area is disposed between the multiple column areas. The columnar region of the interface layer extends from the inner electrode layer to the body region, and The crossing region of the interface layer is disposed on the surface of the dielectric layer.

23. The method according to claim 22, wherein, The step of reducing the coated metal ligand material is carried out in a nitrogen atmosphere at a temperature of 170°C to 300°C for 30 minutes to 3 hours.

24. The method according to claim 21, wherein, The metal ligand material includes copper formate.

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