Automatic dead zone control circuit and LLC resonant converter

Abstract

The invention relates to the technical field of circuit control, in particular to an automatic dead zone control circuit and an LLC resonant converter. The circuit comprises a maximum dead zone control circuit, a narrow pulse generation circuit, a level shift high-voltage tube driving and dead zone detection input circuit, a level shift and comparison circuit and a dead zone control logic circuit. Dead zone time of a high-side driving signal and a low-side driving signal is dynamically adjusted based on a clock input signal and a dead zone state detected in real time, so that automatic dead zone control of a switching tube of the LLC resonant converter is realized, a straight-through phenomenon is effectively avoided, efficiency and reliability of the converter are improved, dependence on an external high-voltage capacitor is reduced, and the reliability of the converter is improved. And the system cost and complexity are further reduced.

Description

Technical Field

[0001] This application relates to the field of circuit control technology, and in particular to an automatic dead-time control circuit and an LLC resonant converter. Background Technology

[0002] In today's power supply technology field, LLC resonant converters, with their advantages of high efficiency and energy saving, have been widely used in many high-efficiency power supply applications. As the performance requirements of electronic devices continue to increase, performance optimization of LLC resonant converters has become a key research direction. Their development has not only driven the advancement of power supply technology but also provided strong support for the stable operation of various electronic devices, playing a vital role in multiple fields such as industry, communications, and consumer electronics.

[0003] Regarding dead-time control in LLC resonant converters, the main technologies include the following approaches. The first is to use an internally fixed dead-time method, where the dead-time is preset and remains constant throughout the entire operation. This method is relatively simple to implement and requires no additional adjustment device. The second is to set an adjustable dead-time via an external pin, allowing users to adjust the dead-time according to specific needs, offering a degree of flexibility. The third is to achieve automatic dead-time control using a high-voltage capacitor, leveraging its characteristics to dynamically adjust the dead-time.

[0004] However, these related technologies have certain drawbacks. The fixed internal dead time cannot be flexibly adjusted according to actual operating conditions, making it difficult to adapt to the operating requirements of different power transistors and limiting the performance of the half-bridge LLC resonant converter. While external pin-based adjustable dead time offers some flexibility, it requires additional pins and adjustment operations, increasing system complexity and cost. Furthermore, achieving automatic dead time control via high-voltage capacitors requires additional high-voltage capacitors, increasing not only cost but also potentially leading to larger size issues. Summary of the Invention

[0005] In order to at least partially solve the above-mentioned technical problems in the related art, this application provides an automatic dead-time control circuit and an LLC resonant converter.

[0006] On the one hand, this application provides an automatic dead-time control circuit, which adopts the following technical solution: An automatic dead-time control circuit includes: The maximum dead-time control circuit is used to generate the high-side dead-time control signal H1 and the low-side dead-time control signal L1 based on the clock input signal CLKin. The narrow pulse generation circuit is located after the maximum dead time control circuit and is used to generate rising edge narrow pulse signal Hon1 and falling edge narrow pulse signal Hoff1 based on the high-side drive signal H2. The input circuit for driving and detecting dead zone of the high-voltage tube with level displacement is connected to the narrow pulse generation circuit. It is used to generate a high-side high-voltage tube turn-on signal hon and a dead zone detection signal H3 based on the rising edge narrow pulse signal Hon1, and to generate a high-side high-voltage tube turn-off signal hoff based on the falling edge narrow pulse signal Hoff1. A level shifting and comparison circuit is connected to the level shifting high voltage tube drive and dead zone detection input circuit, and is used to generate a high-side dead zone comparison signal H4 and a low-side dead zone comparison signal H5 based on the dead zone detection signal H3. The dead-time control logic circuit includes a dead-time signal generation module and a logic combination module. The dead-time signal generation module is connected to the level shifting and comparison circuit and is used to generate a high-side dead-time signal DTH based on the high-side dead-time comparison signal H4, and to generate a low-side dead-time signal DTL based on the low-side dead-time comparison signal H5. The logic combination module is disposed between the maximum dead-time control circuit and the narrow pulse generation circuit and is connected to the dead-time signal generation module. It is used to generate a high-side drive signal H2 based on the high-side dead-time control signal H1 and the high-side dead-time signal DTH, and to generate a low-side drive signal L2 based on the low-side dead-time control signal L1 and the low-side dead-time signal DTL.

[0007] By integrating the above technical solution, including a maximum dead-time control circuit, a narrow pulse generation circuit, a level-shifting high-voltage transistor drive and dead-time detection input circuit, a level-shifting and comparison circuit, and a dead-time control logic circuit, the automatic dead-time control circuit can dynamically adjust the dead time of the high-side drive signal and the low-side drive signal based on the clock input signal and the real-time detected dead-time state. This achieves automatic dead-time control of the LLC resonant converter's switching transistors, effectively avoiding shoot-through, improving the converter's efficiency and reliability, reducing dependence on external high-voltage capacitors, and further reducing system cost and complexity.

[0008] Optionally, the maximum dead time control circuit includes a high-side delay path and a low-side delay path, wherein the high-side delay path is used to generate the high-side dead time control signal H1, and the low-side delay path is used to generate the low-side dead time control signal L1.

[0009] By employing the above technical solution, the maximum dead-time control circuit, which includes both high-side and low-side delay paths, can generate high-side dead-time control signals and low-side dead-time control signals respectively. These control signals provide a safe maximum dead-time limit for subsequent automatic dead-time adjustment, ensuring that the resonant transformer can start normally even under the most unfavorable conditions.

[0010] Optionally, the high-side delay path includes a second inverter U2, a fifth inverter U5, a sixth inverter U6, a second PMOS transistor P2, a fourth NMOS transistor N4, a sixth resistor R6, and a fifth capacitor C5; wherein, the input terminal of the second inverter U2 is used to receive the clock input signal CLKin, and the second inverter U2 outputs the inverted clock signal CLKinn to the gate of the second PMOS transistor P2 and the gate of the fourth NMOS transistor N4; the source of the second PMOS transistor P2 is connected to the power supply terminal VDD, and the drain of the second PMOS transistor P2 is connected to the first terminal of the sixth resistor R6; the fourth The source of NMOS transistor N4 is connected to ground GND, and the drain of the fourth NMOS transistor N4 is connected to the second terminal of the sixth resistor R6; the first terminal of the fifth capacitor C5 is connected to the second terminal of the sixth resistor R6, and the second terminal of the fifth capacitor C5 is connected to ground GND; the input terminal of the fifth inverter U5 is connected to the first terminal of the fifth capacitor C5, the node voltage signal at the first terminal of the fifth capacitor C5 is input to the fifth inverter U5, the output terminal of the fifth inverter U5 is connected to the input terminal of the sixth inverter U6, and the output terminal of the sixth inverter U6 is used to output the high-side dead-time control signal H1.

[0011] The low-side delay path includes an eighth PMOS transistor P8, a ninth NMOS transistor N9, a ninth resistor R9, a sixth capacitor C6, a thirteenth inverter U13, and a fourteenth inverter U14; the gates of the eighth PMOS transistor P8 and the ninth NMOS transistor N9 are used to receive the clock input signal CLKin; the source of the eighth PMOS transistor P8 is connected to the power supply terminal VDD, and the drain of the eighth PMOS transistor P8 is connected to the first terminal of the ninth resistor R9; the source of the ninth NMOS transistor N9 is connected to the ground terminal GN. D, the drain of the ninth NMOS transistor N9 is connected to the second terminal of the ninth resistor R9; the first terminal of the sixth capacitor C6 is connected to the second terminal of the ninth resistor R9, and the second terminal of the sixth capacitor C6 is connected to ground GND; the node voltage signal at the first terminal of the sixth capacitor C6 is input to the thirteenth inverter U13, the output terminal of the thirteenth inverter U13 is connected to the input terminal of the fourteenth inverter U14, and the output terminal of the fourteenth inverter U14 is used to output the low-side dead-time control signal L1.

[0012] By employing the above technical solution, and through an RC charging and discharging network composed of specific PMOS transistors, NMOS transistors, resistors, capacitors, and inverters in the high-side and low-side delay paths, the delay characteristics of the high-side dead-time control signals and the low-side dead-time control signals can be precisely controlled. For example, the high-level delay of the high-side dead-time control signal is longer, and the low-level delay is shorter; similarly, the high-level delay of the low-side dead-time control signal is longer, and the low-level delay is shorter. This asymmetric delay design allows the maximum dead time of the high-side and low-side drive signals to be set according to the characteristics and operating requirements of different switching transistors, thereby optimizing the startup process of the resonant converter while ensuring safety.

[0013] Optionally, the narrow pulse generation circuit includes a rising edge narrow pulse generation path and a falling edge narrow pulse generation path. The rising edge narrow pulse generation path is used to generate a rising edge narrow pulse signal Hon1, and the falling edge narrow pulse generation path is used to generate a falling edge narrow pulse signal Hoff1.

[0014] By employing the above technical solution, the narrow pulse generation circuit includes both rising-edge and falling-edge narrow pulse generation paths, enabling the generation of rising-edge and falling-edge narrow pulse signals respectively. The accurate generation of these narrow pulse signals is crucial for driving the high-voltage transistor; their short pulse widths help reduce the switching power consumption of the drive circuit while ensuring the transmission of the drive signal.

[0015] Optionally, the rising edge narrow pulse generation path includes a first inverter U1, an eighth inverter U8, an eleventh inverter U11, a first PMOS transistor P1, a third NMOS transistor N3, a fifth resistor R5, a fourth capacitor C4, and a third AND gate U3; wherein, the input terminal of the eighth inverter U8 is used to receive the high-side drive signal H2, and the output terminal of the eighth inverter U8 is connected to the input terminal of the eleventh inverter U11, the gate of the first PMOS transistor P1, and the gate of the third NMOS transistor N3; the source of the first PMOS transistor P1 is connected to the power supply terminal VDD, and the drain of the first PMOS transistor P1 is connected to the first resistor R5. The source of the third NMOS transistor N3 is connected to ground GND, and the drain of the third NMOS transistor N3 is connected to the second terminal of the fifth resistor R5; the first terminal of the fourth capacitor C4 is connected to the second terminal of the fifth resistor R5, and the second terminal of the fourth capacitor C4 is connected to ground GND; the node voltage signal at the first terminal of the fourth capacitor C4 is input to the first inverter U1, the output terminal of the first inverter U1 is connected to the first input terminal of the third AND gate U3, the output terminal of the eleventh inverter U11 is connected to the second input terminal of the third AND gate U3, and the output terminal of the third AND gate U3 is used to output a rising edge narrow pulse signal Hon1; The falling-edge narrow pulse generation path includes a 21st inverter U21, a 16th inverter U16, a 9th PMOS transistor P9, a 10th NMOS transistor N10, a 10th resistor R10, and a 17th AND gate U17; wherein, the gates of the 21st inverter U21, the 9th PMOS transistor P9, and the 10th NMOS transistor N10 are used to receive the high-side drive signal H2; the source of the 9th PMOS transistor P9 is connected to the power supply terminal VDD, and the drain of the 9th PMOS transistor P9 is connected to the first terminal of the 10th resistor R10; the source of the 10th NMOS transistor N10 is connected to the ground terminal GND, and the 10th NMOS transistor N10 is connected to the ground terminal GND. The drain of OS transistor N10 is connected to the second terminal of the tenth resistor R10; the first terminal of the seventh capacitor C7 is connected to the second terminal of the tenth resistor R10, the second terminal of the seventh capacitor C7 is connected to ground GND, and the node voltage signal of the first terminal of the seventh capacitor C7 is input to the sixteenth inverter U16; the output terminal of the twenty-first inverter U21 is connected to the first input terminal of the seventeenth AND gate U17, the output terminal of the sixteenth inverter U16 is connected to the second input terminal of the seventeenth AND gate U17, and the output terminal of the seventeenth AND gate U17 is used to output the falling edge narrow pulse signal Hoff1.

[0016] By employing the above technical solution, and through specific delay and logic combinations composed of inverters, PMOS transistors, NMOS transistors, resistors, capacitors, and AND gates in the rising and falling edge narrow pulse generation paths, it is possible to accurately generate narrow-width rising-edge and falling-edge narrow pulse signals based on the rising and falling edges of the high-side drive signal. For example, with appropriate configuration, the narrow pulse width can be precisely controlled to approximately 200 ns, thereby effectively shortening the turn-on time of the high-voltage transistor, significantly reducing the switching power consumption of the drive circuit, and improving overall efficiency.

[0017] Optionally, the level-shifting high-voltage transistor drive and dead-time detection input circuit includes a fourth inverter U4, an eighteenth inverter U18, a third PMOS transistor P3, a tenth PMOS transistor P10, a fifth NMOS transistor N5, a sixth NMOS transistor N6, a seventh NMOS transistor N7, an eighth NMOS transistor N8, an eleventh NMOS transistor N11, a seventh resistor R7, a seventh diode D7, and an eighth diode D8; wherein, the input terminal of the fourth inverter U4 is used to receive the rising edge narrow pulse signal Hon1, and the output terminal of the fourth inverter U4 is connected to the gate of the third PMOS transistor P3 and the gate of the fifth NMOS transistor N5; the third PMOS transistor The source of P3 is connected to the power supply terminal VDD, and the drain of the third PMOS transistor P3 is connected to the first terminal of the seventh resistor R7; the source of the fifth NMOS transistor N5 is connected to the ground terminal GND, and the drain of the fifth NMOS transistor N5 is connected to the second terminal of the seventh resistor R7, which is connected to the output terminal of the high-side high-voltage transistor turn-on signal hon; the gate of the sixth NMOS transistor N6 is connected to the output terminal of the fourth inverter U4, the source of the sixth NMOS transistor N6 is connected to the ground terminal GND, and the drain of the sixth NMOS transistor N6 is connected to the high-side high-voltage transistor turn-on signal hon through the seventh diode D7. The output terminal of the eighth diode D8; the cathode of the eighth diode D8 is connected to the output terminal of the high-side high-voltage transistor turn-on signal hon, and the anode of the eighth diode D8 is connected to ground GND; the gate of the seventh NMOS transistor N7 is connected to the output terminal of the fourth inverter U4, the source of the seventh NMOS transistor N7 is connected to the output terminal of the dead-time detection signal H3, and the drain of the seventh NMOS transistor N7 is connected to the output terminal of the high-side high-voltage transistor turn-on signal hon; the gate of the eighth NMOS transistor N8 is used to receive the rising edge narrow pulse signal Hon1, the source of the eighth NMOS transistor N8 is connected to ground GND, and the drain of the eighth NMOS transistor N8 is connected to the output terminal of the high-side high-voltage transistor turn-on signal hon; the gate of the eighth NMOS transistor N8 is used to receive the rising edge narrow pulse signal Hon1, the source of the eighth NMOS transistor N8 is connected to ground GND, and the drain of the eighth NMOS transistor N8 is connected to the output terminal of the high-side high-voltage transistor turn-on signal hon. The output terminal of the dead zone detection signal H3 is connected to the output terminal of the 18th inverter U18; the input terminal of the 18th inverter U18 is used to receive the falling edge narrow pulse signal Hoff1; the output terminal of the 18th inverter U18 is connected to the gate of the 10th PMOS transistor P10 and the gate of the 11th NMOS transistor N11; the source of the 10th PMOS transistor P10 is connected to the power supply terminal VDD; the drain of the 10th PMOS transistor P10 is connected to the output terminal of the high-side high voltage transistor turn-off signal hoff; the source of the 11th NMOS transistor N11 is connected to the ground terminal GND; and the drain of the 11th NMOS transistor N11 is connected to the output terminal of the high-side high voltage transistor turn-off signal hoff.

[0018] By employing the above technical solution, through a clever combination of specific inverters, PMOS transistors, NMOS transistors, resistors, and diodes in the level-shifting high-voltage transistor drive and dead-time detection input circuit, the level shifting of the rising-edge narrow pulse signal can be achieved, safely and effectively driving the high-side high-voltage transistor while generating a signal for dead-time detection. Specifically, the configuration of the NMOS transistor and diodes prevents the high-voltage transistor from being erroneously turned on or damaged during rapid voltage changes. For example, the high-side high-voltage transistor turn-on signal is clamped below 0.7V at the rapid rising edge of VS and above -0.7V at the falling edge of VS, thereby improving the stability and reliability of the high-voltage side drive. Furthermore, this circuit can convert the actual level information of the high-side high-voltage transistor turn-on signal into a low-level dead-time detection signal, facilitating subsequent logic processing. It also utilizes the high-voltage transistor's own parasitic capacitance to achieve high-frequency coupling detection, reducing the need for an additional 600V high-voltage capacitor and lowering costs.

[0019] Optionally, the level shifting and comparison circuit includes a fourth PMOS transistor P4, a fifth PMOS transistor P5, a sixth PMOS transistor P6, a seventh PMOS transistor P7, an eleventh PMOS transistor P11, a twelfth PMOS transistor P12, a thirteenth PMOS transistor P13, a fourteenth PMOS transistor P14, a fifteenth PMOS transistor P15, an eighth resistor R8, an eleventh resistor R11, a twelfth resistor R12, a tenth comparator U10, and a twentieth comparator U20; wherein the source of the fourth PMOS transistor P4 and the source of the fifth PMOS transistor P5 are connected to the power supply terminal VDD, and the gate of the fourth PMOS transistor P4 and the gate of the fifth PMOS transistor P5 are connected to the power supply terminal VDD. The gates of all PMOS transistors are connected to the bias voltage VBP; the drain of the fourth PMOS transistor P4 is connected to the first terminal of the eighth resistor R8 and the inverting input of the tenth comparator U10; the drain of the fifth PMOS transistor P5 is connected to the non-inverting input of the tenth comparator U10 and the source of the seventh PMOS transistor P7; the output of the tenth comparator U10 is used to output the high-side dead-time comparison signal H4; the source of the sixth PMOS transistor is connected to the second terminal of the eighth resistor R8; the source of the seventh PMOS transistor P7 is connected to the drain of the fifth PMOS transistor P5; the gate of the sixth PMOS transistor is used to receive the dead-time detection signal H3; the gate of the seventh PMOS transistor P4 is connected to the second terminal of the eighth resistor R8 and the inverting input of the tenth comparator U10; the drain of the fifth PMOS transistor P5 is connected to the inverting input of the tenth comparator U10 and the source of the seventh PMOS transistor P7; the gate of the sixth PMOS transistor P4 is connected to the second terminal of the eighth resistor R8 and the source of the seventh PMOS transistor P7 is connected to the drain of the fifth PMOS transistor P5; the gate of the sixth PMOS transistor P4 is used to receive the dead-time detection signal H3; the gate of the seventh PMOS transistor P5 is connected to the second terminal of the eighth resistor R8 and the inverting input of the tenth comparator U10. The gate of MOSFET P7, the drain of the sixth PMOS transistor, and the drain of the seventh PMOS transistor P7 are all connected to ground (GND); the sources of the eleventh PMOS transistor P11, the twelfth PMOS transistor P12, and the thirteenth PMOS transistor P13 are connected to the power supply terminal VDD; the gate and drain of the eleventh PMOS transistor P11 are connected together to form a diode connection, and the gates of the eleventh PMOS transistor P11, the twelfth PMOS transistor P12, and the thirteenth PMOS transistor P13 are all connected to the bias voltage VBP; the drain of the eleventh PMOS transistor is connected to ground through the eleventh resistor R11, and the source of the twelfth PMOS transistor P11 is connected to the power supply terminal VDD; the gate and drain of the eleventh PMOS transistor P11 are connected to ground through the eleventh resistor R11, and the source of the twelfth PMOS transistor P12 is connected to the power supply terminal VDD; the gate and drain of the eleventh PMOS transistor P11 are ... The drain of P12 is connected to the non-inverting input of the twentieth comparator U20 and the source of the fourteenth PMOS transistor P14. The drain of the thirteenth PMOS transistor P13 is connected to the inverting input of the twentieth comparator U20 and the first terminal of the twelfth resistor R12. The output of the twentieth comparator U20 is used to output the low-side dead-time comparison signal H5. The gate of the fourteenth PMOS transistor P14 is used to receive the dead-time detection signal H3. The drain of the fourteenth PMOS transistor P14 is connected to ground. The source of the fifteenth PMOS transistor P15 is connected to the second terminal of the twelfth resistor R12. The gate and drain of the fifteenth PMOS transistor P15 are connected to ground.

[0020] By employing the above technical solution, and through a combination of specific PMOS transistors, resistors, and comparators in the level shifting and comparison circuit, and utilizing a reference voltage source, the level-shifted dead-zone detection signal can be accurately compared with a preset reference level. This current mirror circuit and comparator design can accurately detect voltage changes at the high-voltage side node and convert them into high-side dead-zone comparison signals and low-side dead-zone comparison signals. For example, when the dead-zone detection signal voltage is below -100mV or above 100mV, the comparator will output a high level, providing an accurate basis for subsequent dead-zone signal generation and ensuring the sensitivity and accuracy of dead-zone detection.

[0021] Optionally, the dead-time signal generation module includes a ninth inverter U9, a nineteenth inverter U19, a twelfth D flip-flop, and a twenty-second D flip-flop; wherein, the input terminal of the ninth inverter U9 receives the high-side dead-time comparison signal H4, the output terminal of the ninth inverter U9 is connected to the CP input terminal of the twelfth D flip-flop U12, the RN input terminal of the twelfth D flip-flop U12 is used to receive the clock input signal CLKin, the D input terminal of the twelfth D flip-flop U12 is connected to the power supply terminal VDD, and the output terminal of the twelfth D flip-flop U12 is used to output the high-side dead-time signal DTH; the input terminal of the nineteenth inverter U19 is used to receive the low-side dead-time comparison signal H5, the output terminal of the nineteenth inverter U19 is connected to the CP input terminal of the twenty-second D flip-flop U22, the RN input terminal of the twenty-second D flip-flop U22 is used to receive the clock input signal CLKin, the D input terminal of the twenty-second D flip-flop U22 is connected to the power supply terminal VDD, and the output terminal of the twenty-second D flip-flop U22 is used to output the low-side dead-time signal DTL.

[0022] By employing the above technical solution, through a combination of a specific inverter and a D flip-flop in the dead-time signal generation module, the high-side dead-time comparison signal and the low-side dead-time comparison signal output from the level shifting and comparator circuit can be accurately converted into high-side dead-time signals and low-side dead-time signals with the assistance of a clock signal. The use of D flip-flops ensures the synchronous and stable output of the dead-time signal, triggering only when specific conditions are met (such as a high clock level and a falling edge generated by the comparator output). This effectively converts the analog dead-time detection result into a digital logic signal, providing precise dead-time compensation instructions for the final generation of the drive signal.

[0023] Optionally, the logic combination module includes a seventh OR gate U7 and a fifteenth OR gate U15; wherein, the first input terminal of the seventh OR gate U7 is used to receive the high-side dead-time control signal H1, the second input terminal of the seventh OR gate U7 is used to receive the high-side dead-time signal DTH, and the output terminal of the seventh OR gate U7 is used to output the high-side drive signal H2; the first input terminal of the fifteenth OR gate U15 is used to receive the low-side dead-time control signal L1, the second input terminal of the fifteenth OR gate U15 is used to receive the low-side dead-time signal DTL, and the output terminal of the fifteenth OR gate U15 is used to output the low-side drive signal L2.

[0024] By employing the above technical solution, a specific OR gate in the logic combination module can perform a logical OR operation between the high-side / low-side dead-time control signal generated by the maximum dead-time control circuit and the high-side / low-side dead-time signal generated by the dead-time signal generation module. This combination ensures that the resonant converter uses maximum dead-time control during startup and automatic dead-time control after startup, thus ensuring the startup characteristics and operating efficiency of the resonant converter.

[0025] On the other hand, this application also provides an LLC resonant converter, which adopts the following technical solution: An LLC resonant converter includes the automatic dead-time control circuit.

[0026] By integrating the automatic dead-time control circuit into the LLC resonant converter, the converter can achieve automatic dead-time adjustment of the output switching transistor. This not only effectively prevents transistor shoot-through and improves converter efficiency and stability, but also utilizes the parasitic capacitance of the first high-voltage transistor for high-frequency coupling detection, eliminating the need for an additional expensive 600V high-voltage capacitor, significantly reducing manufacturing costs and circuit complexity. Simultaneously, the simplified and reliable pulse drive circuit design results in lower power consumption of the level shifting circuit without affecting the accuracy of the automatic dead-time input detection signal, thus realizing a low-cost, high-performance LLC resonant converter.

[0027] In summary, this application includes at least one of the following beneficial technical effects: 1. By integrating a maximum dead-time control circuit, a narrow pulse generation circuit, a level-shifting high-voltage transistor drive and dead-time detection input circuit, a level-shifting and comparison circuit, and a dead-time control logic circuit, this automatic dead-time control circuit can dynamically adjust the dead time of the high-side drive signal and the low-side drive signal based on the clock input signal and the real-time detected dead-time state. This enables automatic dead-time control of the LLC resonant converter's switching transistors, effectively avoiding shoot-through, improving the converter's efficiency and reliability, and reducing dependence on external high-voltage capacitors, further reducing system cost and complexity.

[0028] 2. By using RC charging and discharging networks composed of specific PMOS transistors, NMOS transistors, resistors, capacitors, and inverters in the high-side and low-side delay paths, the delay characteristics of the high-side and low-side dead-time control signals can be precisely controlled. For example, the high-level delay of the high-side dead-time control signal is longer, and the low-level delay is shorter; similarly, the high-level delay of the low-side dead-time control signal is longer, and the low-level delay is shorter. This asymmetric delay design allows the maximum dead time of the high-side and low-side drive signals to be set according to the characteristics and operating requirements of different switching transistors, thereby optimizing the switching process while ensuring safety.

[0029] 3. By using specific delay and logic combinations of inverters, PMOS transistors, NMOS transistors, resistors, capacitors, and AND gates in the rising and falling edge narrow pulse generation paths, it is possible to accurately generate narrow-width rising and falling edge narrow pulse signals based on the rising and falling edges of the high-side drive signal. For example, with appropriate configuration, the narrow pulse width can be precisely controlled to approximately 200 ns, thereby effectively shortening the turn-on time of the high-voltage transistor, significantly reducing the switching power consumption of the drive circuit, and improving overall efficiency.

[0030] 4. By cleverly combining specific inverters, PMOS transistors, NMOS transistors, resistors, and diodes in the high-voltage transistor drive and dead-time detection input circuit, the level shift of the rising edge narrow pulse signal can be achieved, safely and effectively driving the high-side high-voltage transistor, while also generating a signal for dead-time detection. Specifically, the configuration of the NMOS transistor and diodes prevents the high-voltage transistor from being accidentally turned on or damaged during rapid voltage changes. For example, the high-side high-voltage transistor turn-on signal is clamped below 0.7V at the rapid rising edge of VS, and above -0.7V at the falling edge of VS, thereby improving the stability and reliability of the high-voltage side drive. Furthermore, this circuit can convert the actual level information of the high-side high-voltage transistor turn-on signal into a low-level dead-time detection signal, facilitating subsequent logic processing. It also utilizes the high-voltage transistor's own parasitic capacitance to achieve high-frequency coupling detection, reducing the need for an additional 600V high-voltage capacitor and lowering costs.

[0031] 5. By integrating the automatic dead-time control circuit into the LLC resonant converter, the converter can achieve automatic dead-time adjustment of the output switching transistor. This not only effectively prevents transistor shoot-through and improves the converter's efficiency and stability, but also utilizes the parasitic capacitance of the first high-voltage transistor itself for high-frequency coupling detection, eliminating the need for an additional expensive 600V high-voltage capacitor, significantly reducing manufacturing costs and circuit complexity. Simultaneously, the simplified and reliable pulse drive circuit design results in lower power consumption of the level shifting circuit without affecting the accuracy of the automatic dead-time input detection signal, thus realizing a low-cost, high-performance LLC resonant converter. Attached Figure Description

[0032] Figure 1 This diagram illustrates an overall block diagram of an automatic dead-time control circuit according to an embodiment of this application. Figure 2 A circuit diagram illustrating an automatic dead-time control circuit according to an embodiment of this application is shown; Figure 3 A schematic diagram of the level timing of an automatic dead-time control circuit according to an embodiment of this application is shown. Figure 4 A circuit diagram illustrating the maximum dead-time control circuit of an embodiment of this application is shown; Figure 5 A schematic diagram illustrating the level timing of the maximum dead-time control circuit according to an embodiment of this application is provided. Figure 6 A circuit diagram illustrating a narrow pulse generation circuit according to an embodiment of this application is shown; Figure 7 A schematic diagram illustrating the level timing of the narrow pulse generation circuit according to an embodiment of this application is shown. Figure 8 A circuit diagram illustrating the level-shift high-voltage tube drive and dead-zone detection input circuit of an embodiment of this application is shown; Figure 9 A circuit diagram illustrating the level shift and comparison circuit of an embodiment of this application is shown; Figure 10 A circuit diagram illustrating the dead-time control logic circuit of an embodiment of this application is shown; Figure 11 A schematic diagram illustrating the level timing of the dead-time control logic circuit according to an embodiment of this application is provided. Figure 12 A circuit diagram illustrating an embodiment of the LLC resonant converter of this application is shown.

[0033] Figure labeling: 10, Maximum dead time control circuit; 20, Narrow pulse generation circuit; 30, Level shift high voltage tube drive and dead time detection input circuit; 40, Level shift and comparison circuit; 51, Dead time signal generation module; 52, Logic combination module. Detailed Implementation

[0034] The following combination Figure 1 - Figure 12 This application will be described in further detail.

[0035] This application discloses an automatic dead-time control circuit.

[0036] Figure 1 An overall block diagram of an automatic dead-time control circuit according to an embodiment of this application is shown. Figure 2 A circuit diagram illustrating an automatic dead-time control circuit according to an embodiment of this application is shown. Figure 3A schematic diagram illustrating the level timing of an automatic dead-time control circuit according to an embodiment of this application is shown. (Refer to...) Figure 1 , Figure 2 and Figure 3 The automatic dead-time control circuit includes a maximum dead-time control circuit 10, a narrow pulse generation circuit 20, a level shift high-voltage tube drive and dead-time detection input circuit 30, a level shift and comparison circuit 40, and a dead-time control logic circuit (including a dead-time signal generation module 51 located after the level shift and comparison circuit 40 and a logic combination module 52 located between the maximum dead-time control circuit 10 and the narrow pulse generation circuit 20).

[0037] Figure 4 A circuit diagram illustrating the maximum dead-time control circuit of an embodiment of this application is shown. (Refer to...) Figure 4 The maximum dead time control circuit 10 includes a high-side delay path and a low-side delay path. The maximum dead time control circuit 10 receives the clock input signal CLKin, generates a high-side dead time control signal H1 through the high-side delay path, and generates a low-side dead time control signal L1 through the low-side delay path.

[0038] The high-side delay path includes a second inverter U2, a fifth inverter U5, a sixth inverter U6, a second PMOS transistor P2, a fourth NMOS transistor N4, a sixth resistor R6, and a fifth capacitor C5. The input of the second inverter U2 receives the clock input signal CLKin, and its output is the inverted clock signal CLKinn (i.e., the inverted version of the clock input signal CLKin), which is output to the gates of the second PMOS transistor P2 and the fourth NMOS transistor N4. The source of the second PMOS transistor P2 is connected to the power supply terminal VDD, and its drain is connected to the first terminal of the sixth resistor R6. The source of the fourth NMOS transistor N4 is connected to ground GND, and its drain is connected to the second terminal of the sixth resistor R6. The first terminal of the fifth capacitor C5 is connected to the second terminal of the sixth resistor R6, and the second terminal of the fifth capacitor C5 is connected to ground GND. The input terminal of the fifth inverter U5 is connected to the first terminal of the fifth capacitor C5, and the node voltage signal at the first terminal of the fifth capacitor C5 is input to the fifth inverter U5. The output terminal of the fifth inverter U5 is connected to the input terminal of the sixth inverter U6, and the output terminal of the sixth inverter U6 is used to output the high-side dead-time control signal H1.

[0039] The low-side delay path includes the eighth PMOS transistor P8, the ninth NMOS transistor N9, the ninth resistor R9, the sixth capacitor C6, the thirteenth inverter U13, and the fourteenth inverter U14. The gates of the eighth PMOS transistor P8 and the ninth NMOS transistor N9 are used to receive the clock input signal CLKin. The source of the eighth PMOS transistor P8 is connected to the power supply terminal VDD, and the drain of the eighth PMOS transistor P8 is connected to the first terminal of the ninth resistor R9. The source of the ninth NMOS transistor N9 is connected to ground GND, and the drain of the ninth NMOS transistor N9 is connected to the second terminal of the ninth resistor R9. The first terminal of the sixth capacitor C6 is connected to the second terminal of the ninth resistor R9, and the second terminal of the sixth capacitor C6 is connected to ground GND. The node voltage signal at the first terminal of the sixth capacitor C6 is input to the thirteenth inverter U13. The output of the thirteenth inverter U13 is connected to the input of the fourteenth inverter U14, and the output of the fourteenth inverter U14 is used to output the low-side dead-time control signal L1.

[0040] Figure 5 A schematic diagram illustrating the level timing of the maximum dead-time control circuit according to an embodiment of this application is shown. (Refer to the accompanying reference.) Figure 4 and Figure 5 The maximum dead time control circuit 10 generates a high-side dead time control signal H1 and a low-side dead time control signal L1 with specific delay characteristics based on the clock input signal CLKin through two RC charging and discharging networks, which are used as the maximum dead time control signals.

[0041] In the high-side delay path, the second PMOS transistor P2, the sixth resistor R6, the fourth NMOS transistor N4, and the fifth capacitor C5 form an RC charging and discharging network controlled by the clock inversion signal CLKinn. When the clock input signal CLKin is high, the clock inversion signal CLKinn is low. At this time, the second PMOS transistor P2 is turned on, and the fourth NMOS transistor N4 is turned off. The fifth capacitor C5 is charged from VDD through the second PMOS transistor P2 and the sixth resistor R6. Due to the presence of the sixth resistor R6, the charging time of the fifth capacitor C5 (which determines the delay) is relatively long. When the clock input signal CLKin is low, the clock inversion signal CLKinn is high. At this time, the second PMOS transistor P2 is turned off, and the fourth NMOS transistor N4 is turned on. The fifth capacitor C5 discharges rapidly to ground GND directly through the fourth NMOS transistor N4. The voltage waveform on the fifth capacitor C5 is shaped and buffered by the fifth inverter U5 and the sixth inverter U6, finally outputting the high-side dead-time control signal H1. Because the charging of the fifth capacitor C5 (corresponding to the high-level turn-on delay) is performed through the sixth resistor R6, it has a relatively long delay; while the discharging (corresponding to the low-level turn-off delay) is performed directly through the fourth NMOS transistor N4, which is faster. Therefore, this design results in a large high-level delay and a small low-level delay for the high-side dead-time control signal H1.

[0042] In the low-side delay path, the eighth PMOS transistor P8, the ninth resistor R9, the ninth NMOS transistor N9, and the sixth capacitor C6 form another RC charging and discharging network directly controlled by the clock input signal CLKin. When the clock input signal CLKin is high, the eighth PMOS transistor P8 is off, the ninth NMOS transistor N9 is on, and the sixth capacitor C6 discharges rapidly to ground GND directly through the ninth NMOS transistor N9. When the clock input signal CLKin is low, the eighth PMOS transistor P8 is on, the ninth NMOS transistor N9 is off, and the sixth capacitor C6 is charged from the power supply terminal VDD through the eighth PMOS transistor P8 and the ninth resistor R9. The voltage waveform on the sixth capacitor C6 is shaped and buffered by the thirteenth inverter U13 and the fourteenth inverter U14, finally outputting the low-side dead-time control signal L1. In the low-side delay path, this design results in a larger high-level delay and a smaller low-level delay for the low-side dead-time control signal L1. By precisely selecting the resistance and capacitance values ​​of the sixth resistor R6, the fifth capacitor C5, the ninth resistor R9, and the sixth capacitor C6, the maximum dead time represented by the high-side dead time control signal H1 and the low-side dead time control signal L1 can be set (for example, it can be set to 1.5µs). When the resonant converter first starts up, because the rising and falling edge detection signals of VS are not yet available, the resonant converter starts with the maximum dead time to prevent abnormal startup of the resonant transformer.

[0043] Figure 6A circuit diagram illustrating a narrow pulse generation circuit according to an embodiment of this application is shown. (Refer to...) Figure 6 The narrow pulse generation circuit 20 includes a rising edge narrow pulse generation path and a falling edge narrow pulse generation path, used to receive the high-side drive signal H2 and generate a rising edge narrow pulse signal Hon1 and a falling edge narrow pulse signal Hoff1.

[0044] The rising-edge narrow pulse generation path includes a first inverter U1, an eighth inverter U8, an eleventh inverter U11, a first PMOS transistor P1, a third NMOS transistor N3, a fifth resistor R5, a fourth capacitor C4, and a third AND gate U3. The input of the eighth inverter U8 receives the high-side drive signal H2, and its output is connected to the input of the eleventh inverter U11, the gate of the first PMOS transistor P1, and the gate of the third NMOS transistor N3. The source of the first PMOS transistor P1 is connected to the power supply VDD, and its drain is connected to the first terminal of the fifth resistor R5. The source of the third NMOS transistor N3 is connected to ground GND, and its drain is connected to the second terminal of the fifth resistor R5. The first terminal of the fourth capacitor C4 is connected to the second terminal of the fifth resistor R5, and the second terminal of the fourth capacitor C4 is connected to ground GND. The node voltage signal at the first terminal of the fourth capacitor C4 is input to the first inverter U1. The output of the first inverter U1 is connected to the first input of the third AND gate U3, the output of the eleventh inverter U11 is connected to the second input of the third AND gate U3, and the output of the third AND gate U3 is used to output the rising edge narrow pulse signal Hon1.

[0045] The falling-edge narrow pulse generation path includes a 21st inverter U21, a 16th inverter U16, a 9th PMOS transistor P9, a 10th NMOS transistor N10, a 10th resistor R10, and a 17th AND gate U17. The gates of the 21st inverter U21, the 9th PMOS transistor P9, and the 10th NMOS transistor N10 are used to receive the high-side drive signal H2. The source of the 9th PMOS transistor P9 is connected to the power supply terminal VDD, and its drain is connected to the first terminal of the 10th resistor R10. The source of the 10th NMOS transistor N10 is connected to ground GND, and its drain is connected to the second terminal of the 10th resistor R10. The first terminal of the 7th capacitor C7 is connected to the second terminal of the 10th resistor R10, and the second terminal of the 7th capacitor C7 is connected to ground GND. The node voltage signal at the first terminal of the 7th capacitor C7 is input to the 16th inverter U16. The output of the twenty-first inverter U21 is connected to the first input of the seventeenth AND gate U17, and the output of the sixteenth inverter U16 is connected to the second input of the seventeenth AND gate U17. The output of the seventeenth AND gate U17 is used to output the falling edge narrow pulse signal Hoff1.

[0046] Figure 7A schematic diagram illustrating the level timing of a narrow pulse generation circuit according to an embodiment of this application is shown. (Refer to the reference diagram.) Figure 6 and Figure 7 The high-side drive signal H2 is input to the eighth inverter U8. The output of the eighth inverter U8 is connected to the eleventh inverter U11, and then to the gates of the first PMOS transistor P1 and the third NMOS transistor N3. The fifth resistor R5 and the fourth capacitor C4 provide a delay, causing the third AND gate U3 to output a narrow pulse on the rising edge of the high-side drive signal H2. Similarly, the seventeenth AND gate U17 outputs a narrow pulse on the falling edge of the high-side drive signal H2. Optionally, the fifth resistor R5, the fourth capacitor C4, the tenth resistor R10, and the seventh capacitor C7 are configured to form a 200ns delay, resulting in a 200ns narrow pulse for both the rising edge narrow pulse signal Hon1 and the falling edge narrow pulse signal Hoff1. The narrow pulses shorten the turn-on time of the high-voltage transistors N1 and N2, significantly reducing power consumption.

[0047] Figure 8 A circuit diagram illustrating the level-shift high-voltage transistor drive and dead-time detection input circuit according to an embodiment of this application is shown. (Refer to...) Figure 8 The input circuit 30 for driving the high-voltage tube with level shift and detecting dead zone is connected to the narrow pulse generation circuit 20, and includes the fourth inverter U4, the eighteenth inverter U18, the third PMOS transistor P3, the tenth PMOS transistor P10, the fifth NMOS transistor N5, the sixth NMOS transistor N6, the seventh NMOS transistor N7, the eighth NMOS transistor N8, the eleventh NMOS transistor N11, the seventh resistor R7, the seventh diode D7, and the eighth diode D8.

[0048] The input of the fourth inverter U4 receives the rising edge narrow pulse signal Hon1. The output of the fourth inverter U4 is connected to the gate of the third PMOS transistor P3 and the gate of the fifth NMOS transistor N5. The source of the third PMOS transistor P3 is connected to VDD, and its drain is connected to the first terminal of the seventh resistor R7. The source of the fifth NMOS transistor N5 is connected to ground GND, and its drain is connected to the second terminal of the seventh resistor R7. The second terminal of the seventh resistor R7 is connected to the output of the high-side high-voltage transistor turn-on signal Hon. The gate of the sixth NMOS transistor N6 is connected to the output of the fourth inverter U4, its source is connected to ground GND, and its drain is connected to the output of the high-side high-voltage transistor turn-on signal Hon through the seventh diode D7. The cathode of the eighth diode D8 is connected to the output of the high-side high-voltage transistor turn-on signal Hon, and its anode is connected to ground GND. The gate of the seventh NMOS transistor N7 is connected to the output of the fourth inverter U4, its source is connected to the output of the dead-time detection signal H3, and its drain is connected to the output of the high-side high-voltage transistor turn-on signal Hon. The gate of the eighth NMOS transistor N8 is used to receive the rising edge narrow pulse signal Hon1, its source is connected to ground GND, and its drain is connected to the output of the dead-time detection signal H3. The input of the eighteenth inverter U18 is used to receive the falling edge narrow pulse signal Hoff1, and its output is connected to the gate of the tenth PMOS transistor P10 and the gate of the eleventh NMOS transistor N11. The source of the tenth PMOS transistor P10 is connected to the power supply VDD, and its drain is connected to the output of the high-side high-voltage transistor turn-off signal hoff. The source of the eleventh NMOS transistor N11 is connected to ground GND, and its drain is connected to the output of the high-side high-voltage transistor turn-off signal hoff.

[0049] In the high-voltage transistor drive and dead-time detection input circuit 30, the sixth NMOS transistor N6 and the seventh diode D7 ensure that when hon1 is low, the voltage is clamped at 0.7V via high-voltage parasitic capacitance at the fast rising edge of VS, preventing the high-voltage transistor (first NMOS transistor N1) from being accidentally turned on. Through the fifth NMOS transistor N5 and the seventh resistor R7, the hon signal is controlled to be greater than 0.2V at the fast rising edge of VS by adjusting the value of the seventh resistor R7; when there is no rising edge of VS, hon is 0V. When hon1 is high, the seventh NMOS transistor N7 is off and the eighth NMOS transistor N8 is on, making the level of the dead-time detection signal H3 0V. When hon1 is low, the seventh NMOS transistor N7 is on and the eighth NMOS transistor N8 is off, and the hon signal is input to H3. Due to the function of the eighth diode D8, the minimum voltage of hon is clamped to -0.7V at the falling edge of VS, providing protection.

[0050] Figure 9A circuit diagram illustrating the level shift and comparison circuit of an embodiment of this application is shown. (Refer to...) Figure 9 The level shift and comparison circuit 40 is connected to the level shift high voltage tube drive and dead zone detection input circuit 30, including the fourth PMOS transistor P4, the fifth PMOS transistor P5, the sixth PMOS transistor P6, the seventh PMOS transistor P7, the eleventh PMOS transistor P11, the twelfth PMOS transistor P12, the thirteenth PMOS transistor P13, the fourteenth PMOS transistor P14, the fifteenth PMOS transistor P15, the eighth resistor R8, the eleventh resistor R11, the twelfth resistor R12, the tenth comparator U10, and the twentieth comparator U20.

[0051] The sources of the fourth PMOS transistor P4 and the fifth PMOS transistor P5 are both connected to the power supply terminal VDD. The gates of both PMOS transistors P4 and P5 are connected to the bias voltage VBP. The drain of PMOS transistor P4 is connected to the first terminal of the eighth resistor R8 and the inverting input of the tenth comparator U10. The drain of PMOS transistor P5 is connected to the non-inverting input of the tenth comparator U10 and the source of the seventh PMOS transistor P7. The output of the tenth comparator U10 is used to output the high-side dead-time comparison signal H4. The source of the sixth PMOS transistor is connected to the second terminal of the eighth resistor R8. The source of the seventh PMOS transistor P7 is connected to the drain of the fifth PMOS transistor P5. The gate of the sixth PMOS transistor is used to receive the dead-time detection signal H3. The gates of the seventh PMOS transistor P7, the drains of the sixth PMOS transistor, and the drains of the seventh PMOS transistor P7 are all connected to ground GND.

[0052] The sources of the eleventh PMOS transistor P11, the twelfth PMOS transistor P12, and the thirteenth PMOS transistor P13 are connected to the power supply terminal VDD. The gate and drain of the eleventh PMOS transistor P11 are connected together, forming a diode connection, and the gates of the eleventh PMOS transistor P11, the twelfth PMOS transistor P12, and the thirteenth PMOS transistor P13 are all connected to the bias voltage VBP. The drain of the eleventh PMOS transistor is connected to ground through the eleventh resistor R11. The drain of the twelfth PMOS transistor P12 is connected to the non-inverting input of the twentieth comparator U20 and the source of the fourteenth PMOS transistor P14. The drain of the thirteenth PMOS transistor P13 is connected to the inverting input of the twentieth comparator U20 and the first terminal of the twelfth resistor R12. The output of the twentieth comparator U20 is used to output the low-side dead-time comparison signal H5. The gate of the fourteenth PMOS transistor P14 is used to receive the dead-time detection signal H3, and its drain is connected to ground. The source of the fifteenth PMOS transistor P15 is connected to the second terminal of the twelfth resistor R12, and the gate and drain are connected to ground.

[0053] In this level shifting and comparison circuit 40, the power supply terminal VDD voltage is 5V. The power supply terminal VDD, the twelfth resistor R12, and the eleventh PMOS transistor P11 constitute the reference bias current. The gate and source potentials of the eleventh PMOS transistor P11, the twelfth PMOS transistor P12, the thirteenth PMOS transistor P13, the fourth PMOS transistor P4, and the fifth PMOS transistor P5 are the same, forming a mirror current source circuit. By adjusting the resistance values ​​of the eighth resistor R8 and the twelfth resistor R12, the voltage difference across the eighth resistor R8 and the twelfth resistor R12 can be made 100mV. When the voltage of the dead-time detection signal H3 is lower than -100mV, the inverting input of the tenth comparator U10 is lower than the non-inverting input, and the output of the tenth comparator U10 is high. When the voltage of the high-side dead-time comparison signal H4 is higher than 100mV, the non-inverting input of the twenty-first comparator U21 is higher than the inverting input, and the output of comparator U21 is high.

[0054] Figure 10 A circuit diagram illustrating the dead-time control logic circuit of an embodiment of this application is shown. Figure 11 A timing diagram illustrating the dead-time control logic circuit of an embodiment of this application is shown. (Refer to...) Figure 10 and Figure 11 The dead-time control logic circuit includes a dead-time signal generation module 51 located after the level shift and comparison circuit 40, and a logic combination module 52 located between the maximum dead-time control circuit 10 and the narrow pulse generation circuit 20.

[0055] The dead-time signal generation module 51 receives the high-side dead-time comparison signal H4 and the low-side dead-time comparison signal H5, and, combined with the system clock, finally generates the high-side dead-time signal DTH and the low-side dead-time signal DTL. The dead-time signal generation module 51 includes a ninth inverter U9, a nineteenth inverter U19, a twelfth D flip-flop, and a twenty-second D flip-flop. The input of the ninth inverter U9 receives the high-side dead-time comparison signal H4, and its output is connected to the CP (clock pulse) input of the twelfth D flip-flop U12. The RN (asynchronous reset) input of the twelfth D flip-flop U12 receives the clock input signal CLKin, its D input is connected to the power supply VDD, and its output outputs the high-side dead-time signal DTH. The input of the nineteenth inverter U19 receives the low-side dead-time comparison signal H5, and its output is connected to the CP input of the twenty-second D flip-flop U22. The RN input of the 22nd D flip-flop U22 receives the clock input signal CLKin. The D input of the 22nd D flip-flop U22 is connected to the power supply VDD. The output of the 22nd D flip-flop U22 outputs the low-side dead-time signal DTL. The logic combination module 52 integrates the high-side dead-time signal DTH and the low-side dead-time signal DTL to generate the high-side drive signal H2 and the low-side drive signal L2. For the high-side dead-time signal DTH to be high, the clock input signal CKLin needs to be high, and the CP input of the 12th D flip-flop U12 needs to be triggered by a rising edge. For the low-side dead-time signal DTL to be high, the clock input signal CLKinn needs to be high, and the CP input of the 22nd D flip-flop U22 needs to be triggered by a rising edge. The logic combination module 52 includes a 7th OR gate U7 and a 15th OR gate U15. The first input of the seventh OR gate U7 is used to receive the high-side dead-time control signal H1, the second input of the seventh OR gate U7 is used to receive the high-side dead-time signal DTH, and the output of the seventh OR gate U7 is used to output the high-side drive signal H2. The first input of the fifteenth OR gate U15 is used to receive the low-side dead-time control signal L1, the second input of the fifteenth OR gate U15 is used to receive the low-side dead-time signal DTL, and the output of the fifteenth OR gate U15 is used to output the low-side drive signal L2.

[0056] The implementation principle of an automatic dead-time control circuit in this application embodiment is as follows: by integrating a maximum dead-time control circuit 10, a narrow pulse generation circuit 20, a level-shifting high-voltage tube drive and dead-time detection input circuit 30, a level-shifting and comparison circuit 40, and a dead-time control logic circuit, this automatic dead-time control circuit can dynamically adjust the dead time of the high-side drive signal and the low-side drive signal based on the clock input signal and the real-time detected dead-time state, thereby realizing automatic dead-time control of the switching transistor of the LLC resonant converter, effectively avoiding shoot-through, improving the efficiency and reliability of the converter, reducing the dependence on external high-voltage capacitors, and further reducing system cost and complexity.

[0057] This application also discloses an LLC resonant converter.

[0058] Figure 12 A circuit diagram illustrating an embodiment of the LLC resonant converter of this application is shown. (Refer to...) Figure 12 This LLC resonant converter integrates the automatic dead-time control circuit described in the above embodiment. It utilizes the parasitic capacitance of the first high-voltage transistor N1 itself for high-frequency coupling detection and automatic dead-time adjustment, eliminating the need for an additional 600V high-voltage capacitor. The first high-voltage transistor N1 acts as both a level shifter and a 600V high-voltage capacitor, resulting in lower chip costs. Furthermore, a simplified and reliable pulse drive circuit drives the first high-voltage transistor N1, minimizing power consumption in the level shifting circuit without affecting the automatic dead-time input detection signal.

[0059] The implementation principle of an LLC resonant converter according to an embodiment of this application is as follows: By integrating the automatic dead-time control circuit into the LLC resonant converter, the converter can achieve automatic dead-time adjustment of the output switching transistor. This not only effectively prevents the switching transistor from shooting through, improving the converter's efficiency and stability, but also utilizes the parasitic capacitance of the first high-voltage transistor itself for high-frequency coupling detection, eliminating the need for an additional expensive 600V high-voltage capacitor, significantly reducing manufacturing costs and circuit complexity. Simultaneously, the simplified and reliable pulse drive circuit design also results in lower power consumption of the level shifting circuit without affecting the accuracy of the automatic dead-time input detection signal, thus realizing a low-cost, high-performance LLC resonant converter.

[0060] The above are all preferred embodiments of this application, and are not intended to limit the scope of protection of this application. Therefore, all equivalent changes made in accordance with the structure, shape and principle of this application should be covered within the scope of protection of this application.

Claims

1. An automatic dead-time control circuit, characterized in that, include: The maximum dead time control circuit (10) is used to generate the high-side dead time control signal H1 and the low-side dead time control signal L1 based on the clock input signal CLKin. Narrow pulse generation circuit (20) is set after the maximum dead time control circuit (10) and is used to generate rising edge narrow pulse signal Hon1 and falling edge narrow pulse signal Hoff1 based on the high-side drive signal H2; The input circuit (30) for driving and detecting dead zone of the high-voltage tube with level displacement is connected to the narrow pulse generation circuit (20) and is used to generate the high-side high-voltage tube turn-on signal hon and the dead zone detection signal H3 based on the rising edge narrow pulse signal Hon1, and to generate the high-side high-voltage tube turn-off signal hoff based on the falling edge narrow pulse signal Hoff1. The level shifting and comparison circuit (40) is connected to the level shifting high voltage tube driving and dead zone detection input circuit (30) and is used to generate the high-side dead zone comparison signal H4 and the low-side dead zone comparison signal H5 based on the dead zone detection signal H3. The dead-time control logic circuit includes a dead-time signal generation module (51) and a logic combination module (52). The dead-time signal generation module (51) is connected to the level shift and comparison circuit (40) and is used to generate a high-side dead-time signal DTH based on the high-side dead-time comparison signal H4 and a low-side dead-time signal DTL based on the low-side dead-time comparison signal H5. The logic combination module (52) is located between the maximum dead-time control circuit (10) and the narrow pulse generation circuit (20) and is connected to the dead-time signal generation module (51). It is used to generate a high-side drive signal H2 based on the high-side dead-time control signal H1 and the high-side dead-time signal DTH, and to generate a low-side drive signal L2 based on the low-side dead-time control signal L1 and the low-side dead-time signal DTL.

2. The automatic dead-time control circuit according to claim 1, characterized in that, The maximum dead time control circuit (10) includes a high-side delay path and a low-side delay path. The high-side delay path is used to generate the high-side dead time control signal H1, and the low-side delay path is used to generate the low-side dead time control signal L1.

3. The automatic dead-time control circuit according to claim 2, characterized in that, The high-side delay path includes a second inverter U2, a fifth inverter U5, a sixth inverter U6, a second PMOS transistor P2, a fourth NMOS transistor N4, a sixth resistor R6, and a fifth capacitor C5; wherein, the input terminal of the second inverter U2 is used to receive the clock input signal CLKin, and the second inverter U2 outputs the inverted clock signal CLKinn to the gate of the second PMOS transistor P2 and the gate of the fourth NMOS transistor N4; the source of the second PMOS transistor P2 is connected to the power supply terminal VDD, and the drain of the second PMOS transistor P2 is connected to the first terminal of the sixth resistor R6; the fourth NMOS transistor... The source of the fourth NMOS transistor N4 is connected to ground GND, and the drain of the fifth NMOS transistor N4 is connected to the second terminal of the sixth resistor R6; the first terminal of the fifth capacitor C5 is connected to the second terminal of the sixth resistor R6, and the second terminal of the fifth capacitor C5 is connected to ground GND; the input terminal of the fifth inverter U5 is connected to the first terminal of the fifth capacitor C5, the node voltage signal at the first terminal of the fifth capacitor C5 is input to the fifth inverter U5, the output terminal of the fifth inverter U5 is connected to the input terminal of the sixth inverter U6, and the output terminal of the sixth inverter U6 is used to output the high-side dead-time control signal H1; The low-side delay path includes an eighth PMOS transistor P8, a ninth NMOS transistor N9, a ninth resistor R9, a sixth capacitor C6, a thirteenth inverter U13, and a fourteenth inverter U14; the gates of the eighth PMOS transistor P8 and the ninth NMOS transistor N9 are used to receive the clock input signal CLKin; the source of the eighth PMOS transistor P8 is connected to the power supply terminal VDD, and the drain of the eighth PMOS transistor P8 is connected to the first terminal of the ninth resistor R9; the source of the ninth NMOS transistor N9 is connected to the ground terminal GN. D, the drain of the ninth NMOS transistor N9 is connected to the second terminal of the ninth resistor R9; the first terminal of the sixth capacitor C6 is connected to the second terminal of the ninth resistor R9, and the second terminal of the sixth capacitor C6 is connected to ground GND; the node voltage signal at the first terminal of the sixth capacitor C6 is input to the thirteenth inverter U13, the output terminal of the thirteenth inverter U13 is connected to the input terminal of the fourteenth inverter U14, and the output terminal of the fourteenth inverter U14 is used to output the low-side dead-time control signal L1.

4. The automatic dead-time control circuit according to claim 1, characterized in that, The narrow pulse generation circuit (20) includes a rising edge narrow pulse generation path and a falling edge narrow pulse generation path. The rising edge narrow pulse generation path is used to generate a rising edge narrow pulse signal Hon1, and the falling edge narrow pulse generation path is used to generate a falling edge narrow pulse signal Hoff1.

5. The automatic dead-time control circuit according to claim 4, characterized in that, The rising edge narrow pulse generation path includes a first inverter U1, an eighth inverter U8, an eleventh inverter U11, a first PMOS transistor P1, a third NMOS transistor N3, a fifth resistor R5, a fourth capacitor C4, and a third AND gate U3; wherein, the input terminal of the eighth inverter U8 is used to receive the high-side drive signal H2, and the output terminal of the eighth inverter U8 is connected to the input terminal of the eleventh inverter U11, the gate of the first PMOS transistor P1, and the gate of the third NMOS transistor N3; the source of the first PMOS transistor P1 is connected to the power supply terminal VDD, and the drain of the first PMOS transistor P1 is connected to the first terminal of the fifth resistor R5; The source of the third NMOS transistor N3 is connected to ground GND, and the drain of the third NMOS transistor N3 is connected to the second terminal of the fifth resistor R5; the first terminal of the fourth capacitor C4 is connected to the second terminal of the fifth resistor R5, and the second terminal of the fourth capacitor C4 is connected to ground GND; the node voltage signal at the first terminal of the fourth capacitor C4 is input to the first inverter U1, the output terminal of the first inverter U1 is connected to the first input terminal of the third AND gate U3, the output terminal of the eleventh inverter U11 is connected to the second input terminal of the third AND gate U3, and the output terminal of the third AND gate U3 is used to output a rising edge narrow pulse signal Hon1; The falling-edge narrow pulse generation path includes a 21st inverter U21, a 16th inverter U16, a 9th PMOS transistor P9, a 10th NMOS transistor N10, a 10th resistor R10, and a 17th AND gate U17; wherein, the gates of the 21st inverter U21, the 9th PMOS transistor P9, and the 10th NMOS transistor N10 are used to receive the high-side drive signal H2; the source of the 9th PMOS transistor P9 is connected to the power supply terminal VDD, and the drain of the 9th PMOS transistor P9 is connected to the first terminal of the 10th resistor R10; the source of the 10th NMOS transistor N10 is connected to the ground terminal GND, and the 10th NMOS transistor N10 is connected to the ground terminal GND. The drain of OS transistor N10 is connected to the second terminal of the tenth resistor R10; the first terminal of the seventh capacitor C7 is connected to the second terminal of the tenth resistor R10, the second terminal of the seventh capacitor C7 is connected to ground GND, and the node voltage signal of the first terminal of the seventh capacitor C7 is input to the sixteenth inverter U16; the output terminal of the twenty-first inverter U21 is connected to the first input terminal of the seventeenth AND gate U17, the output terminal of the sixteenth inverter U16 is connected to the second input terminal of the seventeenth AND gate U17, and the output terminal of the seventeenth AND gate U17 is used to output the falling edge narrow pulse signal Hoff1.

6. The automatic dead-time control circuit according to claim 1, characterized in that, The level-shifting high-voltage transistor drive and dead-zone detection input circuit (30) includes a fourth inverter U4, an eighteenth inverter U18, a third PMOS transistor P3, a tenth PMOS transistor P10, a fifth NMOS transistor N5, a sixth NMOS transistor N6, a seventh NMOS transistor N7, an eighth NMOS transistor N8, an eleventh NMOS transistor N11, a seventh resistor R7, a seventh diode D7, and an eighth diode D8; wherein, the input terminal of the fourth inverter U4 is used to receive the rising edge narrow pulse signal Hon1, and the output terminal of the fourth inverter U4 is connected to the gate of the third PMOS transistor P3 and the gate of the fifth NMOS transistor N5; the third PMOS transistor The source of P3 is connected to the power supply terminal VDD, and the drain of the third PMOS transistor P3 is connected to the first terminal of the seventh resistor R7; the source of the fifth NMOS transistor N5 is connected to the ground terminal GND, and the drain of the fifth NMOS transistor N5 is connected to the second terminal of the seventh resistor R7, which is connected to the output terminal of the high-side high-voltage transistor turn-on signal hon; the gate of the sixth NMOS transistor N6 is connected to the output terminal of the fourth inverter U4, the source of the sixth NMOS transistor N6 is connected to the ground terminal GND, and the drain of the sixth NMOS transistor N6 is connected to the high-side high-voltage transistor turn-on signal hon through the seventh diode D7. The output terminal of the eighth diode D8; the cathode of the eighth diode D8 is connected to the output terminal of the high-side high-voltage transistor turn-on signal hon, and the anode of the eighth diode D8 is connected to ground GND; the gate of the seventh NMOS transistor N7 is connected to the output terminal of the fourth inverter U4, the source of the seventh NMOS transistor N7 is connected to the output terminal of the dead-time detection signal H3, and the drain of the seventh NMOS transistor N7 is connected to the output terminal of the high-side high-voltage transistor turn-on signal hon; the gate of the eighth NMOS transistor N8 is used to receive the rising edge narrow pulse signal Hon1, the source of the eighth NMOS transistor N8 is connected to ground GND, and the drain of the eighth NMOS transistor N8 is connected to the output terminal of the high-side high-voltage transistor turn-on signal hon; the gate of the eighth NMOS transistor N8 is used to receive the rising edge narrow pulse signal Hon1, the source of the eighth NMOS transistor N8 is connected to ground GND, and the drain of the eighth NMOS transistor N8 is connected to the output terminal of the high-side high-voltage transistor turn-on signal hon. The output terminal of the dead zone detection signal H3 is connected to the output terminal of the 18th inverter U18; the input terminal of the 18th inverter U18 is used to receive the falling edge narrow pulse signal Hoff1; the output terminal of the 18th inverter U18 is connected to the gate of the 10th PMOS transistor P10 and the gate of the 11th NMOS transistor N11; the source of the 10th PMOS transistor P10 is connected to the power supply terminal VDD; the drain of the 10th PMOS transistor P10 is connected to the output terminal of the high-side high voltage transistor turn-off signal hoff; the source of the 11th NMOS transistor N11 is connected to the ground terminal GND; and the drain of the 11th NMOS transistor N11 is connected to the output terminal of the high-side high voltage transistor turn-off signal hoff.

7. The automatic dead-time control circuit according to claim 1, characterized in that, The level shifting and comparison circuit (40) includes a fourth PMOS transistor P4, a fifth PMOS transistor P5, a sixth PMOS transistor P6, a seventh PMOS transistor P7, an eleventh PMOS transistor P11, a twelfth PMOS transistor P12, a thirteenth PMOS transistor P13, a fourteenth PMOS transistor P14, a fifteenth PMOS transistor P15, an eighth resistor R8, an eleventh resistor R11, a twelfth resistor R12, a tenth comparator U10, and a twentieth comparator U20; wherein, the source of the fourth PMOS transistor P4 and the source of the fifth PMOS transistor P5 are connected to the power supply terminal VDD, and the gate of the fourth PMOS transistor P4 and the gate of the fifth PMOS transistor P5 are connected to the power supply terminal VDD. The gates of all PMOS transistors are connected to the bias voltage VBP; the drain of the fourth PMOS transistor P4 is connected to the first terminal of the eighth resistor R8 and the inverting input of the tenth comparator U10; the drain of the fifth PMOS transistor P5 is connected to the non-inverting input of the tenth comparator U10 and the source of the seventh PMOS transistor P7; the output of the tenth comparator U10 is used to output the high-side dead-time comparison signal H4; the source of the sixth PMOS transistor is connected to the second terminal of the eighth resistor R8; the source of the seventh PMOS transistor P7 is connected to the drain of the fifth PMOS transistor P5; the gate of the sixth PMOS transistor is used to receive the dead-time detection signal H3; the gate of the seventh PMOS transistor P4 is connected to the second terminal of the eighth resistor R8 and the inverting input of the tenth comparator U10; the drain of the fifth PMOS transistor P5 is connected to the inverting input of the tenth comparator U10 and the source of the seventh PMOS transistor P7; the gate of the sixth PMOS transistor P4 is connected to the second terminal of the eighth resistor R8 and the source of the seventh PMOS transistor P7 is connected to the drain of the fifth PMOS transistor P5; the gate of the sixth PMOS transistor P4 is used to receive the dead-time detection signal H3; the gate of the seventh PMOS transistor P5 is connected to the second terminal of the eighth resistor R8 and the inverting input of the tenth comparator U10. The gate of MOSFET P7, the drain of the sixth PMOS transistor, and the drain of the seventh PMOS transistor P7 are all connected to ground (GND); the sources of the eleventh PMOS transistor P11, the twelfth PMOS transistor P12, and the thirteenth PMOS transistor P13 are connected to the power supply terminal VDD; the gate and drain of the eleventh PMOS transistor P11 are connected together to form a diode connection, and the gates of the eleventh PMOS transistor P11, the twelfth PMOS transistor P12, and the thirteenth PMOS transistor P13 are all connected to the bias voltage VBP; the drain of the eleventh PMOS transistor is connected to ground through the eleventh resistor R11, and the source of the twelfth PMOS transistor P11 is connected to the power supply terminal VDD; the gate and drain of the eleventh PMOS transistor P11 are connected to ground through the eleventh resistor R11, and the source of the twelfth PMOS transistor P12 is connected to the power supply terminal VDD; the gate and drain of the eleventh PMOS transistor P11 are ... The drain of P12 is connected to the non-inverting input of the twentieth comparator U20 and the source of the fourteenth PMOS transistor P14. The drain of the thirteenth PMOS transistor P13 is connected to the inverting input of the twentieth comparator U20 and the first terminal of the twelfth resistor R12. The output of the twentieth comparator U20 is used to output the low-side dead-time comparison signal H5. The gate of the fourteenth PMOS transistor P14 is used to receive the dead-time detection signal H3. The drain of the fourteenth PMOS transistor P14 is connected to ground. The source of the fifteenth PMOS transistor P15 is connected to the second terminal of the twelfth resistor R12. The gate and drain of the fifteenth PMOS transistor P15 are connected to ground.

8. The automatic dead-time control circuit according to claim 1, characterized in that, The dead-time signal generation module (51) includes a ninth inverter U9, a nineteenth inverter U19, a twelfth D flip-flop, and a twenty-second D flip-flop; wherein, the input terminal of the ninth inverter U9 receives the high-side dead-time comparison signal H4, the output terminal of the ninth inverter U9 is connected to the CP input terminal of the twelfth D flip-flop U12, the RN input terminal of the twelfth D flip-flop U12 is used to receive the clock input signal CLKin, the D input terminal of the twelfth D flip-flop U12 is connected to the power supply terminal VDD, and the output terminal of the twelfth D flip-flop U12 is used to output the high-side dead-time signal DTH; the input terminal of the nineteenth inverter U19 is used to receive the low-side dead-time comparison signal H5, the output terminal of the nineteenth inverter U19 is connected to the CP input terminal of the twenty-second D flip-flop U22, the RN input terminal of the twenty-second D flip-flop U22 is used to receive the clock input signal CLKin, the D input terminal of the twenty-second D flip-flop U22 is connected to the power supply terminal VDD, and the output terminal of the twenty-second D flip-flop U22 is used to output the low-side dead-time signal DTL.

9. The automatic dead-time control circuit according to claim 1, characterized in that, The logic combination module (52) includes a seventh OR gate U7 and a fifteenth OR gate U15; wherein, the first input terminal of the seventh OR gate U7 is used to receive the high-side dead-time control signal H1, the second input terminal of the seventh OR gate U7 is used to receive the high-side dead-time signal DTH, and the output terminal of the seventh OR gate U7 is used to output the high-side drive signal H2; the first input terminal of the fifteenth OR gate U15 is used to receive the low-side dead-time control signal L1, the second input terminal of the fifteenth OR gate U15 is used to receive the low-side dead-time signal DTL, and the output terminal of the fifteenth OR gate U15 is used to output the low-side drive signal L2.

10. An LLC resonant converter, characterized in that, Includes the automatic dead-time control circuit as described in any one of claims 1-9.

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