Differential slope analog-to-digital conversion device
By using a differential slope analog-to-digital converter, the differential operation mode allows the comparator circuit to receive slope voltages with opposite positive and negative slopes, solving the problem of high design complexity in slope analog-to-digital converters and achieving more efficient signal conversion.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- REALTEK SEMICON CORP
- Filing Date
- 2024-11-04
- Publication Date
- 2026-05-08
AI Technical Summary
In slope analog-to-digital conversion devices, if the time it takes for the slope signal to rise to a specific level is too short, the required slope will increase significantly, increasing the design complexity of the slope signal generation circuit.
A differential slope analog-to-digital converter is adopted. Through differential operation, the comparator circuit receives slope voltages with opposite positive and negative slopes. The positive and negative slope voltages are fed in by the first and second capacitors during the staggered sampling and feeding time, which reduces the design complexity of the slope voltage generation circuit.
With the increase of the equivalent slope, the analog input signals are made to approach each other, which reduces the design complexity of the ramp voltage generation circuit and improves the conversion efficiency.
Smart Images
Figure CN122001379A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to analog-to-digital conversion technology, and more particularly to a differential slope analog-to-digital conversion device. Background Technology
[0002] An analog-to-digital converter (ADC) is a device used to convert a continuous signal in analog form into a discrete signal in digital form. ADCs can be implemented in different ways; one type is the slope analog-to-digital converter (ADC), which generates a digital signal by comparing the input signal with a slope signal and counting the results.
[0003] However, in slope analog-to-digital conversion devices, if the time required for the ramp signal to climb to a specific level is too short, the required slope will increase significantly, thereby increasing the design complexity of the ramp signal generation circuit. Summary of the Invention
[0004] In view of the problems of the prior art, one object of the present invention is to provide a differential slope analog-to-digital conversion device to improve the prior art.
[0005] This invention includes a differential slope analog-to-digital converter, comprising: a first capacitor, a second capacitor, a ramp voltage generation circuit, and a comparator circuit. The first capacitor is configured to sample a pair of analog input signals during a sampling time. The second capacitor is configured to sample the pair of analog input signals during the sampling time. The ramp voltage generation circuit is configured to feed a positive ramp voltage to the first capacitor according to a first positive ramp and a negative ramp voltage to the second capacitor according to a first negative ramp during a first feed time, and to feed a positive ramp voltage to the second capacitor according to a second positive ramp and a negative ramp voltage to the first capacitor according to a second negative ramp during a second feed time, wherein the first and second feed times are sequentially interleaved with the sampling time. The comparator circuit is configured to receive a first voltage from the first capacitor and a second voltage from the second capacitor during the first and second feed times and compare them to generate a comparison result. A counting circuit is configured to count based on the comparison result to generate a digital output signal.
[0006] The present invention further includes a differential slope analog-to-digital conversion method, comprising: sampling a first capacitor according to a pair of analog input signals during a sampling time; sampling a second capacitor according to the pair of analog input signals during a sampling time; feeding a slope voltage generation circuit to the first capacitor with a positive slope voltage according to a first positive slope and to the second capacitor with a negative slope voltage according to a first negative slope during a first feed-in time; feeding the second capacitor with a positive slope voltage according to a second positive slope and to the first capacitor with a negative slope voltage according to a second negative slope during a second feed-in time, wherein the first feed-in time and the second feed-in time are alternately performed with the sampling time; comparing a first voltage from the first capacitor and a second voltage from the second capacitor during the first feed-in time and the second feed-in time to generate a comparison result; and counting a circuit counting according to the comparison result to generate a digital output signal.
[0007] Regarding the features, implementation, and effects of this case, the preferred embodiments are described in detail below with reference to the drawings. Attached Figure Description
[0008] [ Figure 1A ]to[ Figure 1C The diagram shows a circuit diagram of a differential slope analog-to-digital converter at different operating times in one embodiment of the present invention.
[0009] [ Figure 2 [This shows one embodiment of the present invention, with] Figures 1A to 1C The signal waveform diagram related to the operation of the differential slope analog-to-digital converter;
[0010] [ Figure 3 [This shows one embodiment of the present invention,] Figures 1A to 1C Waveforms of the first connection voltage at the first connection point, the second connection voltage at the second connection point, the first voltage at the second terminal of the first capacitor, and the second voltage at the second terminal of the second capacitor; and
[0011] [ Figure 4 The image shows a flowchart of a differential slope analog-to-digital conversion method according to an embodiment of the present invention. Detailed Implementation
[0012] One objective of this invention is to provide a differential slope analog-to-digital converter, which uses a differential operation mode to allow the comparator circuit to receive slope voltages with opposite positive and negative slopes, thereby achieving the effect of making the analog input signals approach each other with an increase in equivalent slope, and reducing the design complexity of the slope voltage generation circuit.
[0013] Please refer to Figures 1A to 1C . Figures 1A to 1CThis diagram shows a circuit diagram of a differential slope analog-to-digital conversion (ADC) device 100 at different operating times, according to one embodiment of the present invention.
[0014] like Figures 1A to 1C As shown, the differential slope analog-to-digital converter 100 includes: a first capacitor C1, a second capacitor C2, a ramp voltage generation circuit 110, a comparator circuit 120, and a counting circuit 130.
[0015] The differential slope analog-to-digital converter 100 may further include a first input switch 140A, a second input switch 140B, a third input switch 140C, a fourth input switch 140D, a first feed switch 150A, a second feed switch 150B, a first draw switch 155A, a second draw switch 155B, a first connection switch 160A, a second connection switch 160B, a first comparison switch 170A, and a second comparison switch 170B.
[0016] In the aforementioned switches, the first input switch 140A, the second input switch 140B, the third input switch 140C, and the fourth input switch 140D are controlled by the reset signal RES to be turned on only when the reset signal RES is in the first state and turned off when the reset signal RES is in the second state.
[0017] The first feed switch 150A and the second draw switch 155B are controlled by the first feed signal FS1 to be turned on only when the first feed signal FS1 is in a first state and turned off when the first feed signal FS1 is in a second state.
[0018] The second feed switch 150B and the first draw switch 155A are controlled by the second feed signal FS2 to be turned on only when the second feed signal FS2 is in the first state and turned off when the second feed signal FS2 is in the second state.
[0019] The first connection switch 160A, the second connection switch 160B, the first comparison switch 170A, and the second comparison switch 170B are simultaneously controlled by the first feed signal FS1 and the second feed signal FS2, so that they are turned on when either the first feed signal FS1 or the second feed signal FS2 is in a first state, and turned off when both the first feed signal FS1 and the second feed signal FS2 are in a second state.
[0020] In one embodiment, the first state is a high state, the second state is a low state, and Figures 1A to 1C The first state, indicated by 1, is a high state, and the second state, indicated by 0, is a low state, as indicated by the label next to each signal. However, the invention is not limited to this.
[0021] Under the control mechanism of the above signals, each switch can, through different combinations of being on and off during different working times, enable the first capacitor C1, the second capacitor C2, the ramp voltage generation circuit 110, and the comparator circuit 120 to form a [structure / function]. Figures 1A to 1C Different connection relationships.
[0022] Please refer to the following at the same time Figure 2 . Figure 2 This illustrates one embodiment of the present invention, with Figures 1A to 1C The signal waveform diagram related to the operation of the differential slope analog-to-digital converter 100.
[0023] To be more detailed, Figure 2 The states of the reset signal RES, the first feed signal FS1, and the second feed signal FS2 are plotted at sampling time TS, first feed time TF1, and second feed time TF2. Figure 2 As shown, the first feed time TF1 and the second feed time TF2 are alternated with the sampling time TS in sequence. More specifically, the above times can be arranged alternately in the order of sampling time TS, first feed time TF1, sampling time TS, and second feed time TF2, and can be carried out periodically.
[0024] The following will be paired Figures 1A to 1C as well as Figure 2 The detailed structure of the differential slope analog-to-digital converter 100 is described sequentially, along with its operation at sampling time TS, first feed time TF1, and second feed time TF2. Specifically, in... Figures 1A to 1C The switches that are turned on at each time point and the paths that are enabled by the switches are represented by thick lines.
[0025] like Figure 1A As shown, during the sampling time TS, the reset signal RES is in the first state (high state), the first feed signal FS1 is in the second state (low state), and the second feed signal FS2 is in the second state (low state).
[0026] The first capacitor C1 is configured to sample a pair of analog input signals AN1, AN2 during the sampling time TS. The second capacitor C2 is configured to sample the analog input signals AN1, AN2 during the sampling time TS. In different embodiments, the analog input signals AN1, AN2 may be a pair of AC signals, or may include one AC signal and one DC signal.
[0027] More specifically, according to the reset signal RES for the first state, the first input switch 140A is configured to be turned on during the sampling time TS, inputting the first analog input signal (e.g., analog input signal AN1) of the analog input signals AN1 and AN2 to the first terminal of the first capacitor C1. The second input switch 140B is configured to be turned on during the sampling time TS, inputting the second analog input signal (e.g., analog input signal AN2) of the analog input signals AN1 and AN2 to the second terminal of the first capacitor C1.
[0028] The third input switch 140C is configured to be turned on during the sampling time TS, inputting the second analog input signal (e.g., analog input signal AN2) to the first terminal of the second capacitor C2. The fourth input switch 140D is configured to be turned on during the sampling time TS, inputting the first analog input signal (e.g., analog input signal AN1) to the second terminal of the second capacitor C2.
[0029] Conversely, the first feed signal FS1 and the second feed signal FS2, which are in the second state during the sampling time TS, turn off the first connection switch 160A, the second connection switch 160B, the first comparison switch 170A, and the second comparison switch 170B, thereby electrically isolating the two sides of the first capacitor C1 and the second capacitor C2 from other circuits.
[0030] Therefore, the operation of these switches can achieve the purpose of enabling the first capacitor C1 and the second capacitor C2 to sample the analog input signals AN1 and AN2.
[0031] like Figure 1B As shown, during the first feed time TF1, the reset signal RES is in the second state (low state), the first feed signal FS1 is in the first state (high state), and the second feed signal FS2 is in the second state (low state).
[0032] When the reset signal RES is in the second state during the first feed-in time TF1, the first input switch 140A, the second input switch 140B, the third input switch 140C, and the fourth input switch 140D are closed, thereby stopping the analog input signals AN1 and AN2 from being input to the first capacitor C1 and the second capacitor C2. At this time, the first capacitor C1 and the second capacitor C2 stop sampling the analog input signals AN1 and AN2.
[0033] The ramp voltage generating circuit 110 is configured to feed a positive slope voltage to the first capacitor C1 according to a first positive slope and to feed a negative slope voltage to the second capacitor C2 according to a first negative slope during the first feed time TF1.
[0034] In one embodiment, the ramp voltage generating circuit 110 includes a first current feed circuit 180A, a second current feed circuit 180B, a first current draw circuit 190A, and a second current draw circuit 190B. Figures 1A to 1C In the diagram, the first current feed circuit 180A, the second current feed circuit 180B, the first current draw circuit 190A, and the second current draw circuit 190B are each drawn as a current source.
[0035] Based on the first feed signal FS1 in the first state, the first feed switch 150A is configured to conduct only during the first feed time TF1, electrically coupling the first current feed circuit 180A to the first connection point T1. The first connection switch 160A is configured to conduct during the first feed time TF1, electrically coupling the first connection point T1 to the first terminal of the first capacitor C1. Therefore, the first current feed circuit 140A is configured to be electrically coupled to the first capacitor C1 only during the first feed time TF1 to provide a positive slope voltage feed for the current fed into the first capacitor C1.
[0036] Based on the first feed signal FS1 in the first state, the second draw switch 155B is configured to conduct only during the first feed time TF1, electrically coupling the second current draw circuit 190B to the second connection point T2. The second connection switch 160B is configured to conduct during the first feed time TF1, electrically coupling the second connection point T2 to the first terminal of the second capacitor C2. Therefore, the second current draw circuit 190B is configured to be electrically coupled to the second capacitor C2 only during the first feed time TF1, to draw current from the second capacitor C2 for a negative slope voltage feed.
[0037] According to the second feed signal FS2 in the second state, the second feed switch 150B and the first draw switch 155A are closed, so that the first connection point T1 and the second connection point T2 are electrically isolated from the second current feed circuit 180B and the first current draw circuit 190A, respectively.
[0038] Based on the first feed signal FS1 in the first state, the first comparator switch 170A is configured to be turned on during the first feed time TF1, so that the comparator circuit 120 is electrically coupled to the second terminal of the first capacitor C1. The second comparator switch 170B is configured to be turned on during the first feed time TF1, so that the comparator circuit 120 is electrically coupled to the second terminal of the second capacitor C2.
[0039] According to the above operation, the first terminal of the first capacitor C1 is electrically coupled to the ramp voltage generating circuit 110 at the first feed-in time TF1, so that the ramp voltage generating circuit 110 feeds in a positive slope voltage according to the first positive slope. The first terminal of the second capacitor C1 is electrically coupled to the ramp voltage generating circuit 110 at the first feed-in time TF1, so that the ramp voltage generating circuit 110 feeds in a negative slope voltage according to the first negative slope.
[0040] The second terminals of both the first capacitor C1 and the second capacitor C1 are electrically coupled to the comparator circuit 120. Therefore, the comparator circuit 120 is configured to receive and compare a first voltage VS1 from the first capacitor C1 and a second voltage VS2 from the second capacitor C2 during the first feed-in time TF1 to generate a comparison result COUT.
[0041] like Figure 1C As shown, during the second feed time TF2, the reset signal RES is in the second state (low state), the first feed signal FS1 is in the second state (low state), and the second feed signal FS2 is in the first state (high state).
[0042] During the second feed time TF2, the reset signal RES in the second state causes the first input switch 140A, the second input switch 140B, the third input switch 140C, and the fourth input switch 140D to close, thereby stopping the analog input signals AN1 and AN2 from being input to the first capacitor C1 and the second capacitor C2. At this time, the first capacitor C1 and the second capacitor C2 stop sampling the analog input signals AN1 and AN2.
[0043] The ramp voltage generating circuit 110 is configured to feed a positive slope voltage to the second capacitor C2 according to the second positive slope and to feed a negative slope voltage to the first capacitor C1 according to the second negative slope during the second feed time TF2.
[0044] Based on the second feed signal FS2 in the first state, the second feed switch 150B is configured to conduct only during the second feed time TF2, electrically coupling the second current feed circuit 180B to the second connection point T2. The second connection switch 160B is configured to conduct during the second feed time TF2, electrically coupling the second connection point T2 to the first terminal of the second capacitor C1. Therefore, the second current feed circuit 180B is configured to be electrically coupled to the second capacitor C2 only during the second feed time TF2, to provide a positive slope voltage feed for the current fed into the second capacitor C2.
[0045] Based on the second feed signal FS2 in the first state, the first draw switch 155A is configured to conduct only during the second feed time TF2, electrically coupling the first current draw circuit 190A to the first connection point T1. The first connection switch 160A is configured to conduct during the second feed time TF2, electrically coupling the first connection point T1 to the first terminal of the first capacitor C1. Therefore, the first current draw circuit 190A is configured to be electrically coupled to the first capacitor C1 only during the second feed time TF2, to draw current from the first capacitor C1 for a negative slope voltage feed.
[0046] According to the first feed signal FS1 in the second state, the first feed switch 150A and the second draw switch 155B are closed, so that the first connection point T1 and the second connection point T2 are electrically isolated from the first current feed circuit 180A and the second current draw circuit 190B, respectively.
[0047] Based on the second feed signal FS2 in the first state, the first comparator switch 170A is configured to turn on during the second feed time TF2, so that the comparator circuit 120 is electrically coupled to the second terminal of the first capacitor C1. The second comparator switch 170B is configured to turn on during the second feed time TF2, so that the comparator circuit 120 is electrically coupled to the second terminal of the second capacitor C2.
[0048] According to the above operation, the first terminal of the first capacitor C1 is electrically coupled to the ramp voltage generating circuit 110 at the second feed time TF2, so that the ramp voltage generating circuit 110 feeds in a negative slope voltage according to the second negative slope. The first terminal of the second capacitor C1 is electrically coupled to the ramp voltage generating circuit 110 at the second feed time TF2, so that the ramp voltage generating circuit 110 feeds in a positive slope voltage according to the second positive slope.
[0049] The second terminals of both the first capacitor C1 and the second capacitor C1 are electrically coupled to the comparator circuit 120. Therefore, the comparator circuit 120 is configured to receive and compare the first voltage VS1 from the first capacitor C1 and the second voltage VS2 from the second capacitor C2 during the second feed-in time TF2 to generate a comparison result COUT.
[0050] In one embodiment, the comparator circuit 120 compares voltages by subtracting a first voltage VS1 from a second voltage VS2.
[0051] Please refer to Figure 3 . Figure 3 This illustrates one embodiment of the present invention. Figures 1A to 1CThe waveforms of the first connection voltage VT1 at the first connection point T1, the second connection voltage VT2 at the second connection point T2, the first voltage VS1 at the second terminal of the first capacitor C1, and the second voltage VS2 at the second terminal of the second capacitor C2 are shown. The first connection voltage VT1 and the second connection voltage VT2 are plotted independently on different axes, while the first voltage VS1 and the second voltage VS2 are plotted together on one axis.
[0052] The following will correspond Figure 3 This explains the changes of the above voltages at sampling time TS, first feed time TF1, and second feed time TF2.
[0053] During the sampling time TS, since the first feed switch 150A, the second feed switch 150B, the first draw switch 155A, the second draw switch 155B, the first connection switch 160A, the second connection switch 160B, the first comparator switch 170A, and the second comparator switch 170B are all closed, the nodes corresponding to the first connection voltage VT1, the second connection voltage VT2, the first voltage VS1, and the second voltage VS2 are in a floating state. These voltages are all in an unknown state (don't care), and... Figure 3 The area is represented by dots.
[0054] During the first feed-in time TF1, both the first connection voltage VT1 and the first voltage VS1 will increase according to the first positive slope due to the positive slope voltage feed-in corresponding to the first capacitor C1. The second connection voltage VT2 and the second voltage VS2 will decrease according to the first negative slope due to the negative slope voltage feed-in corresponding to the second capacitor C2. When the comparator circuit 120 compares the first voltage VS1 and the second voltage VS2 by subtracting them, the voltage adjustment is equivalent to applying a voltage adjustment to the result of this subtraction based on the first slope corresponding to the subtraction of the first positive slope and the first negative slope.
[0055] During the second feed-in time TF2, both the first connection voltage VT1 and the first voltage VS1 will decrease according to the second negative slope due to the negative slope voltage feed-in corresponding to the first capacitor C1. Conversely, both the second connection voltage VT2 and the second voltage VS2 will increase according to the second positive slope due to the positive slope voltage feed-in corresponding to the second capacitor C2. When the comparator circuit 120 compares the first voltage VS1 and the second voltage VS2 by subtracting them, the voltage adjustment is equivalent to adjusting the voltage based on the second slope obtained by subtracting the second negative slope from the second positive slope.
[0056] In one embodiment, the absolute values of the first positive slope, the second positive slope, the first negative slope, and the second negative slope are all equal to a single slope value, so that the comparator circuit 120 effectively receives a ramp voltage with twice the slope value. However, the invention is not limited thereto.
[0057] The counting circuit 130 is configured to count based on the comparison result COUT to generate a digital output signal DOUT. In one embodiment, the counting circuit 130 is configured at the time point when the first voltage VS1 and the second voltage VS2 cross, for example... Figure 3 The counting is completed at time point TC1 in the first feed time TF1 and time point TC2 in the second feed time TF2, and the counting result is output as a digital output signal DOUT.
[0058] In analog-to-digital converters that generate digital signals by comparing and counting input signals with ramp signals, if the time required for the ramp signal to climb to a specific level is too short, the required slope will increase significantly, increasing the design complexity of the ramp signal generation circuit.
[0059] The differential slope analog-to-digital converter of the present invention uses a differential operation mode to allow the comparator circuit to receive slope voltages with opposite positive and negative slopes, thereby achieving the effect of making the analog input signals approach each other with the increase of the equivalent slope, and reducing the design complexity of the slope voltage generation circuit.
[0060] Please refer to Figure 4 . Figure 4 This diagram shows a flowchart of a differential slope analog-to-digital conversion method 400 according to an embodiment of the present invention.
[0061] In addition to the aforementioned apparatus, the present invention further discloses a differential slope analog-to-digital conversion method 400, applicable to, for example, but not limited to, the differential slope analog-to-digital conversion apparatus 100 of FIG. 1. One embodiment of the differential slope analog-to-digital conversion method 400 is, for example... Figure 4 As shown, it includes the following steps.
[0062] In step S410, the first capacitor C1 is sampled according to the analog input signals AN1 and AN2 during the sampling time TS.
[0063] In step S420, the second capacitor C2 is sampled according to the analog input signals AN1 and AN2 during the sampling time TS.
[0064] In step S430, the ramp voltage generating circuit 110 feeds a positive slope voltage to the first capacitor C1 according to the first positive slope and a negative slope voltage to the second capacitor C2 according to the first negative slope during the first feed time TF1.
[0065] In step S440, the ramp voltage generating circuit 110 feeds a positive slope voltage to the second capacitor C2 according to the second positive slope and a negative slope voltage to the first capacitor C1 according to the second negative slope during the second feed time TF2, wherein the first feed time TF1 and the second feed time TF2 are alternated with the sampling time TS in sequence.
[0066] In step S450, the comparison circuit 120 receives the first voltage VS1 from the first capacitor C1 and the second voltage VS2 from the second capacitor C2 during the first feed time TF1 and the second feed time TF2, and compares them to generate a comparison result COUT.
[0067] In step S460, the counting circuit 130 counts according to the comparison result COUT to generate a digital output signal DOUT.
[0068] It should be noted that the above-described implementation is merely an example. In other embodiments, those skilled in the art can make modifications without departing from the spirit of the invention. For example, the method in the above embodiment of using a switch paired with corresponding control timing to turn on and off, thereby enabling the differential slope analog-to-digital converter to sample the analog input signal and feed in the ramp voltage, is only an example. In other embodiments, other mechanisms, other switch configurations, and other timing control mechanisms can be used to sample the analog input signal and feed in the ramp voltage. The present invention is not limited to a specific circuit architecture.
[0069] In summary, the differential slope analog-to-digital converter of the present invention uses a differential operation mode to allow the comparator circuit to receive slope voltages with opposite positive and negative slopes, thereby achieving the effect of making the analog input signals approach each other with an increase in equivalent slope, and reducing the design complexity of the slope voltage generation circuit.
[0070] Although the embodiments of this case are described above, these embodiments are not intended to limit this case. Those skilled in the art can make changes to the technical features of this case based on the explicit or implicit content of this case. All such changes may fall within the scope of patent protection sought in this case. In other words, the scope of patent protection in this case shall be determined by the scope of the patent application in this specification.
[0071] Symbol Explanation
[0072] 100: Differential slope analog-to-digital converter
[0073] 110: Ramp Voltage Generation Circuit
[0074] 120: Comparator Circuit
[0075] 130: Counting circuit
[0076] 140A: First input switch
[0077] 140B: Second Input Switch
[0078] 140C: Third Input Switch
[0079] 140D: Fourth Input Switch
[0080] 150A: First feeder switch
[0081] 150B: Second feeder switch
[0082] 155A: First draw switch
[0083] 155B: Second draw switch
[0084] 160A: First connection switch
[0085] 160B: Second connection switch
[0086] 170A: First Comparator Switch
[0087] 170B: Second Comparator Switch
[0088] 180A: First current feed circuit
[0089] 180B: Second current feed circuit
[0090] 190A: First current draw circuit
[0091] 190B: Second Current Draw Circuit
[0092] 400: Differential Slope Analog-to-Digital Conversion Method
[0093] S410~S460: Steps
[0094] AN1, AN2: Analog input signals
[0095] C1: First capacitor
[0096] C2: Second capacitor
[0097] COUT: Comparison results
[0098] DOUT: Digital output signal
[0099] FS1: First feed signal
[0100] FS2: Second feed signal
[0101] RES: Reset signal
[0102] T1: First connection point
[0103] T2: Second connection point
[0104] TC1: Time Point
[0105] TC2: Time Point
[0106] TF1: First Feed Time
[0107] TF2: Second Feed Time
[0108] TS: Sampling time
[0109] VS1: First voltage
[0110] VS2: Second voltage
[0111] VT1: First connection voltage
[0112] VT2: Second connection voltage
Claims
1. A differential slope analog-to-digital converter, comprising: A first capacitor is configured to sample a pair of analog input signals during a sampling time; A second capacitor is configured to sample the pair of analog input signals during the sampling time; A ramp voltage generating circuit, configured with: During a first feed-in time, a positive slope voltage is fed into the first capacitor according to a first positive slope, and a negative slope voltage is fed into the second capacitor according to a first negative slope; and During a second feed-in time, the second capacitor is fed with a positive slope voltage according to a second positive slope, and the first capacitor is fed with a negative slope voltage according to a second negative slope, wherein the first feed-in time and the second feed-in time are alternated with the sampling time in sequence. A comparator circuit configured to receive and compare a first voltage from a first capacitor and a second voltage from a second capacitor during the first feed time and the second feed time, to generate a comparison result; and A counting circuit configured to count based on the comparison result to generate a digital output signal.
2. The differential slope analog-to-digital converter as described in claim 1, further comprising: A first input switch is configured to input a first analog input signal of the pair of analog input signals to a first terminal of the first capacitor during the sampling time, wherein the first terminal of the first capacitor is electrically coupled to the ramp voltage generating circuit during the first feed time and the second feed time. A second input switch is configured to input a second analog input signal of the pair of analog input signals to a second terminal of the first capacitor during the sampling time, wherein the second terminal of the first capacitor is electrically coupled to the comparator circuit during the first feed time and the second feed time. A third input switch, configured to input the second analog input signal to a first terminal of the second capacitor during the sampling time, wherein the first terminal of the second capacitor is electrically coupled to the ramp voltage generation circuit during the first feed time and the second feed time; and A fourth input switch is configured to input the first analog input signal to a second terminal of the second capacitor during the sampling time, wherein the second terminal of the second capacitor is electrically coupled to the comparator circuit during the first feed time and the second feed time.
3. The differential slope analog-to-digital converter as claimed in claim 1, wherein the slope voltage generation circuit further comprises: A first current feed circuit is configured to be electrically coupled to the first capacitor only during the first feed time, so as to feed the positive slope voltage into the first capacitor feed current. A second current feed circuit is configured to be electrically coupled to the second capacitor only during the second feed time, so as to feed the positive slope voltage into the second capacitor feed current. A first current-drawing circuit, configured to be electrically coupled to the first capacitor only during the second feed time, to draw current from the first capacitor for the negative slope voltage feed; and A second current-drawing circuit is configured to be electrically coupled to the second capacitor only during the first feed time, so as to draw current from the second capacitor to feed the negative slope voltage.
4. The differential slope analog-to-digital converter as described in claim 3, further comprising: A first feed switch is configured to electrically couple the first current feed circuit to a first connection point only during the first feed time. A second feed switch is configured to electrically couple the second current feed circuit to a second connection point only during the second feed time. A first draw-in switch is configured to electrically couple the first current draw-in circuit to the first connection point only during the second feed-in time; A second draw-in switch is configured to electrically couple the second current draw-in circuit to the second connection point only during the first feed-in time; A first connection switch, configured to electrically couple the first connection point to a first terminal of the first capacitor during the first feed time and the second feed time; and A second connection switch is configured to electrically couple the second connection point to a first terminal of the second capacitor during the first feed time and the second feed time.
5. The differential slope analog-to-digital converter as described in claim 4, further comprising: A first comparator switch, configured to electrically couple the comparator circuit to a second terminal of the first capacitor during the first feed time and the second feed time; and A second comparator switch is configured to electrically couple the comparator circuit to a second terminal of the second capacitor during the first feed time and the second feed time.
6. The differential slope analog-to-digital converter as claimed in claim 1, wherein the pair of analog input signals is a pair of AC signals.
7. The differential slope analog-to-digital converter as claimed in claim 1, wherein the pair of analog input signals comprises an AC signal and a DC signal.
8. The differential slope analog-to-digital converter of claim 1, wherein the comparator circuit performs a comparison by subtracting the first voltage from the second voltage to perform a voltage adjustment at the first feed time equivalent to a first slope corresponding to the subtraction of the first positive slope and the first negative slope, and at the second feed time equivalent to a second slope corresponding to the subtraction of the second negative slope and the second positive slope.
9. A differential slope analog-to-digital conversion method, comprising: A first capacitor is sampled according to a pair of analog input signals during a sampling time; A second capacitor is used to sample the analog input signal during the sampling time. A ramp voltage generating circuit feeds a positive slope voltage to the first capacitor according to a first positive slope and a negative slope voltage to the second capacitor according to a first negative slope during a first feed-in time. The ramp voltage generating circuit feeds a positive slope voltage to the second capacitor according to a second positive slope and a negative slope voltage to the first capacitor according to a second negative slope during a second feed-in time, wherein the first feed-in time and the second feed-in time are alternated with the sampling time in sequence. A comparator circuit receives a first voltage from the first capacitor and a second voltage from the second capacitor during the first feed time and the second feed time, and compares them to generate a comparison result; and A counting circuit is made to count based on the comparison result to generate a digital output signal.
10. The differential slope analog-to-digital conversion method as described in claim 9, further comprising: The comparator circuit performs a comparison by subtracting the first voltage from the second voltage to adjust the voltage at the first feed time based on a first slope corresponding to the subtraction of the first positive slope and the first negative slope, and at the second feed time based on a second slope corresponding to the subtraction of the second negative slope and the second positive slope.