Manufacturing method of metal gate 1.5 T structure SONOS (Silicon Oxide Nitride Oxide Semiconductor) memory

Abstract

The invention discloses a manufacturing method of a metal grid 1.5 T structure SONOS memory. A selection tube and a storage tube adopt the same storage unit grid polycrystalline silicon layer; when the pseudo polycrystalline silicon is removed, a storage unit grid electrode lamination layer in a storage tube grid electrode region is removed through a photomask, a storage unit grid electrode lamination layer in a selection tube grid electrode region is reserved, a semiconductor substrate below the storage tube grid electrode region is exposed, a storage tube grid electrode structure groove is formed, and then an ONO layer is deposited. Enabling the ONO layer to cover the bottom and the side wall of the storage tube gate structure groove to form a storage tube gate groove, depositing a first gate metal layer on the ONO layer, and performing chemical mechanical polishing to form a storage tube metal gate. According to the invention, a metal gate 1.5 T structure SONOS memory with a smaller size can be formed, and a few photomasks are needed.

Description

Technical Field

[0001] This invention relates to semiconductor manufacturing technology, and in particular to a method for manufacturing a SONOS memory with a 1.5T metal gate structure. Background Technology

[0002] In semiconductor integrated circuits, flash memory is widely used in consumer electronics products such as mobile phones and digital cameras, as well as portable systems, due to its non-volatile characteristics. Non-volatile memory technologies mainly include floating gate technology, split gate technology, and SONOS (Silicon-Oxide-Nitride-Oxide-Silicon) technology. SONOS-type flash memory is widely used due to its advantages such as simple process, low operating voltage, high data reliability, and ease of integration into standard CMOS processes.

[0003] Traditional SONOS memory cells have a 2T (transistor) structure, consisting of two independently operating transistors: a select gate (SG) and a memory gate (MG). The memory gate uses an ONO (SiO2-Si3N4-SiO2) layer as its gate dielectric, storing charge within the Si3N4 layer. In contrast, the 1.5T SONOS memory cell has two transistors arranged close together, significantly reducing the cell area compared to the 2T structure. However, it requires two layers of polysilicon gates, necessitating two polysilicon deposition (poly DEP) processes, adding extra photomasks and processes, thus increasing the manufacturing complexity. With advancements in technology nodes, starting from 28nm, logic process technology has transitioned to metal gate processes, making the fabrication of the 1.5T even more complex.

[0004] The current mainstream manufacturing method for SONOS memory with a 1.5T structure is as follows: after depositing the first layer of gate polysilicon, the gate of one of the devices in the SONOS memory cell is first etched, which can be a select transistor or a storage transistor. Then, the gate dielectric of the other device and the peripheral logic devices of the memory (such as core devices and input / output devices) is fabricated. Next, a second layer of polysilicon is deposited, and the gate of the peripheral logic devices of the memory is fabricated using the second layer of polysilicon. The gate of the other device is also formed using the second layer of polysilicon, thus completing the manufacturing of the SONOS memory with a 1.5T structure.

[0005] As mentioned above, after completing the first device in the 1.5T SONOS memory cell, in order to correctly form the gate dielectric of the second device and the peripheral logic device, and to correctly form the shape of the second gate during the etching of the second layer of polysilicon gate, additional photomasks and processes are required, which increases the process complexity and cost. Furthermore, the formation process of the 1.5T SONOS memory cell and the logic device manufacturing process will affect each other, thereby affecting the device performance. Summary of the Invention

[0006] The technical problem to be solved by the present invention is to provide a method for manufacturing a SONOS memory with a 1.5T metal gate structure, which can form a smaller SONOS memory with a 1.5T metal gate structure and requires fewer photomasks.

[0007] To solve the above-mentioned technical problems, the present invention provides a method for manufacturing a SONOS memory with a 1.5T metal gate structure, which includes the following steps;

[0008] S1. A semiconductor substrate 100 is provided, wherein the semiconductor substrate 100 has a logic device active region 102 and a SONOS memory cell active region 103 separated by shallow trench isolation 110;

[0009] S2. A gate oxide layer 130 is formed on a semiconductor substrate;

[0010] S3. Deposit a gate polysilicon layer 140 on the gate oxide layer 130;

[0011] S4. Photolithography: Define the gate region of the memory cell in the active region 103 of the SONOS memory cell, and define the gate region of the logic device in the active region 102 of the logic device;

[0012] Etching stops on the semiconductor substrate 100 and the shallow trench isolation 110, removing the gate polysilicon layer 140 and gate oxide layer 130 outside the gate region of the memory cell and the gate region of the logic device. A memory cell gate stack is formed on the semiconductor substrate 100 of the memory cell gate region, and a logic device gate stack is formed on the semiconductor substrate 100 of the logic device gate region. The memory cell gate stack consists of a memory cell gate oxide layer 131 and a memory cell gate polysilicon layer 141 stacked from bottom to top, and the logic device gate stack consists of a logic device gate oxide layer 132 and a logic device gate polysilicon layer 142 stacked from bottom to top.

[0013] S5. An interlayer dielectric layer 120 covering the semiconductor substrate 100 is formed, and then chemical mechanical polishing is performed to expose the upper surfaces of the memory cell gate polysilicon layer 141 and the logic device gate polysilicon layer 142.

[0014] S6. Photolithography, defining the left and right adjacent select transistor gate regions and memory transistor gate regions in the gate region of the memory cell;

[0015] Etching stops on the semiconductor substrate 100, removing the memory cell gate stack in the gate region of the memory transistor while retaining the memory cell gate stack in the gate region of the select transistor, exposing the semiconductor substrate 100 under the gate region of the memory transistor, and forming a memory transistor gate structure trench 181.

[0016] S7. An ONO layer 150 is deposited on a silicon wafer, such that the ONO layer 150 covers the bottom and sidewalls of the gate structure trench 181 of the memory tube to form a gate trench 182 of the memory tube. The ONO layer 150 also covers the exposed gate polysilicon layer 141 of the memory cell and the upper surface of the gate polysilicon layer 142 of the logic device.

[0017] S8. Deposit a first gate metal layer 161 on the ONO layer 150;

[0018] S9. Perform chemical mechanical polishing to remove the first gate metal layer 161 outside the memory tube gate trench 182, exposing the upper surface of the memory cell gate polysilicon 141 and the upper surface of the logic device gate polysilicon 142 of the remaining select tube gate stack.

[0019] S10. The memory cell gate polysilicon 141 of the memory cell gate stack is removed from the gate region of the select transistor and stops at the gate oxide layer 131 of the memory cell to form the select transistor gate trench 183; and the logic device gate polysilicon 142 is removed and stops at the logic device gate oxide layer 132 to form the logic device gate trench 184.

[0020] S11. Deposit the second gate metal layer 162;

[0021] S12. Perform chemical mechanical polishing to remove the second gate metal layer 162 other than the selector gate trench 183 and the logic device gate trench 184, forming the selector metal gate, the logic device metal gate and the memory gate.

[0022] S13. Perform subsequent processes for SONOS memory cells and logic devices to complete the manufacturing of the 1.5T structure SONOS memory.

[0023] Preferably, in step S1, a trap injection process is performed on the active region to form a P-trap or an N-trap.

[0024] Preferably, the active region 102 of the logic device includes an active region of the core device and an active region of the input / output device.

[0025] Preferably, in step S2, an oxidation process is used to form the gate oxide layer 130;

[0026] Preferably, in step S3, the gate polysilicon layer 140 is formed using a low-pressure chemical vapor deposition process.

[0027] Preferably, in step S7, an ONO layer 150 is deposited using a low-pressure chemical vapor deposition (LPCVD) process or an atomic layer deposition (ALD) method.

[0028] Preferably, the first gate metal layer 161 is AL;

[0029] The second gate metal layer 162 is AL.

[0030] Preferably, in step S4, a memory cell gate stack is formed on the active region 103 of the SONOS memory cell, a logic device gate stack is formed on the active region 102 of the logic device, and then a sidewall 190 is formed on the lateral periphery of the memory cell gate stack and the logic device gate stack.

[0031] Preferably, in step S13, the LDD ion implantation process is performed.

[0032] Preferably, in step S13, an annealing process is performed.

[0033] Preferably, in step S4, hydrofluoric acid (HF) is used to clean away the gate oxide layer 130 outside the gate region of the memory cell and the gate region of the logic device.

[0034] Preferably, after step S6, threshold voltage Vt-adjusted ion implantation is performed on the semiconductor substrate 100 under the exposed gate region of the memory tube, and then step S7 is performed.

[0035] The method for manufacturing a 1.5T metal gate SONOS memory of the present invention involves depositing a gate polysilicon layer 140 on a gate oxide layer 130, then defining a memory cell gate region in the active region 103 of the SONOS memory cell and a logic device gate region in the active region 102 of the logic device by photolithography; then etching away the gate polysilicon layer 140 and the gate oxide layer 130 outside the memory cell gate region and the logic device gate region, forming a memory cell gate stack on the semiconductor substrate 100 of the memory cell gate region, and forming a logic device gate stack on the semiconductor substrate 100 of the logic device gate region, and selecting transistors and... The memory transistor uses the same polysilicon layer 141 for the gate of the same memory cell. During dummy polysilicon removal, a photomask is first used to remove the gate stack of the memory cell in the gate region of the memory transistor while retaining the gate stack of the memory cell in the selector region, exposing the semiconductor substrate 100 under the gate region of the memory transistor to form a gate structure trench 181. Then, an ONO layer 150 is deposited, covering the bottom and sidewalls of the gate structure trench 181 to form a gate trench 182. Finally, a first gate metal layer 161 is deposited on the ONO layer 500 and chemical mechanical polishing (CMP) is performed to form the metal gate of the memory transistor. This method for manufacturing a 1.5T metal gate SONOS memory can form a smaller 1.5T metal gate SONOS memory through process improvements, and can reduce one photomask step compared to the common 2T metal gate SONOS memory manufacturing process. Attached Figure Description

[0036] To more clearly illustrate the technical solution of the present invention, the accompanying drawings used in the present invention will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0037] Figure 1 This is a cross-sectional view of a semiconductor substrate in an embodiment of the manufacturing method of the 1.5T metal gate structure SONOS memory of the present invention;

[0038] Figure 2 This is a cross-sectional view of the gate oxide layer formation in an embodiment of the SONOS memory manufacturing method with a 1.5T metal gate structure according to the present invention;

[0039] Figure 3 This is a cross-sectional view of the deposited gate polysilicon layer in an embodiment of the manufacturing method of the 1.5T metal gate structure SONOS memory of the present invention;

[0040] Figure 4 This is a cross-sectional view of the gate stack of the memory cell in an embodiment of the manufacturing method of the 1.5T metal gate structure SONOS memory of the present invention;

[0041] Figure 5 This is a cross-sectional view of the grinding interlayer dielectric layer in an embodiment of the manufacturing method of the 1.5T metal gate structure SONOS memory of the present invention;

[0042] Figure 6 This is a cross-sectional view of the gate structure trench of the memory tube formed in an embodiment of the manufacturing method of the 1.5T metal gate structure SONOS memory of the present invention;

[0043] Figure 7 This is a cross-sectional view of the deposited ONO layer in an embodiment of the manufacturing method of the 1.5T metal gate structure SONOS memory of the present invention;

[0044] Figure 8 This is a cross-sectional view of the deposition of the first gate metal layer in an embodiment of the manufacturing method of the 1.5T structure SONOS memory with metal gate of the present invention;

[0045] Figure 9 This is a cross-sectional view of the first gate metal layer being ground in an embodiment of the manufacturing method of the 1.5T structure SONOS memory with metal gate of the present invention;

[0046] Figure 10 This is a cross-sectional view of the selected gate trench formed in an embodiment of the manufacturing method of the 1.5T metal gate structure SONOS memory of the present invention;

[0047] Figure 11 This is a cross-sectional view of the deposition of the second gate metal layer in an embodiment of the manufacturing method of the 1.5T structure SONOS memory with metal gate of the present invention;

[0048] Figure 12 This is a cross-sectional view of the metal gate of the select transistor, the metal gate of the logic device, and the metal gate of the memory transistor in an embodiment of the manufacturing method of the 1.5T structure SONOS memory with metal gate of the present invention.

[0049] Explanation of the reference numerals in the figure:

[0050] 100. Semiconductor substrate; 110. Shallow trench isolation; 102. Logic device active region; 103. SONOS memory cell active region; 130. Gate oxide layer; 140. Gate polysilicon layer; 131. Memory cell gate oxide layer; 141. Memory cell gate polysilicon layer; 132. Logic device gate oxide layer; 142. Logic device gate polysilicon layer; 120. Interlayer dielectric layer; 181. Memory transistor gate structure trench; 150. ONO layer; 182. Memory transistor gate trench; 161. First gate metal layer; 183. Selector gate trench; 184. Logic device gate trench; 162. Second gate metal layer; 190. Sidewall. Detailed Implementation

[0051] The technical solutions of the present invention will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative effort are within the scope of protection of the present invention.

[0052] Example 1

[0053] A method for manufacturing a SONOS memory with a 1.5T metal gate structure includes the following steps:

[0054] S1. A semiconductor substrate 100 is provided, wherein the semiconductor substrate 100 has logic device active regions 102 and SONOS memory cell active regions 103 separated by shallow trench isolation 110, such as Figure 1 As shown;

[0055] S2. A gate oxide layer 130 is formed on a semiconductor substrate, such as... Figure 2 As shown;

[0056] S3. Deposit a gate polysilicon layer 140 on the gate oxide layer 130, such as Figure 3 As shown;

[0057] S4. Photolithography: Define the gate region of the memory cell in the active region 103 of the SONOS memory cell, and define the gate region of the logic device in the active region 102 of the logic device;

[0058] Etching stops on the semiconductor substrate 100 and the shallow trench isolation 110, removing the gate polysilicon layer 140 and gate oxide layer 130 outside the gate region of the memory cell and the gate region of the logic device. A memory cell gate stack is formed on the semiconductor substrate 100 of the memory cell gate region, and a logic device gate stack is formed on the semiconductor substrate 100 of the logic device gate region. The memory cell gate stack consists of a memory cell gate oxide layer 131 and a memory cell gate polysilicon layer 141 stacked sequentially from bottom to top, and the logic device gate stack consists of a logic device gate oxide layer 132 and a logic device gate polysilicon layer 142 stacked sequentially from bottom to top. Figure 4 As shown;

[0059] S5. An interlayer dielectric layer 120 is formed over the semiconductor substrate 100, and then chemical mechanical polishing (CMP) is performed to expose the upper surfaces of the memory cell gate polysilicon layer 141 and the logic device gate polysilicon layer 142, such as... Figure 5 As shown;

[0060] S6. Photolithography, defining the left and right adjacent select transistor gate regions and memory transistor gate regions in the gate region of the memory cell;

[0061] Etching stops on the semiconductor substrate 100, removing the memory cell gate stack in the gate region of the memory transistor while retaining the memory cell gate stack in the gate region of the select transistor, exposing the semiconductor substrate 100 under the gate region of the memory transistor, and forming a memory transistor gate structure trench 181, such as... Figure 6 As shown;

[0062] S7. Deposit an ONO (SiO2-Si3N4-SiO2) layer 150 on a silicon wafer, such that the ONO layer 150 covers the bottom and sidewalls of the memory gate structure trench 181 to form the memory gate trench 182. The ONO layer 150 also covers the exposed memory cell gate polysilicon layer 141 and the upper surface of the logic device gate polysilicon layer 142. Figure 7 As shown;

[0063] S8. Deposit a first gate metal layer 161 on the ONO layer 150, such as Figure 8 As shown;

[0064] S9. Perform chemical mechanical polishing to remove the first gate metal layer 161 outside the memory transistor gate trench 182, exposing the upper surface of the remaining select transistor gate stacked memory cell gate polysilicon 141 and the upper surface of the logic device gate polysilicon 142, such as... Figure 9 As shown;

[0065] S10. The gate polysilicon 141 of the memory cell, which is removed from the gate stack of the select transistor gate region, stops at the gate oxide layer 131 of the memory cell, forming a select transistor gate trench 183; and the gate polysilicon 142 of the logic device is removed from the gate oxide layer 132 of the logic device, forming a logic device gate trench 184, as shown. Figure 10 As shown;

[0066] S11. Deposit the second gate metal layer 162, as follows Figure 11 As shown;

[0067] S12. Perform chemical mechanical polishing (CMP) to remove the second gate metal layer 162 outside of the selector gate trench 183 and the logic device gate trench 184, forming the selector metal gate, the logic device metal gate, and the memory transistor metal gate, such as Figure 12 As shown;

[0068] S13. Perform subsequent processes for SONOS memory cells and logic devices to complete the manufacturing of the 1.5T structure SONOS memory.

[0069] The manufacturing method of the SONOS memory with a 1.5T metal gate structure in Example 1 involves depositing a gate polysilicon layer 140 on the gate oxide layer 130, then defining the memory cell gate region in the active region 103 of the SONOS memory cell and the logic device gate region in the active region 102 of the logic device by photolithography; then etching away the gate polysilicon layer 140 and the gate oxide layer 130 outside the memory cell gate region and the logic device gate region, forming a memory cell gate stack on the semiconductor substrate 100 of the memory cell gate region, and forming a logic device gate stack on the semiconductor substrate 100 of the logic device gate region, and selecting the transistor and... The memory transistor uses the same polysilicon layer 141 for the gate of the same memory cell. During dummy polysilicon removal, the memory cell gate stack in the gate region of the memory transistor is removed using a photomask while retaining the gate stack in the selector region, exposing the semiconductor substrate 100 under the gate region of the memory transistor to form a gate structure trench 181. Then, an ONO layer 150 is deposited, covering the bottom and sidewalls of the gate structure trench 181 to form a gate trench 182. Finally, a first gate metal layer 161 is deposited on the ONO layer 500 and chemical mechanical polishing (CMP) is performed to form the metal gate of the memory transistor. The manufacturing method of the 1.5T metal gate structure SONOS memory in Embodiment 1, through process improvement, can form a smaller 1.5T metal gate structure SONOS memory and can reduce one photomask step compared to the common 2T metal gate structure SONOS memory manufacturing process.

[0070] Example 2

[0071] Based on the manufacturing method of the SONOS memory with a 1.5T metal gate structure according to Embodiment 1, in step S1, a well injection process is performed on the active region to form a P-well or N-well; typically, the active region 102 of the logic device includes the active region of the core device and the active region of the input / output (IO) device. The active region 102 of the logic device is used to form the logic device. The active region 102 of the logic device can be divided into the active region of the core device and the active region of the input / output (IO) device. The core device is formed in the active region of the core device, and the input / output device is formed in the active region of the input / output (IO) device; the active region 103 of the SONOS memory cell is used to form the select gate (SG) and memory gate (MG) of the SONOS memory cell.

[0072] Preferably, in step S2, an oxidation process is used to form the gate oxide layer 130.

[0073] Preferably, in step S3, the gate polysilicon layer 140 is formed using a low-pressure chemical vapor deposition (LPCVD) process.

[0074] Preferably, in step S7, an ONO layer 150 is deposited using a low-pressure chemical vapor deposition (LPCVD) process or an atomic layer deposition (ALD) method.

[0075] Preferably, the first gate metal layer 161 is AL.

[0076] Preferably, the second gate metal layer 162 is AL.

[0077] Example 3

[0078] In the manufacturing method of the SONOS memory with a 1.5T metal gate structure based on Embodiment 1, in step S4, a memory cell gate stack is formed on the active region 103 of the SONOS memory cell, a logic device gate stack is formed on the active region 102 of the logic device, and then a sidewall 190 is formed on the lateral periphery of the memory cell gate stack and the logic device gate stack.

[0079] Preferably, in step S4, hydrofluoric acid (HF) is used to clean away the gate oxide layer 130 outside the gate region of the memory cell and the gate region of the logic device.

[0080] Preferably, after step S6, threshold voltage Vt-adjusted ion implantation is performed on the semiconductor substrate 100 under the exposed gate region of the memory tube, and then step S7 is performed.

[0081] Example 4

[0082] Based on the manufacturing method of the 1.5T structure SONOS memory with metal gate in Embodiment 1, in step S13, LDD (lightly doped drain) ion implantation, annealing and other process steps are performed to complete the manufacturing of the 1.5T structure SONOS memory.

[0083] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A method for manufacturing a SONOS memory with a 1.5T metal gate structure, characterized in that, Includes the following steps; S1. A semiconductor substrate (100) is provided, wherein the semiconductor substrate (100) has logic device active regions (102) and SONOS memory cell active regions (103) separated by shallow trench isolation (110); S2. A gate oxide layer (130) is formed on a semiconductor substrate; S3. Deposit a gate polysilicon layer (140) on the gate oxide layer (130); S4. Photolithography, defining the gate region of the memory cell in the active region (103) of the SONOS memory cell, and defining the gate region of the logic device in the active region (102) of the logic device; Etching stops on the semiconductor substrate (100) and shallow trench isolation (110), removing the gate polysilicon layer (140) and gate oxide layer (130) outside the gate region of the memory cell and the gate region of the logic device. A memory cell gate stack is formed on the semiconductor substrate (100) of the gate region of the memory cell, and a logic device gate stack is formed on the semiconductor substrate (100) of the gate region of the logic device. The memory cell gate stack consists of a memory cell gate oxide layer (131) and a memory cell gate polysilicon layer (141) stacked from bottom to top, and the logic device gate stack consists of a logic device gate oxide layer (132) and a logic device gate polysilicon layer (142) stacked from bottom to top. S5. An interlayer dielectric layer (120) covering the semiconductor substrate (100) is formed, and then chemical mechanical polishing is performed to expose the upper surfaces of the memory cell gate polysilicon layer (141) and the logic device gate polysilicon layer (142). S6. Photolithography, defining the left and right adjacent select transistor gate regions and memory transistor gate regions in the gate region of the memory cell; Etching stops on the semiconductor substrate (100), removing the memory cell gate stack in the gate region of the memory transistor and retaining the memory cell gate stack in the gate region of the select transistor, exposing the semiconductor substrate (100) under the gate region of the memory transistor, and forming a gate structure trench (181) of the memory transistor. S7. An ONO layer (150) is deposited on a silicon wafer, such that the ONO layer (150) covers the bottom and sidewalls of the gate structure trench (181) of the memory tube to form a gate trench (182) of the memory tube, and the ONO layer (150) also covers the exposed gate polysilicon layer (141) of the memory cell and the upper surface of the gate polysilicon layer (142) of the logic device. S8. Deposit a first gate metal layer (161) on the ONO layer (150); S9. Perform chemical mechanical polishing to remove the first gate metal layer (161) outside the gate trench (182) of the memory tube, exposing the upper surface of the gate polysilicon (141) of the remaining select tube gate stack and the upper surface of the gate polysilicon (142) of the logic device. S10. The gate polysilicon (141) of the memory cell gate stacked in the gate region of the select transistor is removed and stops at the gate oxide layer (131) of the memory cell to form a gate trench (183) of the select transistor; and the gate polysilicon (142) of the logic device is removed and stops at the gate oxide layer (132) of the logic device to form a gate trench (184) of the logic device. S11. Deposit the second gate metal layer (162); S12. Perform chemical mechanical polishing to remove the second gate metal layer (162) other than the selector gate trench (183) and the logic device gate trench (184) to form the selector metal gate, the logic device metal gate and the memory gate. S13. Perform subsequent processes for SONOS memory cells and logic devices to complete the manufacturing of the 1.5T structure SONOS memory.

2. The method for manufacturing a SONOS memory with a 1.5T metal gate structure according to claim 1, characterized in that, In step S1, a trap injection process is performed on the active region to form a P-trap or an N-trap.

3. The method for manufacturing a SONOS memory with a 1.5T metal gate structure according to claim 1, characterized in that, The active region (102) of the logic device includes the active region of the core device and the active region of the input / output device.

4. The method for manufacturing a SONOS memory with a 1.5T metal gate structure according to claim 1, characterized in that, In step S2, an oxidation process is used to form a gate oxide layer (130).

5. The method for manufacturing a SONOS memory with a 1.5T metal gate structure according to claim 1, characterized in that, In step S3, the gate polysilicon layer (140) is formed using a low-pressure chemical vapor deposition process.

6. The method for manufacturing a SONOS memory with a 1.5T metal gate structure according to claim 1, characterized in that, In step S7, an ONO layer (150) is deposited using a low-pressure chemical vapor deposition process or an atomic layer deposition method.

7. The method for manufacturing a SONOS memory with a 1.5T metal gate structure according to claim 1, characterized in that, The first gate metal layer (161) is AL; The second gate metal layer (162) is AL.

8. The method for manufacturing a SONOS memory with a 1.5T metal gate structure according to claim 1, characterized in that, In step S4, a memory cell gate stack is formed on the active region (103) of the SONOS memory cell, and a logic device gate stack is formed on the active region (102) of the logic device. Then, a sidewall 190 is formed on the lateral periphery of the memory cell gate stack and the logic device gate stack.

9. The method for manufacturing a SONOS memory with a 1.5T metal gate structure according to claim 1, characterized in that, In step S13, the LDD ion implantation process is performed.

10. The method for manufacturing a SONOS memory with a 1.5T metal gate structure according to claim 1, characterized in that, In step S13, the annealing process is performed.

11. The method for manufacturing a SONOS memory with a 1.5T metal gate structure according to claim 1, characterized in that, In step S4, hydrofluoric acid is used to clean away the gate oxide layer (130) outside the gate region of the memory cell and the gate region of the logic device.

12. The method for manufacturing a SONOS memory with a 1.5T metal gate structure according to claim 1, characterized in that, After step S6, threshold voltage-adjusted ion implantation is performed on the semiconductor substrate (100) under the exposed gate region of the memory tube, and then step S7 is performed.

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