Memory structure and forming method thereof
By forming an isolation doped region and a reverse biased PN junction in the memory structure, the crosstalk and substrate leakage current problems in diode and resistive switching memory cell structures are solved, achieving higher density integration and performance improvement, and making it suitable for various memory types.
Patent Information
- Application Number
- CN202411598011.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-11-08
- Publication Date
- 2026-05-08
AI Technical Summary
Existing diode and resistive random access memory cell structures suffer from crosstalk and substrate leakage current problems, which are particularly difficult to solve effectively under high integration density.
By forming an isolation doped region in the substrate and forming a reverse biased PN junction between the word line doped layer and the isolation doped region, leakage current is blocked, while the process flow is simplified and the use of deep trench isolation etching is reduced.
It effectively improves the substrate leakage problem, increases the integration density and performance of the memory structure, is suitable for various memory structures, and reduces the difficulty and cost of the process.
Smart Images
Figure CN122002813A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to semiconductor manufacturing processes, and more specifically to a memory structure and its formation method. Background Technology
[0002] As the manufacturing process of new memory chips shrinks, they become susceptible to crosstalk. To address this issue, transistor-based resistive random access memory (IT1R) and diode-based resistive random access memory (ID1R) structures have been developed. The diode-based ID1R structure has attracted considerable attention due to its simple structure, ease of three-dimensional integration, and ability to achieve high storage density.
[0003] Crosstalk in resistive random access memory (IRRAM) has long been a constraint on its development as a large-scale memory, and this problem intensifies with increasing integration scale and density. In diode-based IRRAM cell structures (1D1R), due to the small diode area and high integration density, crosstalk and substrate leakage current issues arise. To address these issues, deep trench isolation etching is introduced, using multiple layers filled with different insulating materials to solve the substrate leakage problem.
[0004] However, in the existing technology, the substrate leakage problem of diode and resistive random access memory cell structures needs further improvement. Summary of the Invention
[0005] The technical problem solved by this invention is to propose a memory structure and its formation method. A second doped ion is implanted into the substrate exposed by the isolation opening to form an isolation doped region. When leakage occurs in the substrate, the word line doped layer and the substrate of the isolation doped region form a reverse-biased PN junction, cutting off the leakage current and improving the substrate leakage problem. Furthermore, it eliminates the need for a deep trench isolation etching mask, simplifying the process and reducing etching difficulty. In addition, higher density integration can be achieved without significant modifications, and the word line doped layer can control more diode cells, improving the performance of the memory structure.
[0006] To address the aforementioned technical problems, embodiments of the present invention provide a method for forming a memory structure, comprising: providing a substrate including a plurality of active regions and isolation regions located between adjacent active regions; doping the substrate to form a word line doped layer within the substrate, the word line doped layer having first doped ions; doping a substrate located on the word line doped layer or an epitaxial layer on the surface of the substrate to form a diode material layer located on the word line doped layer; etching the substrate, the word line doped layer, and the diode material layer to form a plurality of isolation openings, the isolation openings exposing the substrate of the isolation regions; doping the substrate exposed by the isolation openings to form isolation doped regions within the isolation regions, the isolation doped regions having second doped ions, the conductivity type of the first doped ions being opposite to that of the second doped ions.
[0007] Optionally, the substrate has a conductivity type including P-type; the second doped ion has a conductivity type including P-type; and the substrate has the same conductivity type as the second doped ion.
[0008] Optionally, the substrate has an N-type conductivity; the second doped ion has an N-type conductivity; and the substrate has the same conductivity as the second doped ion.
[0009] Optionally, the ion doping concentration of the isolation doped region is greater than the ion doping concentration of the substrate; the ion doping concentration range of the second doped ion is: 1E10 atom / cm 2 ~1E15atom / cm 2 The ion doping concentration range of the substrate is: 1E10 atom / cm³. 2 ~1E15atom / cm 2 .
[0010] Optionally, the conductivity type of the first doped ion includes P-type or N-type; the conductivity type of the first doped ion is opposite to the conductivity type of the substrate.
[0011] Optionally, the ion doping concentration range of the first doped ion is: 1E10 atom / cm³. 2 ~1E15atom / cm 2 .
[0012] Optionally, the depth range of the isolation opening is:
[0013] Optionally, the method for forming the isolation opening includes: forming a mask layer on the surface of the diode material layer, the mask layer exposing a portion of the surface of the diode material layer; using the mask layer as a mask, etching the diode material layer, the word line doped layer, and the substrate until the surface of the substrate is exposed, thereby forming the isolation opening.
[0014] Optionally, the ion doping concentration of the word line doped layer is greater than the ion doping concentration of the diode material layer.
[0015] Optionally, the active region and the isolation region are arranged sequentially along the X direction.
[0016] Optionally, after forming the isolation doped region, the method further includes: forming an isolation structure within the isolation region; after forming the isolation structure, forming diode isolation openings within the isolation structure, the diode material layer, and the word line doped layer, wherein the diode isolation openings are arranged along the Y direction, and the Y direction is perpendicular to the X direction; forming a diode isolation structure within the diode isolation openings; doping the diode material layer to form a plurality of mutually discrete diode units located on the surface of the word line doped layer; forming a first conductive plug on the surface of each diode unit; forming a bit line parallel to the X direction connecting the plurality of first conductive plugs, wherein the bit line is electrically connected to the plurality of diode units through the plurality of first conductive plugs.
[0017] Optionally, after forming the diode unit, the method further includes forming a plurality of word line lead-out structures located on the diode unit.
[0018] Optionally, after doping the substrate to form a word line doped layer within the substrate, and before doping the substrate on the word line doped layer to form a diode material layer on the word line doped layer, the method further includes forming an epitaxial layer on the substrate surface.
[0019] Optionally, the process of doping the substrate located on the word line doped layer to form a diode material layer located on the word line doped layer further includes: doping the epitaxial layer.
[0020] Accordingly, embodiments of the present invention also provide a memory structure, which is formed by the memory structure forming method described in any of the preceding claims.
[0021] Compared with the prior art, the technical solution of the embodiments of the present invention has the following beneficial effects:
[0022] In the method for forming the memory structure of the present invention, firstly, the conductivity type of the first doped ion is opposite to that of the second doped ion. When substrate leakage occurs, the word line doped layer and the substrate of the isolation doped region form a reverse-biased PN junction, cutting off the leakage current and improving the memory structure that addresses the substrate leakage problem. Secondly, this solution does not require the use of a deep trench isolation etching mask, and the depth of the isolation opening is small, simplifying the process flow and reducing the difficulty of etching the isolation opening. Thirdly, the memory structure can achieve higher density integration without significant modifications, and the increased number of diode cells controlled by the word line doped layer improves the performance of the memory structure. Furthermore, the method of forming a reverse-biased PN junction between the word line doped layer and the substrate of the isolation doped region to reduce substrate leakage current is applicable to various types of memory structures and has a wide range of applications.
[0023] Furthermore, the ion doping concentration of the isolation doped region is greater than the ion doping concentration of the substrate; the ion doping concentration range of the second doped ion is: 1E10 atom / cm³. 2 ~1E15atom / cm 2 The ion doping concentration range of the substrate is: 1E10 atom / cm³. 2 ~1E15atom / cm 2 The doping concentration of the second doped ion is greater than that of the substrate, which enhances the sensitivity of the reverse bias PN junction formed by the word line doped layer and the substrate of the isolation doped region, cuts off leakage current, and improves the performance of the memory structure.
[0024] In the memory structure of this invention, the conductivity type of the first doped ion is opposite to that of the second doped ion. When substrate leakage occurs, the word line doped layer and the substrate of the isolation doped region form a reverse-biased PN junction, cutting off the current and improving the substrate leakage problem. Secondly, the memory structure achieves higher density integration, increasing the number of diode cells controlled by the word line doped layer and improving the performance of the memory structure. Thirdly, the reverse-biased PN junction structure formed by the word line doped layer and the substrate of the isolation doped region is suitable for various types of memory structures, with a wide range of applications. Attached Figure Description
[0025] Figures 1 to 25 This is a schematic diagram of the various steps in the formation process of a memory structure according to an embodiment of the present invention;
[0026] Figures 26 to 34 This is a schematic diagram of the various steps in the formation process of a memory structure according to another embodiment of the present invention;
[0027] Figure 35This is a perspective view of the memory structure according to an embodiment of the present invention. Detailed Implementation
[0028] As described in the background section, the prior art still has many problems. In one embodiment of a method for forming a memory structure, a substrate is provided, the substrate including a plurality of active regions and an isolation region located between adjacent active regions; a plurality of diode cells are formed on the surface of the active regions, and a deep trench isolation opening is provided between adjacent diode cells, the deep trench isolation opening exposing the surface of the isolation region substrate; a deep trench isolation structure is formed within the deep trench isolation opening.
[0029] On the one hand, the deep trench etching process is quite difficult and has high requirements for the process; on the other hand, the deep trench etching process is not compatible with complementary metal-oxide-semiconductor (CMOS) processes, and the oxide isolation effect of the deep trench isolation structure is poor, which can easily cause substrate leakage.
[0030] To address the aforementioned technical problems, the present invention provides a method for forming a memory structure. First, the conductivity type of the first doped ion is opposite to that of the second doped ion. When substrate leakage occurs, the word line doped layer and the substrate of the isolation doped region form a reverse-biased PN junction, cutting off the leakage current and improving the memory structure's ability to handle substrate leakage. Second, this solution eliminates the need for a deep trench isolation etching mask, and the isolation opening has a smaller depth, simplifying the process and reducing the difficulty of etching the isolation opening. Third, the memory structure can achieve higher density integration without significant modifications, increasing the number of diode cells controlled by the word line doped layer and improving the memory structure's performance. Furthermore, the method of forming a reverse-biased PN junction between the word line doped layer and the substrate of the isolation doped region to reduce substrate leakage current is applicable to various types of memory structures, offering a wide range of applications.
[0031] To make the above-mentioned objectives, features and beneficial effects of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.
[0032] Figures 1 to 25 This is a schematic diagram of the various steps in the formation process of a memory structure according to an embodiment of the present invention.
[0033] Please refer to Figures 1 to 3 , Figure 1 yes Figure 2 and Figure 3 Top view, Figure 2 yes Figure 1 A sectional view at position AA1. Figure 3 yes Figure 1 A cross-sectional view at BB1 provides a substrate 100 including a plurality of active regions I and an isolation region II located between adjacent active regions I.
[0034] The substrate 100 is made of materials including silicon, silicon carbide, silicon germanium, silicon-on-insulator (SOI), or germanium-on-insulator (GOI).
[0035] The ion doping concentration range of the substrate 100 is: 1E10 atom / cm³. 2 ~1E15atom / cm 2 .
[0036] The active region I and the isolation region II are arranged sequentially along the X direction. The active region I provides the structural basis for the subsequent formation of the diode unit 108. The isolation region II provides the structural basis for the formation of the isolation structure 105.
[0037] In some embodiments, the substrate 100 has a conductivity type including P-type; the second doped ion in the subsequently formed isolation doped region 104 has a conductivity type including P-type; and the substrate 100 has the same conductivity type as the second doped ion.
[0038] In other embodiments, the substrate has an N-type conductivity; the second doped ion in the subsequently formed isolation doped region has an N-type conductivity; and the substrate has the same conductivity as the second doped ion.
[0039] The conductivity type of the substrate 100 is the same as that of the second doped ion. The ion doping concentration of the second doped ion is greater than that of the substrate 100, which enhances the sensitivity of the reverse bias PN junction formed by the subsequently formed word line doped layer 101 and the substrate of the isolation doped region 104, cuts off leakage current, and improves the performance of the memory structure.
[0040] Please refer to Figure 4 and Figure 5 , Figure 4 perspective and Figure 2 same, Figure 5 perspective and Figure 3 Similarly, the substrate 100 is doped to form a word line doped layer 101 located within the substrate 100, the word line doped layer 101 having a first doped ion.
[0041] The depth range of the doping treatment is:
[0042] The conductivity type of the first doped ion includes P-type or N-type; the conductivity type of the first doped ion is opposite to the conductivity type of the substrate 100.
[0043] The ion doping concentration range of the first doped ion is: 1E10 atom / cm³ 2~1E15atom / cm 2 .
[0044] The conductivity type of the first doped ion is opposite to that of the second doped ion in the subsequently formed isolation doped region 104. When leakage occurs in the substrate 100, the word line doped layer 101 and the substrate of the subsequently formed isolation doped region 104 form a reverse bias PN junction, which cuts off the leakage current, improves the substrate leakage problem, and enhances the memory structure performance.
[0045] Please refer to Figure 6 and Figure 7 , Figure 6 perspective and Figure 4 same, Figure 7 perspective and Figure 5 Similarly, the substrate 100 located on the word line doping layer 101 is doped to form a diode material layer 102 located on the word line doping layer 101.
[0046] The diode material layer 102 provides the structural basis for the subsequent formation of the diode unit 108.
[0047] In the step of doping the substrate 100 located on the word line doped layer 101 to form a diode material layer 102 located on the word line doped layer 101, the ion doping concentration range of the doping treatment is: 1E10 atom / cm 2 ~1E15atom / cm 2 In the step of doping the substrate 100 located on the word line doping layer 101 to form a diode material layer 102 located on the word line doping layer 101, the conductivity type of the dopant ions in the doping process is the same as the conductivity type of the word line doping layer 101.
[0048] In some embodiments of the present invention, when the first doped ion of the word line doped layer 101 has an N-type conductivity, the diode material layer 102 also has an N-type conductivity.
[0049] In other embodiments, when the first doped ion of the word line doped layer is of P-type conductivity, the diode material layer is of P-type conductivity.
[0050] Please refer to Figure 8 and Figure 9 , Figure 8 perspective and Figure 6 same, Figure 9 perspective and Figure 7Similarly, the substrate 100, the word line doped layer 101, and the diode material layer 102 are etched to form a plurality of isolation openings 103, which expose the substrate 100 of the isolation region II.
[0051] The method for forming the isolation opening 103 includes: forming a mask layer (not shown) on the surface of the diode material layer 102, the mask layer exposing a portion of the surface of the diode material layer 102; using the mask layer as a mask, etching the diode material layer 102, the word line doped layer 101, and the substrate 100 until the surface of the substrate 100 is exposed, thereby forming the isolation opening 103.
[0052] The depth range of the isolation opening 103 is
[0053] On the one hand, the conductivity type of the first doped ion is opposite to that of the second doped ion. When leakage occurs in the substrate 100, the word line doped layer 101 and the substrate of the isolation doped region 104 form a reverse bias PN junction, which cuts off the leakage current, improves the leakage problem of the substrate 100, and enhances the memory structure performance. On the other hand, the leakage problem of the substrate 100 can be improved by the reverse bias PN junction formed by the word line doped layer 101 and the substrate of the isolation doped region 104. Therefore, the depth of the isolation opening 103 can be reduced, the etching difficulty of the isolation opening 103 can be reduced, and the etching mask with deep trench isolation is not required, simplifying the process flow.
[0054] Please refer to Figure 10 and Figure 11 , Figure 10 perspective and Figure 8 same, Figure 11 perspective and Figure 9 Similarly, the substrate 100 exposed by the isolation opening 103 is doped to form an isolation doped region 104 in the isolation region II. The isolation doped region 104 contains a second doped ion, and the conductivity type of the first doped ion is opposite to that of the second doped ion.
[0055] The method of forming a reverse-biased PN junction between the word line doped layer 101 and the substrate of the isolation doped region 104 to reduce substrate leakage current is applicable to a variety of memory structures, such as resistive random access memory (RRAM), ferroelectric random access memory (FeRAM), magnetic random access memory (MRAM), and phase change random access memory (PCRAM), and has a wide range of applications.
[0056] In some embodiments of the present invention, the conductivity type of the substrate 100 includes P-type; the conductivity type of the second doped ion of the isolation doped region 104 includes P-type; and the conductivity type of the substrate 100 is the same as the conductivity type of the second doped ion.
[0057] In other embodiments, the substrate has an N-type conductivity; the second doped ion in the isolation doped region has an N-type conductivity; and the substrate has the same conductivity type as the second doped ion.
[0058] The conductivity type of the substrate 100 is the same as that of the second doped ion. The ion doping concentration of the second doped ion is greater than that of the substrate, which enhances the sensitivity of the reverse bias PN junction formed by the word line doped layer 101 and the substrate of the isolation doped region 104, cuts off leakage current, and improves the performance of the memory structure.
[0059] The ion doping concentration of the isolation doped region 104 is greater than that of the substrate 100; the ion doping concentration range of the second doped ions is: 1E10 atom / cm 2 ~1E15atom / cm 2 .
[0060] The conductivity type of the substrate 100 is the same as that of the second doped ion. The ion doping concentration of the second doped ion is greater than that of the substrate, which enhances the sensitivity of the reverse bias PN junction formed by the word line doped layer 101 and the substrate of the isolation doped region 104, cuts off leakage current, and improves the performance of the memory structure.
[0061] Please refer to Figure 12 and Figure 13 , Figure 12 perspective and Figure 10 same, Figure 13 perspective and Figure 11 Similarly, after forming the isolation doped region 104, the method further includes forming an isolation structure 105 within the isolation region II.
[0062] The material of the isolation structure 105 includes silicon oxide. The method for forming the isolation structure 105 includes deposition.
[0063] Please refer to Figures 14 to 16 , Figure 14 yes Figure 15 and Figure 16 Top view, Figure 15 yes Figure 14 A sectional view at position AA1. Figure 16 yes Figure 14 In the cross-sectional view at position BB1, after the isolation structure 105 is formed, a plurality of diode isolation openings 106 are formed in the isolation structure 105, the diode material layer 102 and the word line doped layer 101. The diode isolation openings 106 are arranged along the Y direction, which is perpendicular to the X direction.
[0064] The diode isolation opening 106 provides a structural basis for forming the diode isolation structure 107.
[0065] Please refer to Figures 17 to 19 , Figure 17 yes Figure 18 and Figure 19 Top view, Figure 18 yes Figure 7 A sectional view at position AA1. Figure 19 yes Figure 17 In the cross-sectional view at position BB1, a diode isolation structure 107 is formed within the diode isolation opening 106.
[0066] Please refer to Figures 20 to 22 , Figure 20 yes Figure 21 and Figure 22 Top view, Figure 21 yes Figure 20 A sectional view at position AA1. Figure 22 yes Figure 20 In the cross-sectional view at position BB1, the diode material layer 102 is doped to form a plurality of discrete diode units 108 located on the surface of the word line doped layer 101.
[0067] The step of doping the diode material layer 102 to form a plurality of discrete diode units 108 located on the surface of the word line doped layer 101 includes: forming a first mask layer (not shown) on the diode material layer 102, the first mask layer exposing a portion of the diode material layer 102; and doping the portion of the diode material layer 102 exposed by the first mask layer to form a plurality of discrete diode units 108 located on the surface of the word line doped layer 101.
[0068] The diode unit 108 includes a first diode layer located on the surface of the word line doped layer and a second diode layer located on the surface of the first diode layer. In the step of doping the diode material layer 102 to form a plurality of discrete diode units 108 located on the surface of the word line doped layer 101, the purpose of the doping process is to form the second diode layer and thus the diode unit 108.
[0069] The ion doping concentration of the first diode layer is the same as that of the diode material layer 102, and the conductivity type of the first diode layer is the same as that of the diode material layer 102; the conductivity type of the second diode layer is opposite to that of the diode material layer 102.
[0070] Specifically, in some embodiments of the present invention, when the conductivity type of the diode material layer 102 is N-type, the conductivity type of the first diode layer is N-type and the conductivity type of the second diode layer is P-type.
[0071] In other embodiments, when the conductivity type of the diode material layer is P-type, the conductivity type of the first diode layer is P-type and the conductivity type of the second diode layer is N-type.
[0072] After forming a plurality of discrete diode units 108 on the surface of word line doped layer 101, the method further includes: forming a second mask layer (not shown) on the diode units 108, the second mask layer exposing a portion of the diode material layer 102, and performing doping treatment on the diode material layer 102 exposed by the second mask layer.
[0073] Specifically, in some embodiments of the present invention, the conductivity type of the doped ions in the doping treatment is the same as that of the doped ions in the first diode layer, and the doping concentration of the ions in the doping treatment is greater than that of the ions in the first diode layer.
[0074] Please refer to Figures 23 to 25 Please refer to the following: Figure 35 A first conductive plug 109 is formed on the surface of each diode unit 108; a bit line 111 is formed parallel to the X direction and connects a plurality of first conductive plugs 109, the bit line 111 being electrically connected to a plurality of diode units 108 through the electrical connection of the plurality of first conductive plugs 109.
[0075] After forming the diode unit 108 and before forming the first conductive plug 109, the method further includes: annealing the surface of the diode unit 108 to form a diode unit 108 having a metal silicide layer.
[0076] After forming the first conductive plug 109, the method further includes forming a plurality of word line lead-out structures 112 located on the diode unit 108.
[0077] After forming the first conductive plug 109, and before forming the bit line 111 that connects the plurality of first conductive plugs 109 parallel to the X direction, the method further includes: forming a storage structure 110 located on the conductive plug 109.
[0078] The storage structure 110 includes: a resistive random access memory (RRAM) storage structure, a ferroelectric random access memory (FeRAM) storage structure, a magnetic random access memory (MRAM) storage structure, and a phase change random access memory (PCRAM) storage structure.
[0079] The word line lead-out structure 112 is electrically connected to the word line doped layer 101.
[0080] The word line leader structure 112 links each of the memory structures 110, and the bit line 111 links multiple memory structures 110. The word line leader structure 112 and the bit line 111 enable the selection and control of each memory structure 110.
[0081] First, when leakage occurs in the substrate 100, the word line doped layer 101 and the substrate of the isolation doped region 104 form a reverse-biased PN junction, cutting off the leakage current and improving the substrate leakage problem. Second, the leakage problem of the substrate 100 can be improved by the reverse-biased PN junction formed by the word line doped layer 101 and the substrate of the isolation doped region 104, eliminating the need for a deep trench isolation etching mask, reducing the depth of the isolation opening 103, simplifying the process flow, and reducing the difficulty of etching the isolation opening 103. Third, the memory structure can achieve higher density integration without significant modifications, and the word line doped layer 101 can control more diode units, improving the performance of the memory structure. In addition, the method of forming a reverse-biased PN junction between the word line doped layer 101 and the substrate of the isolation doped region 104 to reduce substrate leakage current is applicable to various types of memory structures, such as resistive random access memory (RRAM), ferroelectric random access memory (FeRAM), and magnetic random access memory (MRRAM). Access memory (MRAM) and phase-change random access memory (PCRAM) have a wide range of applications.
[0082] Figures 26 to 34 This is a schematic diagram of the various steps in the formation process of a memory structure according to another embodiment of the present invention.
[0083] Please refer to Figures 26 to 28 , Figure 26 yes Figure 27 and Figure 28 Top view, Figure 27 yes Figure 26 A sectional view at position AA1. Figure 28 yes Figure 26 A cross-sectional view at BB1 provides a substrate 200 including a plurality of active regions I and an isolation region II located between adjacent active regions I.
[0084] The substrate 200 is made of materials including silicon, silicon carbide, silicon germanium, silicon-on-insulator (SOI), or germanium-on-insulator (GOI).
[0085] The ion doping concentration range of the substrate 200 is: 1E10 atom / cm³. 2 ~1E15atom / cm 2 .
[0086] The active region I and the isolation region II are arranged sequentially along the X direction.
[0087] In some embodiments of the present invention, the conductivity type of the substrate 200 includes P-type.
[0088] In other embodiments, the substrate has an N-type conductivity.
[0089] Please refer to Figure 29 and Figure 30 , Figure 29 perspective and Figure 27 same, Figure 30 perspective and Figure 28 Similarly, the substrate 200 is doped to form a word line doped layer 201 located within the substrate 200, the word line doped layer 201 having a first doped ion.
[0090] The depth range of the doping treatment is:
[0091] The conductivity type of the first doped ion includes P-type or N-type; the conductivity type of the first doped ion is opposite to the conductivity type of the substrate 200.
[0092] The ion doping concentration range of the first doped ion is: 1E10 atom / cm³ 2 ~1E15atom / cm 2 .
[0093] Please refer to Figure 31 and Figure 32 , Figure 31 perspective and Figure 29 same, Figure 32 perspective and Figure 30 Similarly, an epitaxial layer 202 is formed on the surface of the substrate 200.
[0094] Please refer to Figure 33 and Figure 34 , Figure 33 perspective and Figure 31 same, Figure 34 perspective and Figure 32 Similarly, the substrate 200 located on the word line doping layer 201 is doped to form a diode material layer 203 located on the word line doping layer 201.
[0095] Specifically, in some embodiments of the present invention, in the process of doping the substrate 200 located on the word line doping layer 201 to form the diode material layer 203 located on the word line doping layer 201, the process further includes: doping the epitaxial layer structure 202.
[0096] After forming the diode material layer 203, please refer to... Figures 8 to 25 The similarities to the foregoing embodiments will not be repeated here.
[0097] Accordingly, this embodiment of the invention also provides a memory structure, which is formed by the above-described method for forming a memory structure, and will not be described in detail here.
[0098] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.
Claims
1. A method for forming a memory structure, characterized in that, include: A substrate is provided, comprising a plurality of active regions and an isolation region located between adjacent active regions; The substrate is doped to form a word line doped layer within the substrate, the word line doped layer having a first doped ion; The substrate located on the word line doped layer or the epitaxial layer on the surface of the substrate is doped to form a diode material layer located on the word line doped layer; The substrate, the word line doped layer, and the diode material layer are etched to form a plurality of isolation openings, the isolation openings exposing the substrate of the isolation region; The substrate exposed by the isolation opening is doped to form an isolation doped region within the isolation region. The isolation doped region contains a second doped ion, and the conductivity type of the first doped ion is opposite to that of the second doped ion.
2. The method for forming a memory structure as described in claim 1, characterized in that, The substrate has a conductivity type including P-type; the second doped ion has a conductivity type including P-type; the substrate has the same conductivity type as the second doped ion.
3. The method for forming a memory structure as described in claim 1, characterized in that, The substrate has an N-type conductivity; the second doped ion has an N-type conductivity; and the substrate has the same conductivity type as the second doped ion.
4. The method for forming a memory structure as described in claim 1, characterized in that, The ion doping concentration of the isolation doped region is greater than that of the substrate; the ion doping concentration range of the second doped ion is: 1E10 atom / cm 2 ~1E15atom / cm 2 The ion doping concentration range of the substrate is: 1E10 atom / cm³. 2 ~1E15atom / cm 2 .
5. The method for forming a memory structure as described in claim 1, characterized in that, The conductivity type of the first doped ion includes P-type or N-type; the conductivity type of the first doped ion is opposite to the conductivity type of the substrate.
6. The method for forming a memory structure as described in claim 1, characterized in that, The ion doping concentration range of the first doped ion is: 1E10 atom / cm³ 2 ~1E15atom / cm 2 .
7. The method for forming a memory structure as described in claim 1, characterized in that, The depth range of the isolation opening is 8. The method for forming a memory structure as described in claim 1, characterized in that, The method for forming the isolation opening includes: forming a mask layer on the surface of the diode material layer, the mask layer exposing a portion of the surface of the diode material layer; using the mask layer as a mask, etching the diode material layer, the word line doped layer, and the substrate until the surface of the substrate is exposed, thereby forming the isolation opening.
9. The method for forming a memory structure as described in claim 1, characterized in that, The ion doping concentration of the word line doped layer is greater than the ion doping concentration of the diode material layer.
10. The method for forming a memory structure as described in claim 1, characterized in that, The active region and the isolation region are arranged sequentially along the X direction.
11. The method for forming a memory structure as described in claim 10, characterized in that, After forming the isolation doped region, the method further includes: forming an isolation structure within the isolation region; after forming the isolation structure, forming a plurality of diode isolation openings within the isolation structure, the diode material layer, and the word line doped layer, wherein the diode isolation openings are arranged along the Y direction, and the Y direction is perpendicular to the X direction; forming a diode isolation structure within the diode isolation openings; doping the diode material layer to form a plurality of mutually discrete diode units located on the surface of the word line doped layer; forming a first conductive plug on the surface of each diode unit; forming a bit line parallel to the X direction connecting the plurality of first conductive plugs, wherein the bit line is electrically connected to the plurality of diode units through the plurality of first conductive plugs.
12. The method for forming a memory structure as described in claim 11, characterized in that, After forming the diode unit, the method further includes forming a plurality of word line lead-out structures located on the diode unit.
13. The method for forming a memory structure as described in claim 1, characterized in that, After doping the substrate to form a word line doped layer within the substrate, and before doping the substrate on the word line doped layer to form a diode material layer on the word line doped layer, the method further includes: forming an epitaxial layer on the surface of the substrate.
14. The method for forming a memory structure as described in claim 13, characterized in that, The process of doping the substrate located on the word line doped layer to form a diode material layer located on the word line doped layer also includes: doping the epitaxial layer.
15. A memory structure, characterized in that, The memory structure is formed by the method for forming a memory structure as described in any one of claims 1 to 14.