Wafer-on-substrate integrated circuit structure with edge pad semiconductor wafer

Abstract

An integrated circuit structure includes a memory stack including a plurality of semiconductor wafers horizontally separated from each other, a memory control wafer, an interposer, a logic processor wafer, and a package substrate. Each semiconductor wafer includes a top surface, a bottom surface, four sidewalls, and a plurality of edge pads disposed along the first sidewalls. A memory control wafer is disposed underneath and electrically connected to a plurality of edge pads of each semiconductor wafer, wherein a first sidewall of each semiconductor wafer faces the memory control wafer. An interposer is disposed underneath and electrically connected to the memory control wafer. The logic processor wafer is electrically connected to the memory control wafer. A package substrate is disposed below and electrically connected to the interposer.

Description

Technical Field

[0001] This disclosure generally relates to a wafer-on-a-substrate (COWOS) integrated circuit (IC) structure, and more specifically, to a COWOS IC structure having edge pad semiconductor wafers. Background Technology

[0002] 2.5D / 3D ICs are widely recognized as next-generation semiconductor technologies, offering advantages such as high performance, low power consumption, small physical size, and high integration density. 2.5D / 3D ICs provide a pathway to continuously meet the performance and cost requirements of next-generation devices, while still allowing for more flexible gate lengths and lower process complexity. Therefore, 2.5D / 3D ICs are expected to find broad applicability in applications such as high-performance computing (HPC) and data centers, artificial intelligence (AI) / machine learning (ML), 5G / 6G networks, graphics, smartphones / wearable devices, automotive, and other applications requiring "extreme," ultra-high performance, and higher power devices.

[0003] Commercial 2.5D / 3D ICs (such as 3D High Bandwidth Memory (HBM) logically DRAM memory chip stacks) are increasingly being reused. These HBM devices contain through-silicon vias (TSVs) in the active die and silicon interposer. Furthermore, 2.5D / 3D ICs enable vertical stacking of heterogeneous chips from different processes and nodes, chip reuse, and high-performance applications within small SiP (System-in-Package) wafers, pushing the limits of single-chip solutions at the most advanced nodes. Figure 1 As shown, the substrate-on-wafer-on-chip (COWOS) structure 20 includes an HBM structure 21 with TSV 201 (having multiple DRAM memory chips 211 and controllers 213), a logic chip 22 (e.g., a GPU or SOC chip), a silicon interposer 23 with TSV, and a packaging substrate 24, wherein the HBM structure 21 and the logic chip 22 are stacked on the silicon interposer 23, and then the silicon interposer 23 is stacked on the packaging substrate 24.

[0004] However, 2.5D / 3D ICs employ a packaging topology with bottom / top electrical interconnects, which are generated by the aforementioned interconnect technologies, such as microbumps, TSVs, and redistribution layers (RDLs). Bottom / top electrical interconnects impose stringent constraints on 3D IC designers in optimizing power, performance, area, and cost (PPAC) when developing the best design solution, particularly due to the difficulty of forming TSVs within the semiconductor wafer and the alignment of TSVs across each wafer.

[0005] Furthermore, as the single-chip integration capability of silicon wafers has rapidly grown from GSI (billion-scale: over a billion transistors on a single chip) to TSI (trillion-scale: trillions of transistors on a single chip), the power consumption of operating such a large number of transistors has increased dramatically. This adversely increases the junction temperature of the transistors, and the current-limited heat dissipation capacity (e.g., the very low thermal conductivity of silicon dioxide / silicon) further raises the overall chip temperature. Even worse, in 2.5D / 3D ICs, the insufficient heat dissipation due to the stacking of multiple DRAM memory semiconductor chips (or HBMs) leads to increased chip operating temperatures, which is considered the most serious problem with HBM structures. Summary of the Invention

[0006] According to a first embodiment of this disclosure, an IC structure includes: a memory stack, a memory controller chip, an interposer, a logic processor chip, and a package substrate. The memory stack includes a plurality of semiconductor chips. The plurality of semiconductor chips are horizontally separated from each other, wherein each semiconductor chip includes a top surface, a bottom surface opposite the top surface, and four sidewalls, including a first sidewall, a second sidewall, a third sidewall, and a fourth sidewall, and a plurality of edge pads arranged along the first sidewalls, wherein the area of ​​the bottom surface or the top surface of each semiconductor chip is larger than the area of ​​any sidewall. The memory controller chip is disposed below and electrically connected to the plurality of edge pads of each semiconductor chip, wherein the first sidewall of each semiconductor chip faces the memory controller chip. The interposer is disposed below and electrically connected to the memory controller chip. The logic processor chip is electrically connected to the memory controller chip. The package substrate is disposed below and electrically connected to the interposer.

[0007] According to some embodiments of this disclosure, the memory stack further includes an upwardly extending thermal conductive layer and / or a laterally extending thermal conductive layer. The laterally extending thermal conductive layer covers each of the second sidewalls of the plurality of semiconductor wafers. The upwardly extending thermal conductive layer is attached to the top or bottom surface of the first semiconductor wafer, wherein the thermal conductivity of the laterally extending thermal conductive layer or the upwardly extending thermal conductive layer is higher than that of silicon or silicon dioxide.

[0008] According to some embodiments of this disclosure, the upwardly extending thermally conductive layer is thermally coupled to the laterally extending thermally conductive layer, and the upwardly extending thermally conductive layer or the laterally extending thermally conductive layer comprises silicon carbide, boron nitride, aluminum nitride, tungsten, or copper.

[0009] According to some embodiments of this disclosure, the upwardly extending thermal conductive layer is disposed between the first semiconductor wafer and the second semiconductor wafer, or the upwardly extending thermal conductive layer is located on the outermost sidewall of the memory stack.

[0010] According to some embodiments of this disclosure, each of the semiconductor wafers is a dynamic random access memory wafer and includes data output between 128 and 2048 bits.

[0011] According to some embodiments of this disclosure, each edge pad of each semiconductor wafer includes an edge contact in a back-end process region and a conductive via above the edge contact and in a dielectric layer or redistribution layer (RDL), wherein the area of ​​the conductive via is larger than the area of ​​the edge contact.

[0012] According to some embodiments of this disclosure, the edge contact is electrically connected to a signal pad in the back-end process region of the semiconductor wafer, the signal pad being surrounded by a sealing ring structure.

[0013] According to some embodiments of this disclosure, each edge pad of each semiconductor wafer includes wires in a redistribution layer (RDL) electrically connected to signal pads in a back-end processing region of the semiconductor wafer, the signal pads being surrounded by a sealing ring structure.

[0014] According to some embodiments of this disclosure, the RDL includes a plurality of stacked dielectric layers, and the wires are located therein.

[0015] According to some embodiments of this disclosure, a portion of the wire is configured to be placed in the dicing region of the semiconductor wafer prior to dicing.

[0016] According to some embodiments of this disclosure, the logic processor chip is disposed above the interposer layer, and a heat sink is located above the logic processor chip; wherein the top surface of the heat sink is substantially flush with the top surface of the memory stack.

[0017] According to some embodiments of this disclosure, the memory stack further includes: an upwardly extending thermally conductive layer covering each of the third sidewalls of the plurality of semiconductor wafers; wherein the upwardly extending thermally conductive layer is thermally coupled to a laterally extending thermally conductive layer above each of the second sidewalls of the plurality of semiconductor wafers, and the thermal conductivity of the upwardly extending thermally conductive layer is higher than that of silicon or silicon dioxide. Attached Figure Description

[0018] The aspects of this disclosure are best understood from the following detailed description, which is taken in conjunction with the accompanying drawings. It should be noted that, in accordance with industry standard practice, the various structures are not drawn to scale. In fact, for clarity of discussion, the dimensions of the various structures may be arbitrarily increased or decreased.

[0019] Figure 1 This demonstrates a conventional semiconductor COWOS with high bandwidth memory (HBM).

[0020] Figures 2A to 2CCross-sectional views of structures at different stages of a method for manufacturing an integrated circuit (IC) structure according to some embodiments of the present disclosure are shown.

[0021] Figure 2D A perspective view showing the redistribution layers according to various embodiments of the present disclosure.

[0022] Figure 2E and 2F Cross-sectional views of IC structures according to various embodiments of the present disclosure are shown.

[0023] Figure 2G Various embodiments according to this disclosure are shown. Figure 2B , 2C Cross-sectional views of the redistribution layers of the IC structure shown in Figures 2E and 2F.

[0024] Figures 3A to 3D Cross-sectional views of structures at different stages of a method for manufacturing an IC structure according to some embodiments of the present disclosure are shown.

[0025] Figure 3E and 3F Cross-sectional views of IC structures according to various embodiments of the present disclosure are shown.

[0026] Figure 4A to 4G Cross-sectional views of structures at different stages of a method for manufacturing an IC structure according to some embodiments of the present disclosure are shown.

[0027] Figure 4H to 4N Cross-sectional views of IC structures according to various embodiments of the present disclosure are shown.

[0028] Figure 5A and 5B Cross-sectional views of IC structures according to various embodiments of the present disclosure are shown.

[0029] Figure 5C Various embodiments according to this disclosure are shown. Figure 5A and 5B The diagram shows a cross-sectional view of the interconnect structure of the IC structure.

[0030] Figures 6A to 6E Cross-sectional views illustrating the structure of different stages of a method for manufacturing a semiconductor package according to various embodiments of the present disclosure.

[0031] Figures 7A to 7H Cross-sectional views of structures at different stages of a method for manufacturing a semiconductor package according to various embodiments of the present disclosure are shown.

[0032] Figure 7I and 7J Cross-sectional views of semiconductor packages according to various embodiments of the present disclosure are shown.

[0033] Figure 8A and 8B Perspective views and cross-sectional views of memory chips having multiple edge pads according to some embodiments of the present disclosure are shown respectively.

[0034] Figure 8C A cross-sectional view of a semiconductor wafer containing memory dies having multiple edge pads, according to some embodiments of the present disclosure, is shown.

[0035] Figure 8D and 8E A cross-sectional view of another memory chip having multiple edge pads according to some embodiments of the present disclosure is shown.

[0036] Figure 9A A perspective view showing the structure of a conventional high-bandwidth memory (HBM).

[0037] Figure 9B A perspective view showing a novel high-bandwidth memory (NuHBM) stack / shelf according to some embodiments of the present disclosure.

[0038] Figure 10 A cross-sectional view showing an intermediate stage in the formation of a NuHBM stack / layer according to some embodiments of the present disclosure.

[0039] Figures 11A to 11D This invention illustrates a NuHBM stacking / layer interconnect process according to some embodiments of the present disclosure.

[0040] Figure 12 This invention illustrates IC structures with NuHBM stacks / layers according to some embodiments of the present disclosure.

[0041] Figure 13A and 13B A cross-sectional view of a semiconductor package assembly according to various embodiments of the present disclosure is shown. Detailed Implementation

[0042] This application claims rights to U.S. Provisional Application No. 63 / 730,072, filed December 10, 2024, and is a partial continuation of U.S. Non-Provisional Application No. 18 / 471,670, filed September 21, 2023, which claims rights to U.S. Provisional Application No. 63 / 409,852, filed September 26, 2022. The disclosures of all U.S. applications are incorporated herein by reference in their entirety.

[0043] The following disclosure provides numerous different embodiments or examples for implementing various features of the provided subject matter. Specific examples of components and arrangements will be described below to simplify this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, an embodiment in which a first member is formed above or on a second member may include instances in which the first and second members form direct contact, and may also include instances in which additional members may be formed between the first and second members such that the first and second members do not form direct contact. Additionally, component symbols and / or letters may be repeated in various instances in this disclosure. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0044] Furthermore, for ease of description, spatial relative terms such as "below," "under," "down," "above," "on," "on," and similar terms may be used herein to describe the relationship of one component or member to another component(s), as illustrated in the figures. Spatial relative terms are intended to cover not only the orientation depicted in the figures but also different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or otherwise) and thus the spatial relative descriptive terms used herein may also be interpreted.

[0045] As used herein, although terms such as "first," "second," and "third" describe various components, parts, regions, layers, and / or sections, these components, parts, regions, layers, and / or sections should not be limited by these terms. These terms may be used only to distinguish components, parts, regions, layers, or sections from one another. Unless the context clearly indicates otherwise, the terms such as "first," "second," and "third" as used herein do not imply a sequence or order.

[0046] Embodiments of the present invention disclose methods, processes, and structures for forming redistribution layers (RDLs) and interconnects (e.g., through-silicon vias, through-hole vias, metal vias, metal pads for copper hybrid bonding technology, and microbumps or solder bumps for flip-chip assembly) on the four side surfaces of a 3D IC and a low-profile 3D IC stack (detailed description provided below), wherein each stack layer consists of one or more ICs in the xy direction (in-plane direction) and the z direction (out-plane direction or IC thickness direction).

[0047] Embodiments of the packaging structure proposed in this disclosure allow for at least the following features: (a) five-sided power and signal distribution (through one front and four sides of the 3D IC package); (b) interconnection across the die and multiple sides using a combination of RDLs, TSVs, and through-hole vias (TMVs) through the four sides and / or internal interconnects (e.g., directly from the bottom die or substrate such as an interposer to the top die and other ICs in the stack); (c) RDLs on the side surfaces interconnected in three dimensions using flexible printed circuits (flexible circuits); and (d) the ability to use a variety of interconnect technologies, covering RDLs, TSVs, microbumps, solder bumps, copper hybrid bonding technology, and fine-pitch flexible interconnects (Flex). Therefore, the proposed packaging structure effectively reduces the length of global and IC package interconnect wiring and increases the number of transistors reached in one clock cycle.

[0048] In this invention, the sides of the memory chips are used to interconnect chips in a 2.5D / 3D IC stack to allow for signal and power distribution across the chips. Furthermore, a high thermal conductivity material is placed between two adjacent memory chips and thermally coupled to other high thermal conductivity materials, covering the other sides of the memory chip stack.

[0049] Figures 2A to 2C Cross-sectional views of the structure at different stages of a method for manufacturing an IC structure 100A according to some embodiments of the present disclosure are shown. Figure 2C The IC structure 100A shown is a semiconductor packaging device. The IC structure 100A can be formed from a semiconductor device 100W, which is a wafer-level device, wherein the IC structure 100A is formed by isolating the semiconductor device 100W using a monomerization or dicing process covering mechanical dicing, laser dicing, plasma etching or dicing, dry etching, wet etching (e.g., acid etching), or similar or combinations thereof.

[0050] refer to Figure 2AThe system receives or provides a semiconductor device 100W. First, a substrate 102 is provided or received. According to some embodiments, the substrate 102 is formed of a semiconductor material such as bulk silicon. According to some embodiments, the substrate 102 is formed of other semiconductor materials, such as silicon germanium, silicon carbide, gallium arsenide, or the like. In this embodiment, the substrate 102 is a P-type semiconducting substrate (acceptor type). In some other embodiments, an N-type semiconductor substrate (donor type) may be used. Alternatively, the substrate 102 includes: another elemental semiconductor, such as germanium; a compound semiconductor comprising gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, or indium antimonide; an alloy semiconductor comprising SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, or GaInAsP; or combinations thereof. In yet another embodiment, the substrate 102 includes a portion forming a semiconductor-on-insulator (SOI) substrate. In other embodiments, the substrate 102 may include a doped epitaxial layer, a gradient semiconductor layer, and / or a semiconductor layer covering another type of semiconductor layer, such as a silicon-germanium layer stacked on a silicon layer.

[0051] A plurality of conductive vias 104 are formed in substrate 102. The conductive vias 104 may extend from a main surface 102P1 of substrate 102 to a thickness of substrate 102. In this disclosure, "main surface" is used to refer to the upper or lower surface of a circuit or device that has the largest surface area among the six surfaces of the device or layer. Similarly, "secondary surface" is used to refer to the lateral side surfaces of a circuit or device (a circuit or device typically has four such side surfaces) whose surface area is smaller than that of the main surface. The conductive vias 104 may contain conductive materials such as copper, tungsten, molybdenum, cobalt, ruthenium, titanium, tantalum, aluminum, silver, gold, or other suitable materials. The conductive vias 104 may comprise a single-layer or multi-layer structure, which may include a diffusion barrier layer, a seed layer facilitating electroplating, a filler layer, a combination thereof, or the like.

[0052] In the exemplary formation process of conductive via 104, a plurality of holes (not shown) are formed on the main surface 102P1 of substrate 102. Dry etching (e.g., reactive ion etching, RIE), wet etching, combinations thereof, or the like can be used to form the holes. After the opening is made, silicon dioxide can be deposited to passivate the opening using a deposition process such as plasma-enhanced chemical vapor deposition (PECVD), and physical vapor deposition (PVD), sputtering deposition, atomic layer deposition (ALD), or other suitable deposition steps can be performed to deposit material for the conductive via 104 in the holes and over the main surface 102P1. After the entire filling process, the conductive via 104 may be referred to herein as a through-silicon via (TSV).

[0053] According to some embodiments, a planarization process (e.g., chemical mechanical planarization (CMP), dry etching (e.g., using RIE), polishing, wet etching, and / or other suitable etching steps) is performed to remove excess conductive material and planarize the upper surface of the conductive via 104 flush with the main surface 102P1. After planarization, a main RDL 108A with surface treatment and a pad is deposited on the main surface 102P1 for subsequent bonding as needed.

[0054] refer to Figure 2B The device provides or receives another substrate or temporary carrier 106 and bonds the semiconductor structure 100W to the temporary carrier 106. According to some embodiments, the substrate 106 is a carrier substrate or support substrate. The carrier substrate 106 may be formed of glass, silicon, ceramic, or other suitable carrier materials. A release layer 110 is formed over the carrier substrate 106. Examples of release layers include release / adhesive layers commonly used in fan-out processes. The release layer 110 is a temporary layer formed over the carrier substrate 106 and allows for easier removal of the carrier substrate 106 from the semiconductor device 100W by laser irradiation, thermomechanical release, polishing, CMP, dry or wet etching / cleaning, or combinations thereof.

[0055] In addition to being used as a release layer in fan-out processing, the release layer can also be a combination of Ti (titanium) / Au (gold) stacked on the carrier and Ti / Au stacked on the back of the IC structure. The Au here can also be Cu (copper) or solder on both surfaces. Compression or reflow bonding can be used to achieve bonding between the carrier and the IC structure. Annealing is optional and can be performed as needed. When silicon is used as the carrier, the release layer can be SiO2, Si3N4, and other materials commonly used in wafer BEOL and / or MEMS / NEMS processing. The release layer can therefore also serve as a permanent bonding layer between IC structures (e.g., Figure 7B (The bonding layer shown in the image).

[0056] The pre-bonding conditions between the carrier and the IC structure surface may involve: - Chemical mechanical polishing (CMP) is used to achieve a preferred surface roughness (RA) of <1 nm for diamond and silicon, which can be either arithmetic mean roughness or sometimes root mean square roughness. This RA level can be achieved through a combination of CMP for silicon and SiO2 sacrificial layer deposition and CMP SiO2 planarization, and deep reactive ion etching (DRIE) for diamond. - Wet surface pretreatment, which involves ultrasonic deionized (DI) water cleaning, H2SO4 / H2O2 treatment, NH3 / H2O2 treatment, and N2 drying. - Plasma / Inductively Coupled Plasma Reactive Ion Etching (ICP-RIE): O2, H2 / O2, -Dark RIE (DRIE): O2 / CF4, and - The bonding surface (with and / or without adhesive layer) is activated in the bonding machine prior to bonding by using a fast atomic beam gun (FAB) (e.g., using an argon neutral atomic beam of about 1 keV) or by using an ion gun (e.g., using argon ions of about 60 eV) to remove the oxide film in vacuum and expose dangling bonds at the bonding surface.

[0057] - (Note 1: FAB is well-suited for (sputtering) Si / Si, Si / SiO2, metals, compound semiconductors and single-crystal oxides, while ion guns are known to be suitable for SiO2 / SiO2, glass, Si3N4 (silicon nitride) / Si3N4, Si / Si, Si / SiO2, metals, compound semiconductors and single-crystal oxides.) - (Note 2: 10 is required during the bonding process) -6 A vacuum of Pascals is used to prevent re-adsorption onto the activated bonding surface. In addition to the direct bonding methods described above, ultrathin adhesive or bonding layers (such as CVD polysilicon (poly-Si)) can be deposited as permanent bonding layers on mating IC structures. Figure 7B Polysilicon (with a thermal conductivity TC more than 100 times that of SiO2) can be deposited on both the IC structure and the carrier as a temporary release layer to achieve higher low-temperature direct bonding yields. For thermally sensitive applications, polysilicon is preferred over SiO2 for producing thin bonding layers to minimize the impact on the thermal resistivity of the final IC or package structure. Adhesive layers are typically ultra-thin (approximately 100 nm or less) to minimize their thermal impact. When used as a permanent layer, materials with higher TC and lower thermal expansion are preferred. Candidate adhesive layer materials include the following and combinations (or alloys thereof): - Non-metallic materials: Si (e.g., polycrystalline silicon), SiO2, Si3N4, Al2O3 (alumina), diamond, boron nitride, graphene -Metals: Ti, W, Pt, Cr, Au, Cu, Ir, Nickel (Ni), Iron (Fe), Ag-In, Au-In, Ag, Sn, Mo - Oxide-based metal cascades: SrTiO3 cascaded with Ir, YSZ / Si cascaded with Ir, MgO, sapphire or TaO3 cascaded with Ir When metal adhesive layers are used to bond IC structures (e.g., see...) Figure 7BWhen depositing a binder layer, it is recommended to deposit a barrier layer, such as Ti, on the back side of the IC structure before depositing the binder layer to prevent metal diffusion in the silicon lattice, which can poison the device. This is especially true for ultrathin ICs. During diamond CVD, growing diamond on a silicon seed crystal is a common practice. Silicon nitride (Si3N4) is commonly used in wafer BEOL processing. Alumina can be deposited via atomic layer deposition. When it comes to extreme thermal conductivity, graphene is another material worth considering besides diamond. In a monolayer, graphene can have a thermal conductivity of 30 to 50 W / cm·K. It can be considered as a binder or bonding layer to present a suitable 3D molecular structure. Graphene can be grown on silicon (100) surfaces using direct cobalt-assisted two-step ion beam synthesis. It can also be grown on silicon using a simple transfer-free synthesis method. Epitaxial graphene can be grown on crystalline and semi-insulating surfaces (such as SiC and silicon), and graphene nanostructures with excellent properties have been achieved through selective growth processes on SiC surfaces. Besides diamond and graphene, boron nitride is also of interest, especially cubic boron nitride, as it is known to have a similar crystal structure to diamond and a high in-plane TC (approximately 16 W / cm·K). Furthermore, the adhesive layer can be a combination of Ti / Au on one IC structure and Ti / Au on the back side of another structure for bonding. Thin metal platings based on Ti, W, or Cr can also be deposited prior to Au deposition, if desired. Thin layers of transient liquid bonding materials, such as silver-indium (Ag-In) and Au-In, sintered Ag, In, Au, or Cu, can also be applied together with matching metal platings (e.g., Au, Ag, or Cu). The adhesive layer can be deposited by CVD, atomic layer deposition (ALD), physical vapor deposition, thermal oxidation (in the case of silicon), or other methods. After deposition, the adhesive layer can be modulated in the bonding station by a combination of the aforementioned pre-bonded surface pretreatment, DRIE (e.g., using a mixture of SF6 and O2), plasma / ICP-RIE (using O2, Ar, N2, Ar / O2) and FAB (using (e.g.) neutral Ar atoms) or ion gun (using (e.g.) Ar ions).

[0058] After generating the main RDL 108A, the planarized structure having the main RDL 108A is bonded to the substrate 106 using a release layer, and the blocky portion of the substrate 102 below the conductive via 104 is removed to expose the bottom surface of the conductive via 104 (see...). Figure 2B Then you can... Figure 2B Another RDL 108B is deposited on the exposed conductive via 104, which, when completed, may have a surface finish and solder bumps or microbumps as required. After forming RDL 108B, mounting the resulting structure with RDLs 108A and 108B on carrier 106 onto a wafer bonding tape frame, releasing carrier 106, and individualizing the packages, a complete package is formed. Figure 2C The semiconductor structure in it is 100A.

[0059] based on Figures 2A to 2C The process shown can form various layers and structures to produce exposed edge pads, edge vias, and edge TSVs (which can penetrate the thickness of silicon or potting material, or a subset thereof, completely or partially, such as a structure containing only RDL108A with edge pad / via interconnects in the RDL). Figure 2E ), or a structure containing both RDL 108A with edge interconnects and edge TSVs (see Figure 2F The semiconductor structure 100A.

[0060] According to some embodiments, release layer 110 comprises a polymer-based material. According to some embodiments, release layer 110 is a heat-release material based on epoxy resin, such as a photothermal conversion (LTHC) release coating, which loses its adhesiveness upon heating or exposure to laser. According to other embodiments, release layer 110 is an ultraviolet (UV) adhesive, which loses its adhesiveness upon exposure to UV light. Release layer 110 may be a thermoplastic or thermosetting material. According to some embodiments, release layer 110 comprises a polyimide or silicone-based material. According to some other embodiments, release layer 110 is a mixture of metallic and non-metallic materials. Metallic candidates for the release layer may include nickel, chromium, titanium, gold, copper, manganese, iron, cobalt, tungsten, molybdenum, ruthenium, and tantalum, while non-metallic candidates may include metal oxides, nitrides, phosphates, and chromates. Release layer 110 can be disposed and cured by liquid spin coating. In other embodiments, release layer 110 may be a laminated film laminated onto carrier substrate 106. In some other embodiments, the bonding between the substrate 102 and the temporary carrier 106 can be achieved by direct bonding based on, for example, oxide-to-oxide or polyimide-to-polyimide, without the need for release layer 110.

[0061] RDL 108A is part of the interconnect structure 101 of IC structure 100A. RDL 108A includes one or more interconnect conductive paths formed through one or more conductive lines in a conductive line layer and one or more conductive vias (not shown separately) in a conductive via layer to route power and signals of a first circuit from one side of RDL 108A to a second circuit on the same or opposite side of RDL 108A. RDL 108A may include a sealing material (or, for example, a sealant for polyimide or oxide layers that facilitates direct or copper-mixed bonding) sealing the conductive line layer and conductive via layer. According to some embodiments, the sealing material comprises one or more dielectric materials, such as silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, polyimide, combinations thereof, or the like. Due to the use of RDL 108A in interconnect structure 101, the signal and power distribution of devices or circuits in IC structure 100A can meet design requirements. In this disclosure, an RDL (e.g., RDL 108A) formed on the main surface (e.g., main surface 102P1) of a circuit or device is referred to as main RDL 108A. Further structural details of main RDL 108A are discussed below.

[0062] According to some embodiments, substrate 102 is disposed above and bonded to main RDL 108A. Bonding of substrate 102 to main RDL 108A can be performed using thermal bonding, thermoforming bonding, flip-chip bonding, hybrid bonding, or the like. Although not described, conductive vias 104 of substrate 102 are electrically coupled to one of the conductive lines or vias of main RDL 108A to extend the signal transmission network or power transmission network of RDL 108A. Furthermore, the upper portion of substrate 102 is removed or thinned from the top of substrate 102, thus exposing the bottom surface of conductive vias 104. Removal or thinning of the upper portion of substrate 102 can be performed using CMP, polishing, dry etching (e.g., RIE), wet etching, or the like. Subsequently, conductive via 104 becomes TSV 104.

[0063] refer to Figure 2C The semiconductor device 100W is isolated into individual IC structures 100A after the structures having RDL 108A and RDL 108B are mounted on a wafer mounting frame and the carrier 106 is released. The monomerization or dicing process can be performed using diamond blades, lasers, plasma with a masking layer deposited on (e.g.) RDL 108A, wet etching, or a combination thereof to monomerize the semiconductor device 100W along dicing paths to form individual IC structures 100A. The interconnect structures 101 in the IC structure 100A include TSV wafers 122A, internal interconnect structures 108X such as internal pads and vias in RDL 108A and 108B, and edge interconnect structures 118X such as edge pads and vias in the RDL.

[0064] During monomerization or dicing, the area removed is called a dicing, sawing, or wafer run, and it is typically between 50 μm and 100 μm wide. The dicing saw can use a diamond blade rotating at 30,000 revolutions per minute and is cooled with deionized water. To expose edge pads or vias, preferably, the size of the edge pads or vias is comparable to the dicing width, and the cut is made immediately adjacent to the edge pads or vias (but not directly through them), followed by a light wet etching of the silicon as needed and permitted. To minimize underside chipping during mechanical blade dicing, it is advantageous to first cut the wafer placed on a carrier support and then release the carrier. Laser ablation dicing, which can achieve dicing widths of 10 μm, can also be used by first removing the fine-line layer on the dicing surface using a non-contact laser (and exposing the adjacent edge pads), followed by laser scribing and / or blade dicing to cut the remaining substrate. This process reduces problems such as debris, wafer breakage, and layer delamination. In laser ablation dicing, the laser heats the material to a temperature that causes the area under the laser spot to be ablated or simply evaporated. Alternatively, dicing can be performed using dry, liquid-free stealth dicing. Stealth dicing is a two-stage process where a laser beam (e.g., a pulsed Nd:YAG laser with a wavelength of 1064 nm for silicon) is first guided to scan along the desired dicing path to create defect areas, followed by expansion of the underlying thin film (attached to the wafer, then released from the wafer carrier) to induce cracking. Stealth laser dicing has the potential to replace blade dicing as the next-generation ultra-thin wafer monolithization technology supporting 3D IC packaging because it allows for faster dicing, higher accuracy, less damage, and smaller dicing path widths. Compared to mechanical and laser dicing, plasma dicing (also known as deep reactive ion etching) is a relatively new method using Bosch's dry etching process, which can achieve particle-free and contamination-free wafers through high-precision dicing. This method requires a custom photomask design for effective plasma dicing. It uses plasma gases such as sulfur hexafluoride to simultaneously etch all narrow dicing paths into the wafer, resulting in high precision, high throughput, and high quality. Plasma dicing can produce non-rectangular cuts, which is impossible with blade dicing. Plasma dicing causes minimal damage to the wafer surface or trench sidewalls, resulting in better wafer strength, improved device reliability, and longer device life. Plasma dicing is rapidly gaining popularity in the semiconductor industry as a preferred solution, especially as wafers become smaller, thinner, and more complex.

[0065] Due to the monomerization or dicing process, the IC structure 100A contains four sub-planes or side planes 100AS, but Figure 2DOnly two sub-planes 100AS are described. The TSV wafer 122A includes side surfaces 108S on its four sides, while the main RDLs 108A and 108B also include side surfaces 108S on their four sides. The side surfaces 102S of the TSV wafer 122A and the side surfaces 108S of the two main RDLs 108A and 108B together constitute or coincide with the sub-planes 100AS of the IC structure 100A. Through proper arrangement, a TSV 104 is formed in the TSV wafer 122A and, after monomerization or dicing, includes two TSV types: an internal TSV 104A and an edge TSV 104B. The internal TSV 104A is completely surrounded by the substrate 102 and the main RDLs 108A and 108B, while the edge TSV 104B has at least one side surface exposed through the side surfaces 102S of the substrate 102.

[0066] Similarly, main RDL 108A or 108B includes conductive pads 212 and conductive vias 214 formed by conductive components 202 (e.g., conductive lines and conductive vias), respectively. The conductive components 202 comprise two parts: an internal conductive component 202 and an edge conductive component 202. With appropriate arrangement, the conductive pads 212 and conductive vias 214 are formed in the IC structure 100A and, after monomerization or dicing processes, comprise two parts: internal conductive pads / vias 212 and 214 and edge conductive pads / vias 212 and 214. The internal conductive pads / vias 212 and 214 are completely surrounded by the substrate material and sealing material of the two main RDLs 108A and 108B, while the edge conductive pads / vias 212 and 214 have at least one side surface exposed through the side surface 108S of the main RDL 108A or 108B.

[0067] According to some embodiments, the edge conductive pad 212 has at least one upper surface exposed through the main surface 108P of the main RDL 108A or 108B. The inner or edge conductive pad 212 may be disposed on the uppermost conductive layer of the corresponding main RDL 108A or 108B, the uppermost conductive layer being furthest from the TSV wafer 122A. According to some embodiments, the conductive pad 212 is disposed parallel to the main surface 108P of the main RDL 108A or 108B. The conductive pad 212 may not reach the TSV wafer 122A. Furthermore, the edge conductive pad 212 has at least one side surface exposed through the sub-plane 100AS of the IC structure 100A or the sub-surface 108S of the main RDL 108A or 108B.

[0068] Similarly, according to some embodiments, the edge conductive via 214 has at least one upper surface exposed through the main surface 108P of the main RDL 108A or 108B. The edge conductive via 214 may be arranged to extend through the thickness (in the z-direction) of the respective main RDL 108A or 108B. According to some embodiments, the edge conductive via 214 is referred to herein as a TSV of the main RDL 108A or 108B. Furthermore, the edge conductive via 214 has at least one side surface exposed through the sub-plane 100AS of the IC structure 100A or the sub-surface 108S of the main RDL 108A or 108B.

[0069] Figure 2D A perspective view of a main RDL 108A or 108B according to various embodiments of the present disclosure is shown. The main RDL 108A or 108B includes a main surface 108P (e.g., an upper main surface 108P1 and a lower main surface 108P2) and four secondary (side) surfaces 108S (e.g., a front secondary surface 108S1, a rear secondary surface 108S2, a right secondary surface 108S3, and a left secondary surface 108S4). A plurality of conductive components 202 (e.g., conductive pads / vias 212) are formed on the main RDL 108A or 108B and exposed through the four secondary surfaces 108S. (Shown for illustration) Figure 2D Arrangement of conductive pads 212 of the main RDL 108A or 108B. Conductive pads 212 or other conductive components may be formed or exposed through one or more of the four secondary surfaces 108S.

[0070] As discussed above, in this disclosure, Figure 2C TSV 104 of the interconnect structure 101 (see Figure 2C 104A and 104B), conductive pad 212, conductive via 214, and all other conductive components are part of the interconnect structure 101 of IC structure 100A, collectively referred to as conductive assembly 202. TSV 104, conductive pad 212, and conductive via 214 are configured to form at least a portion of the interconnect structure 101 of IC structure 100A for communication with the interconnect structure 100A via the IC structure 100A. Figure 2C The two principal surfaces 108P (i.e., upper principal surface 108P1 and lower principal surface 108P2; see Figure 2D ) and through the four sub-surfaces 108S1 to 108S4 of the IC structure 100A (see Figure 2D Devices electrically coupled to the IC structure 100A or its package layer are fan-in or fan-out interconnected. According to some embodiments, the conductive vias 214 of TSV 104 and main RDLs 108A and 108B can be coupled to form a common TSV for the IC structure 100A. For example, the conductive via 214 on the right edge of the main RDL 108A (… Figure 2CThe right edge TSV 104 and the right edge conductive via 214 of the main RDL 108B constitute the stacked edge TSV of the IC structure 100A to extend through the substrate thickness of the IC structure 100A.

[0071] Figure 2E A cross-sectional view of an IC structure 100B according to various embodiments of the present disclosure is shown. The IC structure 100B is similar to the IC structure 100A in many respects (e.g., main RDL 108A, conductive pad 212, and conductive via 214), therefore, for the sake of brevity, details of such similar aspects are not repeated. The main difference between the IC structure 100A and the IC structure 100B is that the TSV chip 122A of the IC structure 100A is replaced by a semiconductor chip 122B in the IC structure 100B, and the main RDL 108B in the IC structure 100A is not present in the IC structure 100B. According to some embodiments, the semiconductor chip 122B may be at least one of a CPU chip, GPU chip, TPU chip, MEMS chip, AP chip, FPGA chip, ASIC chip, memory chip, transceiver chip, network interface chip, integrated photonics chip, packet buffer / router chip, or another suitable chip. The semiconductor chip 122B may include a substrate 102 comprising materials similar to... Figure 2D The material of the substrate 102 of the IC structure 100A shown is illustrated. Therefore, the semiconductor wafer 122B constitutes the substrate or body of the IC structure 100B. According to some embodiments, the semiconductor wafer 122B does not contain any edge interconnect structures 118X exposed through the side surface 102S of the semiconductor wafer 122B.

[0072] Figure 2F A cross-sectional view of an IC structure 100C according to various embodiments of the present disclosure is shown. The IC structure 100C is similar to the IC structure 100B in many respects (e.g., main RDL 108A, conductive pad 212, and conductive via 214), therefore, for the sake of brevity, details of such similar aspects are not repeated. Furthermore, the IC structure 100C includes a semiconductor wafer 122C, which may be at least one of a CPU wafer, GPU wafer, TPU wafer, MEMS wafer, AP wafer, FPGA wafer, ASIC wafer, memory wafer, transceiver wafer, network interface wafer, integrated photonics wafer, packet buffer / router wafer, or another suitable wafer. The semiconductor wafer 122C may contain components similar to... Figure 2DThe substrate 102 of the IC structure 100A shown herein is a substrate 102. The main difference between semiconductor wafer 122C and semiconductor wafer 122B is that semiconductor wafer 122C further includes edge interconnect structures 118X, such as edge conductive pads 222, exposed through the sub-plane or side surface 102S of semiconductor wafer 122C. According to some embodiments, the edge conductive pads 222 are electrically connected to conductive vias 214 of the main RDL 108A to establish stacked conductive vias for semiconductor wafer 122C. Therefore, semiconductor wafer 122C constitutes the body of IC structure 100C.

[0073] Figure 2G Various embodiments according to this disclosure are shown. Figures 2B to 2F The diagram shows a cross-sectional view of the main RDL 108A or 108B of the IC structure 100A, 100B, or 100C. Figure 2G As described, the main RDL 108A or 108B is formed by a first main wire / via layer 240 and a second main wire / via layer 250 below the first main wire / via layer 240. Each of the first main wire / via layer 240 and the second main wire / via layer 250 includes one or more conductive wires and conductive vias extending in a horizontal or vertical direction (all of which are part of the common conductive component 202 of the interconnection structure 101 in the main RDL 108A or 108B). The conductive wires or vias are electrically insulated by a dielectric layer called an intermetallic dielectric (IMD) layer. The IMD layer may contain one or more dielectric materials, such as silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, polyimide, or other suitable dielectric materials. Some conductive vias in the first primary wire / via layer 240 extend halfway in the vertical direction, while some conductive vias in the first primary wire / via layer 240 (e.g., conductive via 214-1) extend through the entire thickness of the first primary wire / via layer 240. Similarly, some conductive vias in the second primary wire / via layer 250 extend halfway in the vertical direction, while some conductive vias in the second primary wire / via layer 250 (e.g., conductive via 214-2) extend through the thickness of the second primary wire / via layer 250. Conductive vias 214-1 and 214-2 are electrically connected to form a stacked conductive via 214 through the primary RDL 108A or 108B. According to some embodiments, the first primary wire / via layer 240 includes two conductive wire layers and a conductive via layer between the two conductive wire layers, wherein conductive vias 216 are arranged in the conductive via layer to electrically connect two conductive wires in adjacent conductive wire layers. refer to Figure 2F and Figure 2G , Figure 2FThe conductive via 214 of the IC structure 100C shown is considered to be a conductive via connecting adjacent first and second main wire / via layers 240 and 250. According to some embodiments, the stacked conductive via 214 is part of the edge interconnect structure 118X and is exposed through the sub-surface 108S of the main RDL 108A or 108B. Although Figure 2G Only two main wire / via layers 240 and 250 are described, but this disclosure is not limited thereto. Other numbers of main wire / via layers and the configuration of conductive wires or conductive vias in each main wire / via layer are also within the scope of this disclosure.

[0074] Figures 3A to 3D Cross-sectional views of the structure at different stages of a method for manufacturing an IC structure 300A according to some embodiments of the present disclosure are shown. Figure 3D The IC structure 300A shown is a semiconductor packaging device. The IC structure 300A can be formed from a semiconductor device 300W, which is a wafer-level device, wherein the IC structure 300A is formed by separating the semiconductor device 300W through a monomerization or dicing process.

[0075] refer to Figure 3A It receives or provides the carrier substrate 106. Furthermore, a release layer 110 is formed above the carrier substrate 106, as... Figures 2A to 2C In this configuration, multiple semiconductor wafers 122D are arranged above the release layer 110. The semiconductor wafers 122D may include at least one of a CPU wafer, GPU wafer, TPU wafer, MEMS wafer, AP wafer, FPGA wafer, ASIC wafer, memory wafer, transceiver wafer, network interface wafer, integrated photonics wafer, packet buffer / router wafer, or other suitable wafer. Furthermore, multiple conductive pillars or vias 232 are formed at suitable spacing above the release layer 110 between adjacent semiconductor wafers 122D and sealed by a molding compound or suitable potting material (e.g., epoxy resin, such as Epotek 377). Figure 3B As shown in the diagram. Conductive vias 232 may be alternately formed in the semiconductor wafer 122D. Multiple semiconductor wafers 122D and conductive vias (pillars) 232, referred to herein as a reconfigured structure, are arranged on the carrier surface 110S or carrier substrate 106 of the release layer 110. The conductive vias 232 may contain conductive materials, such as tungsten, copper, titanium, tantalum, molybdenum, ruthenium, cobalt, aluminum, silver, gold, or another suitable material. The multiple semiconductor wafers 122D and conductive vias 232 may have substantially equal heights. According to some embodiments, the semiconductor wafers 122D and conductive vias 232 are arranged above the release layer 110 via a pick-and-place bonding process.

[0076] refer to Figure 3BThe reconstructed structure of the semiconductor device 300W is molded or sealed using a potting material (e.g., sealing material, molding material, or insulating component) 242. The potting material 242 may comprise a dielectric material, such as silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, epoxy-based molding material, polymeric material, or the like. A molding or deposition process is performed to deposit the potting material 242 between the semiconductor wafer 122D and a conductive via 232, which may be created prior to bonding the semiconductor wafer 122D and depositing the potting material. According to some embodiments, a planarization process (e.g., CMP, polishing, wet etching, dry etching (e.g., RIE), and / or another suitable etching step) is performed to remove excess potting material 242 and planarize the upper surface of the potting material 242 to expose the conductive via 232 from the upper surface of the semiconductor wafer 122D. According to some embodiments, since the conductive via 232 is within and laterally surrounded by the potting material 242, the conductive via 232 is also referred to herein as a through-hole (TMV) 232.

[0077] refer to Figure 3C The main RDL 108A is formed above the upper surface of the potting material 242, the semiconductor wafer 122D, and the TMV 232. The materials, configuration, and method for forming the main RDL 108A are similar to those in the reference. Figures 2B to 2G The materials, configurations, and methods described are omitted for brevity, avoiding repetitive descriptions of the main RDL 108A.

[0078] refer to Figure 3D The semiconductor device 300W is isolated into individual IC structures 300A by performing a monomerization or dicing process. Furthermore, the carrier substrate 106 is removed or detached from the semiconductor device 300W by releasing the release layer 110. Conductive pads / vias 212 / 214 are formed in the IC structure 300A through appropriate arrangement and include two types of pads / vias after the monomerization or dicing process: internal conductive pads / vias (not shown separately) 212 and edge conductive pads / vias 214. The properties of the conductive pads / vias 212 and 214 are similar to... Figure 2F The properties of IC structure 100C shown are presented herein, and for the sake of brevity, repeated descriptions are omitted. The main difference between IC structure 300A and IC structure 100C is that in IC structure 300A, the semiconductor wafer 122D is laterally surrounded or sealed by potting material 242, while in the case of 100C, only the edges of the wafer and RDL are exposed. The semiconductor wafer 122D and the potting material 242 constitute the main body of IC structure 300A.

[0079] Figure 3EA cross-sectional view of an IC structure 300B according to various embodiments of the present disclosure is shown. The IC structure 300B is similar to the IC structure 300A in many respects (e.g., the main RDL 108A, conductive pad 212, and conductive via 214), therefore, for the sake of brevity, details of such similar aspects are not repeated. The main difference between the IC structure 300A and the IC structure 300B is that, in addition to the semiconductor wafer 122D and the potting material 242, the body of the IC structure 300B further includes an edge TMV 232 that extends through or partially through the thickness of the semiconductor wafer 122D. The edge TMV 232 is part of the edge interconnect structure 118X.

[0080] Figure 3F A cross-sectional view of an IC structure 300C according to various embodiments of the present disclosure is shown. The IC structure 300C is similar to the IC structure 300B in many respects (e.g., main RDL 108A, conductive pad 212, conductive via 214, and TMV 232), therefore, for the sake of brevity, details of such similar aspects are not repeated. Furthermore, the IC structure 300C includes a semiconductor wafer 122D1, which replaces semiconductor wafer 122D and may be at least one of a CPU wafer, GPU wafer, TPU wafer, MEMS wafer, AP wafer, FPGA wafer, ASIC wafer, memory wafer, transceiver wafer, network interface wafer, integrated photonics wafer, packet buffer / router wafer, or another suitable wafer. The main difference between semiconductor wafer 122D and semiconductor wafer 122D1 is that semiconductor wafer 122D1 further includes portions of an edge interconnect structure 118X, such as edge conductive pads 222 exposed through the sub-plane or side surface 102S of semiconductor wafer 122D1. The materials, configuration, and methods for forming the edge conductive pads 222 of the IC structure 300C are similar to those in the reference. Figure 2F The materials, configuration, and methods for the conductive via 222 are described. Therefore, the body of the IC structure 300C includes a semiconductor wafer 122D1, a potting material 242, the conductive via 222, and a TMV 232. According to some embodiments, the main RDL 108A of the IC structure 300C includes a conductive via 214 electrically connected to the TMV 232 in the body of the IC structure 300C for creating stacked conductive vias for the IC structure 300C.

[0081] Figure 4A to 4G Cross-sectional views of the structure at different stages of a method for manufacturing an IC structure 400A according to some embodiments of the present disclosure are shown. Figure 4G The IC structure 400A shown is a semiconductor packaging device. The IC structure 400A can be comprised of a semiconductor device 100W (see...). Figure 4AThe semiconductor device 100W is a wafer-level device, wherein the IC structure 400A is formed by separating the semiconductor device 400W through a monomerization or dicing process.

[0082] refer to Figure 4A The substrate 102 is used to receive or supply semiconductor device 100W. Furthermore, conductive vias 104 are formed in the substrate 102. (See reference) Figure 4B For example, the bulk portion of the substrate 102 beneath the conductive via 104 is removed via CMP, grinding, or etching steps, transforming the conductive via 104 into a TSV 104. A monomerization or dicing process is then performed to separate the semiconductor device 100W into multiple TSV wafers 122E, similar to the reference process. Figure 2C The TSV chip 122A is described.

[0083] refer to Figure 4C A carrier substrate 106 is received or provided in a semiconductor device 400W. Furthermore, a release layer 110 is formed above the carrier substrate 106. A plurality of TSV wafers 122E and a plurality of TMVs 232 are arranged above the release layer 110 to form a reconstructed structure on the carrier surface 110S of the release layer 110 or on the carrier substrate 106. The TMVs 232 may be arranged alternately with the TSV wafers 122E. The TMVs 232 may contain conductive materials, such as tungsten, copper, titanium, tantalum, molybdenum, cobalt, ruthenium, aluminum, silver, gold, or another suitable material. The plurality of TSV wafers 122E and the plurality of TMVs 232 may have substantially equal heights. According to some embodiments, the TSV wafers 122E and TMVs 232 are arranged above the release layer 110 via a pick-and-place bonding process.

[0084] refer to Figure 4D A potting material (e.g., sealing material or molding material) 242 is used to mold or seal the semiconductor device 400W. A deposition process or molding process is performed to deposit the potting material 242 between the TSV wafer 122E and the TMV 232. According to some embodiments, a planarization process (e.g., CMP, polishing, wet etching, or another suitable etching step) is performed to remove excess potting material 242 and planarize the upper surface of the potting material 242, the upper surface of the TSV wafer 122E, and the upper surface of the TMV 232 to expose the TSV and TMV.

[0085] refer to Figure 4E The main RDL 108A is formed above the upper surfaces of the potting material 242, the TSV wafer 122E, and the TMV 232. The materials, configuration, and method for forming the main RDL 108A are similar to those in the reference. Figures 2B to 2G The materials, configurations, and methods described are omitted for brevity, avoiding repetitive descriptions of the main RDL 108A.

[0086] According to some embodiments, modifications may be made. Figure 4C and 4D The sequence of processing steps is shown in the diagram. For example, firstly, multiple TSV wafers 122E are arranged above the release layer 110, without TMV 232. Subsequently, a potting material 242 is deposited to fill the gaps between the TSV wafers 122E and the potting material 242 is planarized. An opening step is performed by, for example, laser to form vias between the TSV wafers 122E, which are then filled with a conductive material to form TMV 232. The vias may be laterally surrounded by the potting material 242.

[0087] refer to Figure 4F Another carrier substrate 116 is provided or received in another semiconductor device 401W. Another release layer 120 is formed over the carrier substrate 116. Furthermore, Figure 4E The structure is flipped so that its RDL 108A side is bonded to the second carrier substrate 116 and the carrier 106 is released by using the release layer 120. Subsequently, another main RDL 108B with surface treatment and bonding pads is formed on the other side of the TSV wafer 122E, encapsulation material 242 and TMV 232 supported by the second carrier 116. The materials, configuration and method of forming the carrier substrate 116, the release layer 120 and the main RDL 108B are similar to those in the reference. Figure 2C The materials, configuration, and methods for the carrier substrate 106, release layer 110, and main RDL 108A described herein will not be repeated in detail for the sake of brevity. Furthermore, the carrier substrate 116 is removed from the semiconductor device 401W by releasing the release layer 120 after wafer mounting.

[0088] refer to Figure 4G The monomerization or dicing process is performed to separate the reconstructed structure of the semiconductor device 401W into individual IC structures 400A. Through appropriate arrangement, the TMV 232 and the edge TSV 104B are formed within the IC structure 400A and include... - Two types of TMV after monomerization or dicing processes: internal TMV (not shown) and edge TMV 232, and - Two types of TSVs after monomerization or cutting processes: internal TSV and edge TSV 104B.

[0089] The properties of the conductive pad 212 and conductive via 214 of the main RDL 108A or 108B are similar to those of the conductive pad 212 and conductive via 214. Figure 2CThe properties of IC structure 100A shown are presented herein, and for the sake of brevity, repeated descriptions are omitted. The main difference between IC structure 400A and IC structure 100A is that IC structure 400A further includes potting material 242 filling the space between semiconductor wafer 122D and TMV 232. Semiconductor wafer 122D, TMV 232, and potting material 242 constitute the main body of IC structure 400A.

[0090] Figure 4H to 4N Cross-sectional views of IC structures 400B, 400C, 400D, 400E, 400F, 400G, and 400H according to various embodiments of the present disclosure are shown respectively. Since IC structures 400B, 400C, 400D, 400E, 400F, 400G, and 400H are considered variations of the base IC structure 400A in many respects, the following description will focus only on the differences between IC structure 400A and the other IC structures 400B to 400H.

[0091] refer to Figure 4H The main difference between IC structure 400B and IC structure 400A is that in IC structure 400B, the TSV wafer 122E containing the internal TSV is laterally surrounded or sealed by the potting material 242, and there is no edge TSV in IC structure 400B.

[0092] refer to Figure 4I The main difference between IC structure 400C and IC structure 400A is that IC structure 400C does not contain TMV 232. (Reference) Figure 4J IC structure 400D has neither edge TSV nor edge TMV, while both TSV and TMV exist in IC structure 400A.

[0093] Figure 4K to 4N The IC structures 400E, 400F, 400G, and 400H shown can be considered as multi-chip versions of the corresponding single-chip IC structures 400A, 400B, 400C, and 400D, with multiple chips arranged in the same package layer of IC structures 400E to 400H. (Reference) Figure 4KThe main difference between IC structure 400E and IC structure 400A is that, in addition to the first semiconductor wafer (i.e., TSV wafer 122E), IC structure 400E further includes a second semiconductor wafer 122D, which may have the same or different sizes. Therefore, the main body of IC structure 400E includes semiconductor wafer 122D, TSV wafer 122E, TMV 232, potting material 242, and RDLs 108A and 108B. Semiconductor wafer 122D and TSV wafer 122E are arranged in the same packaging layer. Semiconductor wafer 122D (which may also contain internal or edge TSVs) is laterally surrounded or encapsulated by potting material 242. Furthermore, in IC structure 400E, TMV 232 serves as an edge TMV, which can be electrically connected to the edge conductive vias 214 of the main RDL 108A and the edge conductive vias 214 of the main RDL 108B to form a stacked TSV extending through the entire thickness of IC structure 400E.

[0094] refer to Figure 4L The main difference between IC structure 400F and IC structure 400E is that in IC structure 400F, the TSV wafer 122E is further laterally surrounded or sealed by potting material 242 and IC structure 400F does not contain edge TSV.

[0095] refer to Figure 4M The main difference between IC structure 400G and IC structure 400E is that IC structure 400G, which contains edge TSV 104B, does not have edge TMV 232.

[0096] refer to Figure 4N The IC structure 400H can be considered as a combination of features of IC structures 400F and 400G, wherein the main body of the IC structure 400H only includes a semiconductor wafer 122D, a TSV wafer 122E, a potting material 242, and RDLs 108A and 108B, without edge TSVs and edge TMVs. According to some embodiments, the potting material 242 laterally surrounds and seals the semiconductor wafers 122D and 122E. The potting material 242 is exposed through two sub-planes 102S of the main body of the IC structure 400H.

[0097] Figure 5A A cross-sectional view of an IC structure 500A according to various embodiments of the present disclosure is shown. The main body of the IC structure 500A includes a semiconductor wafer 122F, a TMV 232, and a potting material 242. The semiconductor wafer 122F may include at least one of a CPU wafer, GPU wafer, TPU wafer, MEMS wafer, AP wafer, FPGA wafer, ASIC wafer, memory wafer, transceiver wafer, network interface wafer, integrated photonics wafer, packet buffer / router wafer, or another suitable wafer. The semiconductor wafer 122F is similar to... Figure 3F The semiconductor wafer 122D1 shown is an example in which the edge conductive pads 222 are replaced by multiple TSVs 104 (including internal TSVs 104A and edge TSVs 104B), one of which is exposed through the sub-plane 500AS of the IC structure 500A. Furthermore, compared to the aforementioned IC structure, the IC structure 500A further includes a sub-RDL 118A disposed on the sub-plane 500AS and electrically connected to the main RDL 108A.

[0098] Figure 5C More detailed description of various embodiments according to this disclosure Figure 5A The diagram shows a cross-sectional view of the sub-RDL118A of the IC structure 500A. Sub-RDL118A is similar to the reference design. Figure 2G The described main RDL 108, such as main RDL 108A or 108B. Figure 5C The sub-RDL 118A shown in the image contains similar features. Figure 2G The first and second main wire / via layers 240 and 250 of the main RDL 108A or 108B, and the two main wire / via layers 340 and 350. (Reference) Figure 5C The secondary RDL 118A includes a front interconnect surface 118F and a rear interconnect surface 118R opposite to the front interconnect surface 118F. The secondary RDL 118A is electrically connected to the edge interconnect structure 118X of the IC structure 500A, such as the edge TSV 104B of the semiconductor wafer 122F or the edge conductive pad 212 of the main RDL 108A. According to some embodiments, the secondary RDL 118A is considered part of the edge interconnect structure 118X of the IC structure 500A. Using this configuration, the main RDL 108A can be electrically connected to the semiconductor wafer 122F via the main surface 102P of the substrate 102 of the IC structure 500A and the main surface 108P of the main RDL 108A facing the substrate 102 through the internal interconnect structure 108X. Furthermore, it can be electrically connected to the semiconductor wafer 122F via the side surface (sub-plane) 102S of the main body of the IC structure 500A and the front interconnect surface 118F of the sub-RDL 118A through the edge interconnect structure 118X including the edge TSV 104B and the sub-RDL 118A. Therefore, compared to an IC structure without the sub-RDL 118A and other edge interconnects, the IC structure 500A provides enhanced wiring capabilities and design flexibility for the semiconductor wafer 122F.

[0099] Figure 5BA cross-sectional view of an IC structure 500B according to various embodiments of the present disclosure is shown. The IC structure 500B is substantially similar to the IC structure 500A in many respects; therefore, for the sake of brevity, descriptions of similar features are not repeated. The main difference between the IC structure 500B and the IC structure 500A is that, in addition to the sub-RDL 118A disposed on the left sub-plane 500BS1 of the IC structure 500B, the IC structure 500B further includes a sub-RDL 118B disposed on the right sub-plane 500BS2 of the IC structure 500B opposite to the sub-RDL 118A. The material and configuration of the sub-RDL 118B may be similar to those of the sub-RDL 118A, such as... Figure 5C As described herein. However, the other configurations and numbers of the main wire / via layers of sub-RDLs 118A and 118B are also within the scope of this disclosure. Therefore, sub-RDL 118B is also considered to be part of the edge interconnect structure 118X of IC structure 500B and is electrically connected to main RDL 108A.

[0100] Figures 6A to 6E Cross-sectional views of structures at different stages of a method for manufacturing a semiconductor package 600A according to various embodiments of the present disclosure are shown. According to some embodiments, Figure 6E The IC structure 600A shown is a semiconductor packaging device. The IC structure 600A can be formed from a semiconductor device 600W, which is a wafer-level device. Figure 6E The IC structure 600A is formed by separating the semiconductor device 600W through a monomerization or dicing process.

[0101] refer to Figure 6A A carrier substrate 106 is provided or received. A release layer 110 is formed above the upper surface of the carrier substrate 106. A plurality of semiconductor wafers, such as semiconductor wafers 122E, 122G, and 122H, are fabricated. The TSV wafer 122E can be replaced by the aforementioned semiconductor wafers, such as semiconductor wafers 100A, 100B, 100C, 300A, 300B, 300C, and 400A to 400H. The TSV wafer 122E includes a plurality of TSVs 104 and a main RDL 108A on the upper surface of the TSVs 104. According to some embodiments, the semiconductor wafers 122G or 122H may be a CPU wafer, a GPU wafer, a TPU wafer, a MEMS wafer, an AP wafer, an FPGA wafer, an ASIC wafer, a memory wafer, a transceiver wafer, a network interface wafer, an integrated photonics wafer, a packet buffer / router wafer, another suitable wafer, or at least one of the aforementioned semiconductor wafers.

[0102] The semiconductor wafers 122E, 122G, and 122H may be similar or different in size or dimensions. For example, semiconductor wafers 122E, 122G, and 122H may have substantially the same or different height, length, or width.

[0103] A pick-and-place process is performed to pick up a known good die (KGD) from semiconductor wafers 122E, 122G, and 122H and bond the KGD over release layer 110. After semiconductor wafer 122H is placed over release layer 110, a bonding layer or wafer attachment layer 160 is formed on semiconductor wafer 122H. Bonding layer 160 may facilitate attachment of semiconductor wafer 122G to semiconductor wafer 122H. According to some embodiments, bonding layer 160 is a wafer attachment film, an array of microbumps configured to perform flip-chip bonding, a direct bonding layer configured to produce a bonding, or a hybrid bonding layer. According to some embodiments, semiconductor wafers 122G and 122H are vertically stacked. Semiconductor wafer 122E may be arranged side-by-side adjacent to stacked semiconductor wafers 122G and 122H in the same package layer. Semiconductor wafers 122E, 122G, and 122H may have substantially the same or different sizes.

[0104] refer to Figure 6B A 600W semiconductor device is molded or sealed using a potting material or suitable material 252. The material and configuration of the potting material 252 are similar to those of the potting material 242 and may include a molding compound and a thick-film photoresist. A molding or deposition process is performed to deposit the potting material 252 between and embed it into semiconductor wafers 122E, 122G, and 122H. The potting material 252 may have a height greater than the height of semiconductor wafers 122E, 122G, and 122H. According to some embodiments, a planarization process (e.g., CMP, polishing, etching (dry and / or wet), or another suitable etching step) is performed to remove excess potting material 252 and produce a uniform upper surface of the potting material 252 (see [link to documentation]). Figure 6B ).

[0105] Figure 6C This describes the formation of multiple vias 252R within the potting material 252. The vias can be created by laser ablation. Alternatively, if a thick-film photoresist is used as the sealing material, it can be laminated, patterned, and developed to create vias extending from the upper surface of the potting material 252 to the bonding pads, and to give the semiconductor wafers 122E, 122G, and 122H appropriate surface treatments, wherein the pads are exposed beneath the vias 252R.

[0106] refer to Figure 6DFor example, a suitably passivated conductive material is deposited in the via 252R by PVD, CVD, ALD, electroplating, or the like. The conductive material may include at least one of tungsten, copper, titanium, molybdenum, cobalt, ruthenium, tantalum, aluminum, silver, gold, and other suitable materials. Therefore, one or more conductive pillars 224 are formed above and electrically connected to the semiconductor wafer 122G. At least one conductive pillar 224 formed on the sub-plane 600AS2 of the semiconductor device 600W (currently, this sub-plane 600AS2 is still an imaginary plane before the dicing process) is configured as an edge conductive pillar 224. Furthermore, one or more conductive plugs 234 are formed above and electrically connected to the TSV wafer 122E and / or the semiconductor wafer 122H. Therefore, the main body of IC structure 600A includes semiconductor wafers 122E, 122H, and 122G, main RDL 108A, bonding layer 160, potting material 252, conductive vias 104, internal conductive pillars 224, conductive plugs 234, and edge conductive pillars 224. According to some embodiments, TSV 104, conductive pillars 224, and conductive plugs 334 have substantially the same or different lengths.

[0107] Another main RDL 108C is formed above the upper surface of the potting material 252 and is electrically connected to the semiconductor wafers 122E, 122G, and 122H. According to some embodiments, the main RDL 108C includes at least an edge conductive pad 212 on the sub-plane 600AS1 or 600AS2 of the semiconductor wafer 600W (currently, the sub-planes 600AS1 and 600AS2 are still imaginary planes before the dicing process).

[0108] Subsequently, after the wafer is mounted, the carrier substrate 106 is removed or detached from the semiconductor device 600W by removing or releasing the release layer 110 from the semiconductor device 600W. Figure 6E This demonstrates the individual IC structures 600A formed by isolating a semiconductor device 600W into individual IC structures 600A using a monomerization or dicing process. With appropriate arrangement, edge conductive pads 212, edge TSVs 104B, and edge conductive pillars 224 can be formed and exposed through at least one of the sub-planes 600AS1 and 600AS2 of the IC structure 600A. A main RDL 108C is configured to be electrically connected to semiconductor wafers 122E, 122G, and 122H via internal interconnect structures 108X (e.g., conductive plugs 234 and internal conductive copper pillars 224). Furthermore, the main RDL 108C is configured to be electrically connected to semiconductor wafers 122E, 122G, and 122H via edge interconnect structures 118X (e.g., edge TSVs 104 and edge conductive pillars 224). Therefore, wiring distances can be reduced by means of the edge interconnect structure 118X.

[0109] refer to Figure 6E and Figure 5A and 5B According to some embodiments, the secondary RDLs 118A and 118B of IC structures 500A and 500B are adapted to IC structure 600A. In other words, although not shown separately, secondary RDLs 118A or 118B can be arranged on secondary surfaces 600AS1 and 600AS2 respectively to be electrically connected to the main RDL 108C and the edge TSV 104 (in Figure 6E Use 104 instead of 104B to match Figure 6D (Consistent) and / or conductive components 202 of edge conductive posts 224. According to some embodiments, when the IC structure 600A includes edge conductive plug 234, sub-RDL 118A or 118B may be electrically connected to this edge conductive plug 234.

[0110] The embodiments of this disclosure discussed above offer advantages. The common edge conductive component 202 may appear in the form of an edge conductive pad 212, an edge conductive via 214, an edge TSV 104, or an edge TMV 224, as... Figure 6E As shown in the diagram. Additionally, primary RDLs 108A and 108C or secondary RDLs 118A and 118B (see...) Figure 5B It can form conductive pads 212 with or without edges, conductive vias 214 with or without edges, conductive TSVs 104 with or without edges, and conductive vias 222 with or without edges (see...). Figure 2F and 3F ), with or without edge TMV 232 ( Figure 5B The edge conductive assembly 202 may or may not have edge conductive pillars 224 and edge conductive plugs 234. The edge conductive assembly 202 may be disposed on the periphery of the IC structure or the periphery of the RDL. Furthermore, the edge conductive via 222 may cover all or part of the thickness of the corresponding IC structure body. Additionally, edge TSV 104, edge TMV 232, edge conductive pillars 224, and edge conductive plugs 234 may appear inside the IC structure to facilitate internal interconnections of IC structures in different stacked layers and edge interconnections arranged on the sides.

[0111] Conductive pillar 224, conductive plug 234 and TMV 232 ( Figure 5BThe via is formed based on the opening and filling process steps, and can be generated by various methods, including bonding vertical conductors (e.g., Cu coated with palladium (Pd)), laser vias, and through-film photosensitive thick film (TPTF) methods. The bonding vertical conductor method follows the high-copper pillar process steps, replacing the high-copper pillar formation steps with conductor bonding. When using Pd-coated Cu, thin gold (Au) can be used as a bonding pad. In the laser via method, the IC is first bonded to the carrier substrate 106, followed by, for example, overmolding, planarization, laser via opening, Cu plating on the via sidewalls, via electroplating or filling with photosensitive polymer or solder, planarization, RDL generation, carrier release, and cutting. The TPTF process flow consists of the following sequential steps: laminating a thick photosensitive film onto the bonding IC, multiple or single exposures and development to create TMV vias (i.e., through-holes penetrating the photosensitive thick film), barrier / seed layer deposition, Cu plating, via filling as needed, backside grinding / planarization, RDL generation, carrier release, and dicing. The IC here can have both RDL and TSV. Multiple exposures provide process freedom for forming vias of different sizes and depths. TMV-related processes can accommodate multiple ICs in the xy plane and vertical z-axis, such as... Figure 6E As explained in the text. Furthermore... Figure 6E The semiconductor wafers 122E, 122H and / or 122G in the semiconductor wafers can be bonded to Figure 6A Solder bumps or copper pillar microbumps are pre-fabricated on the carrier substrate 106. After wafer bonding, overmolding can occur, followed by planarization and RDL generation.

[0112] Figures 7A to 7H Cross-sectional views of structures at different stages of a method for manufacturing a semiconductor package 700A according to various embodiments of the present disclosure are shown. According to some embodiments, Figure 7H The semiconductor package 700A shown is a semiconductor packaging device. The semiconductor package 700A can be formed from semiconductor devices 700W and 701W, which are wafer-level devices. The semiconductor package 700A is formed by separating the semiconductor device 701W through a monomerization or dicing process.

[0113] Figures 7A to 7C This illustrates that multiple IC structures 142 form a multi-high IC stack 322. (Reference) Figure 7A The carrier substrate or support substrate 106 is provided or received. A release layer 110 is formed above the upper surface of the carrier substrate 106. A pick-and-place process is performed to pick up multiple known good IC structures 142 (e.g., IC structure 142A) and to bond the IC structures by means of a bonding layer to form a first layer of a low-profile IC stack 312 at appropriate spacing above the release layer 110 (e.g., ...). Figure 7A(As shown in the figure) to improve yield. According to some embodiments, IC structure 142 may be composed of IC structures 400A, 400B, 400C, 400D, 400E, 400F, 400G, 400H, 500A, 500B and / or 600A; however, other types of IC structures (e.g. IC structures 100A, 100B, 100C, 300A, 300B, 300C and / or similar) are also possible. Figure 7B The IC structure 142, which is illustrated for demonstration purposes and includes 142A, 142B, 142C, and 142D, may contain memory and / or processor analog chips. The IC structure 142 may also include MEMS devices, passive devices, and analog, mixed-signal, and digital signal processing ICs.

[0114] refer to Figure 7B Multiple IC structures 142 (e.g., IC structure 142B) are bonded to corresponding IC structures 142A to form a second layer of a low-profile IC stack 312. Bonding IC structures 142B to IC structures 142A can be achieved using thermocompression bonding (TCB), flip-chip bonding, hybrid bonding, direct bonding, bonding via an adhesive layer (e.g., Ti / Au), wafer attachment film or paste, or other suitable bonding processes. The process of forming the low-profile IC stack 312 can continue until a predetermined number of layers (total number of layers) K is reached, where the number of layers K is a natural number. Figure 7B In the example depicted, the number of levels K is 4, meaning that each dwarf IC stack 312 consists of four stacked IC structures 142A, 142B, 142C, and 142D. This process produces a known good dwarf IC stack. Alternatively, a dwarf IC stack 312 can be formed by joining multiple 142Ds to multiple 142Cs, wherein the resulting structures are further processed as needed and then released, a known good structure is picked up, a known good structure is joined to multiple known good 142Bs, and so on, and the process is repeated until... Figure 7B A short IC stack 312 is formed in the middle.

[0115] After the first low-profile IC stack 312 is completed, a release (or bonding) layer 140 of suitable thickness is formed over each low-profile IC stack 312. The material of the release layer 140 may differ from the material of the release layer 110 to avoid interference between them during the respective release process. Subsequently, another set of known good low-profile IC stacks 312 is formed over the release layer 140 of the first known good low-profile IC stack 312. Figure 7B As shown, the formation of the low-profile IC stack 312 and the formation of the release layer 140 are performed alternately until a predetermined L low-profile IC stacks are reached to form Figure 7CThe high IC stack 322 is formed by stacking the low IC stacks 312, where the number of low IC stacks L (i.e., the total number of low IC stacks) is a natural number. In the depicted example, the number of low IC stacks L is 4. Therefore, the low IC stacks 312 are stacked to form the high IC stack 322 through the release layer 140.

[0116] refer to Figure 7C Each high IC stack 322 is released from the carrier substrate 106 by releasing the release layer 110. Therefore, four low IC stacks 312 and three release layers 140 are arranged alternately to form a row of high IC stacks 322. In the depicted example, there are three rows of high IC stacks 322 in the semiconductor device 700W. The numbers K, L, and the number of columns introduced above are for illustrative purposes. Other numbers are also within the scope of this disclosure.

[0117] Figures 7D to 7H This describes a semiconductor package 700A formed by stacking multiple high-performance ICs (322). (Reference) Figure 7D The carrier substrate 116 is provided or received. A release layer 120 is formed above the upper surface of the carrier substrate 116. A pick-and-place process is performed to pick up and join multiple known good high-quality IC stacks 322 and arrange them at appropriate spacing above the release layer 120 to improve yield. The high-quality IC stacks 322 are reconstructed on the carrier substrate 116 and bonded to the release layer 120 through their side surfaces. In other words, the high-quality IC stacks 322 are laid down such that the vertically stacked IC structures 142 in the high-quality IC stacks 322 are positioned upright in the xy plane or in the IC length and width directions, with one of their four side surfaces bonded to the release layer 120.

[0118] refer to Figure 7E The reconstructed high IC stack 322 of the semiconductor device 701W is molded or sealed using potting material 262. The material and configuration of potting material 262 are similar to those of potting materials 242 or 252. A molding or deposition process is performed to deposit potting material 262 between the laid-down high IC stack 322. According to some embodiments, a planarization process (e.g., CMP, polishing, etching (dry and / or wet) or another suitable etching step) is performed to remove excess potting material 262 and planarize the upper surface of potting material 262 so that it is flush with the side surfaces of the high IC stack 322. Subsequently, an edge interconnect structure RDL 118A is formed over or bonded to at least the edge interconnects on the side surfaces (sub-planes) of the high IC stack 322.

[0119] Figure 7FThe diagram illustrates the formation of another edge interconnect structure RDL 118B on the opposite surface of the high IC stack 322, opposite to sub-RDL 118A. Another carrier substrate 126 is provided or received in another semiconductor device 702W. Another release layer 130 is formed over the carrier substrate 126 to facilitate the formation of sub-RDL 118B. The materials, configuration, and methods for forming the carrier substrate 126 and sub-RDLs 118A and 118B are similar to those described above. Figure 5B The sub-RDL 108A and 108B described in the document Figure 2C The main RDLs 108A and 108B are used in this context, so for the sake of brevity, details of such similar features will not be repeated. The material of release layer 130 may differ from that of release layer 120 to avoid interference between them during the respective release processes. Subsequently, in Figure 7E After the semiconductor structure 701W is bonded to the second carrier 126 on the side of RDL 118A, the carrier substrate 116 is removed from the semiconductor device 701W by removing the release layer 120. The edge interconnect RDL structure 118B is formed or bonded to the lower sub-surface of the high IC stack 322, which is opposite to the upper sub-surface of the high IC stack 322.

[0120] refer to Figure 7G A monomerization or dicing process is performed to isolate the semiconductor device 701W into a high-IC stack structure 700L. The monomerization or dicing process may be performed to cut through the semiconductor device 701W at the location of the potting material 262, wherein the potting material 262 is cleaned by, for example, dry and / or wet etching, while taking care to keep each high-IC stack 322 intact during the dicing process. According to some embodiments, a wet etching or cleaning process is performed to remove residual potting material 262 remaining on the high-IC stack structure 700L.

[0121] Figure 7H This describes the formation of individual semiconductor packages 700A (i.e., low-profile IC stacked structures) from corresponding IC structures (i.e., high IC stacked structures 700L). Release processes, monomerization processes, and / or dicing processes are performed to separate release layers 140 from each of the high IC stacked structures 700L. Figure 7B This allows the different semiconductor packages 700A (i.e., the respective low-profile IC stacks 312 containing edge interconnect RDL structures 118A and 118B) to be separated from each other. According to some embodiments, etching or dicing processes are performed to facilitate the release process, such as by dicing, continuous-wave laser beam, dry etching (e.g., by plasma), and / or wet etching to cut through the sub-RDLs 118A and 118B at the location of the release layer 140. Figure 7HAs described, the semiconductor package 700A includes a stack of low-profile IC stack 142 and two sub-RDLs 118A and 118B disposed on two side surfaces of the low-profile IC stack 142. Sub-RDLs 118A and 118B can help increase the wiring area of ​​IC structure 142, reduce wiring distance, and improve the wiring capability and design flexibility of semiconductor package 700A.

[0122] Figure 7I and 7J Cross-sectional views of semiconductor packages 700B and 700C according to various embodiments of the present disclosure are shown. Semiconductor packages 700B and 700C can be considered as detailed versions of semiconductor package 700A, with some minor variations. For example, refer to... Figure 7I The semiconductor package 700B includes three IC structures 142A, 142B, and 142C stacked vertically. Each IC structure 142A, 142B, or 142C includes a corresponding body and a corresponding main RDL 108A, 108B, or 108C disposed on a corresponding upper main surface 142AP, 142BP, or 142CP on its top side. The body of IC structure 142A includes a semiconductor wafer 143A, an edge TMV 232, an edge TSV 104, and a potting material 242, wherein the semiconductor wafer 143A includes a plurality of TSVs 104 and a plurality of TMVs 232. Similarly, the body of IC structure 142B includes a semiconductor wafer 143B, an edge TMV 232, and a potting material 242, wherein the semiconductor wafer 143B includes a plurality of TSVs 104 and a plurality of TMVs 232. Similarly, the main body of IC structure 142C includes a semiconductor wafer 143C, edge TMV 232, and encapsulation material 242, wherein the semiconductor wafer 143C includes multiple TSVs 104 and multiple TMVs 232. IC structures 142A, 142B, and 142C may be of different sizes and may contain various combinations of internal and edge interconnects covering the TSVs and TMVs. According to some embodiments, semiconductor wafers 143A, 143B, or 143C may be at least one of a CPU wafer, GPU wafer, TPU wafer, MEMS wafer, AP wafer, FPGA wafer, ASIC wafer, memory wafer, transceiver wafer, network interface wafer, integrated photonics wafer, packet buffer / router wafer, or another suitable wafer (e.g., an interconnect wafer, such as an interposer). According to some embodiments, semiconductor package 700B includes only a single sub-RDL 118A disposed on the left sub-plane 700BS of semiconductor package 700B.

[0123] According to some embodiments, IC structures 142A, 142B, and 142C are characterized by substantially equal or unequal thicknesses T1, T2, and T3, respectively. Each IC structure 142A, 142B, or 142C may contain a thickness ranging from about 30 μm to about 775 μm.

[0124] Sub-RDL 118A includes a front interconnect surface 118F and a rear interconnect surface 118R opposite to the front interconnect surface 118F. Sub-RDL 118A is electrically connected to the sub-plane 700BS via the front interconnect surface 118F to facilitate wiring efficiency and flexibility. For example, sub-RDL 118A includes conductive traces or wires 172 that extend along the longitudinal axis of sub-RDL 118A and electrically connect the edge conductive pads 212 of the main RDL 108C and the edge TSV 104B of semiconductor wafers 143C and 143A, while bypassing the bodies of IC structures 142A, 142B, and 142C. Furthermore, sub-RDL 118A can be used to connect other circuitry via the rear interconnect surface 118R. For example, sub-RDL 118A includes one or more conductive bumps, microbumps, or bump pad arrays 244 (all of which are external connections referred to as sub-RDL 118A) on the back interconnect surface 118R, wherein the conductive bumps 244 are configured to electrically connect sub-RDL 118A to circuitry or layers adjacent to sub-RDL 118A.

[0125] refer to Figure 7J Semiconductor package 700C is similar to semiconductor package 700B in many respects, and for the sake of brevity, descriptions of such similar features will not be repeated. According to some embodiments, semiconductor package 700C includes three IC structures 142D, 142E, and 142F stacked together, wherein each IC structure 142D, 142E, or 142F includes a respective body and two respective main RDLs 108A / 108D, 108B / 108E, and 108C / 108F disposed on respective upper and lower main surfaces 142AP, 142BP, and 142CP.

[0126] The difference between semiconductor package 700C and semiconductor package 700B further lies in the following: In the case of 700C, the sub-RDL 118A disposed on the sub-plane 700CS1 of semiconductor package 700C includes an array of conductive pads 254 on the rear interconnect surface 118R of sub-RDL 118A. According to some embodiments, the conductive pads 254 have an upper surface coplanar with the rear interconnect surface 118R of sub-RDL 118A. This coplanar arrangement of sub-RDL 118A facilitates hybrid bonding with other circuits or layers. Additionally, compared to semiconductor package 700B, semiconductor package 700C further includes another sub-RDL 118B disposed on the sub-plane 700CS2. The interconnect configuration in sub-RDL 118B may be similar to or different from the interconnect configuration in sub-RDL 118A. Sub-RDL 118B may include external connections, such as microbumps, hybrid bonding layers, direct bonding layers, flexible circuit connections, combinations thereof, or the like. In addition, the secondary RDL 118A (or 118B) includes conductive traces or wires 172 that extend along the longitudinal axis of the secondary RDL 118A and are electrically connected to the edge conductive pads 212 of the main RDLs 108C and 108B and the edge conductive vias 214 of the main RDL 108D, while bypassing the bodies of the IC structures 142D, 142E and 142F to achieve power supply and signal transmission across the chip and multiple surfaces.

[0127] According to some embodiments, IC structures 142D, 142E, and 142F have substantially equal or unequal thicknesses T4, T5, and T6, respectively. Each IC structure 142D, 142E, or 142F may contain a thickness ranging from about 30 μm to about 775 μm.

[0128] Semiconductor packages 700A, 700B, and 700C allow for power supply and signal transmission across the die and multiple sides via an internal interconnect structure 108X covering the TMV, main RDL 108, and TSV; an edge interconnect structure 118X covering the secondary RDL 118 and edge interconnects; and both the internal interconnect structure 108X and the edge interconnect structure 118X. These semiconductor packages with multi-sided power supply and signal transmission enable "PPAC optimization per cubic millimeter" for 3D ICs (using low-profile IC stacks as an example in this paper), where the vertical dimension of the 3D IC can be extended to encompass the IC, interposer, IC packaging substrate, IC package, and system PCB (e.g., see...). Figure 7I and 7J ).

[0129] refer to Figure 7A and 7BAccording to some embodiments, the carrier substrate 106 can be a 12-inch wafer carrier or a larger panel carrier to improve carrier utilization. (Reference) Figure 7B The release layer 140 may also be a permanent bonding layer, such as a die attach film (DAF) for stacked wafer packaging, similar to the film used to bond wafers (IC structures, 142A to 142D) to jointly form a low-profile 3D IC stack 312, wherein the film is pre-placed on the back side of the wafers 142A to 142B while still in wafer form, and the wafer / film combination is picked up for wafer bonding of wafer tape after wafer dicing.

[0130] refer to Figure 7E As previously described, a reconstructed high IC stack 322 of the semiconductor device 701W is molded or sealed using potting material 262. The material and configuration of potting material 262 are similar to those of potting materials 242 or 252. A molding or deposition process is performed to deposit potting material 262 between the laid-down high IC stack 322. According to some embodiments, an overmolding operation is performed to deposit potting material 262. According to some embodiments, potting material 262 may also be a permanent bonding layer, such as a molding compound or encapsulation material. According to some embodiments, a planarization process (e.g., CMP, polishing, etching (dry and / or wet) or other suitable etching operation) is performed to remove excess potting material 262 and planarize the upper surface of potting material 262, making it flush with the side surfaces of the high IC stack 322, which are also planarized simultaneously with the potting material 262. Subsequently, an edge interconnect structure RDL 118A is formed or bonded to at least one edge interconnect on the side surface (sub-plane) of the high IC stack 322. According to some embodiments, a bumping process is performed for the wafer edge interconnect, wherein a plurality of bonding pads are formed on one side of the high IC stack 322 or RDL 118A to electrically connect the high IC stack 322 to the RDL 118A.

[0131] refer to Figure 7F Other carrier substrates 126 are provided or received in other semiconductor devices 702W. Other release layers 130 are formed over the carrier substrate 126 to facilitate the formation of RDL 118B. Figure 7E The semiconductor device 701W is bonded to a second carrier 126 on the side of RDL 118A. Subsequently, the carrier substrate 116 is released from the semiconductor device 701W by releasing the release layer 120. According to some embodiments, after removing the carrier substrate 116 and before forming RDL 118B, a planarization operation is performed on the exposed sub-surfaces of the high IC stack 322 and the potting material 262. The edge interconnect RDL structure 118B is formed or bonded to the lower sub-surface of the high IC stack 322 opposite to the upper sub-surface of the high IC stack 322.

[0132] refer to Figure 7G The carrier substrate 126 is removed or detached from the semiconductor device 702W by releasing the release layer 130. A monomerization or dicing process is performed to separate the semiconductor device 702W into high-IC stack structures 700L. The monomerization or dicing process may be performed to cut through the semiconductor device 702W at the location of the potting material 262, which may bypass metal lines or even dielectric passivation layers, to facilitate clean monomerization of the etching or dicing operation, wherein the potting material 262 is cleaned by, for example, dry and / or wet etching, while taking care to keep each high-IC stack structure 700L intact during the dicing process. According to some embodiments, a wet etching or cleaning process is performed to remove residual potting material 262 remaining on the high-IC stack structure 700L. According to some embodiments, a planarization operation is performed on the exposed main surface of the high-IC stack structure 700L to remove residual potting material 262.

[0133] refer to Figure 7H Individual semiconductor packages 700A (i.e., low-profile IC stack structure 312) are formed from corresponding IC structures (i.e., high IC stack structure 700L). Release processes, monomerization processes, and / or dicing processes are performed to remove the release layer 140 from each of the high IC stack structures 700L. Figure 7B This allows the different semiconductor packages 700A (i.e., the respective low-profile IC stacks 312 containing edge interconnect RDL structures 118A and 118B) to be separated from each other. According to some embodiments, etching or dicing processes are performed to facilitate the release process, such as by dicing, continuous-wave laser beam, dry etching (e.g., by plasma), and / or wet etching to cut through the sub-RDLs 118A and 118B at the location of the release layer 140, which may bypass metal lines or even dielectric passivation layers, to promote clean monolithization of the etching or dicing operation. According to some embodiments, a combination of wet etching, dicing, and planarization operations is performed.

[0134] Figure 8A Perspective and cross-sectional views of an edge pad semiconductor wafer (or, hereinafter, a semiconductor wafer) 11 according to some embodiments of the present disclosure are shown. The edge pad semiconductor wafer 11 has a top surface 11P1, a bottom surface 11P2, and four sidewalls 11S1, 11S2, 11S3, and 11S4, wherein the area of ​​the top / bottom surface 11P1 / 11P2 is significantly larger than the area of ​​the sidewalls 11S1, 11S2, 11S3, and 11S4 (e.g., ...). Figure 8A (As shown in the illustration). The semiconductor wafer 11 is further included. Figure 8A The edge pad semiconductor wafer 11 shown in the figure has an "edge pad" 19 in the form of a peripheral pad at its periphery, side or sidewall (e.g., sidewall 11S1, 11S2, 11S3 and / or 11S4).

[0135] Furthermore, in this disclosure, the plurality of edge pad semiconductor wafers 11 arranged in a stack / layer may be named a novel high-bandwidth memory (NuHBM) or NuHBM system. Hereinafter, a NuHBM system may also be referred to as a memory stack or memory layer (or NuHBM stack or NuHBM layer), which includes, for example... Figure 8A The multiple edge pad semiconductor wafers or exemplary semiconductor wafers 11 shown in the figure.

[0136] refer to Figure 8B In one embodiment, the edge pad semiconductor wafer 11 includes a memory wafer 1021 and a redistribution layer (RDL) 15 located above the top surface of a memory wafer 1021. The memory wafer 1021 may also be a DRAM wafer. In one embodiment, the memory wafer 1021 of the edge pad semiconductor wafer 11 does not have through-silicon vias (TSVs), and the memory wafer 1021 includes edge pads along one of its side surfaces. One or more signal pads 12 and sealing rings 13 surrounding the signal pads 12 are present in the memory wafer 1021. The memory wafer 1021 may include a BEOL (back-end processing) region disposed on the front side of the memory wafer 1021. In one embodiment, each edge pad 19 of each semiconductor wafer 11 includes a wire 17 in the redistribution layer 15 (RDL), and the wire 17 is electrically connected to the signal pad 12 in the back-end processing (BEOL) region of the semiconductor wafer 11, the signal pad 12 being surrounded by a sealing ring 103. Reference Figure 8B In the substrate of memory chip 1021, all signal pads 12 are located in the area defined by the sealing ring 13 of the substrate, and edge pads 19 are located in RDL 15 and electrically connected to the signal pads 12 in the BEOL area (see...). Figure 8B If necessary, an additional edge redistribution layer (RDL) can be formed to cover the edge pads 19 of the NuHBM stack, so as to create larger edge bumps or larger edge pads in the edge RDL.

[0137] In some embodiments, the interconnect structure of RDL 15 may include multiple wire layers, multiple conductive vias, and one or more edge pads 19. The wires, conductive vias, and edge pads together constitute various conductive paths of the interconnect structure. Figure 8B The wires 17 and vertical conductive vias are arranged in RDL 15 and electrically connect the signal pad 12 to the edge pad 19.

[0138] Figure 8C This image shows a cross-sectional view of a semiconductor wafer 103 containing a plurality of edge pad semiconductor wafers, representing a portion of some embodiments of the present disclosure. In some embodiments, such as Figure 8CAs shown, multiple edge pad semiconductor wafers (e.g., exemplary edge pad semiconductor wafers 10a and 10b) are formed on semiconductor wafer 103. The boundaries of adjacent edge pad semiconductor wafers 10a and 10b are defined by dicing regions SL. In some embodiments, each edge pad semiconductor wafer 10a or 10b includes a memory wafer 1031a or 1031b and an RDL 15a or 15b disposed above the corresponding memory wafer 1031a or 1031b. The memory wafer 1031a or 1031b further includes signal pads 12a or 12b and sealing rings 13a or 13b located in the memory wafers 1031a and 1031b, respectively. In addition, the RDL 15a or 15b includes one or more wires 17a or 17b or vias 18a or 18b, whichever is suitable for the RDL design, electrically connected to the corresponding signal pad 12a or 12b, respectively. RDL 15a (or 15b) further includes stacked dielectric or separating layers 15a1, 15a2, and 15a3 (or 15b1, 15b2, or 15b3), and a wire 17a or 17b is located therein. In some embodiments, after wafer dicing is performed in the dicing region SL, the exposed portion of the wire or via 17a or 17b serves as an edge pad, as previously described, for example... Figure 8B As shown in the illustration. In one embodiment, the dielectric layer or separation layer may be made of SiO2.

[0139] Figure 8D and 8E A cross-sectional view of an edge pad semiconductor wafer or wafer 11 according to some embodiments of the present disclosure is shown. In some embodiments, the memory wafer 1021 of the edge pad semiconductor wafer 11 has edge contacts 27 formed during BEOL region processing, for example, in an M4 or M5 metal layer. To increase the contact area of ​​the edge pad, a dielectric layer 16 having one or more conductive vias 29 or wires is formed over the memory wafer 1021. Reference Figure 8D The conductive via 29 may correspond to or be aligned with a corresponding edge contact 27. In some embodiments, the area of ​​the conductive via 29 (e.g., the exposed lateral area) is larger than the area of ​​the edge contact 27. In some embodiments, the edge contact 27 is electrically or physically connected to the corresponding conductive via 29. Therefore, each edge pad 25 of the edge pad semiconductor wafer 11 may include an edge contact 27 and a conductive via 29. In another embodiment, the dielectric layer 16 is replaced by RDL 15, as... Figure 8E As shown in the image. Figure 8D and Figure 8E The same numerical labels in the text refer to components that are essentially the same or functionally identical, and their relevant descriptions can be consulted. For the sake of brevity, they will not be repeated here.

[0140] Figure 9AThis is a perspective view of a conventional High Frequency Bandwidth Memory (HBM) architecture 30a, which includes multiple DRAM chips 31 (e.g., 12 chips in HBM3 or 16 chips in HBM4) stacked vertically above a control unit 32. Due to the need for multiple TSVs 301, each DRAM chip 31 has a width W1 of approximately 9.5 mm, a length L1 of approximately 10.5 mm, and a relatively thin thickness T1' of approximately 0.05 mm. Typically, four DRAM chips 31 are grouped together to output a 1K-bit data bus width, with each DRAM chip 31 outputting 256 bits. Therefore, when the 12 DRAM chips in an HBM3 configuration are divided into three groups, each group of four DRAM chips can output 1K bits of data.

[0141] Figure 9B A perspective view of a NuHBM stack / layer 30b according to some embodiments of the present disclosure is shown. Compared to a conventional HBM structure 30a, the NuHBM stack / layer 30b of the present invention includes a plurality of edge pad semiconductor wafers 33, a plurality of high thermal conductivity layers 34 (optional), and memory controllers 36. In some embodiments, the plurality of edge pad semiconductor wafers 33 are horizontally separated or horizontally stacked together, for example, 16 or 24 or more wafers. In some embodiments, each edge pad semiconductor wafer 33 has a width W2 of about 3 mm to 9.5 mm, a length L2 of about 10.5 mm (as is generally used in the HBM stack structure 30a), and a conventional thickness T2' of about 50 to 100 μm, wherein it does not have a TSV. Furthermore, for heat dissipation purposes, a high thermal conductivity "HTC" material or layer 34 (e.g., SiC / AlN / BN / W / Cu / undoped polysilicon / large crystalline silicon, etc.) is disposed adjacent to one edge pad semiconductor wafer 33 or between two disposed edge pad semiconductor wafers 33. Furthermore, although Figure 9B Not shown separately, but one or more HTC materials or layers (e.g., Figure 12 The top high thermal conductivity layer 63 shown in the figure can be used to cover the top of the edge pad semiconductor wafer or wafer 33 and coupled to other HTC layers 34 located between the edge pad semiconductor wafers 33.

[0142] The NuHBM stack 30b may further include a plurality of edge pads 35 arranged along a lower sidewall 33S1 of a length L2 of approximately 10.5 mm. For example, when using hybrid bonding with a pitch of approximately 5 µm, each edge pad semiconductor wafer 33 has 2,100 edge (I / O) pads 35 (10.5 mm / 5 µm = 2,100) in the length L2 direction; and when using solder ball bonding with a pitch of approximately 30 µm, each edge pad semiconductor wafer 33 has 350 edge pads 35 (10.5 mm / 30 µm = 350); and when the pitch is 40 µm and the length L2 is 10.5 mm, 262 edge pads 35 can be provided (where the I / O output data is 128 bits). If needed, the edge RDL (see U.S. Applications 18 / 471,670 and 19 / 059,275, all of which are incorporated herein by reference) can optionally be used to form edge pads with a large area. Therefore, assuming half of the edge pads 35 are used for data I / O, each edge pad semiconductor wafer 33 can have 175 bits of output data (assuming a junction pitch of approximately 30 µm) or 1K bits of output data (assuming a junction pitch of approximately 5 µm), or other numbers of edge pads 35 depending on the junction pitch. Multiple edge pad semiconductor wafers 33 (i.e., NuHBM stacks / layers) are electrically coupled to the memory controller 36 via the edge pads 35, such that the memory controller 36 can output data with a desired data width, combined output data of two or more edge pad semiconductor wafers 33, or combined output data of all edge pad semiconductor wafers 33, based on the number of output data from one edge pad semiconductor wafer 33. Depending on the size of the memory wafer, its edge pads can contain 128 to 2048 bits.

[0143] Figure 10 This image shows a cross-sectional view illustrating an intermediate stage in the formation of a NuHBM stack / layer 40 according to some embodiments of the present disclosure. (See also...) Figure 10 As shown in the upper and lower figures, multiple NuHBM stacks / layers 40 can be formed by bonding multiple edge pad semiconductor wafers 41 and HTC layers 42 to a carrier 43, followed by: More edge pad semiconductor wafers 41 of the same size are stacked to first form a low-profile NuHBM stack 410, wherein a high thermal conductivity "HTC" material or layer 42 (e.g., AlN / BN / W / Cu / undoped polysilicon / large crystalline silicon, etc.) is inserted between two adjacent edge pad semiconductor wafers 41. In some embodiments, the thermal conductivity (or thermal conductivity coefficient) of the high thermal conductivity layer 42 is higher than that of Si or SiO2.

[0144] Multiple short NuHBM stacks 410 are combined together to form a NuHBM stack 40 that is thick enough for subsequent processing.

[0145] The carrier 43 is released, and the NuHBM stack 40 is released.

[0146] Figures 11A to 11D This demonstrates an interconnect process for a NuHBM stack / layer 50 according to some embodiments of the present disclosure. With the NuHBM stack / layer 50, its side surfaces can then be bonded to another carrier 51 and encapsulated using a polymer material 53, such as Epotek 377 epoxy resin. The polymer is then cured in a vacuum, followed by: Multiple NuHBM stacks 50 are bonded to a carrier 51 having a release layer 52, then potted and planarized (and lightly etched or ground to ensure all edge connections are exposed), and encapsulated using a polymer material 53. If necessary, additional edge RDLs may be formed to cover these edge pads of the NuHBM stack to create larger edge bumps or larger edge pads, as described above.

[0147] The wafer of the bonding memory controller 54.

[0148] Multiple NuHBM stacks 50 are bonded to a carrier 55 having a release layer 56, the carrier 51 is removed by releasing the release layer 52, and a high thermal conductivity layer 57 is generated (or covering the sidewalls of one / two / three other high 3D IC structure stacks; or covering the remaining sidewalls of the high 3D IC structure stack without RDL layer structures).

[0149] The carrier 55 is removed by releasing the release layer 56, and the NuHBM stack 50 having the memory control wafer (memory controller) 54 and the high thermal conductivity layer 57 is cut and released.

[0150] Therefore, as Figure 12 As shown, the released NuHBM stack with memory controls can replace the HBM in a conventional COWOS architecture. Figure 12 This demonstrates a COWOS IC structure with NuHBM stacking / layering according to some embodiments of this disclosure. For example... Figure 12 As shown, the memory stack 60 includes multiple semiconductor wafers 61, an upwardly extending thermally conductive layer 62, and a top high thermal conductivity layer 63. The multiple semiconductor wafers 61 are horizontally separated from each other, wherein a reference... Figure 8A and Figure 12Each semiconductor wafer 61 includes a top surface 11P1, a bottom surface 11P2 opposite to the top surface, and four sidewalls, including a first sidewall 11S1 or 61S1, a second sidewall 11S2 or 61S2, a third sidewall 11S3 or 61S3, and a fourth sidewall 11S4, and a plurality of edge pads 25 arranged along the first sidewall 61S1, wherein the area of ​​the bottom or top surface is larger than the area of ​​any sidewall. An upwardly extending thermally conductive layer 62 is disposed between two adjacent semiconductor wafers 61, wherein the thermal conductivity of the upwardly extending thermally conductive layer 62 is higher than that of Si or SiO2. If necessary, an adhesive layer may be used between the upwardly extending thermally conductive layer 62 and the semiconductor wafer 61.

[0151] The COWOS IC structure 600 includes the memory stack 60, memory controller chip 64, interposer layer 65, logic processor chip 66, and package substrate 67 described above. The memory controller chip 64 is disposed directly below and electrically connected to a plurality of edge pads 25 of each semiconductor chip 61. The interposer layer 65 is disposed below and electrically connected to the memory controller chip 64. The logic processor chip 66 is electrically connected to the memory controller chip 64. The package substrate 67 is disposed below and electrically connected to the interposer layer 65. In some embodiments, the memory controller chip 64 may include a plurality of TSVs 641 for electrical connections between the edge pads of the semiconductor chips 61 and the interposer layer 65. In some embodiments, the interposer layer 65 may be a silicon interposer that includes a plurality of TSVs 651 for electrical connections between the memory controller chip 64 and the package substrate 67. The interposer layer 65 may include wiring on its top surface for electrical connections between the memory controller chip 64 and the logic processor chip 66. In some embodiments, the logic processor chip 66 may be disposed above the interposer layer 65. An additional heat sink (not shown) may be placed on top of the logic processor chip 66, such that the top surface of the heat sink is flush with or substantially the same as the top surface of the memory stack 60.

[0152] The NuHBM stack 60 with memory controller chip 64 can be bonded to interposer layer 65 or IC chip, such as Figure 12As shown in the illustration, in this embodiment, the NuHBM stack 60 includes multiple semiconductor wafers 61 (e.g., DDR4 wafers, DDR5 wafers, LDDR4 wafers, LDDR5 wafers, or GDDR7 wafers, etc.), each semiconductor wafer 61 being horizontally separated from the others. Power / signals from each semiconductor wafer 61 can be transmitted to the memory control wafer 64 without passing through other semiconductor wafers 61. Furthermore, due to the presence of an intermediate high thermal conductivity layer (or an upwardly extending thermal conductivity layer) 62 (e.g., a dummy Si wafer, SiC, AlN, BN, W, copper, etc.) between two adjacent semiconductor wafers 61 and a top high thermal conductivity layer 63 connected to other sidewalls of the NuHBM stack 60, heat generated from these two semiconductor wafers 61 can be dissipated through the intermediate high thermal conductivity layer 62 to the top high thermal conductivity layer 63, and then transferred to other heat sinks (not shown) connected to the top high thermal conductivity layer 63.

[0153] In another embodiment, the upwardly extending thermally conductive layer 62 between two adjacent semiconductor wafers 61 may be omitted, but the top high thermal conductivity layer 63 is still disposed on top of the NuHBM stack 60. In another embodiment, the upwardly extending thermally conductive layer 62 is attached to the outermost sidewall of the NuHBM, and the top high thermal conductivity layer 63 is further disposed on top of the NuHBM stack 60. In another embodiment, the memory stack 60 further includes an upwardly extending thermally conductive layer covering each third sidewall 61S3 of the plurality of semiconductor wafers 61; wherein the upwardly extending thermally conductive layer is thermally coupled to a laterally extending thermally conductive layer (top high thermal conductivity layer 63) above each second sidewall 61S2 of the plurality of semiconductor wafers 61, and the thermal conductivity of the upwardly extending thermally conductive layer is higher than that of Si or SiO2.

[0154] As mentioned earlier, if a large number of signals need to be transmitted in a low-profile 3D IC structure stack, then a large number of edge RDLs can be formed on two or more sides of the semiconductor wafer 61. As mentioned earlier, if high heat dissipation requirements are required, then a large number of high thermal conductivity layers can be formed on two or more sides.

[0155] Subsequently, the low-profile IC stack 312 or semiconductor package 700A can be bonded to another interposer or IC chip, such as Figure 13AAs shown, a semiconductor package assembly 1900 is formed, comprising a 3D IC structure stack 1901, a substrate 1902, an interposer 1904, and a logic controller chip 1906. In this embodiment, the 3D IC structure stack 1901 includes a plurality of DRAM semiconductor wafers 1920 (or a plurality of DRAM wafers and a control IC) and side RDLs 118, with each DRAM semiconductor wafer 1920 horizontally separated from the others. Laterally extending RDL structures 118 on the sidewalls of the plurality of DRAM semiconductor wafers (or DRAM and control ICs) 1920 are bonded to the logic memory controller chip 1906 or the interposer 1904, and then the interposer 1904 is bonded to the substrate 1902. The RDL structures 118 can be used to handle the power / signal functions of each DRAM semiconductor wafer 1920, and the RDL structures 118 are connected to the logic memory controller chip 1906 and the interposer 1904. Unlike conventional HBM structures, in this invention, each DRAM semiconductor chip 1920 can independently transmit or receive power / signals without passing through other DRAM semiconductor chips, and each DRAM semiconductor chip can generate high-bandwidth data with low latency. Therefore, it can be appropriately named HBLM (High Bandwidth Low Latency Memory), and the combination of horizontally separated DRAM semiconductor chips 1920 can be named HBLM stack.

[0156] Furthermore, since there is an intermediate (upwardly extending) high thermal conductivity layer 1912 (e.g., AlN, BN, W, copper, SiC, etc.) and an optional HTC adhesive layer 1908 between the main surfaces of two adjacent DRAM semiconductor wafers 1920, which can be connected to a top (laterally extending) HTC layer 1914 (e.g., AlN, BN, W, copper, SiC, etc.) on other sidewalls of the low-profile 3D IC structure stack 1901, the heat generated from these two DRAM semiconductor wafers 1920 can be transferred from the wafers through the intermediate high thermal conductivity layer 1912 to the top high thermal conductivity layer 1914 and to a heat dissipation device (e.g., a cooling plate; not shown) thermally coupled to the HTC layer 1914.

[0157] According to some embodiments, RDL 118 further includes a plurality of bonding pads 1927 on the upper surface of RDL 118, and an interposer 1904 is electrically connected to the DRAM semiconductor wafer 1920.

[0158] In cases where more signal transmission is required in multiple DRAM semiconductor wafers 1920, as described above, more upwardly extending RDL structures 1916 can be formed in, for example... Figure 13BOn two or more sides shown, a bottom RDL structure 118 is formed on one side of a plurality of DRAM semiconductor wafers 1920, and another side RDL structure (or side RDL structure) may be formed on other sides of the plurality of DRAM semiconductor wafers 1920 opposite to or adjacent to the intermediate high thermal conductivity layer 1912, wherein the bottom RDL structure 118 is electrically connected to these side RDL structures 1916.

[0159] In situations where greater heat dissipation is required in multiple DRAM semiconductor wafers 1920, as described above, more intermediate HTC layers 1917, similar to the intermediate HTC 1912 or the top HTC 1914, can be formed on two or more sides and / or one or both of the main surface, such as... Figure 13B As shown, the middle HTC layer 1917 is thermally coupled to the top HTC 1914 and the middle HTC 1912. According to some embodiments, the thermal conductivity of HTC layers 1912, 1914 and 1917 is higher than that of silicon or SiO2.

[0160] According to some embodiments, reference Figure 13A and 13B The IC stack 1901 comprises multiple IC structures 1920 horizontally separated from each other. Each IC structure 1920 can be... Figures 2C-2F Semiconductor structures in 3D~3F, 4G~4N, and 5A~5B, having a top surface 108P1, a bottom surface 108P2 opposite to the top surface 108P1, and four sidewalls 108S, each having a first sidewall 1920S1 or 108S1, a second sidewall 1920S2 or 108S2, a third sidewall 1920S3 or 108S3 (parallel to the paper), and a fourth sidewall (shown in...). Figure 13B The sidewall opposite to the sidewall 1920S3, and parallel to Figure 2D The area of ​​the paper or sidewall 108S4). The area of ​​the bottom surface 108P2 or the top surface 108P1 is greater than Figure 2C The area of ​​any sidewall 102S (e.g., 1920S1 (108S1), 1920S2 (108S2), 1920S3 (108S3), or 108S4). The low-profile 3D stack 1901 may further include a laterally extending RDL structure 118 that covers the first sidewall 1920S1 of each of the plurality of IC structures 1920.

[0161] According to some embodiments, reference Figure 13A , 13B , Figure 4G to 4N From 5A to 5B and 6E, each semiconductor structure includes a first integrated circuit (IC) structure, for example... Figure 13A Or a 13B IC structure 1920 or Figure 4G to 4NThe chip 122E, and a first adjacent structure physically separated from the first IC structure, such as Figure 13A Or 13B high thermal conductivity layer 1912, or Figure 4G to 4N The molding compound layer 242 and / or wafer 122D. First IC structure and first adjacent structure: (1) arranged along a first sidewall 1912S1 extending in the Z direction, as shown in Figure 13A Or as shown in 13B, or (2) arranged along the first sidewall 1912S1 extending in the XZ plane, as Figure 13A Or as shown in 13B. In condition (2) above, refer to... Figure 4K to 4N The XZ plane of each of the IC structures 400E to 400H can face the RDL structure 118 and form an electrical connection with it. The first IC structure 122E and the first adjacent structure 122D can be arranged on the XZ plane of each of the IC structures 400E to 400H and along the X direction, such as... Figure 13A or Figure 13B As shown in the illustration. According to some embodiments, Figure 13A and 13B The laterally extended RDL structure 118 shown includes a plurality of first bonding pads 1927 arranged along the first sidewall of an individual semiconductor structure 1920, wherein the plurality of first bonding pads are above or facing the edge of the first IC structure and the edge of the first adjacent structure.

[0162] In some embodiments, the first IC structure may include more than one semiconductor wafer, for example Figure 4K to 4N or Figure 6D The wafers 122E, 122G, and / or 122H are shown in the diagram. The first adjacent structure 122D may be an active wafer or an HTC virtual interconnect spacer. The interconnect spacer may be a passive or active silicon interposer. According to some embodiments, the interconnect spacer is a semiconductor interposer having a set of through-semiconductor vias (TSVs) electrically coupled to a subset of a first plurality of bonding pads or external connectors.

[0163] According to some embodiments, the first adjacent structure includes another IC structure (e.g., Figure 4G to 4N The semiconductor wafer 122D shown in the figure), interconnect spacers (e.g. Figure 4G to 4N The intermediate layer 122D shown in the figure), molding compound layer (e.g. Figure 4G to 4N The potting material or molding compound layer 242 shown in the figure) or the high thermal conductivity (HTC) layer (e.g.) Figure 4G to 4N The wafer 122D shown in the figure has a higher thermal conductivity than Si or SiO2 to dissipate heat from adjacent IC structures.

[0164] According to some embodiments, the number of the first plurality of bonding pads 1927 is greater than 1,300 to 1,500 per IC structure 1920.

[0165] According to some embodiments, reference Figure 4G , Figure 4I , Figure 4K , Figure 4M , Figure 5A and Figure 5B The first IC structure 122E or another IC structure serving as the first adjacent structure includes a set of through-semiconductor vias (TSVs) 104B exposed from the sidewall 102S of the XZ plane and electrically coupled to... Figure 13A or Figure 13B The first plurality of bonding pads 1927 of the laterally extended RDL structure 118 of the 3D IC stack 1901 shown in the figure.

[0166] According to some embodiments, reference Figure 4G , Figure 4H , Figure 4K , Figure 4L , Figure 5A and Figure 5B The molding compound layer 242 includes a set of through-mold sealing vias (TMVs) 232 exposed from the molding sidewall 102S of the XZ plane, and electrically coupled to... Figure 13A Or the laterally extended RDL structure 118 of the 3D IC stack 1901 shown in 13B (e.g., see also...) Figure 5A A subset of the first plurality of mating pads 1927 shown in RDL 118A in 5B.

[0167] According to some embodiments, reference Figure 4G , Figure 4H , Figure 4K , Figure 4L , Figure 5A and Figure 5B The first adjacent structure 122D may include interconnect spacers with or without active components, having a set of through-semiconductor vias (TSVs), similar to TSV 104B in the first IC structure 122E, exposed from the sidewall 102S of the XZ plane and electrically coupled to... Figure 13A Or a subset of the first plurality of bonding pads 1927 of the laterally extended RDL structure 118 of the low 3DIC stack 1901 shown in 13B.

[0168] According to some embodiments, the IC stack 1901 further includes one of the semiconductor structures 1920, 1912 located between or adjacent to the two semiconductor structures 1920, 1912 (e.g., in a manner similar to...). Figure 13A This can be a high thermal conductivity structure (such as the intermediate high thermal conductivity layer shown in 13B, 1912). The thermal conductivity of this high thermal conductivity structure is higher than that of Si or SiO2.

[0169] According to some embodiments, each IC structure 1920 may be a DRAM semiconductor wafer, and the IC stack 1901 may be an HBM-compatible structure.

[0170] According to some embodiments, the IC stack 1901 further includes a logic control chip 1906 located below and electrically connected to the lateral extension RDL structure 118 of the IC stack 1901.

[0171] According to some embodiments, reference Figure 13A Alternatively, 13B, the IC stack 1901 further includes a laterally extending thermally conductive layer 1914 that covers each of the second sidewalls 1920S2 of the plurality of IC structures 1920, wherein the laterally extending RDL structure 118 is opposite to the laterally extending thermally conductive layer 1914, and the thermal conductivity of the laterally extending thermally conductive layer is higher than that of Si or SiO2.

[0172] According to some embodiments, reference Figure 13A and 13B The IC stack 1901 contains multiple horizontally separated IC structures 1920. (Reference) Figures 2C-2F For each IC structure (3D~3F, 4G~4N, 5A~5B, and 13A), please refer to 1920. Figures 2C to 2F IC structures from 3D to 3F, 4G to 4N, and 5A to 5B, including 100A to 100C, 300A to 300C, 400A to 400H, 500A, and 500B. For example... Figure 2D As shown, each IC structure 1920 has dimensions similar to those of the RDL structures 108A and includes a top surface 108P1, a bottom surface 108P2 opposite to the top surface 108P1, and four sidewalls having a first sidewall 1920S1 or 108S1, a second sidewall 1920S2 or 108S2, a third sidewall 1920S3 or 108S3, and a fourth sidewall 108S4. The area of ​​the bottom surface 108S2 or the top surface 108S1 is larger than the area of ​​any sidewall (e.g., 1920S1 (108S1), 1920S2 (108S2), 1920S3 (108S3), and 108S4). The IC stack 1901 may further include a laterally extending RDL structure 118 that covers each of the first sidewalls 1920S1 (108S1) of each of the plurality of IC structures 1920. IC stack 1901 may also include an upwardly extending thermally conductive layer 1912 between two adjacent IC structures 1920. According to some embodiments, the thermal conductivity of the upwardly extending thermally conductive layer 1912 is higher than that of Si or SiO2, for example, a SiC wafer having the same dimensions as IC structure 1920.

[0173] According to some embodiments, the IC stack 1901 further includes a laterally extending thermally conductive layer 1914 that covers each of the second sidewalls 108S2 or 1920S2 of the plurality of IC structures 1920 and is thermally coupled to each of the upwardly extending thermally conductive layers 1912, wherein the laterally extending RDL structure 118 is opposite to the laterally extending thermally conductive layer 1914, and the thermal conductivity of the laterally extending thermally conductive layer 1914 is higher than that of Si or SiO2, such as SiC wafer.

[0174] According to some embodiments, the upwardly extending thermal conductive layer 1912 or the laterally extending thermal conductive layer 1914 comprises a material of BN, AlN, W, SiC or copper.

[0175] According to some embodiments, reference Figure 13B The IC stack 1901 further includes an upwardly extending RDL structure 1916 that covers each of the third sidewalls 108S3 or 1920S3 of the plurality of IC structures 1920, wherein the upwardly extending RDL structure 1916 is electrically connected to the laterally extending RDL structure 118.

[0176] According to some embodiments, each IC structure 1920 includes a DRAM semiconductor wafer, and the IC stack 1901 is an HBM-compatible structure (i.e., the basic signals transmitted through its own IO pads P31 to P3N are compatible with the signal paths defined by JEDEC for HBM).

[0177] According to some embodiments, the IC stack 1901 further includes a logic control chip 1906 located below and electrically connected to the lateral extension RDL structure 118 of the IC stack 1901.

[0178] According to some embodiments, reference Figure 13A , 13B and Figure 2C , 2D IC structure 1920 may include IC structures 100A to 100C, 300A to 300C, 400A to 400H, 500A, 500B, and 600A, up to 2F, 3D to 3F, 4G to 4N, 5A, 5B, and 6E. For example, refer to... Figure 5A , 5B and Figure 13A Alternatively, 13B, IC structure 1920 includes IC structure 500A, and the IC structure includes a first semiconductor body 122F and an interconnect structure 108A or 108B. The first semiconductor body (122E or 122F) has a first primary surface (102P) and a first secondary surface (102S), wherein the first primary surface is substantially perpendicular to the first secondary surface. The interconnect structure includes a primary redistribution layer (RDL) located above the first primary surface 102P. Figure 5A, 108A), which has a second sub-surface ( Figure 5A The main RDL 108A of the second sub-surface 108S is aligned with the first sub-surface 102S of the first semiconductor body 122F, wherein the first sub-surface 102S and the second sub-surface 108S together form a sub-plane. Figure 5A ,500AS), which may correspond to the first sidewall 1920S1 or the second sidewall 1920S2 of IC structure 1920, wherein the main RDL 108S further includes a first conductive element exposed through the second sub-surface 108S of the main RDL 108A ( ,500AS), Figure 5A ,212, 214).

[0179] According to some embodiments, the first conductive element may be a conductive pad 212 located on surface 108P of the main RDL structure 108A / 108B (see...). Figure 2C ), which is substantially parallel to the first main surface 102P1 and connects the adjacent layers of the main RDL 118A / 118B via conductive via 216 (see Figure 2G ), through the stacked via 214 of the main RDL 118A / 118B (see Figure 2G ), or combinations thereof.

[0180] According to some embodiments, the first semiconductor body ( Figure 4G Or 122E in 4I) further includes at least one through-silicon via 104B ( Figure 4G ), through hole 232 ( Figure 4G ) or through the first exposed insulating component 242 ( Figure 4I ).

[0181] According to some embodiments, Figure 13A The first semiconductor body of the IC structure 1920 shown in 13B can be used as... Figure 4K to 4N or Figure 6E The semiconductor wafers 400A to 400H or 600A shown in the figure are mating components, and include: (1) a plurality of first wafers 122D and 122E disposed in the same package layer. Figure 4K to 4N (2) Multiple vertically stacked second wafers 122G, 122H ( Figure 6E (3) Multiple second wafers 122G, 122H placed side by side with other third wafers 122E in the same package layer. Figure 6E (or combinations thereof). The first, second, and third wafers 122D, 122E, 122G, and 122H have the same or different dimensions.

[0182] According to some embodiments, Figure 13AThe first semiconductor body of the IC structure 1920 shown in 13B (see partial structure of semiconductor wafer 600A other than main RDL 108C) also includes multiple conductive vias 104B (see semiconductor wafer 122E), pillars 224 or plugs 234 of the same or different lengths, electrically connecting multiple first wafers 122E, 122G and 122H to, for example, Figure 6E The main RDL 108C shown along the Z-axis and / or electrically connected to, for example Figure 6E , 13A Or the lateral extension RDL structure 118 of the XZ plane shown in 13B.

[0183] According to some embodiments, Figure 13A Or, as shown in 13B, the laterally extended RDL structure 118 is electrically connected to the first conductive element of the main RDL. Figure 4G Or the conductive pad 212 or conductive via 214 shown in 6D. Figure 6D The column 224 or plug 234 shown in the image.

[0184] According to some embodiments, the laterally extended RDL structure 118 (corresponding to...) Figure 7I The RDL 118A shown in the image contains a hybrid bonding layer or bump pad array (244).

[0185] According to some embodiments, reference Figure 13A and 13B The IC stack 1901 contains multiple horizontally separated IC structures 1920. (Reference) Figure 2C , 2D And 13A, each IC structure 1920 can be Figure 2D The structure 108A shown includes a top surface 108P1, a bottom surface 108P2 opposite to the top surface, and four sidewalls, including a first sidewall 1920S1 or 108S1, a second sidewall 1920S2 or 108S2, a third sidewall 1920S3 or 108S3, and a fourth sidewall 108S4. The area of ​​the bottom or top surface is greater than any of the four sidewalls (e.g., 1920S1 (108S1), 1920S2 (108S2), 1920S3 (108S3), and 108S4). The IC stack 1901 may further include a laterally extending RDL structure 118 that covers each of the first sidewalls 1920S1 (108S1) of each of the plurality of IC structures 1920.

[0186] According to some embodiments, the IC stack 1901 further includes a set of upwardly extending thermally conductive layers 1912, wherein corresponding upwardly extending thermally conductive layers 1912 are disposed between any two adjacent IC structures 1920 of the plurality of IC structures 1920. The IC stack 1901 may also include a first laterally extending thermally conductive layer 1914, which covers each of each second sidewall 1920S2 (108S2) of each of the plurality of IC structures 1920 and is thermally coupled to the set of upwardly extending thermally conductive layers 1912. The thermal conductivity of either the upwardly extending thermally conductive layer 1912 or the first laterally extending thermally conductive layer 1914 is higher than that of Si or SiO2.

[0187] According to some embodiments, reference Figure 13B The IC stack 1901 further includes a second laterally extending thermally conductive layer 1917 that covers each of the third sidewalls 1920S3 (108S3) of the plurality of IC structures 1920. The second laterally extending thermally conductive layer 1917 is thermally coupled to the group of upwardly extending thermally conductive layers 1912.

[0188] According to some embodiments, IC stack 1901 is an HBM-compatible structure and each IC structure 1920 includes a DRAM semiconductor wafer 1920. IC stack 1901 further includes a logic control wafer 1906 located below and electrically connected to the laterally extended RDL structure 118 of IC stack 1901.

[0189] In summary, this invention provides a COWOS IC structure with a NuHBM stack comprising multiple edge-pad semiconductor wafers, each edge pad being located above a side of the semiconductor wafer for interconnection to allow signal and power distribution across the wafer. Furthermore, a high thermal conductivity material is disposed between two adjacent edge-pad semiconductor wafers and thermally coupled to other high thermal conductivity materials, covering the other sides of the NuHBM stack.

[0190] Symbol Explanation 10a, 10b, 11: Semiconductor wafers 11P1: Top surface 11P2: Bottom 11S1, 11S2, 11S3, 11S4: Sidewalls 12, 12a, 12b: Signal pads 13, 13a, 13b: Sealing rings 15, 15a, 15b: Re-fabricated layers 15a1, 15a2, 15a3, 15b1, 15b2, 15b3, 16: Dielectric layer 17, 17a, 17b: Electrical wires 18a, 18b: Through holes 19, 25: Edge pads 20: Wafer-on-a-Chip Structure on Substrate 21: HBM Structure 22: Logic chip 23: Silicon interposer 24: Packaging substrate 25: Edge Pad 27: Edge contact components 29: Conductive via 30a: Conventional High-Voltage Bandwidth Memory (HBM) Architecture 30b: NuHBM stacking / layering 31: DRAM chip 32: Control components 33: Edge pad semiconductor wafer 33S1: Lower sidewall 34: High thermal conductivity layer 35: Edge Pad 36: Memory controller 40: NuHBM stacking / layering 41: Edge Pad Semiconductor Wafer 42: High thermal conductivity layer 43: Carrier 50: NuHBM stacking / layering 51: Carrier 52: Release layer 53: Polymer materials 54: Memory controller 55: Carrier 56: Release layer 57: High thermal conductivity layer 60: Memory Cascading 61: Semiconductor wafers 61S1: First sidewall 61S2: Second sidewall 61S3: Third sidewall 62: Extend the heat-conducting layer upwards 63: Top high thermal conductivity layer 64: Memory controller chip 65: Intermediary layer 66: Logic processor chip 67: Packaging substrate 100A: Semiconductor Packaging Device / Integrated Circuit Structure 100AS: Secondary plane / Side plane 100B, 100C: Integrated Circuit Structure 100W: Semiconductor device 101: Interconnection Structure 102: Substrate 102P, 102P1: Main surface 102S: Side surface 104: Conductive Through-Hole / TSV 104A: Internal TSV 104B: Edge TSV 106: Temporary carrier, substrate 108A, 108B, 108C: Main RDL 108D, 108E, 108F: Main RDL 108P, 108P1, 108P2: Main surface 108S1, 108S2, 108S3, 108S4: Side surfaces 108X: Internal interconnect structure 110: Release Layer 110S: Carrier surface 116: Carrier substrate 118: RDL Structure 118A, 118B: Secondary RDL 118F: Front interconnect surface 118R: Post-interconnect surface 118X: Edge interconnect structure 120: Release Layer 122A, 122B, 122C, 122D, 122D1: Chips 122E, 122F, 122G, 122H: Chips 126: Carrier substrate 130: Release Layer 140: Release Layer 142A, 142B, 142C: Integrated Circuit Structure 142AP, 142BP, 142CP: Main Surface 142AS, 142BS, 142CS: Side surfaces 142D, 142E, 142F: Integrated Circuit Structure 143A, 143B, 143C: Integrated Circuit Structure 160: Bonding layer 172: Conductive traces or wires 201: TSV 202: Conductive components 211: DRAM memory chip 212: Conductive pad / Internal conductive pad / Edge conductive pad 213: Control components 214: Conductive via / Internal via / Edge via 214-1, 214-2: Conductive vias 216: Conductive via 222: Edge conductive pad 224: Internal conductive pillar 232: Edge TMV 234: Conductive plug 240: First main wire / through-hole layer 242, 252, 262: Potting materials 244: Conductive bump 250: Second main wire / via layer 252: Potting Material 252R: Through hole 254: Conductive pad 262: Potting Material 300A, 300B, 300C: Integrated Circuit Structure 300W: Semiconductor device 301: TSV 312: Low-profile integrated circuit stacking 322: High-integration-chaining 340, 350: Main wire / through-hole layer 400A, 400B, 400C, 400D: Integrated Circuit Structure 400E, 400F, 400G, 400H: Integrated Circuit Structure 400W, 401W: Semiconductor devices 410: Low-profile NuHBM stacking 500A, 500B: Integrated Circuit Structure 500AS: Subplane 500BS1: Subplane 600: COWOS Integrated Circuit Structure 600A: Integrated Circuit Structure 600AS1, 600AS2: Subplane 600W: Semiconductor wafer / semiconductor device 641, 651: TSV 700A, 700B, 700C: Semiconductor Packaging 700BS: Subplane 700CS1, 700CS2: Subplane 700L: High-integration-chain structure 700W, 701W, 702W: Semiconductor devices 1021, 1031a, 1031b: Memory chips 1900: Semiconductor package assembly 1901: 3D Integrated Circuit Structure Stacking 1902: Substrate 1904: Intermediate Layer 1906: Logic memory controller chip 1908: HTC adhesive layer 1912: Middle high thermal conductivity layer 1912S1: First sidewall 1914: Top high thermal conductivity layer 1920: DRAM semiconductor wafer 1920S1: First sidewall 1920S2: Second sidewall 1927: Joint Pad

Claims

1. An integrated circuit structure, comprising: The memory stack includes: A plurality of horizontally separated semiconductor wafers, wherein each of the semiconductor wafers includes a top surface, a bottom surface opposite the top surface and four sidewalls, including a first sidewall, a second sidewall, a third sidewall and a fourth sidewall, and a plurality of edge pads arranged along the first sidewall, wherein the area of ​​the bottom surface or the top surface of each of the semiconductor wafers is greater than the area of ​​any sidewall. A memory controller chip is located below and electrically connected to a plurality of edge pads of each of the semiconductor wafers, wherein the first sidewall of each of the semiconductor wafers faces the memory controller chip; An intermediary layer, which is located below and electrically connected to the memory controller chip; A logic processor chip electrically connected to the memory controller chip; and A packaging substrate, which is located below the interposer and electrically connected to it.

2. The integrated circuit structure of claim 1, wherein the memory stack further comprises: A laterally extending thermally conductive layer that covers each of the second sidewalls of the plurality of semiconductor wafers; and / or An upwardly extending thermally conductive layer is attached to the top or bottom surface of the first semiconductor wafer. The thermal conductivity of the laterally extended thermal conductive layer or the upwardly extended thermal conductive layer is higher than that of silicon or silicon dioxide.

3. The integrated circuit structure of claim 2, wherein the upwardly extending thermal conductive layer is thermally coupled to the laterally extending thermal conductive layer, and the upwardly extending thermal conductive layer or the laterally extending thermal conductive layer comprises silicon carbide, boron nitride, aluminum nitride, tungsten, or copper.

4. The integrated circuit structure of claim 2, wherein the upwardly extending thermal conductive layer is disposed between the first semiconductor wafer and the second semiconductor wafer, or the upwardly extending thermal conductive layer is located on the outermost sidewall of the memory stack.

5. The integrated circuit structure of claim 1, wherein each of the semiconductor wafers is a dynamic random access memory wafer and includes data output between 128 and 2048 bits.

6. The integrated circuit structure of claim 1, wherein each of the edge pads of each of the semiconductor wafers comprises: Edge contacts in the back-end process area BEOL; and The conductive via is located above the edge contact and in the dielectric layer or redistribution layer RDL, wherein the area of ​​the conductive via is larger than the area of ​​the edge contact.

7. The integrated circuit structure of claim 6, wherein the edge contact is electrically connected to a signal pad in the back-end processing region of the semiconductor wafer, the signal pad being surrounded by a sealing ring structure.

8. The integrated circuit structure of claim 1, wherein each of the edge pads of each of the semiconductor wafers comprises a wire in a redistribution layer RDL electrically connected to a signal pad in a back-end processing region of the semiconductor wafer, the signal pad being surrounded by a sealing ring structure.

9. The integrated circuit structure of claim 8, wherein the RDL comprises a plurality of stacked dielectric layers and the wire is located therein.

10. The integrated circuit structure of claim 9, wherein a portion of the wire is configured to be disposed in the dicing region SL of the semiconductor wafer prior to dicing.

11. The integrated circuit structure of claim 1, wherein the logic processor chip is disposed above the interposer layer and the heat sink is located above the logic processor chip; wherein the top surface of the heat sink is substantially flush with the top surface of the memory stack.

12. The integrated circuit structure of claim 1, wherein the memory stack further comprises: An upwardly extending thermal conductive layer covers each of the third sidewalls of the plurality of semiconductor wafers; wherein the upwardly extending thermal conductive layer is thermally coupled to a laterally extending thermal conductive layer above each of the second sidewalls of the plurality of semiconductor wafers, and the thermal conductivity of the upwardly extending thermal conductive layer is higher than that of silicon or silicon dioxide.

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