Transistor and preparation method thereof
By using a PECVD process with increased plasma energy gradient to fabricate the second dielectric layer during transistor fabrication, the problem of excessive stress in the dielectric layer leading to cracks was solved, thus improving the transistor yield.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- HC SEMITEK ZHEJIANG CO LTD
- Filing Date
- 2025-12-17
- Publication Date
- 2026-05-08
AI Technical Summary
In existing technologies, the second dielectric layer is prone to cracking due to excessive stress during fabrication, leading to a decrease in transistor yield.
A second dielectric layer is fabricated on the first metal layer using a PECVD process with increasing plasma energy gradient. By gradually increasing the ion bombardment intensity, the compressive stress is avoided from increasing suddenly, thus reducing the generation of cracks in the dielectric layer.
This effectively avoids a sudden increase in compressive stress in the second dielectric layer, improves transistor yield, and reduces the occurrence of dielectric layer cracks.
Smart Images
Figure CN122002833A_ABST
Abstract
Description
Technical Field
[0001] This disclosure relates to the field of power devices, and in particular to a transistor and a method for fabricating the same. Background Technology
[0002] High Electron Mobility Transistor (HEMT) is a heterojunction field-effect transistor that is widely used in wireless communication, automotive electronics and other fields.
[0003] The related technology provides a transistor, the transistor structure including: a channel layer, a barrier layer, a first dielectric layer, a first metal layer, a second dielectric layer and a second metal layer, wherein the barrier layer, the first dielectric layer, the first metal layer, the first dielectric layer and the second metal layer are sequentially stacked on the channel layer.
[0004] During the fabrication of the second dielectric layer, the second dielectric layer is prone to cracks due to high stress, which reduces the transistor yield. Summary of the Invention
[0005] This disclosure provides a transistor and its fabrication method, which can significantly reduce the stress in the dielectric layer and prevent cracks from forming in the dielectric layer. The technical solution is as follows: On one hand, a method for fabricating a transistor is provided, the method comprising: Create the channel layer; A barrier layer is fabricated on the channel layer; A first dielectric layer is fabricated on the barrier layer; A first metal layer is fabricated on the first dielectric layer; A second dielectric layer is fabricated on the first metal layer using a plasma energy gradient-increased PECVD process. A second metal layer is fabricated on the second dielectric layer.
[0006] Optionally, the fabrication of the second dielectric layer on the first metal layer using a plasma energy gradient increasing PECVD process includes: A compound layer of Si is fabricated using a PECVD device, and the radio frequency power gradient of the PECVD device is increased during the fabrication of the second dielectric layer.
[0007] Optionally, during the fabrication of the second dielectric layer, the radio frequency power of the PECVD equipment is gradually increased in the range of 100~300W, with the increase in radio frequency power of the PECVD equipment being 95~105W.
[0008] Optionally, the Si compound layer fabricated using a PECVD device includes: A SiO2 layer is grown under the following conditions: pressure of 2000~5000mT, SiH4 flow rate of 80~260sccm, N2O flow rate of 1200~5000sccm, spacing between the outlet of the PECVD equipment and the wafer of 12.5~13.2mm, and growth time of 29~210s.
[0009] Optionally, the thickness of the second dielectric layer is 700~4000 nm.
[0010] Optionally, a first dielectric layer is fabricated on the barrier layer, comprising: A SiN layer was fabricated on the barrier layer using an MOCVD device as the first dielectric sublayer. An AlN layer is fabricated on the first dielectric sublayer using an MOCVD device, which serves as the second dielectric sublayer. A SiN layer is fabricated on the second dielectric sublayer using an MOCVD device, which serves as the third dielectric sublayer. A SiN layer was fabricated on the third dielectric sublayer using an LPCVD device, serving as the fourth dielectric sublayer. A SiN layer was fabricated on the fourth dielectric sublayer using a PECVD device, which served as the fifth dielectric sublayer. A SiN layer was fabricated on the fifth dielectric sublayer using a PECVD device, which served as the sixth dielectric sublayer. A SiO2 layer is fabricated on the sixth dielectric sublayer using a PECVD apparatus to serve as the seventh dielectric sublayer, wherein the first dielectric layer comprises the first dielectric sublayer to the seventh dielectric sublayer.
[0011] Optionally, the thickness of the first dielectric sublayer is 50-60 nm, the thickness of the second dielectric sublayer is 1-5 nm, the thickness of the third dielectric sublayer is 3-8 nm, the thickness of the fourth dielectric sublayer is 290-310 nm, the thickness of the fifth dielectric sublayer is 590-610 nm, the thickness of the sixth dielectric sublayer is 490-510 nm, and the thickness of the seventh dielectric sublayer is 690-710 nm.
[0012] On the other hand, a transistor is provided, the transistor comprising: a channel layer, a barrier layer, a first dielectric layer, a first metal layer, a second dielectric layer, and a second metal layer; The channel layer, the barrier layer, the first dielectric layer, the first metal layer, the second dielectric layer, and the second metal layer are stacked sequentially. The second dielectric layer is a Si compound layer fabricated using a plasma energy gradient increasing PECVD process.
[0013] Optionally, the thickness of the second dielectric layer is 700~4000 nm.
[0014] Optionally, the first dielectric layer includes a first dielectric sublayer, a second dielectric sublayer, a third dielectric sublayer, a fourth dielectric sublayer, a fifth dielectric sublayer, a sixth dielectric sublayer, and a seventh dielectric sublayer stacked sequentially. The thickness of the first dielectric sublayer is 50~60nm, the thickness of the second dielectric sublayer is 1~5nm, the thickness of the third dielectric sublayer is 3~8nm, the thickness of the fourth dielectric sublayer is 290~310nm, the thickness of the fifth dielectric sublayer is 590~610nm, the thickness of the sixth dielectric sublayer is 490~510nm, and the thickness of the seventh dielectric sublayer is 690~710nm.
[0015] The beneficial effects of the technical solutions provided in this disclosure are: In this embodiment, a barrier layer is fabricated on the channel layer to form a heterojunction, and a first dielectric layer is fabricated on the barrier layer as a gate insulating layer. A second dielectric layer, serving as an interlayer insulating layer between the first and second metal layers, is fabricated using a PECVD process. Ions in the plasma bombard the surface of the depositing second dielectric layer. Directly bombarding the surface of the depositing second dielectric layer with high RF power plasma energy would generate compressive stress in the second dielectric layer, leading to increased stress. However, using a plasma energy gradient-increasing PECVD process on the first metal layer to fabricate the second dielectric layer allows the intensity of ion bombardment to gradually increase during fabrication, thus preventing a sudden increase in compressive stress and allowing the second dielectric layer time to gradually release the gradient-increasing compressive stress. This prevents cracks in the second dielectric layer and improves transistor yield. Attached Figure Description
[0016] To more clearly illustrate the technical solutions in the embodiments of this disclosure, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0017] Figure 1 This is a flowchart of a transistor fabrication method provided in an embodiment of this disclosure; Figure 2 This is a flowchart of another transistor fabrication method provided in this disclosure embodiment; Figure 3 This is a schematic diagram of the structure of a transistor provided in an embodiment of this disclosure; Figure 4 This is a topographic diagram of the second dielectric layer provided by related technologies; Figure 5This is a topographic diagram of the second dielectric layer provided in an embodiment of this disclosure.
[0018] The attached figures are labeled as follows: 100: Substrate; 101: Channel layer; 102: Barrier layer; 103: First dielectric layer; 104: First metal layer; 105: Second dielectric layer; 106: Second metal layer; 107: Buffer layer; 1031: First dielectric sublayer; 1032: Second dielectric sublayer; 1033: Third dielectric sublayer; 1034: Fourth dielectric sublayer; 1035: Fifth dielectric sublayer; 1036: Sixth dielectric sublayer; 1037: Seventh dielectric sublayer. Detailed Implementation
[0019] To make the objectives, technical solutions, and advantages of this disclosure clearer, the embodiments of this disclosure will be described in further detail below with reference to the accompanying drawings.
[0020] Figure 1 This is a flowchart of a transistor fabrication method provided in an embodiment of this disclosure. See also... Figure 1 The method includes the following steps: S11, Create the channel layer.
[0021] S12. A barrier layer is formed on the channel layer.
[0022] The channel layer and barrier layer form a heterojunction that provides a two-dimensional electron gas.
[0023] S13. A first dielectric layer is fabricated on the barrier layer.
[0024] The first dielectric layer can serve as the gate insulating layer.
[0025] Optionally, a gate metal layer may be formed on the barrier layer before the first dielectric layer is fabricated.
[0026] S14. A first metal layer is formed on the first dielectric layer.
[0027] The first metal layer can be a source / drain layer. The source / drain can penetrate the first dielectric layer and contact the heterojunction.
[0028] S15. A second dielectric layer is fabricated on the first metal layer using plasma-enhanced chemical vapor deposition (PECVD) with increased plasma energy gradient.
[0029] The first metal layer can be an interlayer insulating layer.
[0030] S16. A second metal layer is formed on the second dielectric layer.
[0031] The second metal layer can be a source / drain lead layer, which can penetrate the second dielectric layer and contact the source / drain.
[0032] Optionally, the transistor can also repeat S15 and S16 to form a multilayer lead structure.
[0033] In this embodiment, a barrier layer is fabricated on the channel layer to form a heterojunction, and a first dielectric layer is fabricated on the barrier layer as a gate insulating layer. A second dielectric layer, serving as an interlayer insulating layer between the first and second metal layers, is fabricated using a PECVD process. Ions in the plasma bombard the surface of the depositing second dielectric layer. Directly bombarding the surface of the depositing second dielectric layer with high RF power plasma energy would generate compressive stress in the second dielectric layer, leading to increased stress. However, using a plasma energy gradient-increasing PECVD process on the first metal layer to fabricate the second dielectric layer allows the intensity of ion bombardment to gradually increase during fabrication, thus preventing a sudden increase in compressive stress and allowing the second dielectric layer time to gradually release the gradient-increasing compressive stress. This prevents cracks in the second dielectric layer and improves transistor yield.
[0034] Figure 2 This is a flowchart of another transistor fabrication method provided in this disclosure. See also... Figure 2 The method includes the following steps: S21. A buffer layer, a channel layer, and a barrier layer are sequentially formed on the substrate.
[0035] In this embodiment of the disclosure, the substrate can be any one of sapphire substrate, Si substrate, SiC substrate and GaN substrate, and the material of the substrate is not limited in this embodiment of the disclosure.
[0036] For example, the substrate is a Si substrate.
[0037] In this embodiment of the disclosure, a buffer layer, a channel layer, and a barrier layer are sequentially fabricated using a metal-organic chemical vapor deposition (MOCVD) process.
[0038] In one example, step S21 includes: The first step is to fabricate a buffer layer on the substrate.
[0039] In this embodiment of the disclosure, the buffer layer can be a GaN buffer layer.
[0040] In this embodiment of the disclosure, the thickness of the buffer layer can be 900~1100nm.
[0041] For example, the thickness of the buffer layer is 1000 nm.
[0042] The second step is to create a channel layer on the buffer layer.
[0043] In this embodiment of the disclosure, the channel layer can be a GaN channel layer.
[0044] In this embodiment of the disclosure, the thickness of the channel layer can be 5~10nm.
[0045] For example, the thickness of the channel layer is 8 nm.
[0046] The third step is to create a barrier layer on top of the channel layer.
[0047] In this embodiment of the disclosure, the barrier layer can be an AlGaN barrier layer.
[0048] In this embodiment of the disclosure, the thickness of the barrier layer can be 20~50nm.
[0049] For example, the thickness of the barrier layer is 35 nm.
[0050] S22. Fabricate the first dielectric layer on the barrier layer.
[0051] In embodiments of this disclosure, the first dielectric layer may include a first dielectric sublayer, a second dielectric sublayer, a third dielectric sublayer, a fourth dielectric sublayer, a fifth dielectric sublayer, a sixth dielectric sublayer, and a seventh dielectric sublayer.
[0052] In one example, step S22 includes: The first step is to use an MOCVD device to fabricate a SiN layer on the barrier layer as the first dielectric sublayer.
[0053] In this implementation, an MOCVD device is used to fabricate a SiN layer on the barrier layer as the first dielectric sublayer. The fabricated film is denser and has fewer impurities, which passivates the barrier layer and prevents it from being eroded by the external environment (such as humidity, oxidation, etc.).
[0054] In this embodiment of the disclosure, the thickness of the first dielectric sublayer can be 50~60nm.
[0055] In this implementation, the thickness of the first dielectric sublayer is 50~60nm. The first dielectric sublayer is thick enough to provide good protection for the barrier layer. At the same time, the first dielectric sublayer of appropriate thickness can serve as a stress buffer layer to reduce the stress generated during subsequent deposition.
[0056] For example, the thickness of the first dielectric sublayer is 55 nm.
[0057] The second step involves using an MOCVD device to fabricate an AlN layer on the first dielectric sublayer, which serves as the second dielectric sublayer.
[0058] In this implementation, an AlN layer is fabricated on the first dielectric sublayer using an MOCVD device as the second dielectric sublayer. AlN has high thermal conductivity, which can effectively conduct heat and help avoid heat concentration, thus preventing an increase in thermal stress.
[0059] In this embodiment of the disclosure, the thickness of the second dielectric sublayer can be 1~5nm.
[0060] In this implementation, the thickness of the second dielectric sublayer is 1~5nm, which is sufficient to provide a good heat conduction channel and avoid thermal stress concentration.
[0061] For example, the thickness of the second dielectric sublayer is 3 nm.
[0062] The third step is to use an MOCVD device to fabricate a SiN layer on the second dielectric sublayer, which will serve as the third dielectric sublayer.
[0063] In this implementation, an MOCVD device is used to fabricate a SiN layer on the second dielectric sublayer as a third dielectric sublayer. The SiN layer can balance the stress of the AlN layer and reduce stress concentration caused by differences in material properties.
[0064] In this embodiment of the disclosure, the thickness of the third dielectric sublayer can be 3~8nm.
[0065] In this implementation, the thickness of the third dielectric sublayer is 3~8nm, which can balance the stress of the second dielectric sublayer and reduce stress concentration caused by differences in material properties.
[0066] For example, the thickness of the third dielectric sublayer is 5 nm.
[0067] The fourth step involves using a low-pressure chemical vapor deposition (LPCVD) system to fabricate a SiN layer on the third dielectric sublayer, which serves as the fourth dielectric sublayer.
[0068] In this implementation, an LPCVD device is used to fabricate a SiN layer on the third dielectric sublayer as the fourth dielectric sublayer. The SiN layer prepared by LPCVD usually has low stress, which helps to reduce the stress level of the overall transistor structure. At the same time, the fourth dielectric sublayer also has a passivation effect, which can provide protection for the transistor.
[0069] In this embodiment of the disclosure, the thickness of the fourth dielectric sublayer can be 290~310nm.
[0070] In this implementation, the thickness of the fourth dielectric sublayer can be 290~310nm. Using the above thickness can ensure the compactness and uniformity of the fourth dielectric sublayer and enhance the insulation performance of the entire first dielectric layer.
[0071] For example, the thickness of the fourth dielectric sublayer is 300 nm.
[0072] The fifth step involves using a PECVD device to fabricate a SiN layer on the fourth dielectric sublayer, which serves as the fifth dielectric sublayer.
[0073] In this implementation, a SiN layer is fabricated on the fourth dielectric sublayer using a PECVD device, which serves as the fifth dielectric sublayer. PECVD has a high deposition rate and can quickly form a protective layer.
[0074] In this embodiment of the disclosure, the thickness of the fifth dielectric sublayer can be 590~610nm.
[0075] In this implementation, the thickness of the fifth dielectric sublayer can be 590~610nm. Using this thickness can ensure uniform film thickness on large-area transistors, and the cost of the fifth dielectric sublayer is low, making it suitable for mass production.
[0076] For example, the thickness of the fifth dielectric sublayer is 600 nm.
[0077] The sixth step is to use a PECVD device to fabricate a SiN layer on the fifth dielectric sublayer, which will serve as the sixth dielectric sublayer.
[0078] In this implementation, a SiN layer is fabricated on the fifth dielectric sublayer using a PECVD device, which serves as the sixth dielectric sublayer and can further protect the transistor.
[0079] In this embodiment of the disclosure, the thickness of the sixth dielectric sublayer can be 490~510nm.
[0080] In this implementation, the thickness of the sixth dielectric sublayer is 490~510nm, which allows the sixth dielectric sublayer to have sufficient thickness to further protect the transistor.
[0081] For example, the thickness of the sixth dielectric sublayer is 500 nm.
[0082] Step 7: Use a PECVD device to fabricate a SiO2 layer on the sixth dielectric sublayer as the seventh dielectric sublayer. The first dielectric layer includes the first dielectric sublayer to the seventh dielectric sublayer.
[0083] In this implementation, a SiO2 layer is fabricated on the sixth dielectric sublayer using a PECVD device, serving as the seventh dielectric sublayer. The SiO2 layer has a low dielectric constant, which can further enhance the insulation performance of the entire first dielectric layer. At the same time, the SiO2 layer has low stress, which can effectively release the stress accumulated in the preceding dielectric sublayers.
[0084] In this embodiment of the disclosure, the thickness of the seventh dielectric sublayer can be 690~710nm.
[0085] In this implementation, the thickness of the seventh dielectric sublayer is 690~710nm, which allows the seventh dielectric sublayer to have sufficient thickness to enhance the insulation performance of the entire first dielectric layer.
[0086] For example, the thickness of the seventh dielectric sublayer is 700 nm.
[0087] In other embodiments, the first dielectric layer may include fewer film layers, such as only the first dielectric layer, the second dielectric layer, the sixth dielectric layer, and the seventh dielectric layer.
[0088] In other embodiments, the sublayers in the first dielectric layer may also be fabricated in other ways, which will not be elaborated here.
[0089] S23. Fabricate a first metal layer on the first dielectric layer.
[0090] In this embodiment of the disclosure, the first metal layer is fabricated using PECVD.
[0091] In this embodiment of the disclosure, the first metal layer may be a Ti, AlSi and TiN metal stack.
[0092] In other examples, the first metal layer can also be other structures, such as a TiN, Al and TiN metal stack.
[0093] S24. A second dielectric layer is fabricated on the first metal layer using a plasma energy gradient increasing PECVD process.
[0094] In this embodiment of the disclosure, a compound layer of Si is fabricated using a PECVD device.
[0095] In this embodiment, the plasma energy gradient is increased by increasing the radio frequency power gradient of the PECVD equipment during the fabrication of the second dielectric layer. In other embodiments, the plasma energy gradient may be increased in other ways, such as by increasing the gas flow rate gradient.
[0096] In this implementation, the increased RF power gradient of the PECVD equipment can gradually increase the intensity of ion bombardment during the fabrication of the second dielectric layer, thereby preventing a sudden increase in the compressive stress of the second dielectric layer. This allows the second dielectric layer time to gradually release the increased compressive stress, preventing cracks from forming in the second dielectric layer and improving the transistor yield.
[0097] In this embodiment of the disclosure, during the fabrication of the second dielectric layer, the radio frequency power of the PECVD equipment is gradually increased in the range of 100~300W, and the gradient of the increase in the radio frequency power of the PECVD equipment is 95~105W.
[0098] In this implementation, during the fabrication of the second dielectric layer, the RF power of the PECVD equipment increases in a gradient within the range of 100~300W. When the RF power is 100W, the power is relatively low, which can reduce the stress generated during the deposition of the second dielectric layer; when the RF power is 300W, the power is relatively high, which can improve the deposition efficiency of the second dielectric layer. The gradient of the RF power increase of the PECVD equipment is 95~105W. The relatively small gradient of the RF power increase can ensure the uniform distribution of plasma density and ion energy, thereby further reducing the stress generated during the deposition of the second dielectric layer. Secondly, with this gradient, the number of gradient changes will not be too many, which would make the fabrication process too complicated.
[0099] For example, during the fabrication of the second dielectric layer, the RF power of the PECVD equipment is gradually increased in the range of 100~300W, with the RF power of the PECVD equipment increasing by a gradient of 100W, and the time for each gradient change is 10~70s.
[0100] For example, the RF power of PECVD equipment varies in the order of 100W, 200W, and 300W.
[0101] In this embodiment of the disclosure, a SiO2 layer is grown under the following conditions: pressure of 2000~5000mT, SiH4 flow rate of 80~260sccm, N2O flow rate of 1200~5000sccm, spacing between the outlet of the PECVD equipment and the wafer of 12.5~13.2mm, and growth time of 29~210s.
[0102] In this implementation, the pressure is 2000~5000mT, the SiH4 flow rate is 80~260sccm, and the N2O flow rate is 1200~5000sccm. This allows for frequent collisions between SiH4 and N2O, which consumes a certain amount of kinetic energy during deposition, thereby reducing the stress generated during the deposition of the second dielectric layer. The distance between the gas outlet of the PECVD equipment and the wafer is 12.5~13.2mm, which allows for uniform distribution of the deposition gas, improves the deposition rate, and achieves uniform deposition. The growth time is 29~210s, which allows for obtaining the required SiO2 layer thickness under conditions of gradually increasing energy.
[0103] For example, a SiO2 layer is grown under the following conditions: pressure of 3000 mT, SiH4 flow rate of 150 sccm, N2O flow rate of 2000 sccm, spacing between the outlet of the PECVD equipment and the wafer of 13 mm, and growth time of 100 s.
[0104] In this embodiment of the disclosure, the thickness of the second dielectric layer is 700~4000nm.
[0105] In this implementation, the dielectric sublayer of the aforementioned thickness can ensure the deposition quality of the second dielectric layer under the condition of increased plasma energy gradient; at the same time, the second dielectric layer is not too thin, which would make it easy to crack, nor is it too thick, which would make the transistor too thick.
[0106] For example, the thickness of the second dielectric layer is 2000 nm.
[0107] S25. Fabricate a second metal layer on the second dielectric layer.
[0108] In this embodiment of the disclosure, a second metal layer is fabricated using PECVD.
[0109] In this embodiment of the disclosure, the second metal layer may be a Ti, AlSi and TiN metal stack.
[0110] Figure 3 This is a schematic diagram of a transistor structure provided in an embodiment of this disclosure. See also... Figure 3 The transistor includes: a channel layer 101, a barrier layer 102, a first dielectric layer 103, a first metal layer 104, a second dielectric layer 105, and a second metal layer 106.
[0111] The channel layer 101, the barrier layer 102, the first dielectric layer 103, the first metal layer 104, the second dielectric layer 105, and the second metal layer 106 are stacked sequentially. The second dielectric layer 105 is a Si compound layer fabricated using a plasma energy gradient-increased PECVD process.
[0112] In this embodiment, a barrier layer is fabricated on the channel layer to form a heterojunction, and a first dielectric layer is fabricated on the barrier layer as a gate insulating layer. A second dielectric layer, serving as an interlayer insulating layer between the first and second metal layers, is fabricated using a PECVD process. Ions in the plasma bombard the surface of the depositing second dielectric layer. Directly bombarding the surface of the depositing second dielectric layer with high RF power plasma energy would generate compressive stress in the second dielectric layer, leading to increased stress. However, using a plasma energy gradient-increasing PECVD process on the first metal layer to fabricate the second dielectric layer allows the intensity of ion bombardment to gradually increase during fabrication, thus preventing a sudden increase in compressive stress and allowing the second dielectric layer time to gradually release the gradient-increasing compressive stress. This prevents cracks in the second dielectric layer and improves transistor yield.
[0113] In this embodiment of the disclosure, the second dielectric layer 105 is a SiO2 layer.
[0114] In this embodiment of the disclosure, the thickness of the second dielectric layer 105 can be 700~4000nm.
[0115] In this implementation, the dielectric sublayer of the aforementioned thickness can ensure the deposition quality of the second dielectric layer under the condition of increasing growth power gradient; at the same time, the dielectric sublayer is not too thin, which would make it easy to crack, nor is it too thick, which would make the transistor too thick.
[0116] For example, the thickness of the second dielectric layer 105 is 2000 nm.
[0117] In this embodiment of the disclosure, the channel layer 101 may be a GaN layer.
[0118] In this embodiment of the disclosure, the thickness of the channel layer 101 can be 5~10nm.
[0119] For example, the thickness of the channel layer 101 is 8 nm.
[0120] In this embodiment of the disclosure, the barrier layer 102 can be an AlGaN layer.
[0121] In this embodiment of the disclosure, the thickness of the barrier layer 102 can be 20~50nm.
[0122] For example, the thickness of the barrier layer 102 is 35 nm.
[0123] In this embodiment of the disclosure, the first dielectric layer 103 may include a first dielectric sublayer 1031, a second dielectric sublayer 1032, a third dielectric sublayer 1033, a fourth dielectric sublayer 1034, a fifth dielectric sublayer 1035, a sixth dielectric sublayer 1036, and a seventh dielectric sublayer 1037 stacked sequentially.
[0124] In this embodiment of the disclosure, the first dielectric sublayer 1031 can be a SiN layer fabricated using MOCVD technology.
[0125] In this embodiment of the disclosure, the thickness of the first dielectric sublayer 1031 can be 50~60nm.
[0126] In this implementation, the thickness of the first dielectric sublayer is 50~60nm. The first dielectric sublayer is thick enough to provide good protection for the barrier layer. At the same time, the first dielectric sublayer of appropriate thickness can serve as a stress buffer layer to reduce the stress generated during subsequent deposition.
[0127] For example, the thickness of the first dielectric sublayer 1031 is 55 nm.
[0128] In this embodiment of the disclosure, the second dielectric sublayer 1032 can be an AlN layer fabricated using MOCVD technology.
[0129] In this embodiment of the disclosure, the thickness of the second dielectric sublayer 1032 can be 1~5nm.
[0130] In this implementation, the thickness of the second dielectric sublayer is 1~5nm, which is sufficient to provide a good heat conduction channel and avoid thermal stress concentration.
[0131] For example, the thickness of the second dielectric sublayer 1032 is 3 nm.
[0132] In this embodiment of the disclosure, the third dielectric sublayer 1033 can be a SiN layer fabricated using MOCVD technology.
[0133] In this embodiment of the disclosure, the thickness of the third dielectric sublayer 1033 can be 3~8nm.
[0134] In this implementation, the thickness of the third dielectric sublayer is 3~8nm, which can balance the stress of the second dielectric sublayer and reduce stress concentration caused by differences in material properties.
[0135] For example, the thickness of the third dielectric sublayer 1033 is 5 nm.
[0136] In this embodiment of the disclosure, the fourth dielectric sublayer 1034 can be a SiN layer fabricated using LPCVD technology.
[0137] In this embodiment of the disclosure, the thickness of the fourth dielectric sublayer 1034 can be 290~310nm.
[0138] In this implementation, the thickness of the fourth dielectric sublayer can be 290~310nm. Using the above thickness can ensure the compactness and uniformity of the fourth dielectric sublayer and enhance the insulation performance of the entire first dielectric layer.
[0139] For example, the thickness of the fourth dielectric sublayer 1034 is 300 nm.
[0140] In this embodiment of the disclosure, the fifth dielectric sublayer 1035 can be a SiN layer fabricated using a PECVD process.
[0141] In this embodiment of the disclosure, the thickness of the fifth dielectric sublayer 1035 can be 590~610nm.
[0142] In this implementation, the thickness of the fifth dielectric sublayer can be 590~610nm. Using this thickness can ensure uniform film thickness on large-area transistors, and the cost of the fifth dielectric sublayer is low, making it suitable for mass production.
[0143] For example, the thickness of the fifth dielectric sublayer 1035 is 600 nm.
[0144] In this embodiment of the disclosure, the sixth dielectric sublayer 1036 can be a SiN layer fabricated using a PECVD process.
[0145] In this embodiment of the disclosure, the thickness of the sixth dielectric sublayer 1036 can be 490~510nm.
[0146] In this implementation, the thickness of the sixth dielectric sublayer is 490~510nm, which allows the sixth dielectric sublayer to have sufficient thickness to further protect the transistor.
[0147] For example, the thickness of the sixth dielectric sublayer 1036 is 500 nm.
[0148] In this embodiment of the disclosure, the seventh dielectric sublayer 1037 can be a SiO2 layer fabricated using a PECVD process.
[0149] In this embodiment of the disclosure, the thickness of the seventh dielectric sublayer 1037 can be 690~710nm.
[0150] In this implementation, the thickness of the seventh dielectric sublayer is 690~710nm, which allows the seventh dielectric sublayer to have sufficient thickness to enhance the insulation performance of the entire first dielectric layer.
[0151] For example, the thickness of the seventh dielectric sublayer 1037 is 700 nm.
[0152] In this embodiment of the disclosure, the first metal layer 104 and the second metal layer 106 can be a Ti, AlSi and TiN metal stack.
[0153] In this embodiment of the disclosure, the transistor may further include a substrate 100 and a buffer layer 107.
[0154] The buffer layer 107, the channel layer 101, the barrier layer 102, the first dielectric layer 103, the first metal layer 104, the second dielectric layer 105, and the second metal layer 106 are sequentially stacked on the substrate 100.
[0155] In this embodiment of the disclosure, the substrate 100 can be any one of sapphire substrate, Si substrate, SiC substrate and GaN substrate, and the material of the substrate 100 is not limited in this embodiment of the disclosure.
[0156] For example, substrate 100 is a Si substrate.
[0157] In this embodiment of the disclosure, the buffer layer 107 can be a GaN layer.
[0158] In this embodiment of the disclosure, the thickness of the buffer layer 107 can be 900~1100nm.
[0159] For example, the thickness of the buffer layer 107 is 1000 nm.
[0160] Figure 4 This is a topographic diagram of the second dielectric layer provided by related technologies. See also... Figure 4 The second dielectric layer 105 has obvious cracks and a stress of -43.01 MPa.
[0161] Figure 5 This is a topographic diagram of the second dielectric layer provided in an embodiment of this disclosure. See also... Figure 5 The second medium layer 105 does not have cracks.
[0162] In this embodiment of the present disclosure, the second dielectric layer deposited slowly in this embodiment of the present disclosure is free of cracks and the stress is only -18.67 MPa.
[0163] The above description is merely an optional embodiment of this disclosure and is not intended to limit this disclosure. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this disclosure should be included within the protection scope of this disclosure.
Claims
1. A method of fabricating a transistor, comprising: The transistor fabrication method includes: Create the trench layer (101); A barrier layer (102) is fabricated on the channel layer (101). A first dielectric layer (103) is fabricated on the barrier layer (102); A first metal layer (104) is formed on the first dielectric layer (102); A second dielectric layer (105) is fabricated on the first metal layer (104) using a plasma energy gradient increasing PECVD process. A second metal layer (106) is formed on the second dielectric layer (105).
2. The method of claim 1, wherein The fabrication of the second dielectric layer (105) on the first metal layer (104) using the plasma energy gradient increasing PECVD process includes: A compound layer of Si is fabricated using a PECVD device, and the radio frequency power gradient of the PECVD device is increased during the fabrication of the second dielectric layer (105).
3. The transistor fabrication method according to claim 2, characterized in that, During the fabrication of the second dielectric layer (105), the radio frequency power of the PECVD equipment is gradually increased in the range of 100~300W, with the increase in radio frequency power of the PECVD equipment being 95~105W.
4. The transistor fabrication method according to claim 2, characterized in that, Compound layers of Si fabricated using PECVD equipment include: A SiO2 layer is grown under the following conditions: pressure of 2000~5000mT, SiH4 flow rate of 80~260sccm, N2O flow rate of 1200~5000sccm, spacing between the outlet of the PECVD equipment and the wafer of 12.5~13.2mm, and growth time of 29~210s.
5. The transistor fabrication method according to any one of claims 1 to 4, characterized in that, The thickness of the second dielectric layer (105) is 700~4000nm.
6. The transistor fabrication method according to any one of claims 1 to 4, characterized in that, Fabricating a first dielectric layer on the barrier layer (102) includes: A SiN layer was fabricated on the barrier layer (102) using an MOCVD device as the first dielectric sublayer (1031). An AlN layer is fabricated on the first dielectric sublayer (1031) using an MOCVD device, which serves as the second dielectric sublayer (1032). A SiN layer is fabricated on the second dielectric sublayer (1032) using an MOCVD device, which serves as the third dielectric sublayer (1033). A SiN layer was fabricated on the third dielectric sublayer (1033) using an LPCVD device, serving as the fourth dielectric sublayer (1034). A SiN layer was fabricated on the fourth dielectric sublayer (1034) using a PECVD device, which served as the fifth dielectric sublayer (1035). A SiN layer was fabricated on the fifth dielectric sublayer (1035) using a PECVD device, which served as the sixth dielectric sublayer (1036). A SiO2 layer is fabricated on the sixth dielectric sublayer (1036) using a PECVD device as the seventh dielectric sublayer (1037), the first dielectric layer comprising the first dielectric sublayer (1031) to the seventh dielectric sublayer (1037).
7. The transistor fabrication method according to claim 6, characterized in that, The thickness of the first dielectric sublayer (1031) is 50~60nm, the thickness of the second dielectric sublayer (1032) is 1~5nm, the thickness of the third dielectric sublayer (1033) is 3~8nm, the thickness of the fourth dielectric sublayer (1034) is 290~310nm, the thickness of the fifth dielectric sublayer (1035) is 590~610nm, the thickness of the sixth dielectric sublayer (1036) is 490~510nm, and the thickness of the seventh dielectric sublayer (1037) is 690~710nm.
8. A transistor, characterized in that, The transistor includes: a channel layer (101), a barrier layer (102), a first dielectric layer (103), a first metal layer (104), a second dielectric layer (105), and a second metal layer (106). The channel layer (101), the barrier layer (102), the first dielectric layer (103), the first metal layer (104), the second dielectric layer (105) and the second metal layer (106) are stacked sequentially; The second dielectric layer (105) is a Si compound layer fabricated using a plasma energy gradient increasing PECVD process.
9. The transistor according to claim 8, characterized in that, The thickness of the second dielectric layer (105) is 700~4000nm.
10. The transistor according to claim 8 or 9, characterized in that, The first dielectric layer (103) includes a first dielectric sublayer (1031), a second dielectric sublayer (1032), a third dielectric sublayer (1033), a fourth dielectric sublayer (1034), a fifth dielectric sublayer (1035), a sixth dielectric sublayer (1036), and a seventh dielectric sublayer (1037) stacked sequentially. The thickness of the first dielectric sublayer (1031) is 50~60nm, the thickness of the second dielectric sublayer (1032) is 1~5nm, the thickness of the third dielectric sublayer (1033) is 3~8nm, the thickness of the fourth dielectric sublayer (1034) is 290~310nm, the thickness of the fifth dielectric sublayer (1035) is 590~610nm, the thickness of the sixth dielectric sublayer (1036) is 490~510nm, and the thickness of the seventh dielectric sublayer (1037) is 690~710nm.