High electron mobility transistor chip and preparation method thereof
By employing alternating polarization layers and C-doped buffer layers in high electron mobility transistors, superlattice and vertical superjunction structures are formed, solving the problems of complex processes and high costs in silicon-based superjunction devices, and realizing low-cost, high-performance transistor chips.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- HC SEMITEK ZHEJIANG CO LTD
- Filing Date
- 2025-12-18
- Publication Date
- 2026-05-08
AI Technical Summary
Existing silicon-based superjunction devices have complex structures and processes, and high manufacturing costs.
An alternating polarization layer is used to form a superlattice structure consisting of periodically alternating GaN and AlGaN layers. The C doping concentration is gradually increased in the second buffer layer. Combined with the continuous tortuous structure of the first electrode and the spaced arrangement of the second electrode, a natural charge balance and vertical superjunction structure are formed.
It simplifies the structural process, reduces the manufacturing cost, improves the substrate insulation capability, suppresses the on-resistance at high temperatures, and enhances the breakdown voltage and switching speed.
Smart Images
Figure CN122002840A_ABST
Abstract
Description
Technical Field
[0001] This disclosure relates to the field of semiconductor technology, and in particular to a high electron mobility transistor chip and its fabrication method. Background Technology
[0002] HEMT (High Electron Mobility Transistor) is a type of heterojunction field-effect transistor.
[0003] In related technologies, silicon-based superjunction devices achieve charge balance through alternating P / N pillars, thereby significantly reducing on-resistance, increasing breakdown voltage, and improving switching speed.
[0004] However, the aforementioned technologies involve complex structures and processes, resulting in high manufacturing costs. Summary of the Invention
[0005] This disclosure provides a high electron mobility transistor chip and its fabrication method, which effectively simplifies the structural process and reduces fabrication costs. The technical solution is as follows: On one hand, embodiments of this disclosure provide a high electron mobility transistor chip, including a substrate, and alternating polarization layer, a first buffer layer, a second buffer layer, a channel layer, a barrier layer, a superjunction layer and a capping layer sequentially stacked on the substrate; The alternating polarization layer comprises periodically alternating GaN and AlGaN layers to form a superlattice structure; The first buffer layer is a GaN layer; The second buffer layer is a C-doped GaN layer, and the C doping concentration of the second buffer layer gradually increases along the epitaxial growth direction.
[0006] In one implementation of this disclosure, in the alternating polarization layer, the Al composition of the AlGaN layer is 5% to 15%, the number of repetition cycles of the GaN layer and the AlGaN layer is 15 to 25, and the thickness of the GaN layer and the AlGaN layer in each repetition cycle is 15 to 25 nm.
[0007] In one implementation of this disclosure, the C doping concentration of the second buffer layer is 1E18~5E19 cm⁻¹. -3 In the epitaxial growth direction, the C doping concentration of the second buffer layer increases once every 50~150nm.
[0008] In one implementation of this disclosure, the high electron mobility transistor chip includes: a first electrode and a plurality of second electrodes; The first electrode is connected to the barrier layer. The first electrode is a continuous tortuous structure extending along a first direction to form a plurality of adjacent grooves in the first electrode. The first direction is perpendicular to the epitaxial growth direction. The second electrode is connected to the cap layer, and one of the plurality of second electrodes is located in one of the grooves, with the second electrode spaced apart from the groove wall of the corresponding groove.
[0009] In one implementation of this disclosure, the groove has the superjunction layer, and in the first direction, the distance between the superjunction layer and the groove wall is 2~4µm.
[0010] In one implementation of this disclosure, in the first direction, both sides of the superjunction layer have groove walls of the groove, and the distance between the superjunction layer and the groove walls of the groove on both sides is the same.
[0011] In one implementation of this disclosure, the second electrode and the first electrode include a first Ti layer, an Al layer and a second Ti layer stacked sequentially. The thickness of the first Ti layer is 10~50nm; The thickness of the Al layer is 100~500 nm; The thickness of the second Ti layer is 50~150nm.
[0012] In one implementation of this disclosure, the width of the superjunction layer in the first direction is 20~30µm.
[0013] On the other hand, this disclosure provides a method for fabricating a high electron mobility transistor chip, the method being used to fabricate the high electron mobility transistor chip as described above, the method comprising: Provide a substrate; An alternating polarization layer is prepared on one side of the substrate. The alternating polarization layer includes periodically alternating GaN layers and AlGaN layers to form a superlattice structure. A first buffer layer is prepared on one side of the alternating polarization layer, wherein the first buffer layer is a GaN layer; A second buffer layer is prepared on one side of the first buffer layer. The second buffer layer is a C-doped GaN layer, and the C doping concentration of the second buffer layer gradually increases along the epitaxial growth direction. A channel layer, a barrier layer, a superjunction layer, and a capping layer are sequentially prepared on one side of the second buffer layer.
[0014] In one implementation of this disclosure, an alternating polarization layer is prepared on one side of the substrate, comprising: Set the number of repetition cycles to 15-25, and the thickness of each repetition cycle to 15-25 nm; The Al composition of the AlGaN layer is set to 5%~15%.
[0015] The beneficial effects of the technical solutions provided in this disclosure include at least the following: The high electron mobility transistor chip provided in this disclosure has an alternating polarization layer on one side of a substrate. The alternating polarization layer comprises periodically alternating GaN and AlGaN layers to form a superlattice structure. The alternating polarization layer achieves natural charge balance through polarization charges, thereby forming a vertically oriented superjunction structure. Compared to related technologies, the alternating polarization layer effectively simplifies the structural process, thereby reducing fabrication costs.
[0016] Furthermore, a first buffer layer and a second buffer layer are provided on the side of the alternating polarization layer facing away from the substrate. The first buffer layer is a GaN layer, and the second buffer layer is a C-doped GaN layer. The C doping concentration of the second buffer layer gradually increases along the epitaxial growth direction. In this way, the insulation capability of the substrate is improved, and the channel layer phonon scattering can be suppressed by adjusting the C doping concentration, thereby reducing the specific on-resistance at high temperature to below 1.4.
[0017] In addition, the high electron mobility transistor chip provided in this disclosure effectively reduces the on-resistance through superjunction technology, thereby increasing the breakdown voltage and improving the switching speed. Attached Figure Description
[0018] To more clearly illustrate the technical solutions in the embodiments of this disclosure, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0019] Figure 1 This is a schematic diagram of the structure of a high electron mobility transistor provided in an embodiment of this disclosure; Figure 2 This is a top view of the high electron mobility transistor provided in an embodiment of this disclosure; Figure 3 This is a flowchart of a method for fabricating a high electron mobility transistor chip according to an embodiment of this disclosure; Figure 4 This is a flowchart of another method for fabricating a high electron mobility transistor chip provided in this embodiment.
[0020] Icon labels: 10. Substrate; 110. Nucleation layer; 20. Alternating polarization layer; 30. First buffer layer; 40. Second buffer layer; 50. Channel layer; 60. Barrier layer; 70. Superstructure; 80. Cap layer; 910, First electrode; 911, Groove; 920, Second electrode. Detailed Implementation
[0021] To make the objectives, technical solutions, and advantages of this disclosure clearer, the embodiments of this disclosure will be described in further detail below with reference to the accompanying drawings.
[0022] GaN, as a representative of third-generation semiconductor materials, is an important semiconductor material that emerged after Si and GaAs. Due to its excellent properties such as large bandgap, high critical field strength, high carrier saturation velocity, and high temperature resistance and radiation resistance, it has attracted widespread attention.
[0023] GaN-based high electron mobility transistors (HEP transistors) achieve device conduction by creating a conductive channel through a high-concentration, high-mobility two-dimensional electron gas (2DEG) at the heterojunction. Due to their excellent properties such as high thermal conductivity, low on-resistance, and tolerance to high-frequency and high-voltage conditions, GaN-based HEP transistors have become a research hotspot in the fields of high-frequency, high-power devices and switching devices in recent years.
[0024] In related technologies, silicon-based superjunction devices achieve charge balance through alternating P / N pillars, thereby significantly reducing on-resistance, increasing breakdown voltage, and improving switching speed.
[0025] However, the aforementioned technologies involve complex structures and processes, resulting in high manufacturing costs.
[0026] To address the aforementioned technical problems, embodiments of this disclosure provide a high electron mobility transistor. Figure 1 This is a schematic diagram of the structure of the high electron mobility transistor, combined with... Figure 1 In this embodiment, the high electron mobility transistor includes a substrate 10, and alternating polarization layer 20, first buffer layer 30, second buffer layer 40, channel layer 50, barrier layer 60, superjunction layer 70 and capping layer 80 sequentially stacked on the substrate 10.
[0027] The alternating polarization layer 20 comprises periodically alternating GaN and AlGaN layers to form a superlattice structure. The first buffer layer 30 is a GaN layer, and the second buffer layer 40 is a C-doped GaN layer, with the C doping concentration of the second buffer layer 40 gradually increasing along the epitaxial growth direction.
[0028] The high electron mobility transistor chip provided in this disclosure has an alternating polarization layer 20 disposed on one side of a substrate 10. The alternating polarization layer 20 includes periodically alternating GaN layers and AlGaN layers to form a superlattice structure. The alternating polarization layer 20 achieves natural charge balance through polarization charges, thereby forming a vertical superjunction structure. Compared with related technologies, the alternating polarization layer 20 effectively simplifies the structure and process, thereby reducing the fabrication cost.
[0029] Furthermore, a first buffer layer 30 and a second buffer layer 40 are provided on the side of the alternating polarization layer 20 facing away from the substrate 10. The first buffer layer 30 is a GaN layer, and the second buffer layer 40 is a C-doped GaN layer. The C doping concentration of the second buffer layer 40 gradually increases along the epitaxial growth direction. In this way, the insulation capability of the substrate 10 is improved. At the same time, by adjusting the C doping concentration, phonon scattering of the channel layer 50 can be suppressed, and the specific on-resistance at high temperature can be reduced to below 1.4.
[0030] In addition, the high electron mobility transistor chip provided in this disclosure effectively reduces the on-resistance through superjunction technology, thereby increasing the breakdown voltage and improving the switching speed.
[0031] See also Figure 1 In this embodiment, the substrate 10 is a low-resistivity SI substrate 10, a semi-insulating sapphire substrate 10, a SiC substrate 10, etc.
[0032] In this embodiment, a 4-8 inch wafer with a flat edge of 57.5 mm or a notch type with a depth of 1 mm and an opening of 90°-95° is used to smooth out the stress increase caused by the epitaxial structure and reduce the warping of the entire wafer.
[0033] In this embodiment, the thickness of the substrate 10 is 500~1000µm. Within the above range, the thicker the wafer, the smaller the overall wafer warpage.
[0034] In this embodiment, a nucleation layer 110 is provided on one side of the substrate 10.
[0035] For example, the nucleation layer 110 is an AlN layer, and the thickness of the nucleation layer 110 is 100~300nm.
[0036] In this embodiment, the thickness of the nucleation layer 110 is 200 nm.
[0037] For example, in the alternating polarization layer 20, the Al composition of the AlGaN layer is 5% to 15%.
[0038] For example, the number of repeating cycles of the GaN layer and the AlGaN layer is 15 to 25, and the thickness of the GaN layer and the AlGaN layer in each repeating cycle is 15 to 25 nm.
[0039] In this embodiment, the GaN layer and AlGaN layer have 20 repeating cycles, and the thickness of the GaN layer and AlGaN layer in each repeating cycle is 20nm.
[0040] For example, the C doping concentration of the second buffer layer 40 is 1E18~5E19 cm⁻¹ -3 In the epitaxial growth direction, the C doping concentration of the second buffer layer 40 increases once every 50~150nm.
[0041] For example, in the epitaxial growth direction, with a thickness variation interval of 100 nm, the C doping concentration of the first 100 nm thick second buffer layer 40 closest to the substrate 10 is 1E18 cm⁻¹. -3 The second 100nm thick buffer layer has a C doping concentration of 2E18cm⁻¹. -3 The third 100nm thick second buffer layer has a C doping concentration of 3E18 cm⁻¹. -3 And so on.
[0042] It is worth noting that the magnitude of the change in C doping concentration each time can be the same as mentioned above, or it can be different. For example, the C doping concentration of the first 100nm thick second buffer layer 40 closest to the substrate 10 is 1E18cm. -3 The second 100nm thick buffer layer has a C doping concentration of 2E18cm⁻¹. -3 The third 100nm thick second buffer layer has a C doping concentration of 4E18 cm⁻¹. -3 This disclosure does not impose any restrictions.
[0043] See also Figure 1 In this embodiment, the channel layer 50 is an unintentionally doped GaN layer, and the barrier layer 60 is an AlGaN layer.
[0044] For example, the thickness of the channel layer 50 is 100~350nm.
[0045] For example, the thickness of the barrier layer 60 is 10~50 nm, and the Al composition is 10%~30%.
[0046] In this embodiment, the barrier layer 60 is 40 nm thick to increase the 2DEG concentration, and the Al composition is set to 27%.
[0047] For example, the superjunction layer 70 is an unintentionally doped GaN layer with a thickness of 30~80nm.
[0048] In this embodiment, the thickness of the superjunction layer 70 is 60 nm.
[0049] In this embodiment, etching barrier layers are provided on both sides of the superjunction layer 70.
[0050] For example, the etching barrier layer is an AlN layer with a thickness of 0.5µm, which serves as an insertion layer for etching barrier of the capping layer 80.
[0051] In this embodiment, the capping layer 80 is a P-type GaN layer.
[0052] The thickness of the capping layer 80 can be modulated to Vth. In this embodiment, using 75~80nm can increase Vth to 1.5V.
[0053] For example, the capping layer 80 is Mg-doped, with a Mg doping concentration of 1E18~5E19 cm⁻¹. -3 This embodiment uses 5E19cm -3 .
[0054] Figure 2 A top view of a high electron mobility transistor chip, combined with Figure 2 In this embodiment, the high electron mobility transistor chip includes a first electrode 910 and a plurality of second electrodes 920.
[0055] The first electrode 910 is connected to the barrier layer 60. The first electrode 910 is a continuous tortuous structure extending along a first direction, so as to form a plurality of adjacently arranged grooves 911 within the first electrode 910. Figure 1 and Figure 2 (The solid line with arrows in the image) is perpendicular to the epitaxial growth direction. The second electrode 920 is connected to the capping layer 80. One of the multiple second electrodes 920 is located in a groove 911, and the second electrode 920 is spaced apart from the groove wall of the corresponding groove 911.
[0056] In some examples, the first electrode 910 is the gate, and in a bidirectional circuit, the second electrode 920 can be either the source or the drain. For example, for two adjacent second electrodes 920, if one is the source, then the other is the drain. That is, multiple second electrodes 920 arranged at intervals alternately serve as sources or drains.
[0057] In the above implementation, since the second electrode 920 is located in the groove 911 formed by the bending of the first electrode 910, the second electrode 920 has the first electrode 910 on both sides in the first direction. In this way, bidirectional control is achieved through a single gate, which greatly simplifies the structure, driving and control methods of the bidirectional circuit.
[0058] For example, the groove 911 formed by the continuously tortuous first electrode 910 is formed after the gate groove 911 etching process is performed on the ohmic contact metal, which enables the ohmic contact metal to contact the underlying 2DEG.
[0059] In this embodiment, in the first direction, both sides of the super-junction layer 70 have groove walls of groove 911, and the distance between the super-junction layer 70 and the groove walls of the groove 911 on both sides is the same.
[0060] In the above implementation, the high electron mobility transistor chip adopts a completely symmetrical first electrode 910 design and a centrally located second electrode 920. The metallization, charge spacing, and contact resistance of the first electrode 910 are all highly symmetrical. Furthermore, during fabrication, a self-aligned second electrode 920 and a sidewall protection process can be used to create a superjunction structure.
[0061] This design effectively suppresses forward and reverse breakdown voltages and improves bidirectional on-resistance matching. This makes the high electron mobility transistor chip suitable for AC or bidirectional DC applications. Furthermore, due to the superjunction structure, the BVGS voltage can be increased from 10V to 100V compared to traditional normally-off devices, significantly improving electrostatic discharge (ESD) immunity; the HBM can withstand up to 3000V.
[0062] For example, the groove 911 has a super-junction layer 70, and in a first direction, the distance between the super-junction layer 70 and the groove wall of the groove 911 is 2~4µm.
[0063] In this embodiment, in the first direction, the distance between the superjunction layer 70 and the groove wall of the groove 911 is 3µm.
[0064] For example, in the first direction, the width of the superjunction layer 70 is 20~30µm.
[0065] In this embodiment, the width of the superjunction layer 70 is 24.5µm.
[0066] For example, the second electrode 920 and the first electrode 910 include a first Ti layer, an Al layer and a second Ti layer stacked sequentially, that is, the second electrode 920 and the first electrode 910 are Ti / Al / Ti stacked structures.
[0067] For example, the thickness of the first Ti layer is 10~50nm, the thickness of the Al layer is 100~500nm, and the thickness of the second Ti layer is 50~150nm.
[0068] Figure 3 A flowchart illustrating a method for fabricating a high electron mobility transistor chip according to an embodiment of this disclosure is provided. (See attached flowchart.) Figure 3 The preparation method includes: Step 301: Provide a substrate 10.
[0069] Step 302: An alternating polarization layer 20 is prepared on one side of the substrate 10. The alternating polarization layer 20 includes periodically alternating GaN layers and AlGaN layers to form a superlattice structure.
[0070] Step 303: Prepare a first buffer layer 30 on one side of the alternating polarization layer 20. The first buffer layer 30 is a GaN layer.
[0071] Step 304: Prepare a second buffer layer 40 on one side of the first buffer layer 30. The second buffer layer 40 is a C-doped GaN layer, and the C doping concentration of the second buffer layer 40 gradually increases along the epitaxial growth direction.
[0072] Step 305: Sequentially prepare a channel layer 50, a barrier layer 60, a superjunction layer 70, and a capping layer 80 on one side of the second buffer layer 40.
[0073] The fabrication method provided in this disclosure involves forming an alternating polarization layer 20 on one side of a substrate 10. The alternating polarization layer 20 comprises periodically alternating GaN and AlGaN layers to form a superlattice structure. The alternating polarization layer 20 achieves natural charge balance through polarization charges, thereby forming a vertically oriented superjunction structure. Compared to related technologies, the alternating polarization layer 20 effectively simplifies the structural process, thereby reducing fabrication costs.
[0074] Furthermore, a first buffer layer 30 and a second buffer layer 40 are provided on the side of the alternating polarization layer 20 facing away from the substrate 10. The first buffer layer 30 is a GaN layer, and the second buffer layer 40 is a C-doped GaN layer. The C doping concentration of the second buffer layer 40 gradually increases along the epitaxial growth direction. In this way, the insulation capability of the substrate 10 is improved. At the same time, by adjusting the C doping concentration, phonon scattering of the channel layer 50 can be suppressed, and the specific on-resistance at high temperature can be reduced to below 1.4.
[0075] In addition, the fabrication method provided in this disclosure effectively reduces the on-resistance through superjunction technology, thereby increasing the breakdown voltage and improving the switching speed.
[0076] Figure 4A flowchart illustrating another method for fabricating a high electron mobility transistor chip according to an embodiment of this disclosure is provided. Figure 4 The preparation method includes: Step 401: Provide a substrate 10.
[0077] For example, the substrate 10 is a low-resistivity SI substrate 10, a semi-insulating sapphire substrate 10, a SiC substrate 10, etc.
[0078] Step 402: Prepare a core layer 110 on one side of the substrate 10.
[0079] Step 403: Prepare an alternating polarization layer 20 on one side of the nucleation layer 110.
[0080] For example, the number of repetition cycles is set to 15 to 25, the thickness of each repetition cycle is set to 15 to 25 nm, and the Al composition of the AlGaN layer is set to 5% to 15%.
[0081] Step 404: Prepare a first buffer layer 30 on one side of the alternating polarization layer 20.
[0082] Step 405: Prepare a second buffer layer 40 on one side of the first buffer layer 30.
[0083] For example, the C doping concentration of the second buffer layer 40 is 1E18~5E19 cm⁻¹ -3 In the epitaxial growth direction, the C doping concentration of the second buffer layer 40 increases once every 50~150nm.
[0084] Step 406: Prepare a channel layer 50 and a barrier layer 60 sequentially on one side of the second buffer layer 40.
[0085] Step 407: Sequentially prepare a first etch barrier layer, a superjunction layer 70, and a second etch barrier layer on one side of the barrier layer 60.
[0086] Step 408: Prepare a capping layer 80 on one side of the second etch barrier layer.
[0087] Step 409: Prepare the second electrode 920 and the first electrode 910.
[0088] Unless otherwise defined, the technical or scientific terms used herein shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” “third,” and similar terms used in this patent application specification and claims do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Similarly, the terms “an” or “a” and similar terms do not indicate a quantity limitation, but rather indicate the presence of at least one. The terms “comprising” or “including” and similar terms mean that the elements or objects preceding “comprising” or “including” encompass the elements or objects listed following “comprising” or “including” and their equivalents, and do not exclude other elements or objects. The terms “connected” or “linked” and similar terms are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. The terms “upper,” “lower,” “left,” “right,” “top,” and “bottom,” etc., are used only to indicate relative positional relationships, and these relative positional relationships may change accordingly when the absolute position of the described objects changes.
[0089] The above is not intended to limit this disclosure in any way. Although this disclosure has been disclosed above through embodiments, it is not intended to limit this disclosure. Any person skilled in the art can make some modifications or alterations to the above-disclosed technical content to create equivalent embodiments without departing from the scope of the technical solution of this disclosure. Any simple modifications, equivalent changes and alterations made to the above embodiments based on the technical essence of this disclosure without departing from the content of the technical solution of this disclosure shall still fall within the scope of the technical solution of this disclosure.
Claims
1. A high electron mobility transistor chip, characterized in that, It includes a substrate (10), and alternating polarization layer (20), first buffer layer (30), second buffer layer (40), channel layer (50), barrier layer (60), superjunction layer (70) and capping layer (80) sequentially stacked on the substrate (10). The alternating polarization layer (20) includes periodically alternating GaN layers and AlGaN layers to form a superlattice structure; The first buffer layer (30) is a GaN layer; The second buffer layer (40) is a C-doped GaN layer, and the C doping concentration of the second buffer layer (40) gradually increases along the epitaxial growth direction.
2. The high electron mobility transistor chip according to claim 1, characterized in that, In the alternating polarization layer (20), the Al composition of the AlGaN layer is 5%~15%, the number of repetition cycles of the GaN layer and the AlGaN layer is 15~25, and the thickness of the GaN layer and the AlGaN layer in each repetition cycle is 15~25nm.
3. The high electron mobility transistor chip according to claim 1, characterized in that, The C doping concentration of the second buffer layer (40) is 1E18~5E19 cm⁻¹ -3 In the epitaxial growth direction, the C doping concentration of the second buffer layer (40) increases once every 50~150nm.
4. The high electron mobility transistor chip according to claim 1, characterized in that, The high electron mobility transistor chip includes: a first electrode (910) and multiple second electrodes (920). The first electrode (910) is connected to the barrier layer (60). The first electrode (910) is a continuous tortuous structure extending along a first direction, so as to form a plurality of adjacent grooves (911) in the first electrode (910). The first direction is perpendicular to the epitaxial growth direction. The second electrode (920) is connected to the cap layer (80), and one of the plurality of second electrodes (920) is located in a groove (911), and the second electrode (920) is spaced apart from the groove wall of the corresponding groove (911).
5. The high electron mobility transistor chip according to claim 4, characterized in that, The groove (911) has the superjunction layer (70), and in the first direction, the distance between the superjunction layer (70) and the groove wall of the groove (911) is 2~4µm.
6. The high electron mobility transistor chip according to claim 4, characterized in that, In the first direction, the super-junction layer (70) has groove walls of the groove (911) on both sides, and the distance between the super-junction layer (70) and the groove walls of the groove (911) on both sides is the same.
7. The high electron mobility transistor chip according to claim 4, characterized in that, The second electrode (920) and the first electrode (910) comprise a first Ti layer, an Al layer, and a second Ti layer stacked sequentially. The thickness of the first Ti layer is 10~50nm; The thickness of the Al layer is 100~500 nm; The thickness of the second Ti layer is 50~150nm.
8. The high electron mobility transistor chip according to claim 4, characterized in that, In the first direction, the width of the superjunction layer (70) is 20~30µm.
9. A method for fabricating a high electron mobility transistor chip, characterized in that, The preparation method is used to prepare a high electron mobility transistor chip as described in any one of claims 1 to 8, the preparation method comprising: Provide a substrate (10); An alternating polarization layer (20) is prepared on one side of the substrate (10). The alternating polarization layer (20) includes periodically alternating GaN layers and AlGaN layers to form a superlattice structure. A first buffer layer (30) is prepared on one side of the alternating polarization layer (20), wherein the first buffer layer (30) is a GaN layer; A second buffer layer (40) is prepared on one side of the first buffer layer (30). The second buffer layer (40) is a C-doped GaN layer, and the C doping concentration of the second buffer layer (40) gradually increases along the epitaxial growth direction. A channel layer (50), a barrier layer (60), a superjunction layer (70), and a capping layer (80) are sequentially prepared on one side of the second buffer layer (40).
10. The preparation method according to claim 9, characterized in that, An alternating polarization layer (20) is prepared on one side of the substrate (10), comprising: Set the number of repetition cycles to 15-25, and the thickness of each repetition cycle to 15-25 nm; The Al composition of the AlGaN layer is set to 5%~15%.